sam-t2/sam/cpus/vonk/ss/lib/cpu/src/MemoryTransaction.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: MemoryTransaction.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
//============================================================================
// WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
//
// THIS FILE IS ONLY HERE FOR BACKWARDS COMPATIBILITY. DO NOT WRITE NEW CODE
// THAT DEPENDS ON THIS CLASS AND DO NOT ADD MORE CODE TO THIS CLASS HERE.
// THE ORIGINAL OF THIS FILE IS IN THE RIESLING REPOSITORY.
//============================================================================

#ifndef _MEMORYTRANSACTION_H__
#define _MEMORYTRANSACTION_H__

#include "SS_Types.h"

typedef SS_Vaddr VaddrT;
typedef SS_Paddr PaddrT;

class SS_Strand;

class MemoryTransaction {
 public:

    typedef enum { DATA, INSTR } RefT;

    enum Access_T
    {
      READ               = 1 << 0,  // read access
      WRITE              = 1 << 1,  // write access
      ATOMIC             = 1 << 2,  // atomic instruction
      INTERNAL           = 1 << 3,  // internal read/write, allow access to RO/WO area
      TABLE_WALK         = 1 << 4,  // the memory transaction is generated by hardware table walk, rather then instruction fetch or LSU operation.
      NO_WRITE           = 1 << 5,  // do not overwrite data in the object
      MEM_SLAM           = 1 << 6,  // testbench slam a data into (read-only) memory section.
      FOLLOW_ME          = 1 << 7,  // indicate the value is a follow-me
      LITTLE_ENDIAN      = 1 << 8,  // data in little endian format
      NOP                = 1 << 9,  // silently ignore the read/write
      DEBUG              = 1 << 31  // last item, for debug purpose
    };

        typedef uint32_t AccessT;

        /**
          * Default constructor
          */
        MemoryTransaction()
         :
          strand( 0 ),
          size_( 0 ),
          ref_( DATA ),
          vaddr_( ~0x0 ),
          paddr_( ~0x0 )
        {}


        MemoryTransaction( VaddrT vaddr,AccessT a, uint_t id=0 )
         :
          strand(id),
          vaddr_(vaddr),
          paddr_(~0x0),
          ref_(DATA),
          access_(a),
          size_(0)
        {}

        /**
          * Copy constructor
          *
          * @param orig The MemoryTransaction object to copy.
          */
        MemoryTransaction( const MemoryTransaction &orig )
         :
          strand( orig.strand ),
          vaddr_( orig.vaddr_ ),
          paddr_( orig.paddr_ ),
          ref_( orig.ref_ ),
          access_( orig.access_ ),
          size_( orig.size_ )
        {
          for (uint_t i = 0; i < ((size_ + 7) >> 3); i++)
            data_[i] = orig.data_[i];
        }

        /**
          * Destructor
          */
        ~MemoryTransaction()  {}


        /**
          * Assignment operator
          *
          * @param rhs The right hand side of the assignment operator.
          * @return The lvalue of the assignment.
          */
        const MemoryTransaction & operator=( const MemoryTransaction &rhs )
        {
          strand = rhs.strand;
          vaddr_ = rhs.vaddr_;
          paddr_ = rhs.paddr_;
          ref_ = rhs.ref_;
          access_ = rhs.access_;
          size_ = rhs.size_;

          for (uint_t i = 0; i < ((size_ + 7) >> 3); i++)
            data_[i] = rhs.data_[i];
          return *this;
        }

        /**
          * Return a string representation of this MemoryTransaction object.
          */
#if 0
        std::string toString() const{
            ostringstream os;

            os << "reference type:    " << ( ref_ == DATA ? "data" : "instruction" ) << "\n";
            os << "access type:       " << ( access_ == READ ? "read" : "write" ) << "\n";
            os << "virtual addr:    0x" << RIESLING_VADDR_FORMAT << vaddr_ << "\n";
            os << "physical addr:   0x" << RIESLING_VADDR_FORMAT << paddr_ << "\n";
            os << "data:            ";
            for( uint_t i = 0; i < ((size_ + 7) >> 3); i++)
                os  << "0x" << data_[i] << " ";

            os << "\n";
            return os.str();
        }
#endif

        /**
          * Return the virtual address of the transaction
          */
        VaddrT vaddr() const                        { return vaddr_; }
        VaddrT getVaddr() const { return vaddr_; }

        /**
          * Set the virtual address of the transaction
          */
        void vaddr( VaddrT va )                     { vaddr_ = va; }

        /**
          * Return the physical address of the transaction
          */
        PaddrT paddr() const                        { return paddr_; }
        PaddrT getPaddr() const { return paddr_; }

        /**
          * Set the physcial address of the transaction
          */
        void paddr( PaddrT pa )                     { paddr_ = pa; }


        /**
          * Return the type of the transaction, either DATA or INSTR
          */
        RefT referenceType() const                  { return ref_; }
        RefT getReferenceType() const { return ref_; }

        /**
          * Set the type of the transaction, either DATA or INSTR
          */
        void referenceType( RefT r )                { ref_ = r; }


        /**
          * Set access characteristics of the transaction.
          *
          * @param val The value of the access word.  The following values can be
          * ored into the access word:
          * READ     - a read transaction
          * WRITE    - a write transaction
          * INTERNAL - an internal transaction mean that the transaction may
          *            not be subject to some MMU checks
          * REVERSE_BYTE_ORDER
          *
          */
        void reset_access()                         { access_ = 0; }
        void access( AccessT val )
        {
          assert((val & (READ|WRITE)) && (val & (READ|WRITE)) != (READ|WRITE));
          access_ = val;
        }
        AccessT access() const                      { return access_; }
        AccessT getAccess() const { return access_; }

        void size( uint_t s )                       { size_ = s; }
        uint8_t size() const                        { return size_; }

        uint64_t getData ( uint_t dword = 0 ) const { return data_[dword]; }

        void     setData( uint_t dword, uint64_t data )         { data_[dword] = data; }
        void     setData( uint64_t data )                       { data_[0] = data; }
        void     setData( uint64_t *data )                       {
          data_[0] = data[0];
          data_[1] = data[1];
          data_[2] = data[2];
          data_[3] = data[3];
          data_[4] = data[4];
          data_[5] = data[5];
          data_[6] = data[6];
          data_[7] = data[7];
        }

        bool readXact() const                     { return access_ & READ; }
        bool writeXact() const                    { return access_ & WRITE; }
        bool internalXact() const                 { return access_ & INTERNAL; }
        bool memSlamXact() const                 { return access_ & MEM_SLAM; }
        bool debugXact() const                     { return access_ & DEBUG; }
        bool tablewalk() const                    { return access_ & TABLE_WALK; }
        bool noWriteXact() const { return access_ & NO_WRITE; }
        bool followmeXact() const { return access_ & FOLLOW_ME; }
        bool atomicXact() const { return access_ & ATOMIC; }
        bool noOperationXact() const              { return access_ & NOP; }


        void setStrand( uint_t id )       { strand = id; }
        uint_t getStrand()           const    { return strand; }


    protected:
        uint_t                  strand;               // The strand that generated the transaction.
        VaddrT                  vaddr_;               // The virtual address of the access
        PaddrT                  paddr_;               // The physical address of the access
        RefT                    ref_;                 // DATA/INSTR access
        AccessT                 access_;              // READ/WRITE and other flags
        uint_t                  size_;                // The number of bytes this transaction is accessing
        uint64_t                data_[8];             // Largest request is 64 bytes
};
#endif /* __MEMORYTRANSACTION_H__ */