projects / OpenSPARC-T2-SAM / blame
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|---|---|---|
| 920dae64 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: SS_Registers.h | |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
| 7 | * | |
| 8 | * The above named program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public | |
| 10 | * License version 2 as published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * The above named program is distributed in the hope that it will be | |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | * General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public | |
| 18 | * License along with this work; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 20 | * | |
| 21 | * ========== Copyright Header End ============================================ | |
| 22 | */ | |
| 23 | #ifndef __SS_Registers_h__ | |
| 24 | #define __SS_Registers_h__ | |
| 25 | ||
| 26 | class SS_Registers | |
| 27 | { | |
| 28 | public: | |
| 29 | enum Error | |
| 30 | { | |
| 31 | OK, | |
| 32 | NOT_AVAILABLE, | |
| 33 | VALUE_OUT_OF_RANGE // set tl, gl, cwp can return this | |
| 34 | }; | |
| 35 | ||
| 36 | enum Index | |
| 37 | { | |
| 38 | INDEX_BEGIN = 0, | |
| 39 | ||
| 40 | // %g[0,..,7], %o[0,..,7], %l[0,..,7], %i[0,..,7] | |
| 41 | ||
| 42 | IRF_OFS = INDEX_BEGIN, | |
| 43 | G0 = IRF_OFS, | |
| 44 | G1, G2, G3, G4, G5, G6, G7, | |
| 45 | O0, O1, O2, O3, O4, O5, O6, O7, | |
| 46 | L0, L1, L2, L3, L4, L5, L6, L7, | |
| 47 | I0, I1, I2, I3, I4, I5, I6, I7, | |
| 48 | IRF_END, | |
| 49 | ||
| 50 | // %d[0,2,..,62] | |
| 51 | ||
| 52 | DRF_OFS = IRF_END, | |
| 53 | D0 = DRF_OFS, | |
| 54 | D2, D4, D6, D8, D10, D12, D14, | |
| 55 | D16, D18, D20, D22, D24, D26, D28, D30, | |
| 56 | D32, D34, D36, D38, D40, D42, D44, D46, | |
| 57 | D48, D50, D52, D54, D56, D58, D60, D62, | |
| 58 | DRF_END, | |
| 59 | ||
| 60 | // %asr[0,..,31] | |
| 61 | ||
| 62 | ASR_OFS = DRF_END, | |
| 63 | ASR0 = ASR_OFS, | |
| 64 | ASR1, ASR2, ASR3, ASR4, ASR5, ASR6, ASR7, | |
| 65 | ASR8, ASR9, ASR10, ASR11, ASR12, ASR13, ASR14, ASR15, | |
| 66 | ASR16, ASR17, ASR18, ASR19, ASR20, ASR21, ASR22, ASR23, | |
| 67 | ASR24, ASR25, ASR26, ASR27, ASR28, ASR29, ASR30, ASR31, | |
| 68 | ASR_END, | |
| 69 | // | |
| 70 | // %pr[0,..,31] | |
| 71 | ||
| 72 | PR_OFS = ASR_END, | |
| 73 | PR0 = PR_OFS, | |
| 74 | PR1, PR2, PR3, PR4, PR5, PR6, PR7, | |
| 75 | PR8, PR9, PR10, PR11, PR12, PR13, PR14, PR15, | |
| 76 | PR16, PR17, PR18, PR19, PR20, PR21, PR22, PR23, | |
| 77 | PR24, PR25, PR26, PR27, PR28, PR29, PR30, PR31, | |
| 78 | PR_END, | |
| 79 | ||
| 80 | // %hpr[0,..,31] | |
| 81 | ||
| 82 | HPR_OFS = PR_END, | |
| 83 | HPR0 = HPR_OFS, | |
| 84 | HPR1, HPR2, HPR3, HPR4, HPR5, HPR6, HPR7, | |
| 85 | HPR8, HPR9, HPR10, HPR11, HPR12, HPR13, HPR14, HPR15, | |
| 86 | HPR16, HPR17, HPR18, HPR19, HPR20, HPR21, HPR22, HPR23, | |
| 87 | HPR24, HPR25, HPR26, HPR27, HPR28, HPR29, HPR30, HPR31, | |
| 88 | HPR_END, | |
| 89 | ||
| 90 | // %sim[0,..,31] - simulator state (npc, fsr, ...) | |
| 91 | ||
| 92 | SIM_OFS = HPR_END, | |
| 93 | SIM0 = SIM_OFS, | |
| 94 | SIM1, SIM2, SIM3, SIM4, SIM5, SIM6, SIM7, | |
| 95 | SIM8, SIM9, SIM10, SIM11, SIM12, SIM13, SIM14, SIM15, | |
| 96 | SIM16, SIM17, SIM18, SIM19, SIM20, SIM21, SIM22, SIM23, | |
| 97 | SIM24, SIM25, SIM26, SIM27, SIM28, SIM29, SIM30, SIM31, | |
| 98 | SIM_END, | |
| 99 | ||
| 100 | INDEX_END = SIM_END, | |
| 101 | ||
| 102 | ALIAS_BEGIN = SIM_END, | |
| 103 | ||
| 104 | // %f[0,..,63] | |
| 105 | ||
| 106 | FRF_OFS = SIM_END, | |
| 107 | F0 = FRF_OFS, | |
| 108 | F1, F2, F3, F4, F5, F6, F7, | |
| 109 | F8, F9, F10, F11, F12, F13, F14, F15, | |
| 110 | F16, F17, F18, F19, F20, F21, F22, F23, | |
| 111 | F24, F25, F26, F27, F28, F29, F30, F31, | |
| 112 | F32, F33, F34, F35, F36, F37, F38, F39, | |
| 113 | F40, F41, F42, F43, F44, F45, F46, F47, | |
| 114 | F48, F49, F50, F51, F52, F53, F54, F55, | |
| 115 | F56, F57, F58, F59, F60, F61, F62, F63, | |
| 116 | ||
| 117 | FRF_END, | |
| 118 | ALIAS_END = FRF_END, | |
| 119 | ||
| 120 | // REG_ is the prefix for the product specific registers that we | |
| 121 | // want to enumerate and that don't fall in the above given ranges | |
| 122 | // or ASR, PR, HRP, SIM. The enumeration starts at a nice offset | |
| 123 | // from ALIAS_END to leave us room to grow. | |
| 124 | ||
| 125 | REG_OFS = ALIAS_END + 1024, | |
| 126 | ||
| 127 | // Aliases | |
| 128 | ||
| 129 | ASR_Y = ASR0, | |
| 130 | ASR_CCR = ASR2, | |
| 131 | ASR_ASI = ASR3, | |
| 132 | ASR_TICK = ASR4, | |
| 133 | ASR_PC = ASR5, | |
| 134 | ASR_FPRS = ASR6, | |
| 135 | ASR_PCR = ASR16, | |
| 136 | ASR_PIC = ASR17, | |
| 137 | ASR_GSR = ASR19, | |
| 138 | ASR_SOFTINT_SET = ASR20, | |
| 139 | ASR_SOFTINT_CLR = ASR21, | |
| 140 | ASR_SOFTINT = ASR22, | |
| 141 | ASR_TICK_CMPR = ASR23, | |
| 142 | ASR_STICK = ASR24, | |
| 143 | ASR_STICK_CMPR = ASR25, | |
| 144 | ASR_CPS = ASR28, | |
| 145 | ||
| 146 | PR_TPC = PR0, | |
| 147 | PR_TNPC = PR1, | |
| 148 | PR_TSTATE = PR2, | |
| 149 | PR_TT = PR3, | |
| 150 | PR_TICK = PR4, | |
| 151 | PR_TBA = PR5, | |
| 152 | PR_PSTATE = PR6, | |
| 153 | PR_TL = PR7, | |
| 154 | PR_PIL = PR8, | |
| 155 | PR_CWP = PR9, | |
| 156 | PR_CANSAVE = PR10, | |
| 157 | PR_CANRESTORE = PR11, | |
| 158 | PR_CLEANWIN = PR12, | |
| 159 | PR_OTHERWIN = PR13, | |
| 160 | PR_WSTATE = PR14, | |
| 161 | PR_GL = PR16, | |
| 162 | ||
| 163 | HPR_HPSTATE = HPR0, | |
| 164 | HPR_HTSTATE = HPR1, | |
| 165 | HPR_HINTP = HPR3, | |
| 166 | HPR_HTBA = HPR5, | |
| 167 | HPR_HVER = HPR6, | |
| 168 | HPR_HSTICK_CMPR = HPR31, | |
| 169 | ||
| 170 | SIM_NPC = SIM0, | |
| 171 | SIM_FSR = SIM1, | |
| 172 | SIM_STRAND_ID = SIM2, | |
| 173 | SIM_MAX_WP = SIM3, | |
| 174 | SIM_MAX_TL = SIM4, | |
| 175 | SIM_MAX_PTL = SIM5, | |
| 176 | SIM_MAX_GL = SIM6, | |
| 177 | SIM_MAX_PGL = SIM7, | |
| 178 | SIM_PA_BITS = SIM8, | |
| 179 | SIM_VA_BITS = SIM9, | |
| 180 | SIM_RSTV_ADDR = SIM10, | |
| 181 | SIM_STATE = SIM11, | |
| 182 | SIM_INST_COUNT = SIM12, | |
| 183 | SIM_FAILPC = SIM13 | |
| 184 | }; | |
| 185 | ||
| 186 | enum Sizes | |
| 187 | { | |
| 188 | IRF_SIZE = IRF_END - IRF_OFS, | |
| 189 | DRF_SIZE = DRF_END - DRF_OFS, | |
| 190 | ASR_SIZE = ASR_END - ASR_OFS, | |
| 191 | PR_SIZE = PR_END - PR_OFS, | |
| 192 | HPR_SIZE = HPR_END - HPR_OFS, | |
| 193 | FRF_SIZE = FRF_END - FRF_OFS, | |
| 194 | SIM_SIZE = SIM_END - SIM_OFS | |
| 195 | }; | |
| 196 | ||
| 197 | friend Index operator+( Index i, int j) { return Index(int(i)+j); } | |
| 198 | ||
| 199 | static bool is_irf( Index i ) { return (IRF_OFS <= i) && (i < IRF_END); } | |
| 200 | static bool is_drf( Index i ) { return (DRF_OFS <= i) && (i < DRF_END); } | |
| 201 | static bool is_asr( Index i ) { return (ASR_OFS <= i) && (i < ASR_END); } | |
| 202 | static bool is_pr( Index i ) { return ( PR_OFS <= i) && (i < PR_END); } | |
| 203 | static bool is_hpr( Index i ) { return (HPR_OFS <= i) && (i < HPR_END); } | |
| 204 | static bool is_sim( Index i ) { return (SIM_OFS <= i) && (i < SIM_END); } | |
| 205 | ||
| 206 | static bool is_frf( Index i ) { return (FRF_OFS <= i) && (i < FRF_END); } | |
| 207 | ||
| 208 | static const char* irf_name[IRF_SIZE]; | |
| 209 | static const char* drf_name[DRF_SIZE]; | |
| 210 | static const char* asr_name[ASR_SIZE]; | |
| 211 | static const char* pr_name[ PR_SIZE]; | |
| 212 | static const char* hpr_name[HPR_SIZE]; | |
| 213 | static const char* sim_name[SIM_SIZE]; | |
| 214 | ||
| 215 | static const char* frf_name[FRF_SIZE]; | |
| 216 | ||
| 217 | static const char* get_name( Index ); | |
| 218 | }; | |
| 219 | ||
| 220 | #endif |