sam-t2/sam/cpus/vonk/ss/lib/cpu/src/SS_Registers.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: SS_Registers.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
#ifndef __SS_Registers_h__
#define __SS_Registers_h__

class SS_Registers
{
  public:
    enum Error
    {
      OK,
      NOT_AVAILABLE,
      VALUE_OUT_OF_RANGE        // set tl, gl, cwp can return this
    };

    enum Index
    {
      INDEX_BEGIN = 0,

      // %g[0,..,7], %o[0,..,7], %l[0,..,7], %i[0,..,7]

      IRF_OFS = INDEX_BEGIN,
      G0 = IRF_OFS,
          G1, G2, G3, G4, G5, G6, G7,
      O0, O1, O2, O3, O4, O5, O6, O7,
      L0, L1, L2, L3, L4, L5, L6, L7,
      I0, I1, I2, I3, I4, I5, I6, I7,
      IRF_END,

      // %d[0,2,..,62]

      DRF_OFS = IRF_END,
      D0 = DRF_OFS,
           D2,  D4,  D6,  D8,  D10, D12, D14,
      D16, D18, D20, D22, D24, D26, D28, D30,
      D32, D34, D36, D38, D40, D42, D44, D46,
      D48, D50, D52, D54, D56, D58, D60, D62,
      DRF_END,

      // %asr[0,..,31]

      ASR_OFS = DRF_END,
      ASR0 = ASR_OFS,
             ASR1,  ASR2,  ASR3,  ASR4,  ASR5,  ASR6,  ASR7,
      ASR8,  ASR9,  ASR10, ASR11, ASR12, ASR13, ASR14, ASR15,
      ASR16, ASR17, ASR18, ASR19, ASR20, ASR21, ASR22, ASR23,
      ASR24, ASR25, ASR26, ASR27, ASR28, ASR29, ASR30, ASR31,
      ASR_END,
      //
      // %pr[0,..,31]

      PR_OFS = ASR_END,
      PR0 = PR_OFS,
            PR1,  PR2,  PR3,  PR4,  PR5,  PR6,  PR7,
      PR8,  PR9,  PR10, PR11, PR12, PR13, PR14, PR15,
      PR16, PR17, PR18, PR19, PR20, PR21, PR22, PR23,
      PR24, PR25, PR26, PR27, PR28, PR29, PR30, PR31,
      PR_END,

      // %hpr[0,..,31]

      HPR_OFS = PR_END,
      HPR0 = HPR_OFS,
             HPR1,  HPR2,  HPR3,  HPR4,  HPR5,  HPR6,  HPR7,
      HPR8,  HPR9,  HPR10, HPR11, HPR12, HPR13, HPR14, HPR15,
      HPR16, HPR17, HPR18, HPR19, HPR20, HPR21, HPR22, HPR23,
      HPR24, HPR25, HPR26, HPR27, HPR28, HPR29, HPR30, HPR31,
      HPR_END,

      // %sim[0,..,31] - simulator state (npc, fsr, ...)

      SIM_OFS = HPR_END,
      SIM0 = SIM_OFS,
             SIM1,  SIM2,  SIM3,  SIM4,  SIM5,  SIM6,  SIM7,
      SIM8,  SIM9,  SIM10, SIM11, SIM12, SIM13, SIM14, SIM15,
      SIM16, SIM17, SIM18, SIM19, SIM20, SIM21, SIM22, SIM23,
      SIM24, SIM25, SIM26, SIM27, SIM28, SIM29, SIM30, SIM31,
      SIM_END,

      INDEX_END = SIM_END,

      ALIAS_BEGIN = SIM_END,

      // %f[0,..,63]

      FRF_OFS = SIM_END,
      F0 = FRF_OFS,
           F1,  F2,  F3,  F4,  F5,  F6,  F7,
      F8,  F9,  F10, F11, F12, F13, F14, F15,
      F16, F17, F18, F19, F20, F21, F22, F23,
      F24, F25, F26, F27, F28, F29, F30, F31,
      F32, F33, F34, F35, F36, F37, F38, F39,
      F40, F41, F42, F43, F44, F45, F46, F47,
      F48, F49, F50, F51, F52, F53, F54, F55,
      F56, F57, F58, F59, F60, F61, F62, F63,

      FRF_END,
      ALIAS_END = FRF_END,

      // REG_ is the prefix for the product specific registers that we
      // want to enumerate and that don't fall in the above given ranges
      // or ASR, PR, HRP, SIM. The enumeration starts at a nice offset
      // from ALIAS_END to leave us room to grow.

      REG_OFS = ALIAS_END + 1024,

      // Aliases

      ASR_Y             = ASR0,
      ASR_CCR           = ASR2,
      ASR_ASI           = ASR3,
      ASR_TICK          = ASR4,
      ASR_PC            = ASR5,
      ASR_FPRS          = ASR6,
      ASR_PCR           = ASR16,
      ASR_PIC           = ASR17,
      ASR_GSR           = ASR19,
      ASR_SOFTINT_SET   = ASR20,
      ASR_SOFTINT_CLR   = ASR21,
      ASR_SOFTINT       = ASR22,
      ASR_TICK_CMPR     = ASR23,
      ASR_STICK         = ASR24,
      ASR_STICK_CMPR    = ASR25,
      ASR_CPS           = ASR28,

      PR_TPC            = PR0,
      PR_TNPC           = PR1,
      PR_TSTATE         = PR2,
      PR_TT             = PR3,
      PR_TICK           = PR4,
      PR_TBA            = PR5,
      PR_PSTATE         = PR6,
      PR_TL             = PR7,
      PR_PIL            = PR8,
      PR_CWP            = PR9,
      PR_CANSAVE        = PR10,
      PR_CANRESTORE     = PR11,
      PR_CLEANWIN       = PR12,
      PR_OTHERWIN       = PR13,
      PR_WSTATE         = PR14,
      PR_GL             = PR16,

      HPR_HPSTATE       = HPR0,
      HPR_HTSTATE       = HPR1,
      HPR_HINTP         = HPR3,
      HPR_HTBA          = HPR5,
      HPR_HVER          = HPR6,
      HPR_HSTICK_CMPR   = HPR31,

      SIM_NPC           = SIM0,
      SIM_FSR           = SIM1,
      SIM_STRAND_ID     = SIM2,
      SIM_MAX_WP        = SIM3,
      SIM_MAX_TL        = SIM4,
      SIM_MAX_PTL       = SIM5,
      SIM_MAX_GL        = SIM6,
      SIM_MAX_PGL       = SIM7,
      SIM_PA_BITS       = SIM8,
      SIM_VA_BITS       = SIM9,
      SIM_RSTV_ADDR     = SIM10,
      SIM_STATE         = SIM11,
      SIM_INST_COUNT    = SIM12,
      SIM_FAILPC        = SIM13
    };

    enum Sizes
    {
      IRF_SIZE = IRF_END - IRF_OFS,
      DRF_SIZE = DRF_END - DRF_OFS,
      ASR_SIZE = ASR_END - ASR_OFS,
       PR_SIZE =  PR_END -  PR_OFS,
      HPR_SIZE = HPR_END - HPR_OFS,
      FRF_SIZE = FRF_END - FRF_OFS,
      SIM_SIZE = SIM_END - SIM_OFS
    };

    friend Index operator+( Index i, int j)     { return Index(int(i)+j); }

    static bool is_irf( Index i )       { return (IRF_OFS <= i) && (i < IRF_END); }
    static bool is_drf( Index i )       { return (DRF_OFS <= i) && (i < DRF_END); }
    static bool is_asr( Index i )       { return (ASR_OFS <= i) && (i < ASR_END); }
    static bool is_pr(  Index i )       { return ( PR_OFS <= i) && (i <  PR_END); }
    static bool is_hpr( Index i )       { return (HPR_OFS <= i) && (i < HPR_END); }
    static bool is_sim( Index i )       { return (SIM_OFS <= i) && (i < SIM_END); }

    static bool is_frf( Index i )       { return (FRF_OFS <= i) && (i < FRF_END); }

    static const char* irf_name[IRF_SIZE];
    static const char* drf_name[DRF_SIZE];
    static const char* asr_name[ASR_SIZE];
    static const char*  pr_name[ PR_SIZE];
    static const char* hpr_name[HPR_SIZE];
    static const char* sim_name[SIM_SIZE];

    static const char* frf_name[FRF_SIZE];

    static const char* get_name( Index );
};

#endif