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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: pci.h | |
5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
7 | * | |
8 | * The above named program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public | |
10 | * License version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * The above named program is distributed in the hope that it will be | |
13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public | |
18 | * License along with this work; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
20 | * | |
21 | * ========== Copyright Header End ============================================ | |
22 | */ | |
23 | #ifndef _PCI_NEW_INTERFACE_H | |
24 | #define _PCI_NEW_INTERFACE_H | |
25 | ||
26 | #include <sys/int_types.h> | |
27 | #include <sys/types.h> | |
28 | #include <sys/pci.h> //defines the pci specific constants | |
29 | //and structure definitions | |
30 | #include <stdio.h> | |
31 | #include <assert.h> | |
32 | #include "types.h" | |
33 | #include "mmi.h" | |
34 | #include "module.h" | |
35 | ||
36 | enum confHeaderType {pciHeader0, pciHeader1, pciHeaderNull}; | |
37 | ||
38 | enum pciXactnStatus { TARGET_RETRY, TARGET_DISCONNECT, TARGET_ABORT, MASTER_ABORT, MASTER_TIMEOUT, PERR, SERR, SUCCESS, SIM_INTERNAL_ERROR}; | |
39 | ||
40 | static const char *pci_space_names[] = {"PCI_CFG", "PCI_IO", "PCI_MEM32", "PCI_MEM64"}; | |
41 | ||
42 | // PCI address spaces | |
43 | enum pci_space_t {PCI_CFG, PCI_IO, PCI_MEM32, PCI_MEM64, PCI_NSPACES}; | |
44 | ||
45 | class pciBusIf { | |
46 | public: | |
47 | ||
48 | // configuration related functions | |
49 | virtual bool busif_add_device(const char *devname, uint8_t device, uint8_t function)=0; | |
50 | virtual bool busif_delete_device(const char *devname)=0; | |
51 | virtual bool busif_map(const char *devname, pci_space_t, uint64_t base, uint64_t size)=0; | |
52 | virtual bool busif_unmap(const char *devname, pci_space_t, uint64_t base)=0; | |
53 | //virtual int busif_add_interrupt(int device, int dev_type, int slot_irl[])=0; | |
54 | virtual int busif_add_interrupt(int device, int dev_type, int slot_irl[], bool isMulti=false)=0; | |
55 | virtual int busif_free_interrupt(int device)=0; | |
56 | virtual bool busif_interrupt_in(bool set, int dev_number, int line, SAM_DeviceId *samId = 0)=0; | |
57 | virtual uint64_t busif_get_lowest_base(pci_space_t, uint64_t sz); | |
58 | // for supporting fakeprom devices. return the | |
59 | // lowest available aligned base address in a PCI space | |
60 | // for size 'sz' | |
61 | virtual int busif_get_busno() = 0; | |
62 | // get bus number of this bus. The bus number is the secondary | |
63 | // bus number for this bus on the upstream bridge. | |
64 | ||
65 | // functions that may be called when a device is a PCI master | |
66 | // device implementations that derive from genericPciDev cannot | |
67 | // call these functions directly. they must call pciMasterIf functions. | |
68 | virtual pciXactnStatus busif_dma(bool wr, uint64_t vaddr, void *data, long count, SAM_DeviceId * samId = 0)=0; | |
69 | virtual pciXactnStatus busif_special_cycle(uint16_t mssg, uint16_t data); | |
70 | virtual pciXactnStatus busif_intr_ack(uint64_t * data); | |
71 | virtual pciXactnStatus busif_access_w_size(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t size, SAM_DeviceId *samId = 0) = 0; | |
72 | virtual pciXactnStatus busif_access_w_byte_enables(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t byte_enable,SAM_DeviceId * samId = 0) = 0; | |
73 | }; | |
74 | ||
75 | // interface exported to the pci bus module by generic pci_dev class | |
76 | // the pci bus can only access these functions | |
77 | class genericPciDevIf { | |
78 | public: | |
79 | virtual const char *devif_getBusName()=0; | |
80 | virtual int devif_getDevice()=0; | |
81 | virtual int devif_getFunction()=0; | |
82 | virtual mmi_instance_t devif_getInstance()=0; | |
83 | virtual const char *devif_getName()=0; | |
84 | ||
85 | //access contiguous 'size' bytes from offset | |
86 | virtual pciXactnStatus devif_access_w_size(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t size, SAM_DeviceId * samId = 0) = 0; | |
87 | //access bytes based upon the byte_enable signals. a byte lane is meaningful if the corresping enable is 1. | |
88 | //byte enables if used must be set by the bridge/master | |
89 | virtual pciXactnStatus devif_access_w_byte_enable(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t byte_enable = 0xff, SAM_DeviceId * samId = 0) = 0; | |
90 | virtual pciXactnStatus devif_special_cycle(uint16_t mssg, uint16_t data) = 0; | |
91 | virtual pciXactnStatus devif_intr_ack(uint64_t * data) = 0; | |
92 | }; | |
93 | ||
94 | // functions that may be called when a device is a PCI target. | |
95 | // these functions are to be implemented by the device specific derived | |
96 | // class. The genericPciDev class will call these functions as a result of calls from | |
97 | // PciBus to provide device specific services. If a particular function is not | |
98 | // implemented (overridden) then its assumed the device does not implement the | |
99 | // function and error flags are set correspondingly. | |
100 | class pciTargetIf{ | |
101 | public: | |
102 | virtual pciXactnStatus pciTarget_mem32access(uint64_t offset, bool wr,uint64_t * buf, uint8_t size) = 0; | |
103 | virtual pciXactnStatus pciTarget_mem64access(uint64_t offset, bool wr,uint64_t * buf, uint8_t size) = 0; | |
104 | virtual pciXactnStatus pciTarget_ioaccess(uint64_t offset, bool wr,uint64_t * buf, uint8_t size) = 0; | |
105 | virtual pciXactnStatus pciTarget_special_cycle(uint16_t mssg, uint16_t data) = 0; | |
106 | virtual pciXactnStatus pciTarget_intr_ack(uint64_t *data) = 0; | |
107 | // the interrupt controller if present should load the | |
108 | // vector into the buffer. All other devices must ignore | |
109 | // the call (ie should not implement the function). | |
110 | ||
111 | }; | |
112 | ||
113 | /* | |
114 | proposed pciTargetIf to be implemented at some point of time. dmaread/write should just be mem | |
115 | space r/w with data larger than 64 bits and data pointer being a byte array. | |
116 | ||
117 | pciXactnStatus devif_memread(uint64_t addr, uint64_t * data, uint8_t size, addr_mode =SAC); | |
118 | pciXactnStatus devif_memwrite(uint64_t addr, uint64_t * data, uint8_t size, addr_mode =SAC); | |
119 | pciXactnStatus devif_confread(uint64_t offset, uint64_t* data, uint8_t size); | |
120 | pciXactnStatus devif_confwrite(uint64_t offset, uint64_t* data, uint8_t size); | |
121 | pciXactnStatus devif_ioread(uint64_t offset, uint64_t* data, uint8_t size); | |
122 | pciXactnStatus devif_iowrite(uint64_t offset, uint64_t* data, uint8_t size); | |
123 | pciXactnStatus devif_dmaread(uint64_t addr, void * data, uint32_t lenght, addr_mode = SAC); | |
124 | pciXactnStatus devif_dmawrite(uint64_t addr, void * data, uint32_t lenght, addr_mode = SAC); | |
125 | pciXactnStatus pciTarget_special_cycle(uint16_t mssg, uint16_t data) = 0; | |
126 | pciXactnStatus pciTarget_intr_ack(uint64_t *data) = 0; | |
127 | ||
128 | */ | |
129 | ||
130 | ||
131 | ||
132 | ||
133 | ||
134 | ||
135 | //these functions can be called by a pci device when it acts as a master on PCI bus. | |
136 | //these services are implemented by genericPciDevice and are routed over the PCI bus. | |
137 | class pciMasterIf{ | |
138 | public: | |
139 | virtual bool pciMaster_set_int(int line, bool raise) = 0; //not exactly a master function..... | |
140 | virtual pciXactnStatus pciMaster_dma(bool wr, uint64_t vaddr, void *data, long count) = 0; | |
141 | virtual pciXactnStatus pciMaster_intr_ack_cycle(uint64_t * data) = 0; | |
142 | virtual pciXactnStatus pciMaster_special_cycle(uint16_t mssg, uint16_t data) = 0; | |
143 | virtual pciXactnStatus pciMaster_bus_access_w_size(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t size) = 0; | |
144 | virtual pciXactnStatus pciMaster_bus_access_w_byte_enable(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t byte_enable = 0xff) = 0; | |
145 | }; | |
146 | ||
147 | //PCI bridge interface | |
148 | class pciBridgeIf:public pciTargetIf{ | |
149 | public: | |
150 | //virtual int busif_add_interrupt(mmi_instance_t busMod,int device,int dev_type, int slot_irl[])=0; | |
151 | virtual int busif_add_interrupt(mmi_instance_t busMod,int device,int dev_type, int slot_irl[],bool isMulti = false)=0; | |
152 | virtual int busif_free_interrupt(mmi_instance_t busMod, int dev_number)=0; | |
153 | virtual int busif_interrupt_in(bool set,mmi_instance_t busMod, int device, int line, SAM_DeviceId *samId = 0) = 0; | |
154 | virtual int busif_dma_out(uint64_t vaddr, void *data, long count, mmi_instance_t caller,uint16_t requesterId, SAM_DeviceId *samId = 0)=0; | |
155 | virtual int busif_dma_in(uint64_t vaddr, void *data, long count, mmi_instance_t caller,uint16_t requesterId, SAM_DeviceId *samId = 0)=0; | |
156 | virtual int busif_get_secondary_busno() = 0; | |
157 | // return bus number for the pci bus on the secondary interface | |
158 | }; | |
159 | ||
160 | ||
161 | //exportable interfaces | |
162 | #define PCI_BRIDGE_INTERFACE "PciBridgeIf" | |
163 | #define PCI_GENERIC_DEV_INTERFACE "genericPciDevIf" | |
164 | #define PCI_BUS_INTERFACE "PciBusIf" | |
165 | ||
166 | #endif | |
167 | ||
168 | ||
169 |