sam-t2/sam/devices/common/include/pci.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: pci.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
#ifndef _PCI_NEW_INTERFACE_H
#define _PCI_NEW_INTERFACE_H

#include <sys/int_types.h>
#include <sys/types.h>
#include <sys/pci.h>            //defines the pci specific constants
                                //and structure definitions
#include <stdio.h>
#include <assert.h>
#include "types.h"
#include "mmi.h"
#include "module.h"

enum confHeaderType {pciHeader0, pciHeader1, pciHeaderNull};

enum pciXactnStatus { TARGET_RETRY, TARGET_DISCONNECT, TARGET_ABORT, MASTER_ABORT, MASTER_TIMEOUT, PERR, SERR, SUCCESS, SIM_INTERNAL_ERROR};

static const char *pci_space_names[] = {"PCI_CFG", "PCI_IO", "PCI_MEM32", "PCI_MEM64"};

// PCI address spaces
enum pci_space_t {PCI_CFG, PCI_IO, PCI_MEM32, PCI_MEM64, PCI_NSPACES};

class pciBusIf {
public:

        // configuration related functions
        virtual bool busif_add_device(const char *devname, uint8_t device, uint8_t function)=0;
        virtual bool busif_delete_device(const char *devname)=0;
        virtual bool busif_map(const char *devname, pci_space_t, uint64_t base, uint64_t size)=0;
        virtual bool busif_unmap(const char *devname, pci_space_t, uint64_t base)=0;
        //virtual int busif_add_interrupt(int device, int dev_type, int slot_irl[])=0;
        virtual int busif_add_interrupt(int device, int dev_type, int slot_irl[], bool isMulti=false)=0;
        virtual int busif_free_interrupt(int device)=0;
        virtual bool busif_interrupt_in(bool set, int dev_number, int line, SAM_DeviceId *samId = 0)=0;
        virtual uint64_t busif_get_lowest_base(pci_space_t, uint64_t sz);
                // for supporting fakeprom devices. return the
                // lowest available aligned base address in a PCI space
                // for size 'sz'
        virtual int busif_get_busno() = 0;
        // get bus number of this bus. The bus number is the secondary
        // bus number for this bus on the upstream bridge.

        // functions that may be called when a device is a PCI master
        // device implementations that derive from genericPciDev cannot
        // call these functions directly. they must call pciMasterIf functions.
        virtual pciXactnStatus busif_dma(bool wr, uint64_t vaddr, void *data, long count, SAM_DeviceId * samId = 0)=0;
        virtual pciXactnStatus busif_special_cycle(uint16_t mssg, uint16_t data);
        virtual pciXactnStatus busif_intr_ack(uint64_t * data);
        virtual pciXactnStatus busif_access_w_size(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t size, SAM_DeviceId *samId = 0) = 0;
        virtual pciXactnStatus busif_access_w_byte_enables(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t byte_enable,SAM_DeviceId * samId = 0) = 0;
};

// interface exported to the pci bus module by generic pci_dev class
// the pci bus can only access these functions
class genericPciDevIf {
public:
        virtual const char *devif_getBusName()=0;
        virtual int devif_getDevice()=0;
        virtual int devif_getFunction()=0;
        virtual mmi_instance_t devif_getInstance()=0;
        virtual const char *devif_getName()=0;

        //access contiguous 'size' bytes from offset
        virtual pciXactnStatus devif_access_w_size(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t size, SAM_DeviceId * samId = 0) = 0;
        //access bytes based upon the byte_enable signals. a byte lane is meaningful if the corresping enable is 1.
        //byte enables if used must be set by the bridge/master
        virtual pciXactnStatus devif_access_w_byte_enable(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t byte_enable = 0xff, SAM_DeviceId * samId = 0) = 0;
        virtual pciXactnStatus devif_special_cycle(uint16_t mssg, uint16_t data) = 0;
        virtual pciXactnStatus devif_intr_ack(uint64_t * data) = 0;
};

// functions that may be called when a device is a PCI target.
// these functions are to be implemented by the device specific derived
// class. The genericPciDev class will call these functions as a result of calls from
// PciBus to provide device specific services. If a particular function is not
// implemented (overridden) then its assumed the device does not implement the
// function and error flags are set correspondingly.
class pciTargetIf{
public:
        virtual pciXactnStatus pciTarget_mem32access(uint64_t offset, bool wr,uint64_t * buf, uint8_t size) = 0;
        virtual pciXactnStatus pciTarget_mem64access(uint64_t offset, bool wr,uint64_t * buf, uint8_t size) = 0;
        virtual pciXactnStatus pciTarget_ioaccess(uint64_t offset, bool wr,uint64_t * buf, uint8_t size) = 0;
        virtual pciXactnStatus pciTarget_special_cycle(uint16_t mssg, uint16_t data) = 0;
        virtual pciXactnStatus pciTarget_intr_ack(uint64_t *data) = 0;
                // the interrupt controller if present should load the
                // vector into the buffer. All other devices must ignore
                // the call (ie should not implement the function).

};

/*
proposed pciTargetIf to be implemented at some point of time. dmaread/write should just be mem
space r/w with data larger than 64 bits and data pointer being a byte array.

pciXactnStatus devif_memread(uint64_t  addr, uint64_t * data, uint8_t size, addr_mode =SAC);
pciXactnStatus devif_memwrite(uint64_t  addr, uint64_t * data, uint8_t size, addr_mode =SAC);
pciXactnStatus devif_confread(uint64_t offset, uint64_t* data, uint8_t size);
pciXactnStatus devif_confwrite(uint64_t offset, uint64_t* data, uint8_t size);
pciXactnStatus devif_ioread(uint64_t offset, uint64_t* data, uint8_t size);
pciXactnStatus devif_iowrite(uint64_t offset, uint64_t* data, uint8_t size);
pciXactnStatus devif_dmaread(uint64_t addr, void * data, uint32_t lenght, addr_mode = SAC);
pciXactnStatus devif_dmawrite(uint64_t addr, void * data, uint32_t lenght, addr_mode = SAC);
pciXactnStatus pciTarget_special_cycle(uint16_t mssg, uint16_t data) = 0;
pciXactnStatus pciTarget_intr_ack(uint64_t *data) = 0;

*/


//these functions can be called by a pci device when it acts as a master on PCI bus.
//these services are implemented by genericPciDevice and are routed over the PCI bus.
class pciMasterIf{
public:
        virtual bool pciMaster_set_int(int line, bool raise) = 0;       //not exactly a master function.....
        virtual pciXactnStatus pciMaster_dma(bool wr, uint64_t vaddr, void *data, long count) = 0;
        virtual pciXactnStatus pciMaster_intr_ack_cycle(uint64_t * data) = 0;
        virtual pciXactnStatus pciMaster_special_cycle(uint16_t mssg, uint16_t data) = 0;
        virtual pciXactnStatus pciMaster_bus_access_w_size(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t size) = 0;
        virtual pciXactnStatus pciMaster_bus_access_w_byte_enable(pci_space_t, uint64_t paddr, uint64_t offset, bool_t wr, uint64_t* buf, uint8_t byte_enable = 0xff) = 0;
};

//PCI bridge interface
class pciBridgeIf:public pciTargetIf{
public:
        //virtual int busif_add_interrupt(mmi_instance_t busMod,int device,int dev_type, int slot_irl[])=0;
        virtual int busif_add_interrupt(mmi_instance_t busMod,int device,int dev_type, int slot_irl[],bool isMulti = false)=0;
        virtual int busif_free_interrupt(mmi_instance_t busMod, int dev_number)=0;
        virtual int busif_interrupt_in(bool set,mmi_instance_t busMod, int device, int line, SAM_DeviceId *samId = 0) = 0;
        virtual int busif_dma_out(uint64_t vaddr, void *data, long count, mmi_instance_t caller,uint16_t requesterId, SAM_DeviceId *samId = 0)=0;
        virtual int busif_dma_in(uint64_t vaddr, void *data, long count, mmi_instance_t caller,uint16_t requesterId, SAM_DeviceId *samId = 0)=0;
        virtual int busif_get_secondary_busno() = 0;
        // return bus number for the pci bus on the secondary interface
};


//exportable interfaces
#define PCI_BRIDGE_INTERFACE            "PciBridgeIf"
#define PCI_GENERIC_DEV_INTERFACE       "genericPciDevIf"
#define PCI_BUS_INTERFACE               "PciBusIf"

#endif