Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / schizo / include / schizo_prop.h
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: schizo_prop.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23#ifndef _SCHIZOPROP_H
24#define _SCHIZOPROP_H
25/*
26 * schizo node:
27 */
28/*
29 * SCHIZO_VERION had been set arbitrarily to 3, but that was incorrect...
30 *
31 * My reference machine archsvr7 has eight schizo all with version# 2,
32 * and it is running Solaris10_update2, so I can't see how 3 is required.
33 * I'm setting it back to 2.
34 */
35#define SCHIZO_VERSION 2
36
37
38
39
40static int schizo_version = SCHIZO_VERSION;
41
42static int schizo_io_safari_portid;
43
44static int three = 3;
45static int two = 2;
46
47/*
48 * pbm nodes:
49 */
50
51#define SCHIZO_PCI_A_CSRBASE_OFFSET 0x600000
52#define SCHIZO_PCI_A_CSRBASE_PADDR SAFARIBASE_PADDR + SCHIZO_PCI_A_CSRBASE_OFFSET
53#define SCHIZO_PCI_B_CSRBASE_OFFSET 0x700000
54#define SCHIZO_PCI_B_CSRBASE_PADDR SAFARIBASE_PADDR + SCHIZO_PCI_B_CSRBASE_OFFSET
55
56typedef struct {
57 u_int lo;
58 u_int hi;
59} sam_pci_bus_range_t;
60
61
62static sam_pci_bus_range_t schizo_pci_a_bus_range = { 0x0, 0x0 };
63static sam_pci_bus_range_t schizo_pci_b_bus_range = { 0x0, 0x0 };
64
65
66struct schizo_pci_ranges{
67 uint32_t child_hi;
68 uint32_t child_mid;
69 uint32_t child_lo;
70 uint32_t parent_hi;
71 uint32_t parent_lo;
72 uint32_t size_hi;
73 uint32_t size_lo;
74};
75
76struct schizo_regs{
77 uint32_t addr_hi;
78 uint32_t addr_lo;
79 uint32_t size_hi;
80 uint32_t size_lo;
81};
82
83static uint32_t schizo_pci_a_interrupts[4];
84static uint32_t schizo_pci_b_interrupts[4];
85
86
87static struct schizo_pci_ranges schizo_pci_b_ranges[3];
88static struct schizo_pci_ranges schizo_pci_a_ranges[3];
89static struct schizo_regs schizo_pci_a_reg[3];
90static struct schizo_regs schizo_pci_b_reg[3];
91
92static property schizo_pci_a_props[] =
93 { { "sam-name", 0,0},
94 { "name", 4, "pci"} ,
95 { "reg", RARRAY(schizo_pci_a_reg)},
96 { "ranges", ARRAY(schizo_pci_a_ranges)},
97 { "device_type", 4, "pci" },
98 { "bus-range", ARRAY(schizo_pci_a_bus_range) },
99 { "#address-cells", ARRAY(three) },
100 { "#size-cells", ARRAY(two) },
101 { "interrupts", ARRAY(schizo_pci_a_interrupts) },
102 { "portid", ARRAY(schizo_io_safari_portid) },
103 { "compatible", ARRAY("pci108e,8001") },
104 { "version#", ARRAY(schizo_version) },
105 { 0,0,0 },
106 };
107
108static struct property schizo_pci_b_props[] =
109 { { "sam-name", 0,0},
110 { "name", 4, "pci" },
111 { "reg", RARRAY(schizo_pci_b_reg)},
112 { "ranges", ARRAY(schizo_pci_b_ranges)},
113 { "device_type", 4, "pci" },
114 { "bus-range", ARRAY(schizo_pci_b_bus_range) },
115 { "#address-cells", ARRAY(three) },
116 { "#size-cells", ARRAY(two) },
117 { "interrupts", ARRAY(schizo_pci_b_interrupts) },
118 { "portid", ARRAY(schizo_io_safari_portid) },
119 { "compatible", ARRAY("pci108e,8001") },
120 { "version#", ARRAY(schizo_version) },
121 { 0,0,0 },
122 };
123
124static caddr_t v_schizo_regs = 0;
125caddr_t v_pci_b_conf_base = 0;
126caddr_t v_pci_a_conf_base = 0;
127#endif