sam-t2/sam/devices/schizo/include/schizo_prop.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: schizo_prop.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
#ifndef _SCHIZOPROP_H
#define _SCHIZOPROP_H
/*
 * schizo node:
 */
/*
 * SCHIZO_VERION had been set arbitrarily to 3, but that was incorrect...
 *
 * My reference machine archsvr7 has eight schizo all with version# 2,
 * and it is running Solaris10_update2, so I can't see how 3 is required.
 * I'm setting it back to 2.
 */
#define SCHIZO_VERSION 2


static int schizo_version = SCHIZO_VERSION;

static int schizo_io_safari_portid;

static int three = 3;
static int two = 2;

/*
 * pbm nodes:
 */

#define SCHIZO_PCI_A_CSRBASE_OFFSET     0x600000
#define SCHIZO_PCI_A_CSRBASE_PADDR      SAFARIBASE_PADDR + SCHIZO_PCI_A_CSRBASE_OFFSET
#define SCHIZO_PCI_B_CSRBASE_OFFSET     0x700000
#define SCHIZO_PCI_B_CSRBASE_PADDR      SAFARIBASE_PADDR + SCHIZO_PCI_B_CSRBASE_OFFSET

typedef struct {
        u_int lo;
        u_int hi;
} sam_pci_bus_range_t;


static sam_pci_bus_range_t schizo_pci_a_bus_range = { 0x0, 0x0 };
static sam_pci_bus_range_t schizo_pci_b_bus_range = { 0x0, 0x0 };


struct schizo_pci_ranges{
        uint32_t child_hi;
        uint32_t child_mid;
        uint32_t child_lo;
        uint32_t parent_hi;
        uint32_t parent_lo;
        uint32_t size_hi;
        uint32_t size_lo;
};

struct schizo_regs{
        uint32_t addr_hi;
        uint32_t addr_lo;
        uint32_t size_hi;
        uint32_t size_lo;
};

static  uint32_t schizo_pci_a_interrupts[4];
static  uint32_t schizo_pci_b_interrupts[4];


static struct schizo_pci_ranges schizo_pci_b_ranges[3];
static struct schizo_pci_ranges schizo_pci_a_ranges[3];
static struct schizo_regs schizo_pci_a_reg[3];
static struct schizo_regs schizo_pci_b_reg[3];

static property schizo_pci_a_props[] =
        {       { "sam-name",           0,0},
                { "name",               4, "pci"} ,
                { "reg",                RARRAY(schizo_pci_a_reg)},
                { "ranges",             ARRAY(schizo_pci_a_ranges)},
                { "device_type",        4, "pci" },
                { "bus-range",          ARRAY(schizo_pci_a_bus_range) },
                { "#address-cells",     ARRAY(three) },
                { "#size-cells",        ARRAY(two) },
                { "interrupts",         ARRAY(schizo_pci_a_interrupts) },
                { "portid",             ARRAY(schizo_io_safari_portid) },
                { "compatible",         ARRAY("pci108e,8001") },
                { "version#",           ARRAY(schizo_version) },
                { 0,0,0 },
        };

static struct property schizo_pci_b_props[] =
        {       { "sam-name",           0,0},
                { "name",               4, "pci" },
                { "reg",                RARRAY(schizo_pci_b_reg)},
                { "ranges",             ARRAY(schizo_pci_b_ranges)},
                { "device_type",        4, "pci" },
                { "bus-range",          ARRAY(schizo_pci_b_bus_range) },
                { "#address-cells",     ARRAY(three) },
                { "#size-cells",        ARRAY(two) },
                { "interrupts",         ARRAY(schizo_pci_b_interrupts) },
                { "portid",             ARRAY(schizo_io_safari_portid) },
                { "compatible",         ARRAY("pci108e,8001") },
                { "version#",           ARRAY(schizo_version) },
                { 0,0,0 },
        };

static caddr_t v_schizo_regs = 0;
caddr_t v_pci_b_conf_base = 0;
caddr_t v_pci_a_conf_base = 0;
#endif