projects / OpenSPARC-T2-SAM / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / schizo / include / schizo_regs.h
CommitLineData
920dae64
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: schizo_regs.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright (C) 1996, Sun Microsystems, Inc.
25 */
26#ifndef _SCHIZO_REGS_H_
27#define _SCHIZO_REGS_H_
28
29#pragma ident "@(#)1.3 03/04/30 schizo_regs.h"
30
31/* schizo register addresses (bottom 32 bits) */
32
33#define UPA_PORT_ID_OFFSET 0x0000 // UPA port ID Register
34#define UPA_CONFIG_OFFSET 0x0008 // UPA configuration Reg
35
36#define IOMMU_CNTRL_OFFSET 0x0200
37#define IOMMU_TSB_BASE_OFFSET 0x0208
38#define IOMMU_FLUSH_PAGE 0x0210
39#define IOMMU_FLUSH_CONTEXT 0x0218
40
41
42#define PCI_BUS_CNTRL_OFFSET 0x2000
43#define PCI_BUS_AFSR_OFFSET 0x2010
44#define PCI_BUS_AFAR_OFFSET 0x2018
45#define PCI_BUS_DIAG_OFFSET 0x2020
46
47#define pci_diag_mask 0x000e
48#define STC_CNTRL_OFFSET 0x2800
49#define STC_PGE_FLUSHI_OFFSET 0x2808
50#define STC_FLUSHS_OFFSET 0x2810
51#define STC_CXT_FLUSHI_OFFSET 0x2818
52
53#define UPA64S_SLOT0_IMR_OFFSET 0x6000
54#define UPA64S_SLOT1_IMR_OFFSET 0x8000
55
56#define PERF_MONITOR_OFFSET 0x0100
57#define PERF_COUNTER_OFFSET 0x0108
58#define IDLE_CHECK_DIAGNOSTICS 0x0110
59
60#define T_C0_COUNT_OFFSET 0x1c00
61#define T_C0_LIMIT_OFFSET 0x1c08
62#define T_C1_COUNT_OFFSET 0x1c10
63#define T_C1_LIMIT_OFFSET 0x1c18
64
65#define TIMER_REGS_START 0x1c00
66#define TIMER_REGS_END 0x1c1f
67
68#define IOMMU_DIAGS_START 0xa400
69#define IOMMU_DIAGS_END 0xa6ff
70
71#define STC_DIAGS_START 0xb000
72#define STC_DIAGS_END 0x17fff
73
74/* The Streaming Cache Registers */
75#define STC_DATA_DIAG_STR 0x0000b000
76#define STC_DATA_DIAG_END 0x0000b7ff
77#define STC_ERROR_DIAG_STR 0x0000b800
78#define STC_ERROR_DIAG_END 0x0000b9ff
79#define STC_PTAG_DIAG_STR 0x0000ba00
80#define STC_PTAG_DIAG_END 0x0000ba7f
81#define STC_LTAG_DIAG_STR 0x0000bb00
82#define STC_LTAG_DIAG_END 0x0000bb7f
83#define STC_CNTX_MTCH_STR 0x00010000
84#define STC_CNTX_MTCH_END 0x00017fff
85
86/* Interrupt Retry Timer Register */
87#define INTR_RETRY_OFFSET 0x1a00
88
89/* PCI Consistent DMA Flush/Sync Register */
90#define PCI_DMA_FLUSH_SYNC_REG 0x1a08
91
92/* Interrupt State Diagnostic Registers */
93#define PCIBUS_ISR_OFFSET 0xa800
94#define OBIO_ISR_OFFSET 0xa808
95
96/* Interrupt Mapping Registers in schizo 64 in total*//* pp 126 */
97#define INTR_MAP_START 0x1000
98#define INTR_MAP_END 0x11f0
99
100/* Interrupt Clear Registers-45 in total *//* pp 127 */
101// should have 64 of them.
102#define CLR_REG_START 0x1400
103//#define CLR_REG_END 0x15b8
104#define CLR_REG_END 0x15f8
105
106#define CIR_OFFSET(off) ((off) >= CLR_REG_START && (off) <= CLR_REG_END)
107#define MAP_OFFSET(off) ((off) >= INTR_MAP_START && (off) <= INTR_MAP_END)
108
109#define MDU_OFFSET(off) (CIR_OFFSET(off) || MAP_OFFSET(off))
110
111/* IOMMU Registers */
112#define PCIBUS_VA_DIAG 0x0000a400
113#define TLB_TAG_CMPR 0x0000a408
114#define LRU_Q_DIAG_STR 0x0000a500
115#define LRU_Q_DIAG_END 0x0000a57f
116#define TLB_TAG_DIAG_STR 0x0000a580
117#define TLB_TAG_DIAG_END 0x0000a5ff
118#define TLB_DATA_DIAG_STR 0x0000a600
119#define TLB_DATA_DIAG_END 0x0000a67f
120
121/*
122 * Offsets of address spaces with psycho.
123 *
124 * Note: These are 32 bit offsets only.
125 */
126
127#define PCI_CONFIG_SPACE_START 0x01000000
128
129#define PCI_BUS_B_CONFIG_SPACE_START 0x01000000
130#define PCI_BUS_B_CONFIG_SPACE_END 0x0100ffff
131
132#define PCI_BUS_A_CONFIG_SPACE_START 0x01010000
133#define PCI_BUS_A_CONFIG_SPACE_END 0x0101ffff
134
135#define PCI_BUS_A_IO_SPACE_START 0x02000000
136#define PCI_BUS_A_IO_SPACE_END 0x0200ffff
137
138#define PCI_BUS_B_IO_SPACE_START 0x02010000
139#define PCI_BUS_B_IO_SPACE_END 0x0201ffff
140
141#define PCI_BUS_A_MEM_SPACE_START 0x00000000
142#define PCI_BUS_A_MEM_SPACE_END 0x7fffffff
143
144#define PCI_BUS_B_MEM_SPACE_START 0x80000000
145#define PCI_BUS_B_MEM_SPACE_END 0xffffffff
146
147#define PCI_BUS_DVMA_START 0x00000000
148#define PCI_BUS_DVMA_END 0x7fffffff
149
150/* PBM configuration headers */
151// epp 175
152#define VENDOR_ID 0x108e
153
154#define CONFIG_VENDOR_ID 0x00
155#define CONFIG_DEVICE_ID 0x02
156#define CONFIG_COMMAND 0x04
157#define CONFIG_STATUS 0x06
158#define CONFIG_REVISION_ID 0x08
159#define CONFIG_PROG_IF_CODE 0x09
160#define CONFIG_SUB_CLASS_CODE 0x0a
161#define CONFIG_BASE_CLASS_CODE 0x0b
162#define CONFIG_LATENCY_TIMER 0x0d
163#define CONFIG_HEADER_TYPE 0x0e
164#define CONFIG_BUS_NUMBER 0x40
165#define CONFIG_SUB_BUS_NUMBER 0x41
166
167/* PBM configuration headers not defined in schizo */
168#define CONFIG_CACHE_LINE_SIZE 0xc
169#define CONFIG_BIST 0xf
170#define CONFIG_BASE_ADDR_00 0x10
171#define CONFIG_BASE_ADDR_01 0x14
172#define CONFIG_BASE_ADDR_02 0x18
173#define CONFIG_BASE_ADDR_03 0x1c
174#define CONFIG_BASE_ADDR_04 0x20
175#define CONFIG_BASE_ADDR_05 0x24
176#define CONFIG_SUB_VENDOR_ID 0x2c
177#define CONFIG_SUB_SYSTEM_ID 0x2e
178#define CONFIG_EXPANSION_ROM 0x30
179#define CONFIG_ROM_ADDR 0x32
180#define CONFIG_CAP_POINTER 0x34
181#define CONFIG_INTERRUPT_LINE 0x3c
182#define CONFIG_INTERRUPT_PIN 0x3d
183#define CONFIG_MIN_GNT 0x3e
184#define CONFIG_MAX_LAT 0x3f
185#define CONFIG_CAP_ID 0x44
186#define CONFIG_NEXTITEM_POINTER 0x45
187#define CONFIG_POWER_CAP 0x46
188#define CONFIG_POWER_CTRL 0x48
189#define CONFIG_POWER_BRIDGE_SUPPORT 0x4a
190#define CONFIG_POWER_DATA 0x4b
191/* For Address range Calculation */
192typedef enum Address_space {
193 reserved,
194 schizo_internals,
195 newlinkbase,
196 newlinkaltbase,
197 upa0base,
198 upa1base,
199 bootbus,
200 pci_bus_a_config,
201 pci_bus_a_mem,
202 pci_bus_b_config,
203 pci_bus_b_mem,
204 memory_controller
205} Address_space;
206
207typedef enum Safari_space {
208 fcode,
209 scsrbase,
210 nlcsrbase,
211 pciacsrbase,
212 pciaiobase,
213 pcibcsrbase,
214 pcibiobase,
215 rsvd
216} Safari_space;
217
218/* To find what the internal addr range is. */
219typedef enum Register_set {
220 mdu_regs,
221 timer_regs,
222 iommu_diags,
223 stc_diags,
224 other
225} Register_set;
226
227/* Register descriptions. */
228
229// schizo control/status register, pp 123 & 148
230const unsigned int SCHIZO_CSR_OFFSET = 0x10000;
231//const uint64_t SCHIZO_CSR_MASK = 0x0;
232
233typedef struct s_schizo_cntrl {
234 uint32_t rsvd1:6; /* 63:58, 0x0, r */
235 uint32_t dtl_mode:24; /* 57:34, 0x777df7, r */
236 uint32_t sto:2; /* 33:32, 0x0, rw, Safari Timeout */
237 uint32_t rsvd3:2; /* 31:30, 0x0, r */
238 uint32_t nid:5; /* 29:25, 0x0, rw, Safari Node id */
239 uint32_t aid:5; /* 24:20, 0x8, r, Agent id */
240 uint32_t rsvd2:5; /* 19:15, 0x0, r */
241 uint32_t lpa_bnd:6;
242 uint32_t lpa_base:6;
243 uint32_t slowsnp:1;
244 uint32_t hbm:1;
245 uint32_t ssm:1;
246} s_schizo_cntrl;
247
248union u_schizo_cntrl {
249 s_schizo_cntrl s;
250 uint64_t l;
251} u_schizo_cntrl;
252
253//FIXME set in init_regs() but never used, pp ???
254typedef struct s_upa_port_id {
255 uint32_t fcode_esc:8; /* value is 0xfc (FCODE for FERR) */
256 uint32_t rsvd1:21; /* reserved r as zero */
257 uint32_t eccnotv:1; /* whether port can generate ecc */
258 uint32_t oneresd:1; /* -r */
259 uint32_t rsvd2:1; /* read as 0 -r */
260 uint32_t rsvd3:1; /* read as 0 -r */
261 uint32_t preq_dq:6; /* size of Q -r */
262 uint32_t preq_rq:4; /* size of Q -r */
263 uint32_t upacap:5; /* upas features -r */
264 uint32_t jedec:16; /* jedec id -r */
265
266} s_upa_port_id_t;
267
268union u_upa_port_id {
269 s_upa_port_id_t s;
270 uint64_t l;
271} u_upa_port_id_t;
272
273// ecc control register, pp 123 & 159
274const unsigned int ECC_CNTL_OFFSET = 0x10020;
275//const uint64_t ECC_CNTL_MASK = 0x0;
276
277typedef struct s_ecc_cntrl {
278 uint32_t ecc_en:1; /* enables ecc checking -rw */
279 uint32_t ue_inten:1; /* enable interrupt gen. -rw */
280 uint32_t ce_inten:1; /* enable interrupt gen. -rw */
281 uint32_t rsvd1:29; /* not used */
282 uint32_t rsvd2:13; /* not used */
283 uint32_t fmt:1;
284 uint32_t fmecc:4;
285 uint32_t fmd:1;
286 uint32_t fdecc:9;
287 uint32_t rsvd3:4;
288} s_ecc_cntrl_t;
289
290union u_ecc_cntrl {
291 s_ecc_cntrl_t s;
292 uint64_t l;
293} u_ecc_cntrl;
294
295// correctable & uncorrectable error asynchronous fault status registers,
296// pp 123 & 160
297const unsigned int UE_AFSR_OFFSET = 0x10030;
298const unsigned int CE_AFSR_OFFSET = 0x10040;
299
300// UE_AFSR & CE_AFSR have the same register layout
301union {
302 // handle it bit-by-bit
303 struct {
304 unsigned p_pio:1;
305 unsigned p_drd:1;
306 unsigned p_dwr:1;
307 unsigned s_pio:1;
308 unsigned s_dma:1;
309 unsigned rsvd1:1;
310 unsigned errpndg:2;
311 unsigned rsvd2:14;
312 unsigned mask:10;
313 unsigned qw_offset:2;
314 unsigned rsvd3:1;
315 unsigned agent_id:5;
316 unsigned partial:1;
317 unsigned owned_in:1;
318 unsigned rsvd4:2;
319 unsigned mtageccsynd:4;
320 unsigned mtag:3;
321 unsigned rsvd5:4;
322 unsigned eccsynd:9;
323 } s;
324 // or just as a 64bit entity
325 uint64_t ll;
326} U_ceue_afsr;
327
328//FIXME should be replaced by S_ceue_afsr
329typedef struct s_ue_afsr {
330 uint32_t p_pio:1; // [63] prim ue caused by pio
331 uint32_t p_drd:1; // [62] prim ue caued by pci bus dmard
332 uint32_t p_dwr:1; // [61] prim ue caued by pci bus dmawr
333 uint32_t s_pio:1; // [60] sec ue caused by pio
334 uint32_t s_dma:1; // [59] sec ue caued by pci bus dma rd and wr
335 uint32_t rsvd:1; // [58]
336 uint32_t rsvd1:10; // [57:48] read as zero
337 uint32_t bytemask:16; // [47:32] 16 bit UPA byte mask of access
338 uint32_t dw_off:3; // [31:29] transfer size (read-only)
339 uint32_t upa_mid:5; // [28:24} upa mid that caused it (read-only)
340 uint32_t blk:1; // [23] was a block read/write?
341 uint32_t rsvd2:23; // [22:00] read as zero
342} s_ue_afsr;
343
344union u_ue_afsr {
345 s_ue_afsr s;
346 uint64_t l;
347} u_ue_afsr;
348
349// correctable & uncorrectable error asynchronous fault address registers,
350// pp 123 & 163
351const unsigned int UE_AFAR_OFFSET = 0x10038;
352const unsigned int CE_AFAR_OFFSET = 0x10048;
353
354// UE_AFAR & CE_AFAR have the same register layout
355union {
356 // bit-by-bit
357 struct {
358 unsigned int rsvd1:20;
359 unsigned int io_mem_cmd:1;
360 unsigned int address_1:11; // the two address fields must be
361 unsigned int address_2:28; // concatenated to be useful.
362 unsigned int rsvd2:4;
363 } s;
364 // or 64bit as a whole
365 uint64_t ll;
366} U_ceue_afar;
367
368//FIXME should be replaced by S_ceue_afar
369typedef struct s_ue_afar {
370 uint32_t rsvd:20; // [63:44] read as zero
371 uint32_t io_mem:1; // [43] I/O or Memory Safari command
372 uint32_t region:4; // [42:39] which region?
373 uint32_t rsvd1:3; // [38:36] read as zero
374 uint32_t ue_pa_h:4; // [35:32] bits of PA
375 uint32_t ue_pa_l:28; // [31:4] bits of PA
376 uint32_t rsvd2:4; // [3:0] read as zero
377} s_ue_afar_t;
378
379union u_ue_afar {
380 s_ue_afar_t s;
381 uint64_t l;
382} u_ue_afar;
383
384//FIXME should be replaced by S_ceue_afsr
385typedef struct s_ce_afsr {
386 uint32_t p_pio:1; // [63] prim ce caused by pio
387 uint32_t p_drd:1; // [62] prim ce caued by pci bus dmard
388 uint32_t p_dwr:1; // [61] prim ce caued by pci bus dmawr
389 uint32_t s_pio:1; // [60] sec ce caused by pio
390 uint32_t s_dma:1; // [59] sec ce caued by pci bus dma rd and wr
391 uint32_t rsvd:1; // [58]
392 uint32_t rsvd1:2; // [57:56] read as zero
393 uint32_t e_syn:8; // [55:48] ce syndrome bits
394 uint32_t bytemask:16; // [47:32] 16 bit UPA byte mask of access
395 uint32_t dw_off:3; // [31:29] transfer size (read-only)
396 uint32_t upa_mid:5; // [28:24} upa mid that caused it (read-only)
397 uint32_t blk:1; // [23] block transaction
398 uint32_t rsvd2:23; // [22:00] read as zero
399} s_ce_afsr;
400
401union u_ce_afsr {
402 s_ce_afsr s;
403 uint64_t l;
404} u_ce_afsr;
405
406//FIXME should be replaced by S_ceue_afar
407typedef struct s_ce_afar {
408 uint32_t rsvd:20; // [63:44] read as zero
409 uint32_t io_mem:1; // [43] I/O or Memory Safari command
410 uint32_t region:4; // [42:39] which region?
411 uint32_t rsvd1:3; // [38:36] read as zero
412 uint32_t ce_pa_h:4; // [35:32] bits of PA
413 uint32_t ce_pa_l:28; // [31:4] bits of PA
414 uint32_t rsvd2:4; // [3:0] read as zero
415} s_ce_afar;
416
417union u_ce_afar {
418 s_ce_afar s;
419 uint64_t l;
420} u_ce_afar;
421
422//FIXME the pci registers are very different to pp 127 & 183-190 ???
423
424typedef struct s_pci_bus_cntrl {
425 uint32_t rsvd1:29; // [63:35] reserved, read as zero
426 uint32_t pci_serr:1; // [34] set when SERR# asserted
427 uint32_t pci_speed:1; // [33] PCI bus speed
428 uint32_t garb_en:1; // [32] global arbitration enable
429 uint32_t rsvd2:18; // [31:14] reserved, read as zero
430 uint32_t bypass:4; // [13:10] per device bypass enable bits
431 uint32_t wakeup_en:1; // [09] power management wakeup enable
432 uint32_t errint_en:1; // [08] PCI error interrupt enable
433 uint32_t rsvd3:2; // [07:06] reserved, read as zero
434 uint32_t arb_scheme:1; // [05] arbitration scheme
435 uint32_t arb_park:1; // [04] arbitration bus parking
436 uint32_t arb_en:4; // [03:00] PCI DMA arbitration enable
437} s_pci_bus_cntrl;
438
439union u_pci_bus_cntrl {
440 s_pci_bus_cntrl s;
441 uint64_t l;
442} u_pci_bus_cntrl;
443
444typedef struct s_pci_bus_afsr {
445 uint32_t p_ma:1; // [63] if primary error is master abort
446 uint32_t p_ta:1; // [62] if primary error is target abort
447 uint32_t p_rtry:1; // [61] if primary error is excessive retries
448 uint32_t p_perr:1; // [60] if primary error is late error
449 uint32_t s_ma:1; // [59] if secondary error is master abort
450 uint32_t s_ta:1; // [58] if secondary error is target abort
451 uint32_t s_rtry:1; // [57] if secondary error is excessive retries
452 uint32_t s_perr:1; // [56] if secondary error is late error
453 uint32_t rsvd1:8; // [55:48] reserved, read as zero
454 uint32_t bytemask:16; // [47:32] bytemask of failed primary transfer
455 uint32_t blk:1; // [31] failure on block transfer
456 uint32_t rsvd2:1; // [30] reserved, read as zero
457 uint32_t upa_mid:5; // [29:25] UPA MID that caused the error
458 uint32_t rsvd3:25; // [24:00] reserved, read as zero
459} s_pci_bus_afsr;
460
461union u_pci_bus_afsr {
462 s_pci_bus_afsr s;
463 uint64_t l;
464} u_pci_bus_afsr;
465
466typedef struct s_pci_bus_afar {
467 uint32_t rsvd:23; // [63:41] reserved, read as zero
468 uint32_t ue_pa_h1:9; // [40:32] upper 9 bits of PA -r
469 uint32_t ue_pa_h2:12; // [31:20] upper 12 bits of PA -r
470 uint32_t ue_pa_l:20; // [19:00] lower 20 bits of PA -r
471} s_pci_bus_afar;
472
473union u_pci_bus_afar {
474 s_pci_bus_afar s;
475 uint64_t l;
476} u_pci_bus_afar;
477
478typedef struct s_pci_bus_diag {
479 uint32_t rsvd1:32;
480 uint32_t rsvd2:25;
481 uint32_t dis_retry:1;
482 uint32_t dis_intsync:1;
483 uint32_t dis_dwsync:1;
484 uint32_t i_pio_a_par:1;
485 uint32_t i_pio_d_par:1;
486 uint32_t i_dma_d_par:1;
487 uint32_t lpbk_en:1;
488} s_pci_bus_diag;
489
490typedef union u_pci_bus_diag {
491 s_pci_bus_diag s;
492 uint64_t l;
493} u_pci_bus_diag;
494
495// configuration header registers:
496
497typedef union u_vendor_id {
498 uint32_t h;
499} u_vendor_id;
500
501typedef union u_device_id_reg {
502 uint16_t h;
503} u_device_id_reg;
504
505typedef union u_revision_id {
506 uint8_t b;
507} u_revision_id;
508
509typedef union u_prog_if_code {
510 uint8_t b;
511
512} u_prog_if_code;
513
514typedef union u_sub_class_code {
515 uint8_t b;
516} u_sub_class_code;
517
518typedef union u_base_class_code {
519 uint8_t b;
520} u_base_class_code;
521
522typedef union u_bus_number {
523 uint8_t b;
524} u_bus_number;
525
526typedef union u_sub_bus_number {
527 uint8_t b;
528} u_sub_bus_number;
529
530/*config header registers not implemented in schizo*/
531typedef union u_cache_line_size {
532 uint8_t b;
533} u_cache_line_size;
534
535typedef union u_BIST {
536 uint8_t b;
537} u_BIST;
538
539typedef union u_base_address {
540 uint8_t b;
541} u_base_address;
542
543typedef union u_expansion_ROM {
544 uint32_t w;
545} u_expansion_ROM;
546
547typedef union u_interrupt_line {
548 uint8_t b;
549} u_interrupt_line;
550
551typedef union u_interrupt_pin {
552 uint8_t b;
553} u_interrupt_pin;
554
555typedef union u_MIN_GNT {
556 uint8_t b;
557} u_MIN_GNT;
558
559typedef union u_MAX_LAT {
560 uint8_t b;
561} u_MAX_LAT;
562
563
564
565typedef struct s_command {
566 uint16_t rsvd:6; // [15:10] reserved
567 uint16_t fast_en:1; // [09] enable fast back to back cycle to diff targets
568 uint16_t serr_en:1; // [08] enable driving of SERR# pin
569 uint16_t wait:1; // [07] enable use of address/data stepping
570 uint16_t per:1; // [06] enable reporting of paritiy errors
571 uint16_t vga:1; // [05] enable vga pallete snooping
572 uint16_t mwi:1; // [04] enable use of memory write & invalidate
573 uint16_t spcl:1; // [03] enable monitoring of special cycles
574 uint16_t mstr:1; // [02] enable bus master ability
575 uint16_t mem:1; // [01] enable response to PCI MEM cycles
576 uint16_t io:1; // [00] enable response to PCI I/O cycles
577} s_command;
578
579typedef union u_command {
580 s_command s;
581 uint16_t h;
582} u_command;
583
584typedef struct s_status_reg {
585 uint16_t dpe:1; // [15] PBM detects parity error
586 uint16_t sse:1; // [14] PBM signalled system error
587 uint16_t rma:1; // [13] PBM recieves master abort
588 uint16_t rta:1; // [12] PBM recieves target abort
589 uint16_t sta:1; // [11] PBM generates target abort
590 uint16_t dvsl:2; // [10:09] timing of DEVSEL#
591 uint16_t dpar:1; // [08] set when parity error occurs
592 uint16_t fastcap:1; // [07] ability to access fast back to back as target
593 uint16_t cap_66:1; // [06] ability to access fast back to back as target
594 uint16_t rsvd:6; // [05:00] reserved
595} s_status_reg;
596
597typedef union u_status_reg {
598 s_status_reg s;
599 uint16_t h;
600} u_status_reg;
601
602typedef struct s_latency_timer {
603 uint8_t lat_tmr_hi:5; // [07:03]
604 uint8_t lat_tmr_lo:3; // [02:00] read-only
605} s_latency_timer;
606
607typedef union u_latency_timer {
608 s_latency_timer s;
609 uint8_t b;
610} u_latency_timer;
611
612typedef struct s_header_type {
613 uint8_t multi_func:1; // [07]
614 uint8_t hdr_type:7; // [06:00]
615} s_header_type;
616
617typedef union u_header_type {
618 s_header_type s;
619 uint8_t b;
620} u_header_type;
621
622
623
624//---------------------------------------------
625typedef struct s_upa_config {
626 uint32_t rsvd1:32; /* not used */
627 uint32_t rsvd2:24; /* not used */
628 uint32_t sciq1:4; /* size of input req q */
629 uint32_t sciq0:4; /* unsed -rw */
630} s_upa_config;
631
632union u_upa_config {
633 s_upa_config s;
634 uint64_t l;
635} u_upa_config;
636
637
638
639typedef struct s_ecc_diag {
640 uint32_t rsvd:24; /* not used */
641 uint32_t syndrome:8; /* syndrom bits of UPA -r */
642} s_ecc_diag;
643
644union u_ecc_diag {
645 s_ecc_diag s;
646 uint32_t w;
647} u_ecc_diag;
648
649
650typedef struct s_sbus_slot_config {
651 uint32_t rsvd1:32; /* reserved, must be zero-rw */
652 uint32_t rsvd2:5; /* reserved, must be zero-rw */
653 uint32_t sega:11; /* top 11 bits of paddr -rw */
654 uint32_t cp:1; /* cacheable bit -rw */
655 uint32_t etm:1; /* enables ext transfer mode-rw */
656 uint32_t pe:1; /* enables SBus Parity checking-rw */
657 uint32_t rsvd:8; /* not used */
658 uint32_t ba64:1; /* supports 64-byte bursts -rw */
659 uint32_t ba32:1; /* supports 32-byte bursts -rw */
660 uint32_t ba16:1; /* supports 16-byte bursts -rw */
661 uint32_t ba8:1; /* supports 8-byte bursts-rw */
662 uint32_t by:1; /* bypass mode enabled -rw */
663} s_sbus_slot_config_t;
664
665union u_sbus_slot_config {
666 s_sbus_slot_config_t s;
667 uint64_t l;
668} u_sbus_slot_config;
669
670typedef struct s_sbus_afar {
671 uint32_t rsvd:24; /* read as zero -r */
672 uint32_t ue_pa_h1:8; /* upper 8 bits of PA -r */
673 uint32_t ue_pa_h2:12; /* upper 12 bits of PA -r */
674 uint32_t ue_pa_l:20; /* lower 20 bits of PA -r */
675} s_sbus_afar_t;
676
677union u_sbus_afar {
678 s_sbus_afar_t s;
679 uint64_t l;
680} u_sbus_afar;
681
682typedef struct s_perf_monitor {
683 uint32_t rsvd1:32; /* read as zero -r */
684 uint32_t rsvd2:16; /* read as zero -r */
685 uint32_t sel1:4; /* select event for counter1 */
686 uint32_t rsvd3:4; /* read as zero -r */
687 uint32_t sel2:4; /* select event for counter2 */
688 uint32_t rsvd4:4; /* read as zero -r */
689} s_perf_monitor_t;
690
691union u_perf_monitor {
692 s_perf_monitor_t s;
693 uint64_t l;
694} u_perf_monitor;
695
696typedef struct s_perf_counter {
697 uint32_t cnt0:32; /* value of event counter 1-r */
698 uint32_t cnt1:32; /* value of event counter 2-r */
699} s_perf_counter_t;
700
701union u_perf_counter {
702 s_perf_counter_t s;
703 uint64_t l;
704} u_perf_counter;
705
706#endif /* SCHIZO_REGS_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.