projects / OpenSPARC-T2-SAM / blob
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / schizo / include / schizo_regs.h
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: schizo_regs.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
* Copyright (C) 1996, Sun Microsystems, Inc.
*/
#ifndef _SCHIZO_REGS_H_
#define _SCHIZO_REGS_H_
#pragma ident "@(#)1.3 03/04/30 schizo_regs.h"
/* schizo register addresses (bottom 32 bits) */
#define UPA_PORT_ID_OFFSET 0x0000 // UPA port ID Register
#define UPA_CONFIG_OFFSET 0x0008 // UPA configuration Reg
#define IOMMU_CNTRL_OFFSET 0x0200
#define IOMMU_TSB_BASE_OFFSET 0x0208
#define IOMMU_FLUSH_PAGE 0x0210
#define IOMMU_FLUSH_CONTEXT 0x0218
#define PCI_BUS_CNTRL_OFFSET 0x2000
#define PCI_BUS_AFSR_OFFSET 0x2010
#define PCI_BUS_AFAR_OFFSET 0x2018
#define PCI_BUS_DIAG_OFFSET 0x2020
#define pci_diag_mask 0x000e
#define STC_CNTRL_OFFSET 0x2800
#define STC_PGE_FLUSHI_OFFSET 0x2808
#define STC_FLUSHS_OFFSET 0x2810
#define STC_CXT_FLUSHI_OFFSET 0x2818
#define UPA64S_SLOT0_IMR_OFFSET 0x6000
#define UPA64S_SLOT1_IMR_OFFSET 0x8000
#define PERF_MONITOR_OFFSET 0x0100
#define PERF_COUNTER_OFFSET 0x0108
#define IDLE_CHECK_DIAGNOSTICS 0x0110
#define T_C0_COUNT_OFFSET 0x1c00
#define T_C0_LIMIT_OFFSET 0x1c08
#define T_C1_COUNT_OFFSET 0x1c10
#define T_C1_LIMIT_OFFSET 0x1c18
#define TIMER_REGS_START 0x1c00
#define TIMER_REGS_END 0x1c1f
#define IOMMU_DIAGS_START 0xa400
#define IOMMU_DIAGS_END 0xa6ff
#define STC_DIAGS_START 0xb000
#define STC_DIAGS_END 0x17fff
/* The Streaming Cache Registers */
#define STC_DATA_DIAG_STR 0x0000b000
#define STC_DATA_DIAG_END 0x0000b7ff
#define STC_ERROR_DIAG_STR 0x0000b800
#define STC_ERROR_DIAG_END 0x0000b9ff
#define STC_PTAG_DIAG_STR 0x0000ba00
#define STC_PTAG_DIAG_END 0x0000ba7f
#define STC_LTAG_DIAG_STR 0x0000bb00
#define STC_LTAG_DIAG_END 0x0000bb7f
#define STC_CNTX_MTCH_STR 0x00010000
#define STC_CNTX_MTCH_END 0x00017fff
/* Interrupt Retry Timer Register */
#define INTR_RETRY_OFFSET 0x1a00
/* PCI Consistent DMA Flush/Sync Register */
#define PCI_DMA_FLUSH_SYNC_REG 0x1a08
/* Interrupt State Diagnostic Registers */
#define PCIBUS_ISR_OFFSET 0xa800
#define OBIO_ISR_OFFSET 0xa808
/* Interrupt Mapping Registers in schizo 64 in total*//* pp 126 */
#define INTR_MAP_START 0x1000
#define INTR_MAP_END 0x11f0
/* Interrupt Clear Registers-45 in total *//* pp 127 */
// should have 64 of them.
#define CLR_REG_START 0x1400
//#define CLR_REG_END 0x15b8
#define CLR_REG_END 0x15f8
#define CIR_OFFSET(off) ((off) >= CLR_REG_START && (off) <= CLR_REG_END)
#define MAP_OFFSET(off) ((off) >= INTR_MAP_START && (off) <= INTR_MAP_END)
#define MDU_OFFSET(off) (CIR_OFFSET(off) || MAP_OFFSET(off))
/* IOMMU Registers */
#define PCIBUS_VA_DIAG 0x0000a400
#define TLB_TAG_CMPR 0x0000a408
#define LRU_Q_DIAG_STR 0x0000a500
#define LRU_Q_DIAG_END 0x0000a57f
#define TLB_TAG_DIAG_STR 0x0000a580
#define TLB_TAG_DIAG_END 0x0000a5ff
#define TLB_DATA_DIAG_STR 0x0000a600
#define TLB_DATA_DIAG_END 0x0000a67f
/*
* Offsets of address spaces with psycho.
*
* Note: These are 32 bit offsets only.
*/
#define PCI_CONFIG_SPACE_START 0x01000000
#define PCI_BUS_B_CONFIG_SPACE_START 0x01000000
#define PCI_BUS_B_CONFIG_SPACE_END 0x0100ffff
#define PCI_BUS_A_CONFIG_SPACE_START 0x01010000
#define PCI_BUS_A_CONFIG_SPACE_END 0x0101ffff
#define PCI_BUS_A_IO_SPACE_START 0x02000000
#define PCI_BUS_A_IO_SPACE_END 0x0200ffff
#define PCI_BUS_B_IO_SPACE_START 0x02010000
#define PCI_BUS_B_IO_SPACE_END 0x0201ffff
#define PCI_BUS_A_MEM_SPACE_START 0x00000000
#define PCI_BUS_A_MEM_SPACE_END 0x7fffffff
#define PCI_BUS_B_MEM_SPACE_START 0x80000000
#define PCI_BUS_B_MEM_SPACE_END 0xffffffff
#define PCI_BUS_DVMA_START 0x00000000
#define PCI_BUS_DVMA_END 0x7fffffff
/* PBM configuration headers */
// epp 175
#define VENDOR_ID 0x108e
#define CONFIG_VENDOR_ID 0x00
#define CONFIG_DEVICE_ID 0x02
#define CONFIG_COMMAND 0x04
#define CONFIG_STATUS 0x06
#define CONFIG_REVISION_ID 0x08
#define CONFIG_PROG_IF_CODE 0x09
#define CONFIG_SUB_CLASS_CODE 0x0a
#define CONFIG_BASE_CLASS_CODE 0x0b
#define CONFIG_LATENCY_TIMER 0x0d
#define CONFIG_HEADER_TYPE 0x0e
#define CONFIG_BUS_NUMBER 0x40
#define CONFIG_SUB_BUS_NUMBER 0x41
/* PBM configuration headers not defined in schizo */
#define CONFIG_CACHE_LINE_SIZE 0xc
#define CONFIG_BIST 0xf
#define CONFIG_BASE_ADDR_00 0x10
#define CONFIG_BASE_ADDR_01 0x14
#define CONFIG_BASE_ADDR_02 0x18
#define CONFIG_BASE_ADDR_03 0x1c
#define CONFIG_BASE_ADDR_04 0x20
#define CONFIG_BASE_ADDR_05 0x24
#define CONFIG_SUB_VENDOR_ID 0x2c
#define CONFIG_SUB_SYSTEM_ID 0x2e
#define CONFIG_EXPANSION_ROM 0x30
#define CONFIG_ROM_ADDR 0x32
#define CONFIG_CAP_POINTER 0x34
#define CONFIG_INTERRUPT_LINE 0x3c
#define CONFIG_INTERRUPT_PIN 0x3d
#define CONFIG_MIN_GNT 0x3e
#define CONFIG_MAX_LAT 0x3f
#define CONFIG_CAP_ID 0x44
#define CONFIG_NEXTITEM_POINTER 0x45
#define CONFIG_POWER_CAP 0x46
#define CONFIG_POWER_CTRL 0x48
#define CONFIG_POWER_BRIDGE_SUPPORT 0x4a
#define CONFIG_POWER_DATA 0x4b
/* For Address range Calculation */
typedef enum Address_space {
reserved,
schizo_internals,
newlinkbase,
newlinkaltbase,
upa0base,
upa1base,
bootbus,
pci_bus_a_config,
pci_bus_a_mem,
pci_bus_b_config,
pci_bus_b_mem,
memory_controller
} Address_space;
typedef enum Safari_space {
fcode,
scsrbase,
nlcsrbase,
pciacsrbase,
pciaiobase,
pcibcsrbase,
pcibiobase,
rsvd
} Safari_space;
/* To find what the internal addr range is. */
typedef enum Register_set {
mdu_regs,
timer_regs,
iommu_diags,
stc_diags,
other
} Register_set;
/* Register descriptions. */
// schizo control/status register, pp 123 & 148
const unsigned int SCHIZO_CSR_OFFSET = 0x10000;
//const uint64_t SCHIZO_CSR_MASK = 0x0;
typedef struct s_schizo_cntrl {
uint32_t rsvd1:6; /* 63:58, 0x0, r */
uint32_t dtl_mode:24; /* 57:34, 0x777df7, r */
uint32_t sto:2; /* 33:32, 0x0, rw, Safari Timeout */
uint32_t rsvd3:2; /* 31:30, 0x0, r */
uint32_t nid:5; /* 29:25, 0x0, rw, Safari Node id */
uint32_t aid:5; /* 24:20, 0x8, r, Agent id */
uint32_t rsvd2:5; /* 19:15, 0x0, r */
uint32_t lpa_bnd:6;
uint32_t lpa_base:6;
uint32_t slowsnp:1;
uint32_t hbm:1;
uint32_t ssm:1;
} s_schizo_cntrl;
union u_schizo_cntrl {
s_schizo_cntrl s;
uint64_t l;
} u_schizo_cntrl;
//FIXME set in init_regs() but never used, pp ???
typedef struct s_upa_port_id {
uint32_t fcode_esc:8; /* value is 0xfc (FCODE for FERR) */
uint32_t rsvd1:21; /* reserved r as zero */
uint32_t eccnotv:1; /* whether port can generate ecc */
uint32_t oneresd:1; /* -r */
uint32_t rsvd2:1; /* read as 0 -r */
uint32_t rsvd3:1; /* read as 0 -r */
uint32_t preq_dq:6; /* size of Q -r */
uint32_t preq_rq:4; /* size of Q -r */
uint32_t upacap:5; /* upas features -r */
uint32_t jedec:16; /* jedec id -r */
} s_upa_port_id_t;
union u_upa_port_id {
s_upa_port_id_t s;
uint64_t l;
} u_upa_port_id_t;
// ecc control register, pp 123 & 159
const unsigned int ECC_CNTL_OFFSET = 0x10020;
//const uint64_t ECC_CNTL_MASK = 0x0;
typedef struct s_ecc_cntrl {
uint32_t ecc_en:1; /* enables ecc checking -rw */
uint32_t ue_inten:1; /* enable interrupt gen. -rw */
uint32_t ce_inten:1; /* enable interrupt gen. -rw */
uint32_t rsvd1:29; /* not used */
uint32_t rsvd2:13; /* not used */
uint32_t fmt:1;
uint32_t fmecc:4;
uint32_t fmd:1;
uint32_t fdecc:9;
uint32_t rsvd3:4;
} s_ecc_cntrl_t;
union u_ecc_cntrl {
s_ecc_cntrl_t s;
uint64_t l;
} u_ecc_cntrl;
// correctable & uncorrectable error asynchronous fault status registers,
// pp 123 & 160
const unsigned int UE_AFSR_OFFSET = 0x10030;
const unsigned int CE_AFSR_OFFSET = 0x10040;
// UE_AFSR & CE_AFSR have the same register layout
union {
// handle it bit-by-bit
struct {
unsigned p_pio:1;
unsigned p_drd:1;
unsigned p_dwr:1;
unsigned s_pio:1;
unsigned s_dma:1;
unsigned rsvd1:1;
unsigned errpndg:2;
unsigned rsvd2:14;
unsigned mask:10;
unsigned qw_offset:2;
unsigned rsvd3:1;
unsigned agent_id:5;
unsigned partial:1;
unsigned owned_in:1;
unsigned rsvd4:2;
unsigned mtageccsynd:4;
unsigned mtag:3;
unsigned rsvd5:4;
unsigned eccsynd:9;
} s;
// or just as a 64bit entity
uint64_t ll;
} U_ceue_afsr;
//FIXME should be replaced by S_ceue_afsr
typedef struct s_ue_afsr {
uint32_t p_pio:1; // [63] prim ue caused by pio
uint32_t p_drd:1; // [62] prim ue caued by pci bus dmard
uint32_t p_dwr:1; // [61] prim ue caued by pci bus dmawr
uint32_t s_pio:1; // [60] sec ue caused by pio
uint32_t s_dma:1; // [59] sec ue caued by pci bus dma rd and wr
uint32_t rsvd:1; // [58]
uint32_t rsvd1:10; // [57:48] read as zero
uint32_t bytemask:16; // [47:32] 16 bit UPA byte mask of access
uint32_t dw_off:3; // [31:29] transfer size (read-only)
uint32_t upa_mid:5; // [28:24} upa mid that caused it (read-only)
uint32_t blk:1; // [23] was a block read/write?
uint32_t rsvd2:23; // [22:00] read as zero
} s_ue_afsr;
union u_ue_afsr {
s_ue_afsr s;
uint64_t l;
} u_ue_afsr;
// correctable & uncorrectable error asynchronous fault address registers,
// pp 123 & 163
const unsigned int UE_AFAR_OFFSET = 0x10038;
const unsigned int CE_AFAR_OFFSET = 0x10048;
// UE_AFAR & CE_AFAR have the same register layout
union {
// bit-by-bit
struct {
unsigned int rsvd1:20;
unsigned int io_mem_cmd:1;
unsigned int address_1:11; // the two address fields must be
unsigned int address_2:28; // concatenated to be useful.
unsigned int rsvd2:4;
} s;
// or 64bit as a whole
uint64_t ll;
} U_ceue_afar;
//FIXME should be replaced by S_ceue_afar
typedef struct s_ue_afar {
uint32_t rsvd:20; // [63:44] read as zero
uint32_t io_mem:1; // [43] I/O or Memory Safari command
uint32_t region:4; // [42:39] which region?
uint32_t rsvd1:3; // [38:36] read as zero
uint32_t ue_pa_h:4; // [35:32] bits of PA
uint32_t ue_pa_l:28; // [31:4] bits of PA
uint32_t rsvd2:4; // [3:0] read as zero
} s_ue_afar_t;
union u_ue_afar {
s_ue_afar_t s;
uint64_t l;
} u_ue_afar;
//FIXME should be replaced by S_ceue_afsr
typedef struct s_ce_afsr {
uint32_t p_pio:1; // [63] prim ce caused by pio
uint32_t p_drd:1; // [62] prim ce caued by pci bus dmard
uint32_t p_dwr:1; // [61] prim ce caued by pci bus dmawr
uint32_t s_pio:1; // [60] sec ce caused by pio
uint32_t s_dma:1; // [59] sec ce caued by pci bus dma rd and wr
uint32_t rsvd:1; // [58]
uint32_t rsvd1:2; // [57:56] read as zero
uint32_t e_syn:8; // [55:48] ce syndrome bits
uint32_t bytemask:16; // [47:32] 16 bit UPA byte mask of access
uint32_t dw_off:3; // [31:29] transfer size (read-only)
uint32_t upa_mid:5; // [28:24} upa mid that caused it (read-only)
uint32_t blk:1; // [23] block transaction
uint32_t rsvd2:23; // [22:00] read as zero
} s_ce_afsr;
union u_ce_afsr {
s_ce_afsr s;
uint64_t l;
} u_ce_afsr;
//FIXME should be replaced by S_ceue_afar
typedef struct s_ce_afar {
uint32_t rsvd:20; // [63:44] read as zero
uint32_t io_mem:1; // [43] I/O or Memory Safari command
uint32_t region:4; // [42:39] which region?
uint32_t rsvd1:3; // [38:36] read as zero
uint32_t ce_pa_h:4; // [35:32] bits of PA
uint32_t ce_pa_l:28; // [31:4] bits of PA
uint32_t rsvd2:4; // [3:0] read as zero
} s_ce_afar;
union u_ce_afar {
s_ce_afar s;
uint64_t l;
} u_ce_afar;
//FIXME the pci registers are very different to pp 127 & 183-190 ???
typedef struct s_pci_bus_cntrl {
uint32_t rsvd1:29; // [63:35] reserved, read as zero
uint32_t pci_serr:1; // [34] set when SERR# asserted
uint32_t pci_speed:1; // [33] PCI bus speed
uint32_t garb_en:1; // [32] global arbitration enable
uint32_t rsvd2:18; // [31:14] reserved, read as zero
uint32_t bypass:4; // [13:10] per device bypass enable bits
uint32_t wakeup_en:1; // [09] power management wakeup enable
uint32_t errint_en:1; // [08] PCI error interrupt enable
uint32_t rsvd3:2; // [07:06] reserved, read as zero
uint32_t arb_scheme:1; // [05] arbitration scheme
uint32_t arb_park:1; // [04] arbitration bus parking
uint32_t arb_en:4; // [03:00] PCI DMA arbitration enable
} s_pci_bus_cntrl;
union u_pci_bus_cntrl {
s_pci_bus_cntrl s;
uint64_t l;
} u_pci_bus_cntrl;
typedef struct s_pci_bus_afsr {
uint32_t p_ma:1; // [63] if primary error is master abort
uint32_t p_ta:1; // [62] if primary error is target abort
uint32_t p_rtry:1; // [61] if primary error is excessive retries
uint32_t p_perr:1; // [60] if primary error is late error
uint32_t s_ma:1; // [59] if secondary error is master abort
uint32_t s_ta:1; // [58] if secondary error is target abort
uint32_t s_rtry:1; // [57] if secondary error is excessive retries
uint32_t s_perr:1; // [56] if secondary error is late error
uint32_t rsvd1:8; // [55:48] reserved, read as zero
uint32_t bytemask:16; // [47:32] bytemask of failed primary transfer
uint32_t blk:1; // [31] failure on block transfer
uint32_t rsvd2:1; // [30] reserved, read as zero
uint32_t upa_mid:5; // [29:25] UPA MID that caused the error
uint32_t rsvd3:25; // [24:00] reserved, read as zero
} s_pci_bus_afsr;
union u_pci_bus_afsr {
s_pci_bus_afsr s;
uint64_t l;
} u_pci_bus_afsr;
typedef struct s_pci_bus_afar {
uint32_t rsvd:23; // [63:41] reserved, read as zero
uint32_t ue_pa_h1:9; // [40:32] upper 9 bits of PA -r
uint32_t ue_pa_h2:12; // [31:20] upper 12 bits of PA -r
uint32_t ue_pa_l:20; // [19:00] lower 20 bits of PA -r
} s_pci_bus_afar;
union u_pci_bus_afar {
s_pci_bus_afar s;
uint64_t l;
} u_pci_bus_afar;
typedef struct s_pci_bus_diag {
uint32_t rsvd1:32;
uint32_t rsvd2:25;
uint32_t dis_retry:1;
uint32_t dis_intsync:1;
uint32_t dis_dwsync:1;
uint32_t i_pio_a_par:1;
uint32_t i_pio_d_par:1;
uint32_t i_dma_d_par:1;
uint32_t lpbk_en:1;
} s_pci_bus_diag;
typedef union u_pci_bus_diag {
s_pci_bus_diag s;
uint64_t l;
} u_pci_bus_diag;
// configuration header registers:
typedef union u_vendor_id {
uint32_t h;
} u_vendor_id;
typedef union u_device_id_reg {
uint16_t h;
} u_device_id_reg;
typedef union u_revision_id {
uint8_t b;
} u_revision_id;
typedef union u_prog_if_code {
uint8_t b;
} u_prog_if_code;
typedef union u_sub_class_code {
uint8_t b;
} u_sub_class_code;
typedef union u_base_class_code {
uint8_t b;
} u_base_class_code;
typedef union u_bus_number {
uint8_t b;
} u_bus_number;
typedef union u_sub_bus_number {
uint8_t b;
} u_sub_bus_number;
/*config header registers not implemented in schizo*/
typedef union u_cache_line_size {
uint8_t b;
} u_cache_line_size;
typedef union u_BIST {
uint8_t b;
} u_BIST;
typedef union u_base_address {
uint8_t b;
} u_base_address;
typedef union u_expansion_ROM {
uint32_t w;
} u_expansion_ROM;
typedef union u_interrupt_line {
uint8_t b;
} u_interrupt_line;
typedef union u_interrupt_pin {
uint8_t b;
} u_interrupt_pin;
typedef union u_MIN_GNT {
uint8_t b;
} u_MIN_GNT;
typedef union u_MAX_LAT {
uint8_t b;
} u_MAX_LAT;
typedef struct s_command {
uint16_t rsvd:6; // [15:10] reserved
uint16_t fast_en:1; // [09] enable fast back to back cycle to diff targets
uint16_t serr_en:1; // [08] enable driving of SERR# pin
uint16_t wait:1; // [07] enable use of address/data stepping
uint16_t per:1; // [06] enable reporting of paritiy errors
uint16_t vga:1; // [05] enable vga pallete snooping
uint16_t mwi:1; // [04] enable use of memory write & invalidate
uint16_t spcl:1; // [03] enable monitoring of special cycles
uint16_t mstr:1; // [02] enable bus master ability
uint16_t mem:1; // [01] enable response to PCI MEM cycles
uint16_t io:1; // [00] enable response to PCI I/O cycles
} s_command;
typedef union u_command {
s_command s;
uint16_t h;
} u_command;
typedef struct s_status_reg {
uint16_t dpe:1; // [15] PBM detects parity error
uint16_t sse:1; // [14] PBM signalled system error
uint16_t rma:1; // [13] PBM recieves master abort
uint16_t rta:1; // [12] PBM recieves target abort
uint16_t sta:1; // [11] PBM generates target abort
uint16_t dvsl:2; // [10:09] timing of DEVSEL#
uint16_t dpar:1; // [08] set when parity error occurs
uint16_t fastcap:1; // [07] ability to access fast back to back as target
uint16_t cap_66:1; // [06] ability to access fast back to back as target
uint16_t rsvd:6; // [05:00] reserved
} s_status_reg;
typedef union u_status_reg {
s_status_reg s;
uint16_t h;
} u_status_reg;
typedef struct s_latency_timer {
uint8_t lat_tmr_hi:5; // [07:03]
uint8_t lat_tmr_lo:3; // [02:00] read-only
} s_latency_timer;
typedef union u_latency_timer {
s_latency_timer s;
uint8_t b;
} u_latency_timer;
typedef struct s_header_type {
uint8_t multi_func:1; // [07]
uint8_t hdr_type:7; // [06:00]
} s_header_type;
typedef union u_header_type {
s_header_type s;
uint8_t b;
} u_header_type;
//---------------------------------------------
typedef struct s_upa_config {
uint32_t rsvd1:32; /* not used */
uint32_t rsvd2:24; /* not used */
uint32_t sciq1:4; /* size of input req q */
uint32_t sciq0:4; /* unsed -rw */
} s_upa_config;
union u_upa_config {
s_upa_config s;
uint64_t l;
} u_upa_config;
typedef struct s_ecc_diag {
uint32_t rsvd:24; /* not used */
uint32_t syndrome:8; /* syndrom bits of UPA -r */
} s_ecc_diag;
union u_ecc_diag {
s_ecc_diag s;
uint32_t w;
} u_ecc_diag;
typedef struct s_sbus_slot_config {
uint32_t rsvd1:32; /* reserved, must be zero-rw */
uint32_t rsvd2:5; /* reserved, must be zero-rw */
uint32_t sega:11; /* top 11 bits of paddr -rw */
uint32_t cp:1; /* cacheable bit -rw */
uint32_t etm:1; /* enables ext transfer mode-rw */
uint32_t pe:1; /* enables SBus Parity checking-rw */
uint32_t rsvd:8; /* not used */
uint32_t ba64:1; /* supports 64-byte bursts -rw */
uint32_t ba32:1; /* supports 32-byte bursts -rw */
uint32_t ba16:1; /* supports 16-byte bursts -rw */
uint32_t ba8:1; /* supports 8-byte bursts-rw */
uint32_t by:1; /* bypass mode enabled -rw */
} s_sbus_slot_config_t;
union u_sbus_slot_config {
s_sbus_slot_config_t s;
uint64_t l;
} u_sbus_slot_config;
typedef struct s_sbus_afar {
uint32_t rsvd:24; /* read as zero -r */
uint32_t ue_pa_h1:8; /* upper 8 bits of PA -r */
uint32_t ue_pa_h2:12; /* upper 12 bits of PA -r */
uint32_t ue_pa_l:20; /* lower 20 bits of PA -r */
} s_sbus_afar_t;
union u_sbus_afar {
s_sbus_afar_t s;
uint64_t l;
} u_sbus_afar;
typedef struct s_perf_monitor {
uint32_t rsvd1:32; /* read as zero -r */
uint32_t rsvd2:16; /* read as zero -r */
uint32_t sel1:4; /* select event for counter1 */
uint32_t rsvd3:4; /* read as zero -r */
uint32_t sel2:4; /* select event for counter2 */
uint32_t rsvd4:4; /* read as zero -r */
} s_perf_monitor_t;
union u_perf_monitor {
s_perf_monitor_t s;
uint64_t l;
} u_perf_monitor;
typedef struct s_perf_counter {
uint32_t cnt0:32; /* value of event counter 1-r */
uint32_t cnt1:32; /* value of event counter 2-r */
} s_perf_counter_t;
union u_perf_counter {
s_perf_counter_t s;
uint64_t l;
} u_perf_counter;
#endif /* SCHIZO_REGS_H */
Full OpenSPARC architecture tarball including simulator, hypervisor, and OBP.