projects / xeon-phi-kernel-module / blame
| Commit | Line | Data |
|---|---|---|
| 800f879a AT |
1 | /* |
| 2 | * Copyright 2010-2017 Intel Corporation. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License, version 2, | |
| 6 | * as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 11 | * General Public License for more details. | |
| 12 | * | |
| 13 | * Disclaimer: The codes contained in these modules may be specific to | |
| 14 | * the Intel Software Development Platform codenamed Knights Ferry, | |
| 15 | * and the Intel product codenamed Knights Corner, and are not backward | |
| 16 | * compatible with other Intel products. Additionally, Intel will NOT | |
| 17 | * support the codes or instruction set in future products. | |
| 18 | * | |
| 19 | * Intel offers no warranty of any kind regarding the code. This code is | |
| 20 | * licensed on an "AS IS" basis and Intel is not obligated to provide | |
| 21 | * any support, assistance, installation, training, or other services | |
| 22 | * of any kind. Intel is also not obligated to provide any updates, | |
| 23 | * enhancements or extensions. Intel specifically disclaims any warranty | |
| 24 | * of merchantability, non-infringement, fitness for any particular | |
| 25 | * purpose, and any other warranty. | |
| 26 | * | |
| 27 | * Further, Intel disclaims all liability of any kind, including but | |
| 28 | * not limited to liability for infringement of any proprietary rights, | |
| 29 | * relating to the use of the code, even if Intel is notified of the | |
| 30 | * possibility of such liability. Except as expressly stated in an Intel | |
| 31 | * license agreement provided with this code and agreed upon with Intel, | |
| 32 | * no license, express or implied, by estoppel or otherwise, to any | |
| 33 | * intellectual property rights is granted herein. | |
| 34 | */ | |
| 35 | ||
| 36 | /* "Raw" register offsets & bit specifications for Intel MIC (KNF) */ | |
| 37 | #ifndef _MIC_SBOXDEFINE_REGISTERS_H_ | |
| 38 | #define _MIC_SBOXDEFINE_REGISTERS_H_ | |
| 39 | ||
| 40 | ||
| 41 | #define SBOX_OC_I2C_ICR 0x00001000 | |
| 42 | #define SBOX_THERMAL_STATUS 0x00001018 | |
| 43 | #define SBOX_THERMAL_INTERRUPT_ENABLE 0x0000101C | |
| 44 | #define SBOX_STATUS_FAN1 0x00001024 | |
| 45 | #define SBOX_STATUS_FAN2 0x00001028 | |
| 46 | #define SBOX_SPEED_OVERRIDE_FAN 0x0000102C | |
| 47 | #define SBOX_BOARD_TEMP1 0x00001030 | |
| 48 | #define SBOX_BOARD_TEMP2 0x00001034 | |
| 49 | #define SBOX_BOARD_VOLTAGE_SENSE 0x00001038 | |
| 50 | #define SBOX_CURRENT_DIE_TEMP0 0x0000103C | |
| 51 | #define SBOX_CURRENT_DIE_TEMP1 0x00001040 | |
| 52 | #define SBOX_CURRENT_DIE_TEMP2 0x00001044 | |
| 53 | #define SBOX_MAX_DIE_TEMP0 0x00001048 | |
| 54 | #define SBOX_MAX_DIE_TEMP1 0x0000104C | |
| 55 | #define SBOX_MAX_DIE_TEMP2 0x00001050 | |
| 56 | #define SBOX_ELAPSED_TIME_LOW 0x00001074 | |
| 57 | #define SBOX_ELAPSED_TIME_HIGH 0x00001078 | |
| 58 | #define SBOX_FAIL_SAFE_OFFSET 0x00002004 | |
| 59 | #define SBOX_CURRENT_CLK_RATIO 0x00003004 | |
| 60 | #define SBOX_SMPT00 0x00003100 | |
| 61 | #define SBOX_SMPT02 0x00003108 | |
| 62 | #define SBOX_RGCR 0x00004010 | |
| 63 | #define SBOX_DSTAT 0x00004014 | |
| 64 | #define SBOX_PCIE_PCI_REVISION_ID_AND_C_0X8 0x00005808 | |
| 65 | #define SBOX_PCIE_BAR_ENABLE 0x00005CD4 | |
| 66 | #define SBOX_SICR0 0x00009004 | |
| 67 | #define SBOX_SICE0 0x0000900C | |
| 68 | #define SBOX_SICC0 0x00009010 | |
| 69 | #define SBOX_SICR1 0x0000901C | |
| 70 | #define SBOX_SICC1 0x00009028 | |
| 71 | #ifdef CONFIG_MK1OM | |
| 72 | #define SBOX_PMU_PERIOD_SEL 0x00001070 | |
| 73 | #define SBOX_THERMAL_STATUS_INTERRUPT 0x0000107C | |
| 74 | #define SBOX_THERMAL_STATUS_2 0x00001080 | |
| 75 | #define SBOX_THERMAL_TEST_2 0x00001084 | |
| 76 | #define SBOX_COREFREQ 0x00004100 | |
| 77 | #define SBOX_COREVOLT 0x00004104 | |
| 78 | #define SBOX_MEMORYFREQ 0x00004108 | |
| 79 | #define SBOX_MEMVOLT 0x0000410C | |
| 80 | //add defines used by drivers that are the same as DOORBELL_INTX | |
| 81 | #define SBOX_SDBIC0 0x0000CC90 | |
| 82 | #define SBOX_SDBIC1 0x0000CC94 | |
| 83 | #define SBOX_SDBIC2 0x0000CC98 | |
| 84 | #define SBOX_SDBIC3 0x0000CC9C | |
| 85 | #else | |
| 86 | #define SBOX_SDBIC0 0x00009030 | |
| 87 | #define SBOX_SDBIC1 0x00009034 | |
| 88 | #define SBOX_SDBIC2 0x00009038 | |
| 89 | #define SBOX_SDBIC3 0x0000903C | |
| 90 | #define SBOX_COREFREQ 0x00004040 | |
| 91 | #define SBOX_COREVOLT 0x00004044 | |
| 92 | #define SBOX_MEMORYFREQ 0x00004048 | |
| 93 | #define SBOX_MEMVOLT 0x0000404C | |
| 94 | #define SBOX_RSC0 0x0000CC10 | |
| 95 | #define SBOX_RSC1 0x0000CC14 | |
| 96 | ||
| 97 | #endif | |
| 98 | #define SBOX_MXAR0 0x00009040 | |
| 99 | #define SBOX_MXAR0_K1OM 0x00009044 | |
| 100 | #define SBOX_MXAR1 0x00009044 | |
| 101 | #define SBOX_MXAR2 0x00009048 | |
| 102 | #define SBOX_MXAR3 0x0000904C | |
| 103 | #define SBOX_MXAR4 0x00009050 | |
| 104 | #define SBOX_MXAR5 0x00009054 | |
| 105 | #define SBOX_MXAR6 0x00009058 | |
| 106 | #define SBOX_MXAR7 0x0000905C | |
| 107 | #define SBOX_MXAR8 0x00009060 | |
| 108 | #define SBOX_MXAR9 0x00009064 | |
| 109 | #define SBOX_MXAR10 0x00009068 | |
| 110 | #define SBOX_MXAR11 0x0000906C | |
| 111 | #define SBOX_MXAR12 0x00009070 | |
| 112 | #define SBOX_MXAR13 0x00009074 | |
| 113 | #define SBOX_MXAR14 0x00009078 | |
| 114 | #define SBOX_MXAR15 0x0000907C | |
| 115 | #define SBOX_MSIXPBACR 0x00009080 | |
| 116 | #define SBOX_MSIXPBACR_K1OM 0x00009084 | |
| 117 | #define SBOX_DCAR_0 0x0000A000 | |
| 118 | #define SBOX_DHPR_0 0x0000A004 | |
| 119 | #define SBOX_DTPR_0 0x0000A008 | |
| 120 | #define SBOX_DAUX_LO_0 0x0000A00C | |
| 121 | #define SBOX_DAUX_HI_0 0x0000A010 | |
| 122 | #define SBOX_DRAR_LO_0 0x0000A014 | |
| 123 | #define SBOX_DRAR_HI_0 0x0000A018 | |
| 124 | #define SBOX_DITR_0 0x0000A01C | |
| 125 | #define SBOX_DSTAT_0 0x0000A020 | |
| 126 | #define SBOX_DSTATWB_LO_0 0x0000A024 | |
| 127 | #define SBOX_DSTATWB_HI_0 0x0000A028 | |
| 128 | #define SBOX_DCHERR_0 0x0000A02C | |
| 129 | #define SBOX_DCHERRMSK_0 0x0000A030 | |
| 130 | #define SBOX_DCAR_1 0x0000A040 | |
| 131 | #define SBOX_DHPR_1 0x0000A044 | |
| 132 | #define SBOX_DTPR_1 0x0000A048 | |
| 133 | #define SBOX_DAUX_LO_1 0x0000A04C | |
| 134 | #define SBOX_DAUX_HI_1 0x0000A050 | |
| 135 | #define SBOX_DRAR_LO_1 0x0000A054 | |
| 136 | #define SBOX_DRAR_HI_1 0x0000A058 | |
| 137 | #define SBOX_DITR_1 0x0000A05C | |
| 138 | #define SBOX_DSTAT_1 0x0000A060 | |
| 139 | #define SBOX_DSTATWB_LO_1 0x0000A064 | |
| 140 | #define SBOX_DSTATWB_HI_1 0x0000A068 | |
| 141 | #define SBOX_DCHERR_1 0x0000A06C | |
| 142 | #define SBOX_DCHERRMSK_1 0x0000A070 | |
| 143 | #define SBOX_DCAR_2 0x0000A080 | |
| 144 | #define SBOX_DHPR_2 0x0000A084 | |
| 145 | #define SBOX_DTPR_2 0x0000A088 | |
| 146 | #define SBOX_DAUX_LO_2 0x0000A08C | |
| 147 | #define SBOX_DAUX_HI_2 0x0000A090 | |
| 148 | #define SBOX_DRAR_LO_2 0x0000A094 | |
| 149 | #define SBOX_DRAR_HI_2 0x0000A098 | |
| 150 | #define SBOX_DITR_2 0x0000A09C | |
| 151 | #define SBOX_DSTAT_2 0x0000A0A0 | |
| 152 | #define SBOX_DSTATWB_LO_2 0x0000A0A4 | |
| 153 | #define SBOX_DSTATWB_HI_2 0x0000A0A8 | |
| 154 | #define SBOX_DCHERR_2 0x0000A0AC | |
| 155 | #define SBOX_DCHERRMSK_2 0x0000A0B0 | |
| 156 | #define SBOX_DCAR_3 0x0000A0C0 | |
| 157 | #define SBOX_DHPR_3 0x0000A0C4 | |
| 158 | #define SBOX_DTPR_3 0x0000A0C8 | |
| 159 | #define SBOX_DAUX_LO_3 0x0000A0CC | |
| 160 | #define SBOX_DAUX_HI_3 0x0000A0D0 | |
| 161 | #define SBOX_DRAR_LO_3 0x0000A0D4 | |
| 162 | #define SBOX_DRAR_HI_3 0x0000A0D8 | |
| 163 | #define SBOX_DITR_3 0x0000A0DC | |
| 164 | #define SBOX_DSTAT_3 0x0000A0E0 | |
| 165 | #define SBOX_DSTATWB_LO_3 0x0000A0E4 | |
| 166 | #define SBOX_DSTATWB_HI_3 0x0000A0E8 | |
| 167 | #define SBOX_DCHERR_3 0x0000A0EC | |
| 168 | #define SBOX_DCHERRMSK_3 0x0000A0F0 | |
| 169 | #define SBOX_DCAR_4 0x0000A100 | |
| 170 | #define SBOX_DHPR_4 0x0000A104 | |
| 171 | #define SBOX_DTPR_4 0x0000A108 | |
| 172 | #define SBOX_DAUX_LO_4 0x0000A10C | |
| 173 | #define SBOX_DAUX_HI_4 0x0000A110 | |
| 174 | #define SBOX_DRAR_LO_4 0x0000A114 | |
| 175 | #define SBOX_DRAR_HI_4 0x0000A118 | |
| 176 | #define SBOX_DITR_4 0x0000A11C | |
| 177 | #define SBOX_DSTAT_4 0x0000A120 | |
| 178 | #define SBOX_DSTATWB_LO_4 0x0000A124 | |
| 179 | #define SBOX_DSTATWB_HI_4 0x0000A128 | |
| 180 | #define SBOX_DCHERR_4 0x0000A12C | |
| 181 | #define SBOX_DCHERRMSK_4 0x0000A130 | |
| 182 | #define SBOX_DCAR_5 0x0000A140 | |
| 183 | #define SBOX_DHPR_5 0x0000A144 | |
| 184 | #define SBOX_DTPR_5 0x0000A148 | |
| 185 | #define SBOX_DAUX_LO_5 0x0000A14C | |
| 186 | #define SBOX_DAUX_HI_5 0x0000A150 | |
| 187 | #define SBOX_DRAR_LO_5 0x0000A154 | |
| 188 | #define SBOX_DRAR_HI_5 0x0000A158 | |
| 189 | #define SBOX_DITR_5 0x0000A15C | |
| 190 | #define SBOX_DSTAT_5 0x0000A160 | |
| 191 | #define SBOX_DSTATWB_LO_5 0x0000A164 | |
| 192 | #define SBOX_DSTATWB_HI_5 0x0000A168 | |
| 193 | #define SBOX_DCHERR_5 0x0000A16C | |
| 194 | #define SBOX_DCHERRMSK_5 0x0000A170 | |
| 195 | #define SBOX_DCAR_6 0x0000A180 | |
| 196 | #define SBOX_DHPR_6 0x0000A184 | |
| 197 | #define SBOX_DTPR_6 0x0000A188 | |
| 198 | #define SBOX_DAUX_LO_6 0x0000A18C | |
| 199 | #define SBOX_DAUX_HI_6 0x0000A190 | |
| 200 | #define SBOX_DRAR_LO_6 0x0000A194 | |
| 201 | #define SBOX_DRAR_HI_6 0x0000A198 | |
| 202 | #define SBOX_DITR_6 0x0000A19C | |
| 203 | #define SBOX_DSTAT_6 0x0000A1A0 | |
| 204 | #define SBOX_DSTATWB_LO_6 0x0000A1A4 | |
| 205 | #define SBOX_DSTATWB_HI_6 0x0000A1A8 | |
| 206 | #define SBOX_DCHERR_6 0x0000A1AC | |
| 207 | #define SBOX_DCHERRMSK_6 0x0000A1B0 | |
| 208 | #define SBOX_DCAR_7 0x0000A1C0 | |
| 209 | #define SBOX_DHPR_7 0x0000A1C4 | |
| 210 | #define SBOX_DTPR_7 0x0000A1C8 | |
| 211 | #define SBOX_DAUX_LO_7 0x0000A1CC | |
| 212 | #define SBOX_DAUX_HI_7 0x0000A1D0 | |
| 213 | #define SBOX_DRAR_LO_7 0x0000A1D4 | |
| 214 | #define SBOX_DRAR_HI_7 0x0000A1D8 | |
| 215 | #define SBOX_DITR_7 0x0000A1DC | |
| 216 | #define SBOX_DSTAT_7 0x0000A1E0 | |
| 217 | #define SBOX_DSTATWB_LO_7 0x0000A1E4 | |
| 218 | #define SBOX_DSTATWB_HI_7 0x0000A1E8 | |
| 219 | #define SBOX_DCHERR_7 0x0000A1EC | |
| 220 | #define SBOX_DCHERRMSK_7 0x0000A1F0 | |
| 221 | #define SBOX_DCR 0x0000A280 | |
| 222 | #define SBOX_APICICR0 0x0000A9D0 | |
| 223 | #define SBOX_APICICR1 0x0000A9D8 | |
| 224 | #define SBOX_APICICR2 0x0000A9E0 | |
| 225 | #define SBOX_APICICR3 0x0000A9E8 | |
| 226 | #define SBOX_APICICR4 0x0000A9F0 | |
| 227 | #define SBOX_APICICR5 0x0000A9F8 | |
| 228 | #define SBOX_APICICR6 0x0000AA00 | |
| 229 | #define SBOX_APICICR7 0x0000AA08 | |
| 230 | #define SBOX_SCRATCH0 0x0000AB20 | |
| 231 | #define SBOX_SCRATCH1 0x0000AB24 | |
| 232 | #define SBOX_SCRATCH2 0x0000AB28 | |
| 233 | #define SBOX_SCRATCH3 0x0000AB2C | |
| 234 | #define SBOX_SCRATCH4 0x0000AB30 | |
| 235 | #define SBOX_SCRATCH5 0x0000AB34 | |
| 236 | #define SBOX_SCRATCH6 0x0000AB38 | |
| 237 | #define SBOX_SCRATCH7 0x0000AB3C | |
| 238 | #define SBOX_SCRATCH8 0x0000AB40 | |
| 239 | #define SBOX_SCRATCH9 0x0000AB44 | |
| 240 | #define SBOX_SCRATCH10 0x0000AB48 | |
| 241 | #define SBOX_SCRATCH11 0x0000AB4C | |
| 242 | #define SBOX_SCRATCH12 0x0000AB50 | |
| 243 | #define SBOX_SCRATCH13 0x0000AB54 | |
| 244 | #define SBOX_SCRATCH14 0x0000AB58 | |
| 245 | #define SBOX_SCRATCH15 0x0000AB5C | |
| 246 | #define SBOX_RDMASR0 0x0000B180 | |
| 247 | #define SBOX_SBQ_FLUSH 0x0000B1A0 // Pseudo-register, not autogen, must add manually | |
| 248 | #define SBOX_TLB_FLUSH 0x0000B1A4 | |
| 249 | #define SBOX_GTT_PHY_BASE 0x0000C118 | |
| 250 | #define SBOX_EMON_CNT0 0x0000CC28 | |
| 251 | #define SBOX_EMON_CNT1 0x0000CC2C | |
| 252 | #define SBOX_EMON_CNT2 0x0000CC30 | |
| 253 | #define SBOX_EMON_CNT3 0x0000CC34 | |
| 254 | ||
| 255 | #endif |