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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: pcx_bfg_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifndef FPGA | |
36 | module pcx_bfg_dp ( | |
37 | pcx_spc_grant_px, | |
38 | pcx_spc_grant_pa, | |
39 | tcu_scan_en, | |
40 | l2clk, | |
41 | scan_in, | |
42 | tcu_pce_ov, | |
43 | ccx_aclk, | |
44 | ccx_bclk, | |
45 | scan_out, | |
46 | ccx_aclk_out, | |
47 | ccx_bclk_out, | |
48 | tcu_pce_ov_out, | |
49 | tcu_scan_en_out); | |
50 | wire pce_ov; | |
51 | wire stop; | |
52 | wire siclk; | |
53 | wire soclk; | |
54 | wire se; | |
55 | wire i_dff_grant_x_scanin; | |
56 | wire i_dff_grant_x_scanout; | |
57 | wire [13:0] pcx_spc_grant_x; | |
58 | wire scan_out_prebuf; | |
59 | ||
60 | ||
61 | output [13:0] pcx_spc_grant_px; | |
62 | ||
63 | input [13:0] pcx_spc_grant_pa; | |
64 | ||
65 | // globals | |
66 | input tcu_scan_en ; | |
67 | input l2clk; | |
68 | input scan_in; | |
69 | input tcu_pce_ov; // scan signals | |
70 | input ccx_aclk; | |
71 | input ccx_bclk; | |
72 | output scan_out; | |
73 | ||
74 | // buffer the high fanout nets | |
75 | output ccx_aclk_out; | |
76 | output ccx_bclk_out; | |
77 | output tcu_pce_ov_out; | |
78 | output tcu_scan_en_out; | |
79 | ||
80 | // scan renames | |
81 | assign pce_ov = tcu_pce_ov_out; | |
82 | assign stop = 1'b0; | |
83 | assign siclk = ccx_aclk_out; | |
84 | assign soclk = ccx_bclk_out; | |
85 | assign se = tcu_scan_en_out ; | |
86 | // end scan | |
87 | ||
88 | pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 buf_hfn ( | |
89 | .din ({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}), | |
90 | .dout ({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out}) | |
91 | ); | |
92 | ||
93 | ||
94 | pcx_bfg_dp_msff_macro__stack_14r__width_14 i_dff_grant_x ( | |
95 | .scan_in(i_dff_grant_x_scanin), | |
96 | .scan_out(i_dff_grant_x_scanout), | |
97 | .clk (l2clk), | |
98 | .din (pcx_spc_grant_pa[13:0]), | |
99 | .dout (pcx_spc_grant_x[13:0]), | |
100 | .en (1'b1), | |
101 | .se(se), | |
102 | .siclk(siclk), | |
103 | .soclk(soclk), | |
104 | .pce_ov(pce_ov), | |
105 | .stop(stop) | |
106 | ); | |
107 | ||
108 | pcx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_14 i_buf_grant_x ( | |
109 | .din (pcx_spc_grant_x[13:0]), | |
110 | .dout (pcx_spc_grant_px[13:0]) | |
111 | ); | |
112 | ||
113 | pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 buf_scanout ( | |
114 | .din (scan_out_prebuf), | |
115 | .dout (scan_out) | |
116 | ); | |
117 | ||
118 | // fixscan start: | |
119 | assign i_dff_grant_x_scanin = scan_in ; | |
120 | assign scan_out_prebuf = i_dff_grant_x_scanout ; | |
121 | // fixscan end: | |
122 | endmodule // pcx_bfc_dp | |
123 | ||
124 | ||
125 | // | |
126 | // buff macro | |
127 | // | |
128 | // | |
129 | ||
130 | ||
131 | ||
132 | ||
133 | ||
134 | module pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 ( | |
135 | din, | |
136 | dout); | |
137 | input [3:0] din; | |
138 | output [3:0] dout; | |
139 | ||
140 | ||
141 | ||
142 | ||
143 | ||
144 | ||
145 | buff #(4) d0_0 ( | |
146 | .in(din[3:0]), | |
147 | .out(dout[3:0]) | |
148 | ); | |
149 | ||
150 | ||
151 | ||
152 | ||
153 | ||
154 | ||
155 | ||
156 | ||
157 | endmodule | |
158 | ||
159 | ||
160 | ||
161 | ||
162 | ||
163 | ||
164 | ||
165 | ||
166 | ||
167 | // any PARAMS parms go into naming of macro | |
168 | ||
169 | module pcx_bfg_dp_msff_macro__stack_14r__width_14 ( | |
170 | din, | |
171 | clk, | |
172 | en, | |
173 | se, | |
174 | scan_in, | |
175 | siclk, | |
176 | soclk, | |
177 | pce_ov, | |
178 | stop, | |
179 | dout, | |
180 | scan_out); | |
181 | wire l1clk; | |
182 | wire siclk_out; | |
183 | wire soclk_out; | |
184 | wire [12:0] so; | |
185 | ||
186 | input [13:0] din; | |
187 | ||
188 | ||
189 | input clk; | |
190 | input en; | |
191 | input se; | |
192 | input scan_in; | |
193 | input siclk; | |
194 | input soclk; | |
195 | input pce_ov; | |
196 | input stop; | |
197 | ||
198 | ||
199 | ||
200 | output [13:0] dout; | |
201 | ||
202 | ||
203 | output scan_out; | |
204 | ||
205 | ||
206 | ||
207 | ||
208 | cl_dp1_l1hdr_8x c0_0 ( | |
209 | .l2clk(clk), | |
210 | .pce(en), | |
211 | .aclk(siclk), | |
212 | .bclk(soclk), | |
213 | .l1clk(l1clk), | |
214 | .se(se), | |
215 | .pce_ov(pce_ov), | |
216 | .stop(stop), | |
217 | .siclk_out(siclk_out), | |
218 | .soclk_out(soclk_out) | |
219 | ); | |
220 | dff #(14) d0_0 ( | |
221 | .l1clk(l1clk), | |
222 | .siclk(siclk_out), | |
223 | .soclk(soclk_out), | |
224 | .d(din[13:0]), | |
225 | .si({scan_in,so[12:0]}), | |
226 | .so({so[12:0],scan_out}), | |
227 | .q(dout[13:0]) | |
228 | ); | |
229 | ||
230 | ||
231 | ||
232 | ||
233 | ||
234 | ||
235 | ||
236 | ||
237 | ||
238 | ||
239 | ||
240 | ||
241 | ||
242 | ||
243 | ||
244 | ||
245 | ||
246 | ||
247 | ||
248 | ||
249 | endmodule | |
250 | ||
251 | ||
252 | ||
253 | ||
254 | ||
255 | ||
256 | ||
257 | ||
258 | ||
259 | // | |
260 | // buff macro | |
261 | // | |
262 | // | |
263 | ||
264 | ||
265 | ||
266 | ||
267 | ||
268 | module pcx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_14 ( | |
269 | din, | |
270 | dout); | |
271 | input [13:0] din; | |
272 | output [13:0] dout; | |
273 | ||
274 | ||
275 | ||
276 | ||
277 | ||
278 | ||
279 | buff #(14) d0_0 ( | |
280 | .in(din[13:0]), | |
281 | .out(dout[13:0]) | |
282 | ); | |
283 | ||
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | ||
290 | ||
291 | endmodule | |
292 | ||
293 | ||
294 | ||
295 | ||
296 | ||
297 | // | |
298 | // buff macro | |
299 | // | |
300 | // | |
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | module pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 ( | |
307 | din, | |
308 | dout); | |
309 | input [0:0] din; | |
310 | output [0:0] dout; | |
311 | ||
312 | ||
313 | ||
314 | ||
315 | ||
316 | ||
317 | buff #(1) d0_0 ( | |
318 | .in(din[0:0]), | |
319 | .out(dout[0:0]) | |
320 | ); | |
321 | ||
322 | ||
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | endmodule | |
330 | ||
331 | `endif // `ifndef FPGA | |
332 | ||
333 | `ifdef FPGA | |
334 | `timescale 1 ns / 100 ps | |
335 | module pcx_bfg_dp(pcx_spc_grant_px, pcx_spc_grant_pa, tcu_scan_en, l2clk, | |
336 | scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out, ccx_aclk_out, | |
337 | ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out); | |
338 | ||
339 | output [13:0] pcx_spc_grant_px; | |
340 | input [13:0] pcx_spc_grant_pa; | |
341 | input tcu_scan_en; | |
342 | input l2clk; | |
343 | input scan_in; | |
344 | input tcu_pce_ov; | |
345 | input ccx_aclk; | |
346 | input ccx_bclk; | |
347 | output scan_out; | |
348 | output ccx_aclk_out; | |
349 | output ccx_bclk_out; | |
350 | output tcu_pce_ov_out; | |
351 | output tcu_scan_en_out; | |
352 | ||
353 | wire pce_ov; | |
354 | wire stop; | |
355 | wire siclk; | |
356 | wire soclk; | |
357 | wire se; | |
358 | wire i_dff_grant_x_scanin; | |
359 | wire i_dff_grant_x_scanout; | |
360 | wire [13:0] pcx_spc_grant_x; | |
361 | wire scan_out_prebuf; | |
362 | ||
363 | assign pce_ov = tcu_pce_ov_out; | |
364 | assign stop = 1'b0; | |
365 | assign siclk = ccx_aclk_out; | |
366 | assign soclk = ccx_bclk_out; | |
367 | assign se = tcu_scan_en_out; | |
368 | assign i_dff_grant_x_scanin = scan_in; | |
369 | assign scan_out_prebuf = i_dff_grant_x_scanout; | |
370 | ||
371 | buff_macro__dbuff_8x__stack_none__width_4 buf_hfn( | |
372 | .din ({ccx_aclk, ccx_bclk, | |
373 | tcu_pce_ov, tcu_scan_en}), | |
374 | .dout ({ccx_aclk_out, ccx_bclk_out, | |
375 | tcu_pce_ov_out, tcu_scan_en_out})); | |
376 | msff_macro__stack_14r__width_14 i_dff_grant_x( | |
377 | .scan_in (i_dff_grant_x_scanin), | |
378 | .scan_out (i_dff_grant_x_scanout), | |
379 | .clk (l2clk), | |
380 | .din (pcx_spc_grant_pa[13:0]), | |
381 | .dout (pcx_spc_grant_x[13:0]), | |
382 | .en (1'b1), | |
383 | .se (se), | |
384 | .siclk (siclk), | |
385 | .soclk (soclk), | |
386 | .pce_ov (pce_ov), | |
387 | .stop (stop)); | |
388 | buff_macro__dbuff_32x__rep_1__stack_none__width_14 i_buf_grant_x( | |
389 | .din (pcx_spc_grant_x[13:0]), | |
390 | .dout (pcx_spc_grant_px[13:0])); | |
391 | buff_macro__dbuff_8x__stack_none__width_1 buf_scanout( | |
392 | .din (scan_out_prebuf), | |
393 | .dout (scan_out)); | |
394 | endmodule | |
395 | ||
396 | module buff_macro__dbuff_32x__rep_1__stack_none__width_14(din, dout); | |
397 | ||
398 | input [13:0] din; | |
399 | output [13:0] dout; | |
400 | ||
401 | buff #(14) d0_0( | |
402 | .in (din[13:0]), | |
403 | .out (dout[13:0])); | |
404 | endmodule | |
405 | ||
406 | module msff_macro__stack_14r__width_14(din, clk, en, se, scan_in, siclk, soclk, | |
407 | pce_ov, stop, dout, scan_out); | |
408 | ||
409 | input [13:0] din; | |
410 | input clk; | |
411 | input en; | |
412 | input se; | |
413 | input scan_in; | |
414 | input siclk; | |
415 | input soclk; | |
416 | input pce_ov; | |
417 | input stop; | |
418 | output [13:0] dout; | |
419 | output scan_out; | |
420 | ||
421 | wire l1clk; | |
422 | wire siclk_out; | |
423 | wire soclk_out; | |
424 | wire [12:0] so; | |
425 | ||
426 | cl_dp1_l1hdr_8x c0_0( | |
427 | .l2clk (clk), | |
428 | .pce (en), | |
429 | .aclk (siclk), | |
430 | .bclk (soclk), | |
431 | .l1clk (l1clk), | |
432 | .se (se), | |
433 | .pce_ov (pce_ov), | |
434 | .stop (stop), | |
435 | .siclk_out (siclk_out), | |
436 | .soclk_out (soclk_out)); | |
437 | dff #(14) d0_0( | |
438 | .l1clk (l1clk), | |
439 | .siclk (siclk_out), | |
440 | .soclk (soclk_out), | |
441 | .d (din[13:0]), | |
442 | .si ({scan_in, so[12:0]}), | |
443 | .so ({so[12:0], scan_out}), | |
444 | .q (dout[13:0])); | |
445 | endmodule | |
446 | ||
447 | ||
448 | `endif // `ifdef FPGA | |
449 |