Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_cru_csr_dmc_dbg_sel_b_reg_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_cru_csr_dmc_dbg_sel_b_reg_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | dmc_dbg_sel_b_reg_csrbus_read_data | |
46 | ); | |
47 | ||
48 | //==================================================================== | |
49 | // Polarity declarations | |
50 | //==================================================================== | |
51 | // synopsys translate_off | |
52 | input omni_ld; // Omni load | |
53 | // vlint flag_input_port_not_connected off | |
54 | input [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH - 1:0] omni_data; | |
55 | // Omni write data | |
56 | // synopsys translate_on | |
57 | // vlint flag_input_port_not_connected on | |
58 | input clk; // Clock signal | |
59 | input rst_l; // Reset signal | |
60 | input w_ld; // SW load | |
61 | // vlint flag_input_port_not_connected off | |
62 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
63 | // vlint flag_input_port_not_connected on | |
64 | output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH-1:0] dmc_dbg_sel_b_reg_csrbus_read_data; | |
65 | // SW read data | |
66 | ||
67 | //==================================================================== | |
68 | // Type declarations | |
69 | //==================================================================== | |
70 | // synopsys translate_off | |
71 | wire omni_ld; // Omni load | |
72 | // vlint flag_dangling_net_within_module off | |
73 | // vlint flag_net_has_no_load off | |
74 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH - 1:0] omni_data; | |
75 | // Omni write data | |
76 | // synopsys translate_on | |
77 | // vlint flag_dangling_net_within_module on | |
78 | // vlint flag_net_has_no_load on | |
79 | wire clk; // Clock signal | |
80 | wire rst_l; // Reset signal | |
81 | wire w_ld; // SW load | |
82 | // vlint flag_dangling_net_within_module off | |
83 | // vlint flag_net_has_no_load off | |
84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
85 | // vlint flag_dangling_net_within_module on | |
86 | // vlint flag_net_has_no_load on | |
87 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH-1:0] dmc_dbg_sel_b_reg_csrbus_read_data; | |
88 | // SW read data | |
89 | ||
90 | //==================================================================== | |
91 | // Logic | |
92 | //==================================================================== | |
93 | ||
94 | //----- Reset values | |
95 | // verilint 531 off | |
96 | wire [3:0] reset_block_sel = 4'h0; | |
97 | wire [2:0] reset_sub_sel = 3'h0; | |
98 | wire [2:0] reset_signal_sel = 3'h0; | |
99 | // verilint 531 on | |
100 | ||
101 | //----- Active high reset wires | |
102 | wire rst_l_active_high = ~rst_l; | |
103 | ||
104 | //==================================================== | |
105 | // Instantiation of flops | |
106 | //==================================================== | |
107 | ||
108 | // bit 0 | |
109 | csr_sw csr_sw_0 | |
110 | ( | |
111 | // synopsys translate_off | |
112 | .omni_ld (omni_ld), | |
113 | .omni_data (omni_data[0]), | |
114 | .omni_rw_alias (1'b1), | |
115 | .omni_rw1c_alias (1'b0), | |
116 | .omni_rw1s_alias (1'b0), | |
117 | // synopsys translate_on | |
118 | .rst (rst_l_active_high), | |
119 | .rst_val (reset_signal_sel[0]), | |
120 | .csr_ld (w_ld), | |
121 | .csr_data (csrbus_wr_data[0]), | |
122 | .rw_alias (1'b1), | |
123 | .rw1c_alias (1'b0), | |
124 | .rw1s_alias (1'b0), | |
125 | .hw_ld (1'b0), | |
126 | .hw_data (1'b0), | |
127 | .cp (clk), | |
128 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[0]) | |
129 | ); | |
130 | ||
131 | // bit 1 | |
132 | csr_sw csr_sw_1 | |
133 | ( | |
134 | // synopsys translate_off | |
135 | .omni_ld (omni_ld), | |
136 | .omni_data (omni_data[1]), | |
137 | .omni_rw_alias (1'b1), | |
138 | .omni_rw1c_alias (1'b0), | |
139 | .omni_rw1s_alias (1'b0), | |
140 | // synopsys translate_on | |
141 | .rst (rst_l_active_high), | |
142 | .rst_val (reset_signal_sel[1]), | |
143 | .csr_ld (w_ld), | |
144 | .csr_data (csrbus_wr_data[1]), | |
145 | .rw_alias (1'b1), | |
146 | .rw1c_alias (1'b0), | |
147 | .rw1s_alias (1'b0), | |
148 | .hw_ld (1'b0), | |
149 | .hw_data (1'b0), | |
150 | .cp (clk), | |
151 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[1]) | |
152 | ); | |
153 | ||
154 | // bit 2 | |
155 | csr_sw csr_sw_2 | |
156 | ( | |
157 | // synopsys translate_off | |
158 | .omni_ld (omni_ld), | |
159 | .omni_data (omni_data[2]), | |
160 | .omni_rw_alias (1'b1), | |
161 | .omni_rw1c_alias (1'b0), | |
162 | .omni_rw1s_alias (1'b0), | |
163 | // synopsys translate_on | |
164 | .rst (rst_l_active_high), | |
165 | .rst_val (reset_signal_sel[2]), | |
166 | .csr_ld (w_ld), | |
167 | .csr_data (csrbus_wr_data[2]), | |
168 | .rw_alias (1'b1), | |
169 | .rw1c_alias (1'b0), | |
170 | .rw1s_alias (1'b0), | |
171 | .hw_ld (1'b0), | |
172 | .hw_data (1'b0), | |
173 | .cp (clk), | |
174 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[2]) | |
175 | ); | |
176 | ||
177 | // bit 3 | |
178 | csr_sw csr_sw_3 | |
179 | ( | |
180 | // synopsys translate_off | |
181 | .omni_ld (omni_ld), | |
182 | .omni_data (omni_data[3]), | |
183 | .omni_rw_alias (1'b1), | |
184 | .omni_rw1c_alias (1'b0), | |
185 | .omni_rw1s_alias (1'b0), | |
186 | // synopsys translate_on | |
187 | .rst (rst_l_active_high), | |
188 | .rst_val (reset_sub_sel[0]), | |
189 | .csr_ld (w_ld), | |
190 | .csr_data (csrbus_wr_data[3]), | |
191 | .rw_alias (1'b1), | |
192 | .rw1c_alias (1'b0), | |
193 | .rw1s_alias (1'b0), | |
194 | .hw_ld (1'b0), | |
195 | .hw_data (1'b0), | |
196 | .cp (clk), | |
197 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[3]) | |
198 | ); | |
199 | ||
200 | // bit 4 | |
201 | csr_sw csr_sw_4 | |
202 | ( | |
203 | // synopsys translate_off | |
204 | .omni_ld (omni_ld), | |
205 | .omni_data (omni_data[4]), | |
206 | .omni_rw_alias (1'b1), | |
207 | .omni_rw1c_alias (1'b0), | |
208 | .omni_rw1s_alias (1'b0), | |
209 | // synopsys translate_on | |
210 | .rst (rst_l_active_high), | |
211 | .rst_val (reset_sub_sel[1]), | |
212 | .csr_ld (w_ld), | |
213 | .csr_data (csrbus_wr_data[4]), | |
214 | .rw_alias (1'b1), | |
215 | .rw1c_alias (1'b0), | |
216 | .rw1s_alias (1'b0), | |
217 | .hw_ld (1'b0), | |
218 | .hw_data (1'b0), | |
219 | .cp (clk), | |
220 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[4]) | |
221 | ); | |
222 | ||
223 | // bit 5 | |
224 | csr_sw csr_sw_5 | |
225 | ( | |
226 | // synopsys translate_off | |
227 | .omni_ld (omni_ld), | |
228 | .omni_data (omni_data[5]), | |
229 | .omni_rw_alias (1'b1), | |
230 | .omni_rw1c_alias (1'b0), | |
231 | .omni_rw1s_alias (1'b0), | |
232 | // synopsys translate_on | |
233 | .rst (rst_l_active_high), | |
234 | .rst_val (reset_sub_sel[2]), | |
235 | .csr_ld (w_ld), | |
236 | .csr_data (csrbus_wr_data[5]), | |
237 | .rw_alias (1'b1), | |
238 | .rw1c_alias (1'b0), | |
239 | .rw1s_alias (1'b0), | |
240 | .hw_ld (1'b0), | |
241 | .hw_data (1'b0), | |
242 | .cp (clk), | |
243 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[5]) | |
244 | ); | |
245 | ||
246 | // bit 6 | |
247 | csr_sw csr_sw_6 | |
248 | ( | |
249 | // synopsys translate_off | |
250 | .omni_ld (omni_ld), | |
251 | .omni_data (omni_data[6]), | |
252 | .omni_rw_alias (1'b1), | |
253 | .omni_rw1c_alias (1'b0), | |
254 | .omni_rw1s_alias (1'b0), | |
255 | // synopsys translate_on | |
256 | .rst (rst_l_active_high), | |
257 | .rst_val (reset_block_sel[0]), | |
258 | .csr_ld (w_ld), | |
259 | .csr_data (csrbus_wr_data[6]), | |
260 | .rw_alias (1'b1), | |
261 | .rw1c_alias (1'b0), | |
262 | .rw1s_alias (1'b0), | |
263 | .hw_ld (1'b0), | |
264 | .hw_data (1'b0), | |
265 | .cp (clk), | |
266 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[6]) | |
267 | ); | |
268 | ||
269 | // bit 7 | |
270 | csr_sw csr_sw_7 | |
271 | ( | |
272 | // synopsys translate_off | |
273 | .omni_ld (omni_ld), | |
274 | .omni_data (omni_data[7]), | |
275 | .omni_rw_alias (1'b1), | |
276 | .omni_rw1c_alias (1'b0), | |
277 | .omni_rw1s_alias (1'b0), | |
278 | // synopsys translate_on | |
279 | .rst (rst_l_active_high), | |
280 | .rst_val (reset_block_sel[1]), | |
281 | .csr_ld (w_ld), | |
282 | .csr_data (csrbus_wr_data[7]), | |
283 | .rw_alias (1'b1), | |
284 | .rw1c_alias (1'b0), | |
285 | .rw1s_alias (1'b0), | |
286 | .hw_ld (1'b0), | |
287 | .hw_data (1'b0), | |
288 | .cp (clk), | |
289 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[7]) | |
290 | ); | |
291 | ||
292 | // bit 8 | |
293 | csr_sw csr_sw_8 | |
294 | ( | |
295 | // synopsys translate_off | |
296 | .omni_ld (omni_ld), | |
297 | .omni_data (omni_data[8]), | |
298 | .omni_rw_alias (1'b1), | |
299 | .omni_rw1c_alias (1'b0), | |
300 | .omni_rw1s_alias (1'b0), | |
301 | // synopsys translate_on | |
302 | .rst (rst_l_active_high), | |
303 | .rst_val (reset_block_sel[2]), | |
304 | .csr_ld (w_ld), | |
305 | .csr_data (csrbus_wr_data[8]), | |
306 | .rw_alias (1'b1), | |
307 | .rw1c_alias (1'b0), | |
308 | .rw1s_alias (1'b0), | |
309 | .hw_ld (1'b0), | |
310 | .hw_data (1'b0), | |
311 | .cp (clk), | |
312 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[8]) | |
313 | ); | |
314 | ||
315 | // bit 9 | |
316 | csr_sw csr_sw_9 | |
317 | ( | |
318 | // synopsys translate_off | |
319 | .omni_ld (omni_ld), | |
320 | .omni_data (omni_data[9]), | |
321 | .omni_rw_alias (1'b1), | |
322 | .omni_rw1c_alias (1'b0), | |
323 | .omni_rw1s_alias (1'b0), | |
324 | // synopsys translate_on | |
325 | .rst (rst_l_active_high), | |
326 | .rst_val (reset_block_sel[3]), | |
327 | .csr_ld (w_ld), | |
328 | .csr_data (csrbus_wr_data[9]), | |
329 | .rw_alias (1'b1), | |
330 | .rw1c_alias (1'b0), | |
331 | .rw1s_alias (1'b0), | |
332 | .hw_ld (1'b0), | |
333 | .hw_data (1'b0), | |
334 | .cp (clk), | |
335 | .q (dmc_dbg_sel_b_reg_csrbus_read_data[9]) | |
336 | ); | |
337 | ||
338 | assign dmc_dbg_sel_b_reg_csrbus_read_data[10] = 1'b0; // bit 10 | |
339 | assign dmc_dbg_sel_b_reg_csrbus_read_data[11] = 1'b0; // bit 11 | |
340 | assign dmc_dbg_sel_b_reg_csrbus_read_data[12] = 1'b0; // bit 12 | |
341 | assign dmc_dbg_sel_b_reg_csrbus_read_data[13] = 1'b0; // bit 13 | |
342 | assign dmc_dbg_sel_b_reg_csrbus_read_data[14] = 1'b0; // bit 14 | |
343 | assign dmc_dbg_sel_b_reg_csrbus_read_data[15] = 1'b0; // bit 15 | |
344 | assign dmc_dbg_sel_b_reg_csrbus_read_data[16] = 1'b0; // bit 16 | |
345 | assign dmc_dbg_sel_b_reg_csrbus_read_data[17] = 1'b0; // bit 17 | |
346 | assign dmc_dbg_sel_b_reg_csrbus_read_data[18] = 1'b0; // bit 18 | |
347 | assign dmc_dbg_sel_b_reg_csrbus_read_data[19] = 1'b0; // bit 19 | |
348 | assign dmc_dbg_sel_b_reg_csrbus_read_data[20] = 1'b0; // bit 20 | |
349 | assign dmc_dbg_sel_b_reg_csrbus_read_data[21] = 1'b0; // bit 21 | |
350 | assign dmc_dbg_sel_b_reg_csrbus_read_data[22] = 1'b0; // bit 22 | |
351 | assign dmc_dbg_sel_b_reg_csrbus_read_data[23] = 1'b0; // bit 23 | |
352 | assign dmc_dbg_sel_b_reg_csrbus_read_data[24] = 1'b0; // bit 24 | |
353 | assign dmc_dbg_sel_b_reg_csrbus_read_data[25] = 1'b0; // bit 25 | |
354 | assign dmc_dbg_sel_b_reg_csrbus_read_data[26] = 1'b0; // bit 26 | |
355 | assign dmc_dbg_sel_b_reg_csrbus_read_data[27] = 1'b0; // bit 27 | |
356 | assign dmc_dbg_sel_b_reg_csrbus_read_data[28] = 1'b0; // bit 28 | |
357 | assign dmc_dbg_sel_b_reg_csrbus_read_data[29] = 1'b0; // bit 29 | |
358 | assign dmc_dbg_sel_b_reg_csrbus_read_data[30] = 1'b0; // bit 30 | |
359 | assign dmc_dbg_sel_b_reg_csrbus_read_data[31] = 1'b0; // bit 31 | |
360 | assign dmc_dbg_sel_b_reg_csrbus_read_data[32] = 1'b0; // bit 32 | |
361 | assign dmc_dbg_sel_b_reg_csrbus_read_data[33] = 1'b0; // bit 33 | |
362 | assign dmc_dbg_sel_b_reg_csrbus_read_data[34] = 1'b0; // bit 34 | |
363 | assign dmc_dbg_sel_b_reg_csrbus_read_data[35] = 1'b0; // bit 35 | |
364 | assign dmc_dbg_sel_b_reg_csrbus_read_data[36] = 1'b0; // bit 36 | |
365 | assign dmc_dbg_sel_b_reg_csrbus_read_data[37] = 1'b0; // bit 37 | |
366 | assign dmc_dbg_sel_b_reg_csrbus_read_data[38] = 1'b0; // bit 38 | |
367 | assign dmc_dbg_sel_b_reg_csrbus_read_data[39] = 1'b0; // bit 39 | |
368 | assign dmc_dbg_sel_b_reg_csrbus_read_data[40] = 1'b0; // bit 40 | |
369 | assign dmc_dbg_sel_b_reg_csrbus_read_data[41] = 1'b0; // bit 41 | |
370 | assign dmc_dbg_sel_b_reg_csrbus_read_data[42] = 1'b0; // bit 42 | |
371 | assign dmc_dbg_sel_b_reg_csrbus_read_data[43] = 1'b0; // bit 43 | |
372 | assign dmc_dbg_sel_b_reg_csrbus_read_data[44] = 1'b0; // bit 44 | |
373 | assign dmc_dbg_sel_b_reg_csrbus_read_data[45] = 1'b0; // bit 45 | |
374 | assign dmc_dbg_sel_b_reg_csrbus_read_data[46] = 1'b0; // bit 46 | |
375 | assign dmc_dbg_sel_b_reg_csrbus_read_data[47] = 1'b0; // bit 47 | |
376 | assign dmc_dbg_sel_b_reg_csrbus_read_data[48] = 1'b0; // bit 48 | |
377 | assign dmc_dbg_sel_b_reg_csrbus_read_data[49] = 1'b0; // bit 49 | |
378 | assign dmc_dbg_sel_b_reg_csrbus_read_data[50] = 1'b0; // bit 50 | |
379 | assign dmc_dbg_sel_b_reg_csrbus_read_data[51] = 1'b0; // bit 51 | |
380 | assign dmc_dbg_sel_b_reg_csrbus_read_data[52] = 1'b0; // bit 52 | |
381 | assign dmc_dbg_sel_b_reg_csrbus_read_data[53] = 1'b0; // bit 53 | |
382 | assign dmc_dbg_sel_b_reg_csrbus_read_data[54] = 1'b0; // bit 54 | |
383 | assign dmc_dbg_sel_b_reg_csrbus_read_data[55] = 1'b0; // bit 55 | |
384 | assign dmc_dbg_sel_b_reg_csrbus_read_data[56] = 1'b0; // bit 56 | |
385 | assign dmc_dbg_sel_b_reg_csrbus_read_data[57] = 1'b0; // bit 57 | |
386 | assign dmc_dbg_sel_b_reg_csrbus_read_data[58] = 1'b0; // bit 58 | |
387 | assign dmc_dbg_sel_b_reg_csrbus_read_data[59] = 1'b0; // bit 59 | |
388 | assign dmc_dbg_sel_b_reg_csrbus_read_data[60] = 1'b0; // bit 60 | |
389 | assign dmc_dbg_sel_b_reg_csrbus_read_data[61] = 1'b0; // bit 61 | |
390 | assign dmc_dbg_sel_b_reg_csrbus_read_data[62] = 1'b0; // bit 62 | |
391 | assign dmc_dbg_sel_b_reg_csrbus_read_data[63] = 1'b0; // bit 63 | |
392 | ||
393 | endmodule // dmu_cru_csr_dmc_dbg_sel_b_reg_entry |