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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_cru_default_grp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_cru_default_grp | |
36 | ( | |
37 | clk, | |
38 | dmc_dbg_sel_a_reg_block_sel_hw_read, | |
39 | dmc_dbg_sel_a_reg_sub_sel_hw_read, | |
40 | dmc_dbg_sel_a_reg_signal_sel_hw_read, | |
41 | dmc_dbg_sel_a_reg_select_pulse, | |
42 | dmc_dbg_sel_b_reg_block_sel_hw_read, | |
43 | dmc_dbg_sel_b_reg_sub_sel_hw_read, | |
44 | dmc_dbg_sel_b_reg_signal_sel_hw_read, | |
45 | dmc_dbg_sel_b_reg_select_pulse, | |
46 | dmc_pcie_cfg_bus_num_hw_read, | |
47 | dmc_pcie_cfg_req_id_hw_read, | |
48 | dmc_pcie_cfg_select_pulse, | |
49 | rst_l, | |
50 | daemon_csrbus_wr_in, | |
51 | daemon_csrbus_wr_data_in, | |
52 | read_data_0_out | |
53 | ); | |
54 | ||
55 | //==================================================== | |
56 | // Polarity declarations | |
57 | //==================================================== | |
58 | input clk; // Clock signal | |
59 | output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_INT_SLC] dmc_dbg_sel_a_reg_block_sel_hw_read; | |
60 | // This signal provides the current value of dmc_dbg_sel_a_reg_block_sel. | |
61 | output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_INT_SLC] dmc_dbg_sel_a_reg_sub_sel_hw_read; | |
62 | // This signal provides the current value of dmc_dbg_sel_a_reg_sub_sel. | |
63 | output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_INT_SLC] dmc_dbg_sel_a_reg_signal_sel_hw_read; | |
64 | // This signal provides the current value of dmc_dbg_sel_a_reg_signal_sel. | |
65 | input dmc_dbg_sel_a_reg_select_pulse; // select | |
66 | output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_INT_SLC] dmc_dbg_sel_b_reg_block_sel_hw_read; | |
67 | // This signal provides the current value of dmc_dbg_sel_b_reg_block_sel. | |
68 | output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_INT_SLC] dmc_dbg_sel_b_reg_sub_sel_hw_read; | |
69 | // This signal provides the current value of dmc_dbg_sel_b_reg_sub_sel. | |
70 | output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_INT_SLC] dmc_dbg_sel_b_reg_signal_sel_hw_read; | |
71 | // This signal provides the current value of dmc_dbg_sel_b_reg_signal_sel. | |
72 | input dmc_dbg_sel_b_reg_select_pulse; // select | |
73 | output [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_INT_SLC] dmc_pcie_cfg_bus_num_hw_read; | |
74 | // This signal provides the current value of dmc_pcie_cfg_bus_num. | |
75 | output [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_INT_SLC] dmc_pcie_cfg_req_id_hw_read; | |
76 | // This signal provides the current value of dmc_pcie_cfg_req_id. | |
77 | input dmc_pcie_cfg_select_pulse; // select | |
78 | input rst_l; // HW reset | |
79 | input daemon_csrbus_wr_in; // csrbus_wr | |
80 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
81 | output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
82 | ||
83 | //==================================================== | |
84 | // Type declarations | |
85 | //==================================================== | |
86 | wire clk; // Clock signal | |
87 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_INT_SLC] dmc_dbg_sel_a_reg_block_sel_hw_read; | |
88 | // This signal provides the current value of dmc_dbg_sel_a_reg_block_sel. | |
89 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_INT_SLC] dmc_dbg_sel_a_reg_sub_sel_hw_read; | |
90 | // This signal provides the current value of dmc_dbg_sel_a_reg_sub_sel. | |
91 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_INT_SLC] dmc_dbg_sel_a_reg_signal_sel_hw_read; | |
92 | // This signal provides the current value of dmc_dbg_sel_a_reg_signal_sel. | |
93 | wire dmc_dbg_sel_a_reg_select_pulse; // select | |
94 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_INT_SLC] dmc_dbg_sel_b_reg_block_sel_hw_read; | |
95 | // This signal provides the current value of dmc_dbg_sel_b_reg_block_sel. | |
96 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_INT_SLC] dmc_dbg_sel_b_reg_sub_sel_hw_read; | |
97 | // This signal provides the current value of dmc_dbg_sel_b_reg_sub_sel. | |
98 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_INT_SLC] dmc_dbg_sel_b_reg_signal_sel_hw_read; | |
99 | // This signal provides the current value of dmc_dbg_sel_b_reg_signal_sel. | |
100 | wire dmc_dbg_sel_b_reg_select_pulse; // select | |
101 | wire [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_INT_SLC] dmc_pcie_cfg_bus_num_hw_read; | |
102 | // This signal provides the current value of dmc_pcie_cfg_bus_num. | |
103 | wire [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_INT_SLC] dmc_pcie_cfg_req_id_hw_read; | |
104 | // This signal provides the current value of dmc_pcie_cfg_req_id. | |
105 | wire dmc_pcie_cfg_select_pulse; // select | |
106 | wire rst_l; // HW reset | |
107 | wire daemon_csrbus_wr_in; // csrbus_wr | |
108 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data | |
109 | wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data | |
110 | ||
111 | ||
112 | //==================================================== | |
113 | // Local signals | |
114 | //==================================================== | |
115 | //----- For CSR register: dmc_dbg_sel_a_reg | |
116 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_WIDTH-1:0] dmc_dbg_sel_a_reg_csrbus_read_data; | |
117 | // Entry Based Read Data | |
118 | ||
119 | //----- For CSR register: dmc_dbg_sel_b_reg | |
120 | wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH-1:0] dmc_dbg_sel_b_reg_csrbus_read_data; | |
121 | // Entry Based Read Data | |
122 | ||
123 | //----- For CSR register: dmc_pcie_cfg | |
124 | wire [`FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH-1:0] dmc_pcie_cfg_csrbus_read_data; | |
125 | // Entry Based Read Data | |
126 | ||
127 | //==================================================== | |
128 | // Assignments only (first stage) | |
129 | //==================================================== | |
130 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data = daemon_csrbus_wr_data_in; | |
131 | wire daemon_csrbus_wr = daemon_csrbus_wr_in; | |
132 | ||
133 | //==================================================== | |
134 | // Automatic hw_ld / hw_write | |
135 | //==================================================== | |
136 | ||
137 | //==================================================== | |
138 | // Extern select | |
139 | //==================================================== | |
140 | ||
141 | //===================================================== | |
142 | // OUTPUT: read_data_out | |
143 | //===================================================== | |
144 | dmu_cru_csrpipe_3 dmu_cru_csrpipe_3_inst_1 | |
145 | ( | |
146 | .clk (clk), | |
147 | .rst_l (rst_l), | |
148 | .reg_in (1'b1), | |
149 | .reg_out (1'b1), | |
150 | .data0 (dmc_dbg_sel_a_reg_csrbus_read_data), | |
151 | .sel0 (dmc_dbg_sel_a_reg_select_pulse), | |
152 | .data1 (dmc_dbg_sel_b_reg_csrbus_read_data), | |
153 | .sel1 (dmc_dbg_sel_b_reg_select_pulse), | |
154 | .data2 (dmc_pcie_cfg_csrbus_read_data), | |
155 | .sel2 (dmc_pcie_cfg_select_pulse), | |
156 | .out (read_data_0_out) | |
157 | ); | |
158 | ||
159 | ||
160 | //==================================================== | |
161 | // Instantiation of registers | |
162 | //==================================================== | |
163 | ||
164 | wire dmc_dbg_sel_a_reg_w_ld =dmc_dbg_sel_a_reg_select_pulse & daemon_csrbus_wr; | |
165 | ||
166 | dmu_cru_csr_dmc_dbg_sel_a_reg dmc_dbg_sel_a_reg | |
167 | ( | |
168 | .clk (clk), | |
169 | .rst_l (rst_l), | |
170 | .dmc_dbg_sel_a_reg_w_ld (dmc_dbg_sel_a_reg_w_ld), | |
171 | .csrbus_wr_data (daemon_csrbus_wr_data), | |
172 | .dmc_dbg_sel_a_reg_csrbus_read_data (dmc_dbg_sel_a_reg_csrbus_read_data), | |
173 | .dmc_dbg_sel_a_reg_block_sel_hw_read (dmc_dbg_sel_a_reg_block_sel_hw_read), | |
174 | .dmc_dbg_sel_a_reg_sub_sel_hw_read (dmc_dbg_sel_a_reg_sub_sel_hw_read), | |
175 | .dmc_dbg_sel_a_reg_signal_sel_hw_read (dmc_dbg_sel_a_reg_signal_sel_hw_read) | |
176 | ); | |
177 | ||
178 | wire dmc_dbg_sel_b_reg_w_ld =dmc_dbg_sel_b_reg_select_pulse & daemon_csrbus_wr; | |
179 | ||
180 | dmu_cru_csr_dmc_dbg_sel_b_reg dmc_dbg_sel_b_reg | |
181 | ( | |
182 | .clk (clk), | |
183 | .rst_l (rst_l), | |
184 | .dmc_dbg_sel_b_reg_w_ld (dmc_dbg_sel_b_reg_w_ld), | |
185 | .csrbus_wr_data (daemon_csrbus_wr_data), | |
186 | .dmc_dbg_sel_b_reg_csrbus_read_data (dmc_dbg_sel_b_reg_csrbus_read_data), | |
187 | .dmc_dbg_sel_b_reg_block_sel_hw_read (dmc_dbg_sel_b_reg_block_sel_hw_read), | |
188 | .dmc_dbg_sel_b_reg_sub_sel_hw_read (dmc_dbg_sel_b_reg_sub_sel_hw_read), | |
189 | .dmc_dbg_sel_b_reg_signal_sel_hw_read (dmc_dbg_sel_b_reg_signal_sel_hw_read) | |
190 | ); | |
191 | ||
192 | wire dmc_pcie_cfg_w_ld =dmc_pcie_cfg_select_pulse & daemon_csrbus_wr; | |
193 | ||
194 | dmu_cru_csr_dmc_pcie_cfg dmc_pcie_cfg | |
195 | ( | |
196 | .clk (clk), | |
197 | .rst_l (rst_l), | |
198 | .dmc_pcie_cfg_w_ld (dmc_pcie_cfg_w_ld), | |
199 | .csrbus_wr_data (daemon_csrbus_wr_data), | |
200 | .dmc_pcie_cfg_csrbus_read_data (dmc_pcie_cfg_csrbus_read_data), | |
201 | .dmc_pcie_cfg_bus_num_hw_read (dmc_pcie_cfg_bus_num_hw_read), | |
202 | .dmc_pcie_cfg_req_id_hw_read (dmc_pcie_cfg_req_id_hw_read) | |
203 | ); | |
204 | ||
205 | endmodule // dmu_cru_default_grp |