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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_cib_csr_ilu_int_en.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ilu_cib_csr_ilu_int_en | |
36 | ( | |
37 | clk, | |
38 | rst_l, | |
39 | ilu_int_en_w_ld, | |
40 | csrbus_wr_data, | |
41 | ilu_int_en_csrbus_read_data, | |
42 | ilu_int_en_spare3_s_hw_read, | |
43 | ilu_int_en_spare2_s_hw_read, | |
44 | ilu_int_en_spare1_s_hw_read, | |
45 | ilu_int_en_ihb_pe_s_hw_read, | |
46 | ilu_int_en_spare3_p_hw_read, | |
47 | ilu_int_en_spare2_p_hw_read, | |
48 | ilu_int_en_spare1_p_hw_read, | |
49 | ilu_int_en_ihb_pe_p_hw_read | |
50 | ); | |
51 | ||
52 | //==================================================================== | |
53 | // Polarity declarations | |
54 | //==================================================================== | |
55 | input clk; // Clock | |
56 | input rst_l; // Reset signal | |
57 | input ilu_int_en_w_ld; // SW load bus | |
58 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
59 | output [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH-1:0] ilu_int_en_csrbus_read_data; | |
60 | // SW read data | |
61 | output ilu_int_en_spare3_s_hw_read; // This signal provides the current value | |
62 | // of ilu_int_en_spare3_s. | |
63 | output ilu_int_en_spare2_s_hw_read; // This signal provides the current value | |
64 | // of ilu_int_en_spare2_s. | |
65 | output ilu_int_en_spare1_s_hw_read; // This signal provides the current value | |
66 | // of ilu_int_en_spare1_s. | |
67 | output ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value | |
68 | // of ilu_int_en_ihb_pe_s. | |
69 | output ilu_int_en_spare3_p_hw_read; // This signal provides the current value | |
70 | // of ilu_int_en_spare3_p. | |
71 | output ilu_int_en_spare2_p_hw_read; // This signal provides the current value | |
72 | // of ilu_int_en_spare2_p. | |
73 | output ilu_int_en_spare1_p_hw_read; // This signal provides the current value | |
74 | // of ilu_int_en_spare1_p. | |
75 | output ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value | |
76 | // of ilu_int_en_ihb_pe_p. | |
77 | ||
78 | //==================================================================== | |
79 | // Type declarations | |
80 | //==================================================================== | |
81 | wire clk; // Clock | |
82 | wire rst_l; // Reset signal | |
83 | wire ilu_int_en_w_ld; // SW load bus | |
84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
85 | wire [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH-1:0] ilu_int_en_csrbus_read_data; | |
86 | // SW read data | |
87 | wire ilu_int_en_spare3_s_hw_read; // This signal provides the current value of | |
88 | // ilu_int_en_spare3_s. | |
89 | wire ilu_int_en_spare2_s_hw_read; // This signal provides the current value of | |
90 | // ilu_int_en_spare2_s. | |
91 | wire ilu_int_en_spare1_s_hw_read; // This signal provides the current value of | |
92 | // ilu_int_en_spare1_s. | |
93 | wire ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value of | |
94 | // ilu_int_en_ihb_pe_s. | |
95 | wire ilu_int_en_spare3_p_hw_read; // This signal provides the current value of | |
96 | // ilu_int_en_spare3_p. | |
97 | wire ilu_int_en_spare2_p_hw_read; // This signal provides the current value of | |
98 | // ilu_int_en_spare2_p. | |
99 | wire ilu_int_en_spare1_p_hw_read; // This signal provides the current value of | |
100 | // ilu_int_en_spare1_p. | |
101 | wire ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value of | |
102 | // ilu_int_en_ihb_pe_p. | |
103 | ||
104 | //==================================================================== | |
105 | // Logic | |
106 | //==================================================================== | |
107 | ||
108 | // synopsys translate_off | |
109 | // verilint 123 off | |
110 | // verilint 498 off | |
111 | reg omni_ld; | |
112 | reg [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH-1:0] omni_data; | |
113 | ||
114 | // vlint flag_unsynthesizable_initial off | |
115 | initial | |
116 | begin | |
117 | omni_ld = 1'b0; | |
118 | omni_data = `FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH'b0; | |
119 | end// vlint flag_unsynthesizable_initial on | |
120 | ||
121 | // verilint 123 on | |
122 | // verilint 498 on | |
123 | // synopsys translate_on | |
124 | ||
125 | //----- Hardware Data Out Mux Assignments | |
126 | assign ilu_int_en_spare3_s_hw_read= | |
127 | ilu_int_en_csrbus_read_data [39]; | |
128 | assign ilu_int_en_spare2_s_hw_read= | |
129 | ilu_int_en_csrbus_read_data [38]; | |
130 | assign ilu_int_en_spare1_s_hw_read= | |
131 | ilu_int_en_csrbus_read_data [37]; | |
132 | assign ilu_int_en_ihb_pe_s_hw_read= | |
133 | ilu_int_en_csrbus_read_data [36]; | |
134 | assign ilu_int_en_spare3_p_hw_read= | |
135 | ilu_int_en_csrbus_read_data [7]; | |
136 | assign ilu_int_en_spare2_p_hw_read= | |
137 | ilu_int_en_csrbus_read_data [6]; | |
138 | assign ilu_int_en_spare1_p_hw_read= | |
139 | ilu_int_en_csrbus_read_data [5]; | |
140 | assign ilu_int_en_ihb_pe_p_hw_read= | |
141 | ilu_int_en_csrbus_read_data [4]; | |
142 | ||
143 | //==================================================================== | |
144 | // Instantiation of entries | |
145 | //==================================================================== | |
146 | ||
147 | //----- Entry 0 | |
148 | dmu_ilu_cib_csr_ilu_int_en_entry ilu_int_en_0 | |
149 | ( | |
150 | // synopsys translate_off | |
151 | .omni_ld (omni_ld), | |
152 | .omni_data (omni_data), | |
153 | // synopsys translate_on | |
154 | .clk (clk), | |
155 | .rst_l (rst_l), | |
156 | .w_ld (ilu_int_en_w_ld), | |
157 | .csrbus_wr_data (csrbus_wr_data), | |
158 | .ilu_int_en_csrbus_read_data (ilu_int_en_csrbus_read_data) | |
159 | ); | |
160 | ||
161 | endmodule // dmu_ilu_cib_csr_ilu_int_en |