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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_ilu_cib_default_grp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_ilu_cib_default_grp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_ilu_cib_default_grp
36 (
37 clk,
38 ilu_log_en_spare3_hw_read,
39 ilu_log_en_spare2_hw_read,
40 ilu_log_en_spare1_hw_read,
41 ilu_log_en_ihb_pe_hw_read,
42 ilu_log_en_select_pulse,
43 ilu_int_en_spare3_s_hw_read,
44 ilu_int_en_spare2_s_hw_read,
45 ilu_int_en_spare1_s_hw_read,
46 ilu_int_en_ihb_pe_s_hw_read,
47 ilu_int_en_spare3_p_hw_read,
48 ilu_int_en_spare2_p_hw_read,
49 ilu_int_en_spare1_p_hw_read,
50 ilu_int_en_ihb_pe_p_hw_read,
51 ilu_int_en_select_pulse,
52 ilu_en_err_select,
53 ilu_en_err_ext_read_data,
54 ilu_log_err_spare3_s_hw_set,
55 ilu_log_err_spare3_s_hw_read,
56 ilu_log_err_spare2_s_hw_set,
57 ilu_log_err_spare2_s_hw_read,
58 ilu_log_err_spare1_s_hw_set,
59 ilu_log_err_spare1_s_hw_read,
60 ilu_log_err_ihb_pe_s_hw_set,
61 ilu_log_err_ihb_pe_s_hw_read,
62 ilu_log_err_spare3_p_hw_set,
63 ilu_log_err_spare3_p_hw_read,
64 ilu_log_err_spare2_p_hw_set,
65 ilu_log_err_spare2_p_hw_read,
66 ilu_log_err_spare1_p_hw_set,
67 ilu_log_err_spare1_p_hw_read,
68 ilu_log_err_ihb_pe_p_hw_set,
69 ilu_log_err_ihb_pe_p_hw_read,
70 ilu_log_err_select_pulse,
71 pec_int_en_pec_hw_read,
72 pec_int_en_pec_ilu_hw_read,
73 pec_int_en_pec_ue_hw_read,
74 pec_int_en_pec_ce_hw_read,
75 pec_int_en_pec_oe_hw_read,
76 pec_int_en_select_pulse,
77 pec_en_err_select,
78 pec_en_err_ext_read_data,
79 ilu_diagnos_enpll1_hw_read,
80 ilu_diagnos_enpll0_hw_read,
81 ilu_diagnos_entx7_hw_read,
82 ilu_diagnos_entx6_hw_read,
83 ilu_diagnos_entx5_hw_read,
84 ilu_diagnos_entx4_hw_read,
85 ilu_diagnos_entx3_hw_read,
86 ilu_diagnos_entx2_hw_read,
87 ilu_diagnos_entx1_hw_read,
88 ilu_diagnos_entx0_hw_read,
89 ilu_diagnos_enrx7_hw_read,
90 ilu_diagnos_enrx6_hw_read,
91 ilu_diagnos_enrx5_hw_read,
92 ilu_diagnos_enrx4_hw_read,
93 ilu_diagnos_enrx3_hw_read,
94 ilu_diagnos_enrx2_hw_read,
95 ilu_diagnos_enrx1_hw_read,
96 ilu_diagnos_enrx0_hw_read,
97 ilu_diagnos_edi_par_hw_read,
98 ilu_diagnos_ehi_par_hw_read,
99 ilu_diagnos_edi_trig_hw_clr,
100 ilu_diagnos_edi_trig_hw_read,
101 ilu_diagnos_ehi_trig_hw_clr,
102 ilu_diagnos_ehi_trig_hw_read,
103 ilu_diagnos_rate_scale_hw_read,
104 ilu_diagnos_select_pulse,
105 ilu_log_err_rw1c_alias,
106 ilu_log_err_rw1s_alias,
107 rst_l,
108 por_l,
109 daemon_csrbus_wr_in,
110 daemon_csrbus_wr_data_in,
111 read_data_0_out,
112 read_data_1_out
113 );
114
115//====================================================
116// Polarity declarations
117//====================================================
118input clk; // Clock signal
119output ilu_log_en_spare3_hw_read; // This signal provides the current value of
120 // ilu_log_en_spare3.
121output ilu_log_en_spare2_hw_read; // This signal provides the current value of
122 // ilu_log_en_spare2.
123output ilu_log_en_spare1_hw_read; // This signal provides the current value of
124 // ilu_log_en_spare1.
125output ilu_log_en_ihb_pe_hw_read; // This signal provides the current value of
126 // ilu_log_en_ihb_pe.
127input ilu_log_en_select_pulse; // select
128output ilu_int_en_spare3_s_hw_read; // This signal provides the current value
129 // of ilu_int_en_spare3_s.
130output ilu_int_en_spare2_s_hw_read; // This signal provides the current value
131 // of ilu_int_en_spare2_s.
132output ilu_int_en_spare1_s_hw_read; // This signal provides the current value
133 // of ilu_int_en_spare1_s.
134output ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value
135 // of ilu_int_en_ihb_pe_s.
136output ilu_int_en_spare3_p_hw_read; // This signal provides the current value
137 // of ilu_int_en_spare3_p.
138output ilu_int_en_spare2_p_hw_read; // This signal provides the current value
139 // of ilu_int_en_spare2_p.
140output ilu_int_en_spare1_p_hw_read; // This signal provides the current value
141 // of ilu_int_en_spare1_p.
142output ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value
143 // of ilu_int_en_ihb_pe_p.
144input ilu_int_en_select_pulse; // select
145input ilu_en_err_select; // select
146input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] ilu_en_err_ext_read_data; // Read Data
147input ilu_log_err_spare3_s_hw_set; // Hardware set signal for
148 // ilu_log_err_spare3_s. When set
149 // ilu_log_err will be set to one.
150output ilu_log_err_spare3_s_hw_read; // This signal provides the current value
151 // of ilu_log_err_spare3_s.
152input ilu_log_err_spare2_s_hw_set; // Hardware set signal for
153 // ilu_log_err_spare2_s. When set
154 // ilu_log_err will be set to one.
155output ilu_log_err_spare2_s_hw_read; // This signal provides the current value
156 // of ilu_log_err_spare2_s.
157input ilu_log_err_spare1_s_hw_set; // Hardware set signal for
158 // ilu_log_err_spare1_s. When set
159 // ilu_log_err will be set to one.
160output ilu_log_err_spare1_s_hw_read; // This signal provides the current value
161 // of ilu_log_err_spare1_s.
162input ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for
163 // ilu_log_err_ihb_pe_s. When set
164 // ilu_log_err will be set to one.
165output ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value
166 // of ilu_log_err_ihb_pe_s.
167input ilu_log_err_spare3_p_hw_set; // Hardware set signal for
168 // ilu_log_err_spare3_p. When set
169 // ilu_log_err will be set to one.
170output ilu_log_err_spare3_p_hw_read; // This signal provides the current value
171 // of ilu_log_err_spare3_p.
172input ilu_log_err_spare2_p_hw_set; // Hardware set signal for
173 // ilu_log_err_spare2_p. When set
174 // ilu_log_err will be set to one.
175output ilu_log_err_spare2_p_hw_read; // This signal provides the current value
176 // of ilu_log_err_spare2_p.
177input ilu_log_err_spare1_p_hw_set; // Hardware set signal for
178 // ilu_log_err_spare1_p. When set
179 // ilu_log_err will be set to one.
180output ilu_log_err_spare1_p_hw_read; // This signal provides the current value
181 // of ilu_log_err_spare1_p.
182input ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for
183 // ilu_log_err_ihb_pe_p. When set
184 // ilu_log_err will be set to one.
185output ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value
186 // of ilu_log_err_ihb_pe_p.
187input ilu_log_err_select_pulse; // select
188output pec_int_en_pec_hw_read; // This signal provides the current value of
189 // pec_int_en_pec.
190output pec_int_en_pec_ilu_hw_read; // This signal provides the current value of
191 // pec_int_en_pec_ilu.
192output pec_int_en_pec_ue_hw_read; // This signal provides the current value of
193 // pec_int_en_pec_ue.
194output pec_int_en_pec_ce_hw_read; // This signal provides the current value of
195 // pec_int_en_pec_ce.
196output pec_int_en_pec_oe_hw_read; // This signal provides the current value of
197 // pec_int_en_pec_oe.
198input pec_int_en_select_pulse; // select
199input pec_en_err_select; // select
200input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] pec_en_err_ext_read_data; // Read Data
201output ilu_diagnos_enpll1_hw_read; // This signal provides the current value of
202 // ilu_diagnos_enpll1.
203output ilu_diagnos_enpll0_hw_read; // This signal provides the current value of
204 // ilu_diagnos_enpll0.
205output ilu_diagnos_entx7_hw_read; // This signal provides the current value of
206 // ilu_diagnos_entx7.
207output ilu_diagnos_entx6_hw_read; // This signal provides the current value of
208 // ilu_diagnos_entx6.
209output ilu_diagnos_entx5_hw_read; // This signal provides the current value of
210 // ilu_diagnos_entx5.
211output ilu_diagnos_entx4_hw_read; // This signal provides the current value of
212 // ilu_diagnos_entx4.
213output ilu_diagnos_entx3_hw_read; // This signal provides the current value of
214 // ilu_diagnos_entx3.
215output ilu_diagnos_entx2_hw_read; // This signal provides the current value of
216 // ilu_diagnos_entx2.
217output ilu_diagnos_entx1_hw_read; // This signal provides the current value of
218 // ilu_diagnos_entx1.
219output ilu_diagnos_entx0_hw_read; // This signal provides the current value of
220 // ilu_diagnos_entx0.
221output ilu_diagnos_enrx7_hw_read; // This signal provides the current value of
222 // ilu_diagnos_enrx7.
223output ilu_diagnos_enrx6_hw_read; // This signal provides the current value of
224 // ilu_diagnos_enrx6.
225output ilu_diagnos_enrx5_hw_read; // This signal provides the current value of
226 // ilu_diagnos_enrx5.
227output ilu_diagnos_enrx4_hw_read; // This signal provides the current value of
228 // ilu_diagnos_enrx4.
229output ilu_diagnos_enrx3_hw_read; // This signal provides the current value of
230 // ilu_diagnos_enrx3.
231output ilu_diagnos_enrx2_hw_read; // This signal provides the current value of
232 // ilu_diagnos_enrx2.
233output ilu_diagnos_enrx1_hw_read; // This signal provides the current value of
234 // ilu_diagnos_enrx1.
235output ilu_diagnos_enrx0_hw_read; // This signal provides the current value of
236 // ilu_diagnos_enrx0.
237output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC] ilu_diagnos_edi_par_hw_read;
238 // This signal provides the current value of ilu_diagnos_edi_par.
239output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC] ilu_diagnos_ehi_par_hw_read;
240 // This signal provides the current value of ilu_diagnos_ehi_par.
241input ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for
242 // ilu_diagnos_edi_trig. When set
243 // ilu_diagnos will be set to zero.
244output ilu_diagnos_edi_trig_hw_read; // This signal provides the current value
245 // of ilu_diagnos_edi_trig.
246input ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for
247 // ilu_diagnos_ehi_trig. When set
248 // ilu_diagnos will be set to zero.
249output ilu_diagnos_ehi_trig_hw_read; // This signal provides the current value
250 // of ilu_diagnos_ehi_trig.
251output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC] ilu_diagnos_rate_scale_hw_read;
252 // This signal provides the current value of ilu_diagnos_rate_scale.
253input ilu_diagnos_select_pulse; // select
254input ilu_log_err_rw1c_alias; // SW load
255input ilu_log_err_rw1s_alias; // SW load
256input rst_l; // HW reset
257input por_l; // HW reset
258input daemon_csrbus_wr_in; // csrbus_wr
259input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
260output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
261output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1_out; // Read Data
262
263//====================================================
264// Type declarations
265//====================================================
266wire clk; // Clock signal
267wire ilu_log_en_spare3_hw_read; // This signal provides the current value of
268 // ilu_log_en_spare3.
269wire ilu_log_en_spare2_hw_read; // This signal provides the current value of
270 // ilu_log_en_spare2.
271wire ilu_log_en_spare1_hw_read; // This signal provides the current value of
272 // ilu_log_en_spare1.
273wire ilu_log_en_ihb_pe_hw_read; // This signal provides the current value of
274 // ilu_log_en_ihb_pe.
275wire ilu_log_en_select_pulse; // select
276wire ilu_int_en_spare3_s_hw_read; // This signal provides the current value of
277 // ilu_int_en_spare3_s.
278wire ilu_int_en_spare2_s_hw_read; // This signal provides the current value of
279 // ilu_int_en_spare2_s.
280wire ilu_int_en_spare1_s_hw_read; // This signal provides the current value of
281 // ilu_int_en_spare1_s.
282wire ilu_int_en_ihb_pe_s_hw_read; // This signal provides the current value of
283 // ilu_int_en_ihb_pe_s.
284wire ilu_int_en_spare3_p_hw_read; // This signal provides the current value of
285 // ilu_int_en_spare3_p.
286wire ilu_int_en_spare2_p_hw_read; // This signal provides the current value of
287 // ilu_int_en_spare2_p.
288wire ilu_int_en_spare1_p_hw_read; // This signal provides the current value of
289 // ilu_int_en_spare1_p.
290wire ilu_int_en_ihb_pe_p_hw_read; // This signal provides the current value of
291 // ilu_int_en_ihb_pe_p.
292wire ilu_int_en_select_pulse; // select
293wire ilu_en_err_select; // select
294wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] ilu_en_err_ext_read_data; // Read Data
295wire ilu_log_err_spare3_s_hw_set; // Hardware set signal for
296 // ilu_log_err_spare3_s. When set ilu_log_err
297 // will be set to one.
298wire ilu_log_err_spare3_s_hw_read; // This signal provides the current value of
299 // ilu_log_err_spare3_s.
300wire ilu_log_err_spare2_s_hw_set; // Hardware set signal for
301 // ilu_log_err_spare2_s. When set ilu_log_err
302 // will be set to one.
303wire ilu_log_err_spare2_s_hw_read; // This signal provides the current value of
304 // ilu_log_err_spare2_s.
305wire ilu_log_err_spare1_s_hw_set; // Hardware set signal for
306 // ilu_log_err_spare1_s. When set ilu_log_err
307 // will be set to one.
308wire ilu_log_err_spare1_s_hw_read; // This signal provides the current value of
309 // ilu_log_err_spare1_s.
310wire ilu_log_err_ihb_pe_s_hw_set; // Hardware set signal for
311 // ilu_log_err_ihb_pe_s. When set ilu_log_err
312 // will be set to one.
313wire ilu_log_err_ihb_pe_s_hw_read; // This signal provides the current value of
314 // ilu_log_err_ihb_pe_s.
315wire ilu_log_err_spare3_p_hw_set; // Hardware set signal for
316 // ilu_log_err_spare3_p. When set ilu_log_err
317 // will be set to one.
318wire ilu_log_err_spare3_p_hw_read; // This signal provides the current value of
319 // ilu_log_err_spare3_p.
320wire ilu_log_err_spare2_p_hw_set; // Hardware set signal for
321 // ilu_log_err_spare2_p. When set ilu_log_err
322 // will be set to one.
323wire ilu_log_err_spare2_p_hw_read; // This signal provides the current value of
324 // ilu_log_err_spare2_p.
325wire ilu_log_err_spare1_p_hw_set; // Hardware set signal for
326 // ilu_log_err_spare1_p. When set ilu_log_err
327 // will be set to one.
328wire ilu_log_err_spare1_p_hw_read; // This signal provides the current value of
329 // ilu_log_err_spare1_p.
330wire ilu_log_err_ihb_pe_p_hw_set; // Hardware set signal for
331 // ilu_log_err_ihb_pe_p. When set ilu_log_err
332 // will be set to one.
333wire ilu_log_err_ihb_pe_p_hw_read; // This signal provides the current value of
334 // ilu_log_err_ihb_pe_p.
335wire ilu_log_err_select_pulse; // select
336wire pec_int_en_pec_hw_read; // This signal provides the current value of
337 // pec_int_en_pec.
338wire pec_int_en_pec_ilu_hw_read; // This signal provides the current value of
339 // pec_int_en_pec_ilu.
340wire pec_int_en_pec_ue_hw_read; // This signal provides the current value of
341 // pec_int_en_pec_ue.
342wire pec_int_en_pec_ce_hw_read; // This signal provides the current value of
343 // pec_int_en_pec_ce.
344wire pec_int_en_pec_oe_hw_read; // This signal provides the current value of
345 // pec_int_en_pec_oe.
346wire pec_int_en_select_pulse; // select
347wire pec_en_err_select; // select
348wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] pec_en_err_ext_read_data; // Read Data
349wire ilu_diagnos_enpll1_hw_read; // This signal provides the current value of
350 // ilu_diagnos_enpll1.
351wire ilu_diagnos_enpll0_hw_read; // This signal provides the current value of
352 // ilu_diagnos_enpll0.
353wire ilu_diagnos_entx7_hw_read; // This signal provides the current value of
354 // ilu_diagnos_entx7.
355wire ilu_diagnos_entx6_hw_read; // This signal provides the current value of
356 // ilu_diagnos_entx6.
357wire ilu_diagnos_entx5_hw_read; // This signal provides the current value of
358 // ilu_diagnos_entx5.
359wire ilu_diagnos_entx4_hw_read; // This signal provides the current value of
360 // ilu_diagnos_entx4.
361wire ilu_diagnos_entx3_hw_read; // This signal provides the current value of
362 // ilu_diagnos_entx3.
363wire ilu_diagnos_entx2_hw_read; // This signal provides the current value of
364 // ilu_diagnos_entx2.
365wire ilu_diagnos_entx1_hw_read; // This signal provides the current value of
366 // ilu_diagnos_entx1.
367wire ilu_diagnos_entx0_hw_read; // This signal provides the current value of
368 // ilu_diagnos_entx0.
369wire ilu_diagnos_enrx7_hw_read; // This signal provides the current value of
370 // ilu_diagnos_enrx7.
371wire ilu_diagnos_enrx6_hw_read; // This signal provides the current value of
372 // ilu_diagnos_enrx6.
373wire ilu_diagnos_enrx5_hw_read; // This signal provides the current value of
374 // ilu_diagnos_enrx5.
375wire ilu_diagnos_enrx4_hw_read; // This signal provides the current value of
376 // ilu_diagnos_enrx4.
377wire ilu_diagnos_enrx3_hw_read; // This signal provides the current value of
378 // ilu_diagnos_enrx3.
379wire ilu_diagnos_enrx2_hw_read; // This signal provides the current value of
380 // ilu_diagnos_enrx2.
381wire ilu_diagnos_enrx1_hw_read; // This signal provides the current value of
382 // ilu_diagnos_enrx1.
383wire ilu_diagnos_enrx0_hw_read; // This signal provides the current value of
384 // ilu_diagnos_enrx0.
385wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC] ilu_diagnos_edi_par_hw_read;
386 // This signal provides the current value of ilu_diagnos_edi_par.
387wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC] ilu_diagnos_ehi_par_hw_read;
388 // This signal provides the current value of ilu_diagnos_ehi_par.
389wire ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for
390 // ilu_diagnos_edi_trig. When set ilu_diagnos
391 // will be set to zero.
392wire ilu_diagnos_edi_trig_hw_read; // This signal provides the current value of
393 // ilu_diagnos_edi_trig.
394wire ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for
395 // ilu_diagnos_ehi_trig. When set ilu_diagnos
396 // will be set to zero.
397wire ilu_diagnos_ehi_trig_hw_read; // This signal provides the current value of
398 // ilu_diagnos_ehi_trig.
399wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC] ilu_diagnos_rate_scale_hw_read;
400 // This signal provides the current value of ilu_diagnos_rate_scale.
401wire ilu_diagnos_select_pulse; // select
402wire ilu_log_err_rw1c_alias; // SW load
403wire ilu_log_err_rw1s_alias; // SW load
404wire rst_l; // HW reset
405wire por_l; // HW reset
406wire daemon_csrbus_wr_in; // csrbus_wr
407wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
408wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
409wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_1_out; // Read Data
410
411
412//====================================================
413// Local signals
414//====================================================
415//----- For CSR register: ilu_log_en
416wire [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_WIDTH-1:0] ilu_log_en_csrbus_read_data;
417 // Entry Based Read Data
418
419//----- For CSR register: ilu_int_en
420wire [`FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH-1:0] ilu_int_en_csrbus_read_data;
421 // Entry Based Read Data
422
423//----- For CSR register: ilu_log_err
424wire [`FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH-1:0] ilu_log_err_csrbus_read_data;
425 // Entry Based Read Data
426
427//----- For CSR register: pec_int_en
428wire [`FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WIDTH-1:0] pec_int_en_csrbus_read_data;
429 // Entry Based Read Data
430
431//----- For CSR register: ilu_diagnos
432wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH-1:0] ilu_diagnos_csrbus_read_data;
433 // Entry Based Read Data
434
435//====================================================
436// Assignments only (first stage)
437//====================================================
438wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data = daemon_csrbus_wr_data_in;
439wire daemon_csrbus_wr = daemon_csrbus_wr_in;
440
441//====================================================
442// Automatic hw_ld / hw_write
443//====================================================
444
445//====================================================
446// Extern select
447//====================================================
448
449//=====================================================
450// OUTPUT: read_data_out
451//=====================================================
452dmu_ilu_cib_csrpipe_6 dmu_ilu_cib_csrpipe_6_inst_1
453 (
454 .clk (clk),
455 .rst_l (rst_l),
456 .reg_in (1'b1),
457 .reg_out (1'b1),
458 .data0 (ilu_log_en_csrbus_read_data),
459 .sel0 (ilu_log_en_select_pulse),
460 .data1 (ilu_int_en_csrbus_read_data),
461 .sel1 (ilu_int_en_select_pulse),
462 .data2 (ilu_en_err_ext_read_data),
463 .sel2 (ilu_en_err_select),
464 .data3 (ilu_log_err_csrbus_read_data),
465 .sel3 (ilu_log_err_select_pulse),
466 .data4 (pec_int_en_csrbus_read_data),
467 .sel4 (pec_int_en_select_pulse),
468 .data5 (pec_en_err_ext_read_data),
469 .sel5 (pec_en_err_select),
470 .out (read_data_0_out)
471 );
472
473dmu_ilu_cib_csrpipe_6 dmu_ilu_cib_csrpipe_6_inst_2
474 (
475 .clk (clk),
476 .rst_l (rst_l),
477 .reg_in (1'b1),
478 .reg_out (1'b1),
479 .data0 (ilu_diagnos_csrbus_read_data),
480 .sel0 (ilu_diagnos_select_pulse),
481 .data1 (64'b0),
482 .sel1 (1'b1),
483 .data2 (64'b0),
484 .sel2 (1'b1),
485 .data3 (64'b0),
486 .sel3 (1'b1),
487 .data4 (64'b0),
488 .sel4 (1'b1),
489 .data5 (64'b0),
490 .sel5 (1'b1),
491 .out (read_data_1_out)
492 );
493
494
495//====================================================
496// Instantiation of registers
497//====================================================
498
499wire ilu_log_en_w_ld =ilu_log_en_select_pulse & daemon_csrbus_wr;
500
501dmu_ilu_cib_csr_ilu_log_en ilu_log_en
502 (
503 .clk (clk),
504 .por_l (por_l),
505 .ilu_log_en_w_ld (ilu_log_en_w_ld),
506 .csrbus_wr_data (daemon_csrbus_wr_data),
507 .ilu_log_en_csrbus_read_data (ilu_log_en_csrbus_read_data),
508 .ilu_log_en_spare3_hw_read (ilu_log_en_spare3_hw_read),
509 .ilu_log_en_spare2_hw_read (ilu_log_en_spare2_hw_read),
510 .ilu_log_en_spare1_hw_read (ilu_log_en_spare1_hw_read),
511 .ilu_log_en_ihb_pe_hw_read (ilu_log_en_ihb_pe_hw_read)
512 );
513
514wire ilu_int_en_w_ld =ilu_int_en_select_pulse & daemon_csrbus_wr;
515
516dmu_ilu_cib_csr_ilu_int_en ilu_int_en
517 (
518 .clk (clk),
519 .rst_l (rst_l),
520 .ilu_int_en_w_ld (ilu_int_en_w_ld),
521 .csrbus_wr_data (daemon_csrbus_wr_data),
522 .ilu_int_en_csrbus_read_data (ilu_int_en_csrbus_read_data),
523 .ilu_int_en_spare3_s_hw_read (ilu_int_en_spare3_s_hw_read),
524 .ilu_int_en_spare2_s_hw_read (ilu_int_en_spare2_s_hw_read),
525 .ilu_int_en_spare1_s_hw_read (ilu_int_en_spare1_s_hw_read),
526 .ilu_int_en_ihb_pe_s_hw_read (ilu_int_en_ihb_pe_s_hw_read),
527 .ilu_int_en_spare3_p_hw_read (ilu_int_en_spare3_p_hw_read),
528 .ilu_int_en_spare2_p_hw_read (ilu_int_en_spare2_p_hw_read),
529 .ilu_int_en_spare1_p_hw_read (ilu_int_en_spare1_p_hw_read),
530 .ilu_int_en_ihb_pe_p_hw_read (ilu_int_en_ihb_pe_p_hw_read)
531 );
532
533wire ilu_log_err_w_ld =ilu_log_err_select_pulse & daemon_csrbus_wr;
534
535dmu_ilu_cib_csr_ilu_log_err ilu_log_err
536 (
537 .clk (clk),
538 .por_l (por_l),
539 .ilu_log_err_w_ld (ilu_log_err_w_ld),
540 .csrbus_wr_data (daemon_csrbus_wr_data),
541 .rw1c_alias (ilu_log_err_rw1c_alias),
542 .rw1s_alias (ilu_log_err_rw1s_alias),
543 .ilu_log_err_csrbus_read_data (ilu_log_err_csrbus_read_data),
544 .ilu_log_err_spare3_s_hw_set (ilu_log_err_spare3_s_hw_set),
545 .ilu_log_err_spare3_s_hw_read (ilu_log_err_spare3_s_hw_read),
546 .ilu_log_err_spare2_s_hw_set (ilu_log_err_spare2_s_hw_set),
547 .ilu_log_err_spare2_s_hw_read (ilu_log_err_spare2_s_hw_read),
548 .ilu_log_err_spare1_s_hw_set (ilu_log_err_spare1_s_hw_set),
549 .ilu_log_err_spare1_s_hw_read (ilu_log_err_spare1_s_hw_read),
550 .ilu_log_err_ihb_pe_s_hw_set (ilu_log_err_ihb_pe_s_hw_set),
551 .ilu_log_err_ihb_pe_s_hw_read (ilu_log_err_ihb_pe_s_hw_read),
552 .ilu_log_err_spare3_p_hw_set (ilu_log_err_spare3_p_hw_set),
553 .ilu_log_err_spare3_p_hw_read (ilu_log_err_spare3_p_hw_read),
554 .ilu_log_err_spare2_p_hw_set (ilu_log_err_spare2_p_hw_set),
555 .ilu_log_err_spare2_p_hw_read (ilu_log_err_spare2_p_hw_read),
556 .ilu_log_err_spare1_p_hw_set (ilu_log_err_spare1_p_hw_set),
557 .ilu_log_err_spare1_p_hw_read (ilu_log_err_spare1_p_hw_read),
558 .ilu_log_err_ihb_pe_p_hw_set (ilu_log_err_ihb_pe_p_hw_set),
559 .ilu_log_err_ihb_pe_p_hw_read (ilu_log_err_ihb_pe_p_hw_read)
560 );
561
562wire pec_int_en_w_ld =pec_int_en_select_pulse & daemon_csrbus_wr;
563
564dmu_ilu_cib_csr_pec_int_en pec_int_en
565 (
566 .clk (clk),
567 .rst_l (rst_l),
568 .pec_int_en_w_ld (pec_int_en_w_ld),
569 .csrbus_wr_data (daemon_csrbus_wr_data),
570 .pec_int_en_csrbus_read_data (pec_int_en_csrbus_read_data),
571 .pec_int_en_pec_hw_read (pec_int_en_pec_hw_read),
572 .pec_int_en_pec_ilu_hw_read (pec_int_en_pec_ilu_hw_read),
573 .pec_int_en_pec_ue_hw_read (pec_int_en_pec_ue_hw_read),
574 .pec_int_en_pec_ce_hw_read (pec_int_en_pec_ce_hw_read),
575 .pec_int_en_pec_oe_hw_read (pec_int_en_pec_oe_hw_read)
576 );
577
578wire ilu_diagnos_w_ld =ilu_diagnos_select_pulse & daemon_csrbus_wr;
579
580dmu_ilu_cib_csr_ilu_diagnos ilu_diagnos
581 (
582 .clk (clk),
583 .rst_l (rst_l),
584 .por_l (por_l),
585 .ilu_diagnos_w_ld (ilu_diagnos_w_ld),
586 .csrbus_wr_data (daemon_csrbus_wr_data),
587 .ilu_diagnos_csrbus_read_data (ilu_diagnos_csrbus_read_data),
588 .ilu_diagnos_enpll1_hw_read (ilu_diagnos_enpll1_hw_read),
589 .ilu_diagnos_enpll0_hw_read (ilu_diagnos_enpll0_hw_read),
590 .ilu_diagnos_entx7_hw_read (ilu_diagnos_entx7_hw_read),
591 .ilu_diagnos_entx6_hw_read (ilu_diagnos_entx6_hw_read),
592 .ilu_diagnos_entx5_hw_read (ilu_diagnos_entx5_hw_read),
593 .ilu_diagnos_entx4_hw_read (ilu_diagnos_entx4_hw_read),
594 .ilu_diagnos_entx3_hw_read (ilu_diagnos_entx3_hw_read),
595 .ilu_diagnos_entx2_hw_read (ilu_diagnos_entx2_hw_read),
596 .ilu_diagnos_entx1_hw_read (ilu_diagnos_entx1_hw_read),
597 .ilu_diagnos_entx0_hw_read (ilu_diagnos_entx0_hw_read),
598 .ilu_diagnos_enrx7_hw_read (ilu_diagnos_enrx7_hw_read),
599 .ilu_diagnos_enrx6_hw_read (ilu_diagnos_enrx6_hw_read),
600 .ilu_diagnos_enrx5_hw_read (ilu_diagnos_enrx5_hw_read),
601 .ilu_diagnos_enrx4_hw_read (ilu_diagnos_enrx4_hw_read),
602 .ilu_diagnos_enrx3_hw_read (ilu_diagnos_enrx3_hw_read),
603 .ilu_diagnos_enrx2_hw_read (ilu_diagnos_enrx2_hw_read),
604 .ilu_diagnos_enrx1_hw_read (ilu_diagnos_enrx1_hw_read),
605 .ilu_diagnos_enrx0_hw_read (ilu_diagnos_enrx0_hw_read),
606 .ilu_diagnos_edi_par_hw_read (ilu_diagnos_edi_par_hw_read),
607 .ilu_diagnos_ehi_par_hw_read (ilu_diagnos_ehi_par_hw_read),
608 .ilu_diagnos_edi_trig_hw_clr (ilu_diagnos_edi_trig_hw_clr),
609 .ilu_diagnos_edi_trig_hw_read (ilu_diagnos_edi_trig_hw_read),
610 .ilu_diagnos_ehi_trig_hw_clr (ilu_diagnos_ehi_trig_hw_clr),
611 .ilu_diagnos_ehi_trig_hw_read (ilu_diagnos_ehi_trig_hw_read),
612 .ilu_diagnos_rate_scale_hw_read (ilu_diagnos_rate_scale_hw_read)
613 );
614
615endmodule // dmu_ilu_cib_default_grp
Full OpenSPARC design & verification tarball including full HDL.