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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_ilu_cib_defines.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dmu_ilu_cib_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`ifdef FIRE_DLC_ILU_CIB_DEFINES
39`else
40`define FIRE_DLC_ILU_CIB_DEFINES
41
42`define FIRE_DLC_ILU_CIB_INSTANCE_ID_VALUE_A 1'h0
43`define FIRE_DLC_ILU_CIB_INSTANCE_ID_VALUE_B 1'h1
44
45//-------------------------------------------------------
46//----- Variable definitions for register dmu_ilu_cib_csr_ilu_log_en
47//-------------------------------------------------------
48
49`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ADDR 27'b000000011001010001000000000
50`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR 30'b000000011001010001000000000000
51`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_EN_HW_ADDR 27'b000000011101010001000000000
52`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_EN_ADDR 30'b000000011101010001000000000000
53
54`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_WIDTH 64
55`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_DEPTH 1
56`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SLC 63:0
57`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_INT_SLC 63:0
58`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_POSITION 0
59`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_LOW_ADDR_WIDTH 0
60`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_ADDR_RANGE 26:0
61`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000011110000
62`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
63`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000011110000
64`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
65`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
66`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
67`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
68`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_RMASK 64'b0000000000000000000000000000000000000000000000000000000011110000
69`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111100001111
70`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
71`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000011110000
72`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_INTERNAL_REG 1
73`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_ZERO_TIME_OMNI 1
74`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_NUM_FIELDS 4
75`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_FID 0
76`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_SLC 7:7
77`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_WIDTH 1
78`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_INT_SLC 0:0
79`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_POSITION 7
80`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
81`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
82`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE3_POR_VALUE 1'b1
83`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_FID 1
84`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_SLC 6:6
85`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_WIDTH 1
86`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_INT_SLC 0:0
87`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_POSITION 6
88`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
89`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
90`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE2_POR_VALUE 1'b1
91`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_FID 2
92`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_SLC 5:5
93`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_WIDTH 1
94`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_INT_SLC 0:0
95`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_POSITION 5
96`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
97`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
98`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_SPARE1_POR_VALUE 1'b1
99`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_FID 3
100`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_SLC 4:4
101`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_WIDTH 1
102`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_INT_SLC 0:0
103`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_POSITION 4
104`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
105`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
106`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_EN_IHB_PE_POR_VALUE 1'b1
107
108//-------------------------------------------------------
109//----- Variable definitions for register dmu_ilu_cib_csr_ilu_int_en
110//-------------------------------------------------------
111
112`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ADDR 27'b000000011001010001000000001
113`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR 30'b000000011001010001000000001000
114`define FIRE_DLC_ILU_CIB_CSR_B_ILU_INT_EN_HW_ADDR 27'b000000011101010001000000001
115`define FIRE_DLC_ILU_CIB_CSR_B_ILU_INT_EN_ADDR 30'b000000011101010001000000001000
116
117`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WIDTH 64
118`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_DEPTH 1
119`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SLC 63:0
120`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_INT_SLC 63:0
121`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_POSITION 0
122`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_LOW_ADDR_WIDTH 0
123`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_ADDR_RANGE 26:0
124`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
125`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
126`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WRITE_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
127`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
128`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
129`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
130`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
131`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
132`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
133`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
134`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
135`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_INTERNAL_REG 1
136`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_ZERO_TIME_OMNI 1
137`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_NUM_FIELDS 8
138`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_FID 0
139`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_SLC 39:39
140`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_WIDTH 1
141`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_INT_SLC 0:0
142`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_POSITION 39
143`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
144`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
145`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_S_POR_VALUE 1'b0
146`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_FID 1
147`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_SLC 38:38
148`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_WIDTH 1
149`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_INT_SLC 0:0
150`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_POSITION 38
151`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
152`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
153`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_S_POR_VALUE 1'b0
154`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_FID 2
155`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_SLC 37:37
156`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_WIDTH 1
157`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_INT_SLC 0:0
158`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_POSITION 37
159`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
160`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
161`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_S_POR_VALUE 1'b0
162`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_FID 3
163`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_SLC 36:36
164`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_WIDTH 1
165`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_INT_SLC 0:0
166`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_POSITION 36
167`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
168`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
169`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_S_POR_VALUE 1'b0
170`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_FID 4
171`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_SLC 7:7
172`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_WIDTH 1
173`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_INT_SLC 0:0
174`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_POSITION 7
175`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
176`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
177`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE3_P_POR_VALUE 1'b0
178`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_FID 5
179`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_SLC 6:6
180`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_WIDTH 1
181`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_INT_SLC 0:0
182`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_POSITION 6
183`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
184`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
185`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE2_P_POR_VALUE 1'b0
186`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_FID 6
187`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_SLC 5:5
188`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_WIDTH 1
189`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_INT_SLC 0:0
190`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_POSITION 5
191`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
192`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
193`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_SPARE1_P_POR_VALUE 1'b0
194`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_FID 7
195`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_SLC 4:4
196`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_WIDTH 1
197`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_INT_SLC 0:0
198`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_POSITION 4
199`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
200`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
201`define FIRE_DLC_ILU_CIB_CSR_ILU_INT_EN_IHB_PE_P_POR_VALUE 1'b0
202
203//-------------------------------------------------------
204//----- Variable definitions for register dmu_ilu_cib_csr_ilu_en_err
205//-------------------------------------------------------
206
207`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ADDR 27'b000000011001010001000000010
208`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR 30'b000000011001010001000000010000
209`define FIRE_DLC_ILU_CIB_CSR_B_ILU_EN_ERR_HW_ADDR 27'b000000011101010001000000010
210`define FIRE_DLC_ILU_CIB_CSR_B_ILU_EN_ERR_ADDR 30'b000000011101010001000000010000
211
212`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_WIDTH 64
213`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_DEPTH 1
214`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SLC 63:0
215`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_INT_SLC 63:0
216`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_POSITION 0
217`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_LOW_ADDR_WIDTH 0
218`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_ADDR_RANGE 26:0
219`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
220`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_READ_ONLY_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
221`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
222`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
223`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
224`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
225`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
226`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
227`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
228`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
229`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
230`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_INTERNAL_REG 0
231`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_EXTERNAL_DECODE_REG 1
232`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_ZERO_TIME_OMNI 0
233`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_NUM_FIELDS 8
234`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_FID 0
235`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_SLC 39:39
236`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_WIDTH 1
237`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_INT_SLC 0:0
238`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_POSITION 39
239`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
240`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
241`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_S_POR_VALUE 1'b0
242`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_FID 1
243`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_SLC 38:38
244`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_WIDTH 1
245`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_INT_SLC 0:0
246`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_POSITION 38
247`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
248`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
249`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_S_POR_VALUE 1'b0
250`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_FID 2
251`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_SLC 37:37
252`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_WIDTH 1
253`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_INT_SLC 0:0
254`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_POSITION 37
255`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
256`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
257`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_S_POR_VALUE 1'b0
258`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_FID 3
259`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_SLC 36:36
260`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_WIDTH 1
261`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_INT_SLC 0:0
262`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_POSITION 36
263`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
264`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
265`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_S_POR_VALUE 1'b0
266`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_FID 4
267`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_SLC 7:7
268`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_WIDTH 1
269`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_INT_SLC 0:0
270`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_POSITION 7
271`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
272`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
273`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE3_P_POR_VALUE 1'b0
274`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_FID 5
275`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_SLC 6:6
276`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_WIDTH 1
277`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_INT_SLC 0:0
278`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_POSITION 6
279`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
280`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
281`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE2_P_POR_VALUE 1'b0
282`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_FID 6
283`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_SLC 5:5
284`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_WIDTH 1
285`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_INT_SLC 0:0
286`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_POSITION 5
287`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
288`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
289`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_SPARE1_P_POR_VALUE 1'b0
290`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_FID 7
291`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_SLC 4:4
292`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_WIDTH 1
293`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_INT_SLC 0:0
294`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_POSITION 4
295`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
296`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
297`define FIRE_DLC_ILU_CIB_CSR_ILU_EN_ERR_IHB_PE_P_POR_VALUE 1'b0
298
299//-------------------------------------------------------
300//----- Variable definitions for register dmu_ilu_cib_csr_ilu_log_err_rw1c_alias
301//-------------------------------------------------------
302
303`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ADDR 27'b000000011001010001000000011
304`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR 30'b000000011001010001000000011000
305`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1C_ALIAS_HW_ADDR 27'b000000011101010001000000011
306`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1C_ALIAS_ADDR 30'b000000011101010001000000011000
307
308`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WIDTH 64
309`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_DEPTH 1
310`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SLC 63:0
311`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_INT_SLC 63:0
312`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_POSITION 0
313`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_LOW_ADDR_WIDTH 0
314`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_ADDR_RANGE 26:0
315`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
316`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
317`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
318`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
319`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
320`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_CLEAR_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
321`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
322`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
323`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
324`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_HW_LD_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
325`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
326`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_INTERNAL_REG 1
327`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_ZERO_TIME_OMNI 1
328`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_NUM_FIELDS 8
329`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_FID 0
330`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_SLC 39:39
331`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_WIDTH 1
332`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_INT_SLC 0:0
333`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_POSITION 39
334`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
335`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
336`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_POR_VALUE 1'b0
337`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_FID 1
338`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_SLC 38:38
339`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_WIDTH 1
340`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_INT_SLC 0:0
341`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_POSITION 38
342`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
343`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
344`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_POR_VALUE 1'b0
345`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_FID 2
346`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_SLC 37:37
347`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_WIDTH 1
348`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_INT_SLC 0:0
349`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_POSITION 37
350`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
351`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
352`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_POR_VALUE 1'b0
353`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_FID 3
354`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_SLC 36:36
355`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_WIDTH 1
356`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_INT_SLC 0:0
357`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_POSITION 36
358`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
359`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
360`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_POR_VALUE 1'b0
361`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_FID 4
362`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_SLC 7:7
363`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_WIDTH 1
364`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_INT_SLC 0:0
365`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_POSITION 7
366`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
367`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
368`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_POR_VALUE 1'b0
369`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_FID 5
370`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_SLC 6:6
371`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_WIDTH 1
372`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_INT_SLC 0:0
373`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_POSITION 6
374`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
375`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
376`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_POR_VALUE 1'b0
377`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_FID 6
378`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_SLC 5:5
379`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_WIDTH 1
380`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_INT_SLC 0:0
381`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_POSITION 5
382`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
383`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
384`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_POR_VALUE 1'b0
385`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_FID 7
386`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_SLC 4:4
387`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_WIDTH 1
388`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_INT_SLC 0:0
389`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_POSITION 4
390`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
391`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
392`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_POR_VALUE 1'b0
393
394//-------------------------------------------------------
395//----- Variable definitions for register dmu_ilu_cib_csr_ilu_log_err_rw1s_alias
396//-------------------------------------------------------
397
398`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR 27'b000000011001010001000000100
399`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR 30'b000000011001010001000000100000
400`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR 27'b000000011101010001000000100
401`define FIRE_DLC_ILU_CIB_CSR_B_ILU_LOG_ERR_RW1S_ALIAS_ADDR 30'b000000011101010001000000100000
402
403`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_WIDTH 64
404`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_DEPTH 1
405`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SLC 63:0
406`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_INT_SLC 63:0
407`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_POSITION 0
408`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_LOW_ADDR_WIDTH 0
409`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_ADDR_RANGE 26:0
410`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
411`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
412`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
413`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
414`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SET_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
415`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
416`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
417`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
418`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
419`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_HW_LD_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
420`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
421`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_INTERNAL_REG 1
422`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_ZERO_TIME_OMNI 1
423`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_NUM_FIELDS 8
424`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_FID 0
425`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_SLC 39:39
426`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_WIDTH 1
427`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_INT_SLC 0:0
428`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_POSITION 39
429`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
430`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
431`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_POR_VALUE 1'b0
432`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_FID 1
433`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_SLC 38:38
434`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_WIDTH 1
435`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_INT_SLC 0:0
436`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_POSITION 38
437`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
438`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
439`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_POR_VALUE 1'b0
440`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_FID 2
441`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_SLC 37:37
442`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_WIDTH 1
443`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_INT_SLC 0:0
444`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_POSITION 37
445`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
446`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
447`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_POR_VALUE 1'b0
448`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_FID 3
449`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_SLC 36:36
450`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_WIDTH 1
451`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_INT_SLC 0:0
452`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_POSITION 36
453`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
454`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
455`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_POR_VALUE 1'b0
456`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_FID 4
457`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_SLC 7:7
458`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_WIDTH 1
459`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_INT_SLC 0:0
460`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_POSITION 7
461`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
462`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
463`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_POR_VALUE 1'b0
464`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_FID 5
465`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_SLC 6:6
466`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_WIDTH 1
467`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_INT_SLC 0:0
468`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_POSITION 6
469`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
470`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
471`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_POR_VALUE 1'b0
472`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_FID 6
473`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_SLC 5:5
474`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_WIDTH 1
475`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_INT_SLC 0:0
476`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_POSITION 5
477`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
478`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
479`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_POR_VALUE 1'b0
480`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_FID 7
481`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_SLC 4:4
482`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_WIDTH 1
483`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_INT_SLC 0:0
484`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_POSITION 4
485`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
486`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
487`define FIRE_DLC_ILU_CIB_CSR_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_POR_VALUE 1'b0
488
489//-------------------------------------------------------
490//----- Variable definitions for register dmu_ilu_cib_csr_pec_int_en
491//-------------------------------------------------------
492
493`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ADDR 27'b000000011001010001100000000
494`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR 30'b000000011001010001100000000000
495`define FIRE_DLC_ILU_CIB_CSR_B_PEC_INT_EN_HW_ADDR 27'b000000011101010001100000000
496`define FIRE_DLC_ILU_CIB_CSR_B_PEC_INT_EN_ADDR 30'b000000011101010001100000000000
497
498`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WIDTH 64
499`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_DEPTH 1
500`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_SLC 63:0
501`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_INT_SLC 63:0
502`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_POSITION 0
503`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_LOW_ADDR_WIDTH 0
504`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_ADDR_RANGE 26:0
505`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_READ_MASK 64'b1000000000000000000000000000000000000000000000000000000000001111
506`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
507`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WRITE_MASK 64'b1000000000000000000000000000000000000000000000000000000000001111
508`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
509`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
510`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
511`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
512`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_RMASK 64'b1000000000000000000000000000000000000000000000000000000000001111
513`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_RESERVED_BIT_MASK 64'b0111111111111111111111111111111111111111111111111111111111110000
514`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
515`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
516`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_INTERNAL_REG 1
517`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_ZERO_TIME_OMNI 1
518`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_NUM_FIELDS 5
519`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_FID 0
520`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_SLC 63:63
521`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_WIDTH 1
522`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_INT_SLC 0:0
523`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_POSITION 63
524`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000
525`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
526`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_POR_VALUE 1'b0
527`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_FID 1
528`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_SLC 3:3
529`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_WIDTH 1
530`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_INT_SLC 0:0
531`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_POSITION 3
532`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
533`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
534`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_ILU_POR_VALUE 1'b0
535`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_FID 2
536`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_SLC 2:2
537`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_WIDTH 1
538`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_INT_SLC 0:0
539`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_POSITION 2
540`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
541`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
542`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_UE_POR_VALUE 1'b0
543`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_FID 3
544`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_SLC 1:1
545`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_WIDTH 1
546`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_INT_SLC 0:0
547`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_POSITION 1
548`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
549`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
550`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_CE_POR_VALUE 1'b0
551`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_FID 4
552`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_SLC 0:0
553`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_WIDTH 1
554`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_INT_SLC 0:0
555`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_POSITION 0
556`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
557`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
558`define FIRE_DLC_ILU_CIB_CSR_PEC_INT_EN_PEC_OE_POR_VALUE 1'b0
559
560//-------------------------------------------------------
561//----- Variable definitions for register dmu_ilu_cib_csr_pec_en_err
562//-------------------------------------------------------
563
564`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ADDR 27'b000000011001010001100000001
565`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR 30'b000000011001010001100000001000
566`define FIRE_DLC_ILU_CIB_CSR_B_PEC_EN_ERR_HW_ADDR 27'b000000011101010001100000001
567`define FIRE_DLC_ILU_CIB_CSR_B_PEC_EN_ERR_ADDR 30'b000000011101010001100000001000
568
569`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_WIDTH 64
570`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_DEPTH 1
571`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_SLC 63:0
572`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_INT_SLC 63:0
573`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_POSITION 0
574`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_LOW_ADDR_WIDTH 0
575`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ADDR_RANGE 26:0
576`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
577`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
578`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
579`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
580`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
581`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
582`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
583`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_RMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
584`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111110000
585`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
586`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
587`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_INTERNAL_REG 0
588`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_EXTERNAL_DECODE_REG 1
589`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ZERO_TIME_OMNI 0
590`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_NUM_FIELDS 4
591`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_FID 0
592`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_SLC 3:3
593`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_WIDTH 1
594`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_INT_SLC 0:0
595`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_POSITION 3
596`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
597`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
598`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_ILU_POR_VALUE 1'b0
599`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_FID 1
600`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_SLC 2:2
601`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_WIDTH 1
602`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_INT_SLC 0:0
603`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_POSITION 2
604`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
605`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
606`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_UE_POR_VALUE 1'b0
607`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_FID 2
608`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_SLC 1:1
609`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_WIDTH 1
610`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_INT_SLC 0:0
611`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_POSITION 1
612`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
613`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
614`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_CE_POR_VALUE 1'b0
615`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_FID 3
616`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_SLC 0:0
617`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_WIDTH 1
618`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_INT_SLC 0:0
619`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_POSITION 0
620`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
621`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
622`define FIRE_DLC_ILU_CIB_CSR_PEC_EN_ERR_OE_POR_VALUE 1'b0
623
624//-------------------------------------------------------
625//----- Variable definitions for register dmu_ilu_cib_csr_ilu_diagnos
626//-------------------------------------------------------
627
628`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ADDR 27'b000000011001010010000000000
629`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR 30'b000000011001010010000000000000
630`define FIRE_DLC_ILU_CIB_CSR_B_ILU_DIAGNOS_HW_ADDR 27'b000000011101010010000000000
631`define FIRE_DLC_ILU_CIB_CSR_B_ILU_DIAGNOS_ADDR 30'b000000011101010010000000000000
632
633`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH 64
634`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_DEPTH 1
635`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_SLC 63:0
636`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_INT_SLC 63:0
637`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_POSITION 0
638`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_LOW_ADDR_WIDTH 0
639`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ADDR_RANGE 26:0
640`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_READ_MASK 64'b0000000000000000000000000000001111111111111111111111111100111100
641`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
642`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WRITE_MASK 64'b0000000000000000000000000000001111111111111111111111111100001100
643`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
644`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000110000
645`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
646`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
647`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RMASK 64'b0000000000000000000000000000001111111111111111111111111100111100
648`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RESERVED_BIT_MASK 64'b1111111111111111111111111111110000000000000000000000000011000011
649`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000110000
650`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_POR_VALUE 64'b0000000000000000000000000000001111111111111111110000000000000000
651`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_INTERNAL_REG 1
652`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ZERO_TIME_OMNI 1
653`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_NUM_FIELDS 23
654`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_FID 0
655`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_SLC 33:33
656`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_WIDTH 1
657`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_INT_SLC 0:0
658`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_POSITION 33
659`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
660`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
661`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL1_POR_VALUE 1'b1
662`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_FID 1
663`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_SLC 32:32
664`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_WIDTH 1
665`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_INT_SLC 0:0
666`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_POSITION 32
667`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
668`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
669`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENPLL0_POR_VALUE 1'b1
670`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_FID 2
671`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_SLC 31:31
672`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_WIDTH 1
673`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_INT_SLC 0:0
674`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_POSITION 31
675`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
676`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
677`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX7_POR_VALUE 1'b1
678`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_FID 3
679`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_SLC 30:30
680`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_WIDTH 1
681`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_INT_SLC 0:0
682`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_POSITION 30
683`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_FMASK 64'b0000000000000000000000000000000001000000000000000000000000000000
684`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
685`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX6_POR_VALUE 1'b1
686`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_FID 4
687`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_SLC 29:29
688`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_WIDTH 1
689`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_INT_SLC 0:0
690`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_POSITION 29
691`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_FMASK 64'b0000000000000000000000000000000000100000000000000000000000000000
692`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
693`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX5_POR_VALUE 1'b1
694`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_FID 5
695`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_SLC 28:28
696`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_WIDTH 1
697`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_INT_SLC 0:0
698`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_POSITION 28
699`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_FMASK 64'b0000000000000000000000000000000000010000000000000000000000000000
700`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
701`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX4_POR_VALUE 1'b1
702`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_FID 6
703`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_SLC 27:27
704`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_WIDTH 1
705`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_INT_SLC 0:0
706`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_POSITION 27
707`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_FMASK 64'b0000000000000000000000000000000000001000000000000000000000000000
708`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
709`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX3_POR_VALUE 1'b1
710`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_FID 7
711`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_SLC 26:26
712`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_WIDTH 1
713`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_INT_SLC 0:0
714`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_POSITION 26
715`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_FMASK 64'b0000000000000000000000000000000000000100000000000000000000000000
716`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
717`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX2_POR_VALUE 1'b1
718`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_FID 8
719`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_SLC 25:25
720`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_WIDTH 1
721`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_INT_SLC 0:0
722`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_POSITION 25
723`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_FMASK 64'b0000000000000000000000000000000000000010000000000000000000000000
724`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
725`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX1_POR_VALUE 1'b1
726`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_FID 9
727`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_SLC 24:24
728`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_WIDTH 1
729`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_INT_SLC 0:0
730`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_POSITION 24
731`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_FMASK 64'b0000000000000000000000000000000000000001000000000000000000000000
732`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
733`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENTX0_POR_VALUE 1'b1
734`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_FID 10
735`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_SLC 23:23
736`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_WIDTH 1
737`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_INT_SLC 0:0
738`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_POSITION 23
739`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_FMASK 64'b0000000000000000000000000000000000000000100000000000000000000000
740`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
741`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX7_POR_VALUE 1'b1
742`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_FID 11
743`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_SLC 22:22
744`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_WIDTH 1
745`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_INT_SLC 0:0
746`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_POSITION 22
747`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_FMASK 64'b0000000000000000000000000000000000000000010000000000000000000000
748`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
749`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX6_POR_VALUE 1'b1
750`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_FID 12
751`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_SLC 21:21
752`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_WIDTH 1
753`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_INT_SLC 0:0
754`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_POSITION 21
755`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_FMASK 64'b0000000000000000000000000000000000000000001000000000000000000000
756`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
757`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX5_POR_VALUE 1'b1
758`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_FID 13
759`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_SLC 20:20
760`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_WIDTH 1
761`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_INT_SLC 0:0
762`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_POSITION 20
763`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
764`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
765`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX4_POR_VALUE 1'b1
766`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_FID 14
767`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_SLC 19:19
768`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_WIDTH 1
769`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_INT_SLC 0:0
770`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_POSITION 19
771`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
772`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
773`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX3_POR_VALUE 1'b1
774`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_FID 15
775`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_SLC 18:18
776`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_WIDTH 1
777`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_INT_SLC 0:0
778`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_POSITION 18
779`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
780`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
781`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX2_POR_VALUE 1'b1
782`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_FID 16
783`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_SLC 17:17
784`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_WIDTH 1
785`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_INT_SLC 0:0
786`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_POSITION 17
787`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
788`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
789`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX1_POR_VALUE 1'b1
790`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_FID 17
791`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_SLC 16:16
792`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_WIDTH 1
793`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_INT_SLC 0:0
794`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_POSITION 16
795`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
796`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
797`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_ENRX0_POR_VALUE 1'b1
798`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_FID 18
799`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_SLC 15:12
800`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_WIDTH 4
801`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_INT_SLC 3:0
802`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_POSITION 12
803`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_FMASK 64'b0000000000000000000000000000000000000000000000001111000000000000
804`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
805`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_PAR_POR_VALUE 4'b0000
806`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_FID 19
807`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_SLC 11:8
808`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_WIDTH 4
809`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_INT_SLC 3:0
810`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_POSITION 8
811`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_FMASK 64'b0000000000000000000000000000000000000000000000000000111100000000
812`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
813`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_PAR_POR_VALUE 4'b0000
814`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_FID 20
815`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_SLC 5:5
816`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_WIDTH 1
817`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_INT_SLC 0:0
818`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_POSITION 5
819`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
820`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
821`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EDI_TRIG_POR_VALUE 1'b0
822`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_FID 21
823`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_SLC 4:4
824`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_WIDTH 1
825`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_INT_SLC 0:0
826`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_POSITION 4
827`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
828`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
829`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_EHI_TRIG_POR_VALUE 1'b0
830`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_FID 22
831`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_SLC 3:2
832`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_WIDTH 2
833`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_INT_SLC 1:0
834`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_POSITION 2
835`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001100
836`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
837`define FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_RATE_SCALE_POR_VALUE 2'b00
838
839
840`endif
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