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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_iil_crdtcnt.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ilu_iil_crdtcnt ( | |
36 | clk, | |
37 | rst_l, | |
38 | cib2iil_pec_drain, | |
39 | k2y_rel_rcd, | |
40 | k2y_rel_enq, | |
41 | d2p_ibc_req, | |
42 | d2p_ibc_nhc, | |
43 | d2p_ibc_phc, | |
44 | d2p_ibc_pdc, | |
45 | p2d_ibc_ack, | |
46 | is_ihb_rcd, | |
47 | credit_type ); | |
48 | ||
49 | ||
50 | // synopsys sync_set_reset "rst_l" | |
51 | ||
52 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
53 | ||
54 | //--------------------------------------------------------------------- | |
55 | // Clock and Reset Signals | |
56 | //--------------------------------------------------------------------- | |
57 | input clk; // input clock | |
58 | input rst_l; // input reset | |
59 | ||
60 | //--------------------------------------------------------------------- | |
61 | // DMA MWr buffer release interface from TMU | |
62 | //--------------------------------------------------------------------- | |
63 | input [8:0] k2y_rel_rcd; // release rcd | |
64 | input k2y_rel_enq; // 1 PCIE FC credit (16-byte data) | |
65 | ||
66 | //--------------------------------------------------------------------- | |
67 | // PCIE FC credits interface to TLU | |
68 | //--------------------------------------------------------------------- | |
69 | output d2p_ibc_req; // request for ingress buffer credits | |
70 | input p2d_ibc_ack; // ack for ingress buffer credits | |
71 | output [7:0] d2p_ibc_nhc; // PCIE FC NPH credits | |
72 | output [7:0] d2p_ibc_phc; // PCIE FC PH credits | |
73 | output [11:0] d2p_ibc_pdc; // PCIE FC PD credits | |
74 | ||
75 | //--------------------------------------------------------------------- | |
76 | // ILU internal module interface | |
77 | //--------------------------------------------------------------------- | |
78 | input cib2iil_pec_drain; // reset FC credits when it is asserted | |
79 | ||
80 | //--------------------------------------------------------------------- | |
81 | // IIL internal interface | |
82 | //--------------------------------------------------------------------- | |
83 | input [1:0] credit_type; | |
84 | // 2'b10 - NPH, 2'b01 - PH, 2'b00 - CPLH | |
85 | input is_ihb_rcd; // collect fc credit, from *xfrfsm.v | |
86 | ||
87 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
88 | ||
89 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
90 | reg d2p_ibc_req; | |
91 | reg [7:0] d2p_ibc_nhc; | |
92 | reg [7:0] d2p_ibc_phc; | |
93 | reg [11:0] d2p_ibc_pdc; | |
94 | ||
95 | reg ibc_req; | |
96 | reg [7:0] ibc_nhc; | |
97 | reg [7:0] ibc_phc; | |
98 | reg [11:0] ibc_pdc; | |
99 | ||
100 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
101 | wire ibc_ack; // sync-flop output | |
102 | ||
103 | wire ld_inc_ibc_pdc; | |
104 | wire ld_inc_ibc_nhc; | |
105 | wire ld_inc_ibc_phc; | |
106 | ||
107 | wire ld_credits; | |
108 | ||
109 | // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
110 | ||
111 | // 0in known_driven -var ld_inc_ibc_pdc | |
112 | // 0in known_driven -var ld_inc_ibc_nhc | |
113 | // 0in known_driven -var ld_inc_ibc_phc | |
114 | // 0in known_driven -var ld_credits | |
115 | ||
116 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< | |
117 | ||
118 | //--------------------------------------------------------------------- | |
119 | // request flops | |
120 | //--------------------------------------------------------------------- | |
121 | always @ (posedge clk) | |
122 | if (!rst_l) begin | |
123 | ibc_req <= 1'b0; | |
124 | end | |
125 | else begin | |
126 | ibc_req <= (ibc_ack ~^ ibc_req) ^ ibc_req; | |
127 | end | |
128 | ||
129 | always @ (posedge clk) | |
130 | if (!rst_l) begin | |
131 | d2p_ibc_req <= 1'b0; | |
132 | end | |
133 | else begin | |
134 | d2p_ibc_req <= ibc_req; | |
135 | end | |
136 | ||
137 | //--------------------------------------------------------------------- | |
138 | // PCIE FC credit flops | |
139 | //--------------------------------------------------------------------- | |
140 | assign ld_inc_ibc_pdc = k2y_rel_enq & k2y_rel_rcd[8]; | |
141 | assign ld_inc_ibc_nhc = credit_type[1] & is_ihb_rcd; | |
142 | assign ld_inc_ibc_phc = credit_type[0] & is_ihb_rcd; | |
143 | ||
144 | always @ (posedge clk) | |
145 | if ((!rst_l) | cib2iil_pec_drain) begin | |
146 | ibc_nhc <= 8'b0; | |
147 | ibc_phc <= 8'b0; | |
148 | ibc_pdc <= 12'b0; | |
149 | end | |
150 | else begin | |
151 | if (ld_inc_ibc_pdc) ibc_pdc <= ibc_pdc + 1'b1; | |
152 | if (ld_inc_ibc_nhc) begin | |
153 | ibc_nhc <= ibc_nhc + 1'b1; | |
154 | end | |
155 | else if (ld_inc_ibc_phc) begin | |
156 | ibc_phc <= ibc_phc + 1'b1; | |
157 | end | |
158 | end | |
159 | ||
160 | assign ld_credits = ibc_req ^ d2p_ibc_req; | |
161 | ||
162 | always @ (posedge clk) | |
163 | begin | |
164 | if (!rst_l) begin | |
165 | d2p_ibc_nhc <= 8'b0; | |
166 | d2p_ibc_phc <= 8'b0; | |
167 | d2p_ibc_pdc <= 12'b0; | |
168 | end | |
169 | else begin | |
170 | if (ld_credits) begin | |
171 | d2p_ibc_pdc <= ibc_pdc; | |
172 | d2p_ibc_phc <= ibc_phc; | |
173 | d2p_ibc_nhc <= ibc_nhc; | |
174 | end | |
175 | end | |
176 | end | |
177 | ||
178 | ||
179 | // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
180 | ||
181 | // sync flop | |
182 | // pcie_common_sync_flop #(1) sync_flop( | |
183 | // .clk(clk), | |
184 | // .din(p2d_ibc_ack), | |
185 | // .dout(ibc_ack)); | |
186 | cl_a1_clksyncff_4x sync_flop ( .d(p2d_ibc_ack), .si(1'b0), .q( ibc_ack), .so(), | |
187 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); | |
188 | ||
189 | endmodule // dmu_ilu_iil_crdtcnt | |
190 | ||
191 |