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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_eqs_csr_eq_head.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_eqs_csr_eq_head.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_eqs_csr_eq_head
36 (
37 clk,
38 rst_l,
39 eq_head_w_ld_0,
40 eq_head_w_ld_1,
41 eq_head_w_ld_2,
42 eq_head_w_ld_3,
43 eq_head_w_ld_4,
44 eq_head_w_ld_5,
45 eq_head_w_ld_6,
46 eq_head_w_ld_7,
47 eq_head_w_ld_8,
48 eq_head_w_ld_9,
49 eq_head_w_ld_10,
50 eq_head_w_ld_11,
51 eq_head_w_ld_12,
52 eq_head_w_ld_13,
53 eq_head_w_ld_14,
54 eq_head_w_ld_15,
55 eq_head_w_ld_16,
56 eq_head_w_ld_17,
57 eq_head_w_ld_18,
58 eq_head_w_ld_19,
59 eq_head_w_ld_20,
60 eq_head_w_ld_21,
61 eq_head_w_ld_22,
62 eq_head_w_ld_23,
63 eq_head_w_ld_24,
64 eq_head_w_ld_25,
65 eq_head_w_ld_26,
66 eq_head_w_ld_27,
67 eq_head_w_ld_28,
68 eq_head_w_ld_29,
69 eq_head_w_ld_30,
70 eq_head_w_ld_31,
71 eq_head_w_ld_32,
72 eq_head_w_ld_33,
73 eq_head_w_ld_34,
74 eq_head_w_ld_35,
75 csrbus_wr_data,
76 eq_head_csrbus_read_data_0,
77 eq_head_csrbus_read_data_1,
78 eq_head_csrbus_read_data_2,
79 eq_head_csrbus_read_data_3,
80 eq_head_csrbus_read_data_4,
81 eq_head_csrbus_read_data_5,
82 eq_head_csrbus_read_data_6,
83 eq_head_csrbus_read_data_7,
84 eq_head_csrbus_read_data_8,
85 eq_head_csrbus_read_data_9,
86 eq_head_csrbus_read_data_10,
87 eq_head_csrbus_read_data_11,
88 eq_head_csrbus_read_data_12,
89 eq_head_csrbus_read_data_13,
90 eq_head_csrbus_read_data_14,
91 eq_head_csrbus_read_data_15,
92 eq_head_csrbus_read_data_16,
93 eq_head_csrbus_read_data_17,
94 eq_head_csrbus_read_data_18,
95 eq_head_csrbus_read_data_19,
96 eq_head_csrbus_read_data_20,
97 eq_head_csrbus_read_data_21,
98 eq_head_csrbus_read_data_22,
99 eq_head_csrbus_read_data_23,
100 eq_head_csrbus_read_data_24,
101 eq_head_csrbus_read_data_25,
102 eq_head_csrbus_read_data_26,
103 eq_head_csrbus_read_data_27,
104 eq_head_csrbus_read_data_28,
105 eq_head_csrbus_read_data_29,
106 eq_head_csrbus_read_data_30,
107 eq_head_csrbus_read_data_31,
108 eq_head_csrbus_read_data_32,
109 eq_head_csrbus_read_data_33,
110 eq_head_csrbus_read_data_34,
111 eq_head_csrbus_read_data_35,
112 eq_head_head_hw_read_0,
113 eq_head_head_hw_read_1,
114 eq_head_head_hw_read_2,
115 eq_head_head_hw_read_3,
116 eq_head_head_hw_read_4,
117 eq_head_head_hw_read_5,
118 eq_head_head_hw_read_6,
119 eq_head_head_hw_read_7,
120 eq_head_head_hw_read_8,
121 eq_head_head_hw_read_9,
122 eq_head_head_hw_read_10,
123 eq_head_head_hw_read_11,
124 eq_head_head_hw_read_12,
125 eq_head_head_hw_read_13,
126 eq_head_head_hw_read_14,
127 eq_head_head_hw_read_15,
128 eq_head_head_hw_read_16,
129 eq_head_head_hw_read_17,
130 eq_head_head_hw_read_18,
131 eq_head_head_hw_read_19,
132 eq_head_head_hw_read_20,
133 eq_head_head_hw_read_21,
134 eq_head_head_hw_read_22,
135 eq_head_head_hw_read_23,
136 eq_head_head_hw_read_24,
137 eq_head_head_hw_read_25,
138 eq_head_head_hw_read_26,
139 eq_head_head_hw_read_27,
140 eq_head_head_hw_read_28,
141 eq_head_head_hw_read_29,
142 eq_head_head_hw_read_30,
143 eq_head_head_hw_read_31,
144 eq_head_head_hw_read_32,
145 eq_head_head_hw_read_33,
146 eq_head_head_hw_read_34,
147 eq_head_head_hw_read_35
148 );
149
150//====================================================================
151// Polarity declarations
152//====================================================================
153input clk; // Clock
154input rst_l; // Reset signal
155input eq_head_w_ld_0; // SW load bus
156input eq_head_w_ld_1; // SW load bus
157input eq_head_w_ld_2; // SW load bus
158input eq_head_w_ld_3; // SW load bus
159input eq_head_w_ld_4; // SW load bus
160input eq_head_w_ld_5; // SW load bus
161input eq_head_w_ld_6; // SW load bus
162input eq_head_w_ld_7; // SW load bus
163input eq_head_w_ld_8; // SW load bus
164input eq_head_w_ld_9; // SW load bus
165input eq_head_w_ld_10; // SW load bus
166input eq_head_w_ld_11; // SW load bus
167input eq_head_w_ld_12; // SW load bus
168input eq_head_w_ld_13; // SW load bus
169input eq_head_w_ld_14; // SW load bus
170input eq_head_w_ld_15; // SW load bus
171input eq_head_w_ld_16; // SW load bus
172input eq_head_w_ld_17; // SW load bus
173input eq_head_w_ld_18; // SW load bus
174input eq_head_w_ld_19; // SW load bus
175input eq_head_w_ld_20; // SW load bus
176input eq_head_w_ld_21; // SW load bus
177input eq_head_w_ld_22; // SW load bus
178input eq_head_w_ld_23; // SW load bus
179input eq_head_w_ld_24; // SW load bus
180input eq_head_w_ld_25; // SW load bus
181input eq_head_w_ld_26; // SW load bus
182input eq_head_w_ld_27; // SW load bus
183input eq_head_w_ld_28; // SW load bus
184input eq_head_w_ld_29; // SW load bus
185input eq_head_w_ld_30; // SW load bus
186input eq_head_w_ld_31; // SW load bus
187input eq_head_w_ld_32; // SW load bus
188input eq_head_w_ld_33; // SW load bus
189input eq_head_w_ld_34; // SW load bus
190input eq_head_w_ld_35; // SW load bus
191input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
192output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_0;
193 // SW read data
194output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_1;
195 // SW read data
196output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_2;
197 // SW read data
198output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_3;
199 // SW read data
200output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_4;
201 // SW read data
202output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_5;
203 // SW read data
204output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_6;
205 // SW read data
206output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_7;
207 // SW read data
208output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_8;
209 // SW read data
210output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_9;
211 // SW read data
212output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_10;
213 // SW read data
214output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_11;
215 // SW read data
216output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_12;
217 // SW read data
218output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_13;
219 // SW read data
220output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_14;
221 // SW read data
222output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_15;
223 // SW read data
224output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_16;
225 // SW read data
226output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_17;
227 // SW read data
228output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_18;
229 // SW read data
230output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_19;
231 // SW read data
232output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_20;
233 // SW read data
234output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_21;
235 // SW read data
236output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_22;
237 // SW read data
238output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_23;
239 // SW read data
240output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_24;
241 // SW read data
242output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_25;
243 // SW read data
244output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_26;
245 // SW read data
246output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_27;
247 // SW read data
248output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_28;
249 // SW read data
250output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_29;
251 // SW read data
252output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_30;
253 // SW read data
254output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_31;
255 // SW read data
256output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_32;
257 // SW read data
258output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_33;
259 // SW read data
260output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_34;
261 // SW read data
262output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_35;
263 // SW read data
264output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_0;
265 // This signal provides the current value of eq_head_head.
266output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_1;
267 // This signal provides the current value of eq_head_head.
268output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_2;
269 // This signal provides the current value of eq_head_head.
270output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_3;
271 // This signal provides the current value of eq_head_head.
272output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_4;
273 // This signal provides the current value of eq_head_head.
274output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_5;
275 // This signal provides the current value of eq_head_head.
276output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_6;
277 // This signal provides the current value of eq_head_head.
278output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_7;
279 // This signal provides the current value of eq_head_head.
280output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_8;
281 // This signal provides the current value of eq_head_head.
282output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_9;
283 // This signal provides the current value of eq_head_head.
284output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_10;
285 // This signal provides the current value of eq_head_head.
286output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_11;
287 // This signal provides the current value of eq_head_head.
288output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_12;
289 // This signal provides the current value of eq_head_head.
290output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_13;
291 // This signal provides the current value of eq_head_head.
292output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_14;
293 // This signal provides the current value of eq_head_head.
294output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_15;
295 // This signal provides the current value of eq_head_head.
296output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_16;
297 // This signal provides the current value of eq_head_head.
298output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_17;
299 // This signal provides the current value of eq_head_head.
300output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_18;
301 // This signal provides the current value of eq_head_head.
302output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_19;
303 // This signal provides the current value of eq_head_head.
304output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_20;
305 // This signal provides the current value of eq_head_head.
306output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_21;
307 // This signal provides the current value of eq_head_head.
308output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_22;
309 // This signal provides the current value of eq_head_head.
310output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_23;
311 // This signal provides the current value of eq_head_head.
312output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_24;
313 // This signal provides the current value of eq_head_head.
314output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_25;
315 // This signal provides the current value of eq_head_head.
316output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_26;
317 // This signal provides the current value of eq_head_head.
318output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_27;
319 // This signal provides the current value of eq_head_head.
320output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_28;
321 // This signal provides the current value of eq_head_head.
322output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_29;
323 // This signal provides the current value of eq_head_head.
324output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_30;
325 // This signal provides the current value of eq_head_head.
326output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_31;
327 // This signal provides the current value of eq_head_head.
328output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_32;
329 // This signal provides the current value of eq_head_head.
330output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_33;
331 // This signal provides the current value of eq_head_head.
332output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_34;
333 // This signal provides the current value of eq_head_head.
334output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_35;
335 // This signal provides the current value of eq_head_head.
336
337//====================================================================
338// Type declarations
339//====================================================================
340wire clk; // Clock
341wire rst_l; // Reset signal
342wire eq_head_w_ld_0; // SW load bus
343wire eq_head_w_ld_1; // SW load bus
344wire eq_head_w_ld_2; // SW load bus
345wire eq_head_w_ld_3; // SW load bus
346wire eq_head_w_ld_4; // SW load bus
347wire eq_head_w_ld_5; // SW load bus
348wire eq_head_w_ld_6; // SW load bus
349wire eq_head_w_ld_7; // SW load bus
350wire eq_head_w_ld_8; // SW load bus
351wire eq_head_w_ld_9; // SW load bus
352wire eq_head_w_ld_10; // SW load bus
353wire eq_head_w_ld_11; // SW load bus
354wire eq_head_w_ld_12; // SW load bus
355wire eq_head_w_ld_13; // SW load bus
356wire eq_head_w_ld_14; // SW load bus
357wire eq_head_w_ld_15; // SW load bus
358wire eq_head_w_ld_16; // SW load bus
359wire eq_head_w_ld_17; // SW load bus
360wire eq_head_w_ld_18; // SW load bus
361wire eq_head_w_ld_19; // SW load bus
362wire eq_head_w_ld_20; // SW load bus
363wire eq_head_w_ld_21; // SW load bus
364wire eq_head_w_ld_22; // SW load bus
365wire eq_head_w_ld_23; // SW load bus
366wire eq_head_w_ld_24; // SW load bus
367wire eq_head_w_ld_25; // SW load bus
368wire eq_head_w_ld_26; // SW load bus
369wire eq_head_w_ld_27; // SW load bus
370wire eq_head_w_ld_28; // SW load bus
371wire eq_head_w_ld_29; // SW load bus
372wire eq_head_w_ld_30; // SW load bus
373wire eq_head_w_ld_31; // SW load bus
374wire eq_head_w_ld_32; // SW load bus
375wire eq_head_w_ld_33; // SW load bus
376wire eq_head_w_ld_34; // SW load bus
377wire eq_head_w_ld_35; // SW load bus
378wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
379wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_0;
380 // SW read data
381wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_1;
382 // SW read data
383wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_2;
384 // SW read data
385wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_3;
386 // SW read data
387wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_4;
388 // SW read data
389wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_5;
390 // SW read data
391wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_6;
392 // SW read data
393wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_7;
394 // SW read data
395wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_8;
396 // SW read data
397wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_9;
398 // SW read data
399wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_10;
400 // SW read data
401wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_11;
402 // SW read data
403wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_12;
404 // SW read data
405wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_13;
406 // SW read data
407wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_14;
408 // SW read data
409wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_15;
410 // SW read data
411wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_16;
412 // SW read data
413wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_17;
414 // SW read data
415wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_18;
416 // SW read data
417wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_19;
418 // SW read data
419wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_20;
420 // SW read data
421wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_21;
422 // SW read data
423wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_22;
424 // SW read data
425wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_23;
426 // SW read data
427wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_24;
428 // SW read data
429wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_25;
430 // SW read data
431wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_26;
432 // SW read data
433wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_27;
434 // SW read data
435wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_28;
436 // SW read data
437wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_29;
438 // SW read data
439wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_30;
440 // SW read data
441wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_31;
442 // SW read data
443wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_32;
444 // SW read data
445wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_33;
446 // SW read data
447wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_34;
448 // SW read data
449wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data_35;
450 // SW read data
451wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_0;
452 // This signal provides the current value of eq_head_head.
453wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_1;
454 // This signal provides the current value of eq_head_head.
455wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_2;
456 // This signal provides the current value of eq_head_head.
457wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_3;
458 // This signal provides the current value of eq_head_head.
459wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_4;
460 // This signal provides the current value of eq_head_head.
461wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_5;
462 // This signal provides the current value of eq_head_head.
463wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_6;
464 // This signal provides the current value of eq_head_head.
465wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_7;
466 // This signal provides the current value of eq_head_head.
467wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_8;
468 // This signal provides the current value of eq_head_head.
469wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_9;
470 // This signal provides the current value of eq_head_head.
471wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_10;
472 // This signal provides the current value of eq_head_head.
473wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_11;
474 // This signal provides the current value of eq_head_head.
475wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_12;
476 // This signal provides the current value of eq_head_head.
477wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_13;
478 // This signal provides the current value of eq_head_head.
479wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_14;
480 // This signal provides the current value of eq_head_head.
481wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_15;
482 // This signal provides the current value of eq_head_head.
483wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_16;
484 // This signal provides the current value of eq_head_head.
485wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_17;
486 // This signal provides the current value of eq_head_head.
487wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_18;
488 // This signal provides the current value of eq_head_head.
489wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_19;
490 // This signal provides the current value of eq_head_head.
491wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_20;
492 // This signal provides the current value of eq_head_head.
493wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_21;
494 // This signal provides the current value of eq_head_head.
495wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_22;
496 // This signal provides the current value of eq_head_head.
497wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_23;
498 // This signal provides the current value of eq_head_head.
499wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_24;
500 // This signal provides the current value of eq_head_head.
501wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_25;
502 // This signal provides the current value of eq_head_head.
503wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_26;
504 // This signal provides the current value of eq_head_head.
505wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_27;
506 // This signal provides the current value of eq_head_head.
507wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_28;
508 // This signal provides the current value of eq_head_head.
509wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_29;
510 // This signal provides the current value of eq_head_head.
511wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_30;
512 // This signal provides the current value of eq_head_head.
513wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_31;
514 // This signal provides the current value of eq_head_head.
515wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_32;
516 // This signal provides the current value of eq_head_head.
517wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_33;
518 // This signal provides the current value of eq_head_head.
519wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_34;
520 // This signal provides the current value of eq_head_head.
521wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC] eq_head_head_hw_read_35;
522 // This signal provides the current value of eq_head_head.
523
524//====================================================================
525// Logic
526//====================================================================
527
528// synopsys translate_off
529// verilint 123 off
530// verilint 498 off
531reg omni_ld_0;
532reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_0;
533
534// vlint flag_unsynthesizable_initial off
535initial
536 begin
537 omni_ld_0 = 1'b0;
538 omni_data_0 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
539 end// vlint flag_unsynthesizable_initial on
540
541reg omni_ld_1;
542reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_1;
543
544// vlint flag_unsynthesizable_initial off
545initial
546 begin
547 omni_ld_1 = 1'b0;
548 omni_data_1 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
549 end// vlint flag_unsynthesizable_initial on
550
551reg omni_ld_2;
552reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_2;
553
554// vlint flag_unsynthesizable_initial off
555initial
556 begin
557 omni_ld_2 = 1'b0;
558 omni_data_2 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
559 end// vlint flag_unsynthesizable_initial on
560
561reg omni_ld_3;
562reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_3;
563
564// vlint flag_unsynthesizable_initial off
565initial
566 begin
567 omni_ld_3 = 1'b0;
568 omni_data_3 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
569 end// vlint flag_unsynthesizable_initial on
570
571reg omni_ld_4;
572reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_4;
573
574// vlint flag_unsynthesizable_initial off
575initial
576 begin
577 omni_ld_4 = 1'b0;
578 omni_data_4 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
579 end// vlint flag_unsynthesizable_initial on
580
581reg omni_ld_5;
582reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_5;
583
584// vlint flag_unsynthesizable_initial off
585initial
586 begin
587 omni_ld_5 = 1'b0;
588 omni_data_5 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
589 end// vlint flag_unsynthesizable_initial on
590
591reg omni_ld_6;
592reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_6;
593
594// vlint flag_unsynthesizable_initial off
595initial
596 begin
597 omni_ld_6 = 1'b0;
598 omni_data_6 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
599 end// vlint flag_unsynthesizable_initial on
600
601reg omni_ld_7;
602reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_7;
603
604// vlint flag_unsynthesizable_initial off
605initial
606 begin
607 omni_ld_7 = 1'b0;
608 omni_data_7 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
609 end// vlint flag_unsynthesizable_initial on
610
611reg omni_ld_8;
612reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_8;
613
614// vlint flag_unsynthesizable_initial off
615initial
616 begin
617 omni_ld_8 = 1'b0;
618 omni_data_8 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
619 end// vlint flag_unsynthesizable_initial on
620
621reg omni_ld_9;
622reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_9;
623
624// vlint flag_unsynthesizable_initial off
625initial
626 begin
627 omni_ld_9 = 1'b0;
628 omni_data_9 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
629 end// vlint flag_unsynthesizable_initial on
630
631reg omni_ld_10;
632reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_10;
633
634// vlint flag_unsynthesizable_initial off
635initial
636 begin
637 omni_ld_10 = 1'b0;
638 omni_data_10 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
639 end// vlint flag_unsynthesizable_initial on
640
641reg omni_ld_11;
642reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_11;
643
644// vlint flag_unsynthesizable_initial off
645initial
646 begin
647 omni_ld_11 = 1'b0;
648 omni_data_11 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
649 end// vlint flag_unsynthesizable_initial on
650
651reg omni_ld_12;
652reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_12;
653
654// vlint flag_unsynthesizable_initial off
655initial
656 begin
657 omni_ld_12 = 1'b0;
658 omni_data_12 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
659 end// vlint flag_unsynthesizable_initial on
660
661reg omni_ld_13;
662reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_13;
663
664// vlint flag_unsynthesizable_initial off
665initial
666 begin
667 omni_ld_13 = 1'b0;
668 omni_data_13 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
669 end// vlint flag_unsynthesizable_initial on
670
671reg omni_ld_14;
672reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_14;
673
674// vlint flag_unsynthesizable_initial off
675initial
676 begin
677 omni_ld_14 = 1'b0;
678 omni_data_14 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
679 end// vlint flag_unsynthesizable_initial on
680
681reg omni_ld_15;
682reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_15;
683
684// vlint flag_unsynthesizable_initial off
685initial
686 begin
687 omni_ld_15 = 1'b0;
688 omni_data_15 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
689 end// vlint flag_unsynthesizable_initial on
690
691reg omni_ld_16;
692reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_16;
693
694// vlint flag_unsynthesizable_initial off
695initial
696 begin
697 omni_ld_16 = 1'b0;
698 omni_data_16 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
699 end// vlint flag_unsynthesizable_initial on
700
701reg omni_ld_17;
702reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_17;
703
704// vlint flag_unsynthesizable_initial off
705initial
706 begin
707 omni_ld_17 = 1'b0;
708 omni_data_17 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
709 end// vlint flag_unsynthesizable_initial on
710
711reg omni_ld_18;
712reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_18;
713
714// vlint flag_unsynthesizable_initial off
715initial
716 begin
717 omni_ld_18 = 1'b0;
718 omni_data_18 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
719 end// vlint flag_unsynthesizable_initial on
720
721reg omni_ld_19;
722reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_19;
723
724// vlint flag_unsynthesizable_initial off
725initial
726 begin
727 omni_ld_19 = 1'b0;
728 omni_data_19 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
729 end// vlint flag_unsynthesizable_initial on
730
731reg omni_ld_20;
732reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_20;
733
734// vlint flag_unsynthesizable_initial off
735initial
736 begin
737 omni_ld_20 = 1'b0;
738 omni_data_20 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
739 end// vlint flag_unsynthesizable_initial on
740
741reg omni_ld_21;
742reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_21;
743
744// vlint flag_unsynthesizable_initial off
745initial
746 begin
747 omni_ld_21 = 1'b0;
748 omni_data_21 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
749 end// vlint flag_unsynthesizable_initial on
750
751reg omni_ld_22;
752reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_22;
753
754// vlint flag_unsynthesizable_initial off
755initial
756 begin
757 omni_ld_22 = 1'b0;
758 omni_data_22 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
759 end// vlint flag_unsynthesizable_initial on
760
761reg omni_ld_23;
762reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_23;
763
764// vlint flag_unsynthesizable_initial off
765initial
766 begin
767 omni_ld_23 = 1'b0;
768 omni_data_23 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
769 end// vlint flag_unsynthesizable_initial on
770
771reg omni_ld_24;
772reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_24;
773
774// vlint flag_unsynthesizable_initial off
775initial
776 begin
777 omni_ld_24 = 1'b0;
778 omni_data_24 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
779 end// vlint flag_unsynthesizable_initial on
780
781reg omni_ld_25;
782reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_25;
783
784// vlint flag_unsynthesizable_initial off
785initial
786 begin
787 omni_ld_25 = 1'b0;
788 omni_data_25 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
789 end// vlint flag_unsynthesizable_initial on
790
791reg omni_ld_26;
792reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_26;
793
794// vlint flag_unsynthesizable_initial off
795initial
796 begin
797 omni_ld_26 = 1'b0;
798 omni_data_26 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
799 end// vlint flag_unsynthesizable_initial on
800
801reg omni_ld_27;
802reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_27;
803
804// vlint flag_unsynthesizable_initial off
805initial
806 begin
807 omni_ld_27 = 1'b0;
808 omni_data_27 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
809 end// vlint flag_unsynthesizable_initial on
810
811reg omni_ld_28;
812reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_28;
813
814// vlint flag_unsynthesizable_initial off
815initial
816 begin
817 omni_ld_28 = 1'b0;
818 omni_data_28 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
819 end// vlint flag_unsynthesizable_initial on
820
821reg omni_ld_29;
822reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_29;
823
824// vlint flag_unsynthesizable_initial off
825initial
826 begin
827 omni_ld_29 = 1'b0;
828 omni_data_29 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
829 end// vlint flag_unsynthesizable_initial on
830
831reg omni_ld_30;
832reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_30;
833
834// vlint flag_unsynthesizable_initial off
835initial
836 begin
837 omni_ld_30 = 1'b0;
838 omni_data_30 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
839 end// vlint flag_unsynthesizable_initial on
840
841reg omni_ld_31;
842reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_31;
843
844// vlint flag_unsynthesizable_initial off
845initial
846 begin
847 omni_ld_31 = 1'b0;
848 omni_data_31 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
849 end// vlint flag_unsynthesizable_initial on
850
851reg omni_ld_32;
852reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_32;
853
854// vlint flag_unsynthesizable_initial off
855initial
856 begin
857 omni_ld_32 = 1'b0;
858 omni_data_32 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
859 end// vlint flag_unsynthesizable_initial on
860
861reg omni_ld_33;
862reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_33;
863
864// vlint flag_unsynthesizable_initial off
865initial
866 begin
867 omni_ld_33 = 1'b0;
868 omni_data_33 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
869 end// vlint flag_unsynthesizable_initial on
870
871reg omni_ld_34;
872reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_34;
873
874// vlint flag_unsynthesizable_initial off
875initial
876 begin
877 omni_ld_34 = 1'b0;
878 omni_data_34 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
879 end// vlint flag_unsynthesizable_initial on
880
881reg omni_ld_35;
882reg [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] omni_data_35;
883
884// vlint flag_unsynthesizable_initial off
885initial
886 begin
887 omni_ld_35 = 1'b0;
888 omni_data_35 = `FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH'b0;
889 end// vlint flag_unsynthesizable_initial on
890
891// verilint 123 on
892// verilint 498 on
893// synopsys translate_on
894
895//----- Hardware Data Out Mux Assignments
896assign eq_head_head_hw_read_0=
897 eq_head_csrbus_read_data_0
898 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
899assign eq_head_head_hw_read_1=
900 eq_head_csrbus_read_data_1
901 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
902assign eq_head_head_hw_read_2=
903 eq_head_csrbus_read_data_2
904 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
905assign eq_head_head_hw_read_3=
906 eq_head_csrbus_read_data_3
907 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
908assign eq_head_head_hw_read_4=
909 eq_head_csrbus_read_data_4
910 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
911assign eq_head_head_hw_read_5=
912 eq_head_csrbus_read_data_5
913 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
914assign eq_head_head_hw_read_6=
915 eq_head_csrbus_read_data_6
916 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
917assign eq_head_head_hw_read_7=
918 eq_head_csrbus_read_data_7
919 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
920assign eq_head_head_hw_read_8=
921 eq_head_csrbus_read_data_8
922 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
923assign eq_head_head_hw_read_9=
924 eq_head_csrbus_read_data_9
925 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
926assign eq_head_head_hw_read_10=
927 eq_head_csrbus_read_data_10
928 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
929assign eq_head_head_hw_read_11=
930 eq_head_csrbus_read_data_11
931 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
932assign eq_head_head_hw_read_12=
933 eq_head_csrbus_read_data_12
934 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
935assign eq_head_head_hw_read_13=
936 eq_head_csrbus_read_data_13
937 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
938assign eq_head_head_hw_read_14=
939 eq_head_csrbus_read_data_14
940 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
941assign eq_head_head_hw_read_15=
942 eq_head_csrbus_read_data_15
943 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
944assign eq_head_head_hw_read_16=
945 eq_head_csrbus_read_data_16
946 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
947assign eq_head_head_hw_read_17=
948 eq_head_csrbus_read_data_17
949 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
950assign eq_head_head_hw_read_18=
951 eq_head_csrbus_read_data_18
952 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
953assign eq_head_head_hw_read_19=
954 eq_head_csrbus_read_data_19
955 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
956assign eq_head_head_hw_read_20=
957 eq_head_csrbus_read_data_20
958 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
959assign eq_head_head_hw_read_21=
960 eq_head_csrbus_read_data_21
961 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
962assign eq_head_head_hw_read_22=
963 eq_head_csrbus_read_data_22
964 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
965assign eq_head_head_hw_read_23=
966 eq_head_csrbus_read_data_23
967 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
968assign eq_head_head_hw_read_24=
969 eq_head_csrbus_read_data_24
970 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
971assign eq_head_head_hw_read_25=
972 eq_head_csrbus_read_data_25
973 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
974assign eq_head_head_hw_read_26=
975 eq_head_csrbus_read_data_26
976 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
977assign eq_head_head_hw_read_27=
978 eq_head_csrbus_read_data_27
979 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
980assign eq_head_head_hw_read_28=
981 eq_head_csrbus_read_data_28
982 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
983assign eq_head_head_hw_read_29=
984 eq_head_csrbus_read_data_29
985 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
986assign eq_head_head_hw_read_30=
987 eq_head_csrbus_read_data_30
988 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
989assign eq_head_head_hw_read_31=
990 eq_head_csrbus_read_data_31
991 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
992assign eq_head_head_hw_read_32=
993 eq_head_csrbus_read_data_32
994 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
995assign eq_head_head_hw_read_33=
996 eq_head_csrbus_read_data_33
997 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
998assign eq_head_head_hw_read_34=
999 eq_head_csrbus_read_data_34
1000 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
1001assign eq_head_head_hw_read_35=
1002 eq_head_csrbus_read_data_35
1003 [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC];
1004
1005//====================================================================
1006// Instantiation of entries
1007//====================================================================
1008
1009//----- Entry 0
1010dmu_imu_eqs_csr_eq_head_entry eq_head_0
1011 (
1012 // synopsys translate_off
1013 .omni_ld (omni_ld_0),
1014 .omni_data (omni_data_0),
1015 // synopsys translate_on
1016 .clk (clk),
1017 .rst_l (rst_l),
1018 .w_ld (eq_head_w_ld_0),
1019 .csrbus_wr_data (csrbus_wr_data),
1020 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_0)
1021 );
1022
1023//----- Entry 1
1024dmu_imu_eqs_csr_eq_head_entry eq_head_1
1025 (
1026 // synopsys translate_off
1027 .omni_ld (omni_ld_1),
1028 .omni_data (omni_data_1),
1029 // synopsys translate_on
1030 .clk (clk),
1031 .rst_l (rst_l),
1032 .w_ld (eq_head_w_ld_1),
1033 .csrbus_wr_data (csrbus_wr_data),
1034 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_1)
1035 );
1036
1037//----- Entry 2
1038dmu_imu_eqs_csr_eq_head_entry eq_head_2
1039 (
1040 // synopsys translate_off
1041 .omni_ld (omni_ld_2),
1042 .omni_data (omni_data_2),
1043 // synopsys translate_on
1044 .clk (clk),
1045 .rst_l (rst_l),
1046 .w_ld (eq_head_w_ld_2),
1047 .csrbus_wr_data (csrbus_wr_data),
1048 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_2)
1049 );
1050
1051//----- Entry 3
1052dmu_imu_eqs_csr_eq_head_entry eq_head_3
1053 (
1054 // synopsys translate_off
1055 .omni_ld (omni_ld_3),
1056 .omni_data (omni_data_3),
1057 // synopsys translate_on
1058 .clk (clk),
1059 .rst_l (rst_l),
1060 .w_ld (eq_head_w_ld_3),
1061 .csrbus_wr_data (csrbus_wr_data),
1062 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_3)
1063 );
1064
1065//----- Entry 4
1066dmu_imu_eqs_csr_eq_head_entry eq_head_4
1067 (
1068 // synopsys translate_off
1069 .omni_ld (omni_ld_4),
1070 .omni_data (omni_data_4),
1071 // synopsys translate_on
1072 .clk (clk),
1073 .rst_l (rst_l),
1074 .w_ld (eq_head_w_ld_4),
1075 .csrbus_wr_data (csrbus_wr_data),
1076 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_4)
1077 );
1078
1079//----- Entry 5
1080dmu_imu_eqs_csr_eq_head_entry eq_head_5
1081 (
1082 // synopsys translate_off
1083 .omni_ld (omni_ld_5),
1084 .omni_data (omni_data_5),
1085 // synopsys translate_on
1086 .clk (clk),
1087 .rst_l (rst_l),
1088 .w_ld (eq_head_w_ld_5),
1089 .csrbus_wr_data (csrbus_wr_data),
1090 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_5)
1091 );
1092
1093//----- Entry 6
1094dmu_imu_eqs_csr_eq_head_entry eq_head_6
1095 (
1096 // synopsys translate_off
1097 .omni_ld (omni_ld_6),
1098 .omni_data (omni_data_6),
1099 // synopsys translate_on
1100 .clk (clk),
1101 .rst_l (rst_l),
1102 .w_ld (eq_head_w_ld_6),
1103 .csrbus_wr_data (csrbus_wr_data),
1104 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_6)
1105 );
1106
1107//----- Entry 7
1108dmu_imu_eqs_csr_eq_head_entry eq_head_7
1109 (
1110 // synopsys translate_off
1111 .omni_ld (omni_ld_7),
1112 .omni_data (omni_data_7),
1113 // synopsys translate_on
1114 .clk (clk),
1115 .rst_l (rst_l),
1116 .w_ld (eq_head_w_ld_7),
1117 .csrbus_wr_data (csrbus_wr_data),
1118 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_7)
1119 );
1120
1121//----- Entry 8
1122dmu_imu_eqs_csr_eq_head_entry eq_head_8
1123 (
1124 // synopsys translate_off
1125 .omni_ld (omni_ld_8),
1126 .omni_data (omni_data_8),
1127 // synopsys translate_on
1128 .clk (clk),
1129 .rst_l (rst_l),
1130 .w_ld (eq_head_w_ld_8),
1131 .csrbus_wr_data (csrbus_wr_data),
1132 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_8)
1133 );
1134
1135//----- Entry 9
1136dmu_imu_eqs_csr_eq_head_entry eq_head_9
1137 (
1138 // synopsys translate_off
1139 .omni_ld (omni_ld_9),
1140 .omni_data (omni_data_9),
1141 // synopsys translate_on
1142 .clk (clk),
1143 .rst_l (rst_l),
1144 .w_ld (eq_head_w_ld_9),
1145 .csrbus_wr_data (csrbus_wr_data),
1146 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_9)
1147 );
1148
1149//----- Entry 10
1150dmu_imu_eqs_csr_eq_head_entry eq_head_10
1151 (
1152 // synopsys translate_off
1153 .omni_ld (omni_ld_10),
1154 .omni_data (omni_data_10),
1155 // synopsys translate_on
1156 .clk (clk),
1157 .rst_l (rst_l),
1158 .w_ld (eq_head_w_ld_10),
1159 .csrbus_wr_data (csrbus_wr_data),
1160 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_10)
1161 );
1162
1163//----- Entry 11
1164dmu_imu_eqs_csr_eq_head_entry eq_head_11
1165 (
1166 // synopsys translate_off
1167 .omni_ld (omni_ld_11),
1168 .omni_data (omni_data_11),
1169 // synopsys translate_on
1170 .clk (clk),
1171 .rst_l (rst_l),
1172 .w_ld (eq_head_w_ld_11),
1173 .csrbus_wr_data (csrbus_wr_data),
1174 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_11)
1175 );
1176
1177//----- Entry 12
1178dmu_imu_eqs_csr_eq_head_entry eq_head_12
1179 (
1180 // synopsys translate_off
1181 .omni_ld (omni_ld_12),
1182 .omni_data (omni_data_12),
1183 // synopsys translate_on
1184 .clk (clk),
1185 .rst_l (rst_l),
1186 .w_ld (eq_head_w_ld_12),
1187 .csrbus_wr_data (csrbus_wr_data),
1188 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_12)
1189 );
1190
1191//----- Entry 13
1192dmu_imu_eqs_csr_eq_head_entry eq_head_13
1193 (
1194 // synopsys translate_off
1195 .omni_ld (omni_ld_13),
1196 .omni_data (omni_data_13),
1197 // synopsys translate_on
1198 .clk (clk),
1199 .rst_l (rst_l),
1200 .w_ld (eq_head_w_ld_13),
1201 .csrbus_wr_data (csrbus_wr_data),
1202 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_13)
1203 );
1204
1205//----- Entry 14
1206dmu_imu_eqs_csr_eq_head_entry eq_head_14
1207 (
1208 // synopsys translate_off
1209 .omni_ld (omni_ld_14),
1210 .omni_data (omni_data_14),
1211 // synopsys translate_on
1212 .clk (clk),
1213 .rst_l (rst_l),
1214 .w_ld (eq_head_w_ld_14),
1215 .csrbus_wr_data (csrbus_wr_data),
1216 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_14)
1217 );
1218
1219//----- Entry 15
1220dmu_imu_eqs_csr_eq_head_entry eq_head_15
1221 (
1222 // synopsys translate_off
1223 .omni_ld (omni_ld_15),
1224 .omni_data (omni_data_15),
1225 // synopsys translate_on
1226 .clk (clk),
1227 .rst_l (rst_l),
1228 .w_ld (eq_head_w_ld_15),
1229 .csrbus_wr_data (csrbus_wr_data),
1230 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_15)
1231 );
1232
1233//----- Entry 16
1234dmu_imu_eqs_csr_eq_head_entry eq_head_16
1235 (
1236 // synopsys translate_off
1237 .omni_ld (omni_ld_16),
1238 .omni_data (omni_data_16),
1239 // synopsys translate_on
1240 .clk (clk),
1241 .rst_l (rst_l),
1242 .w_ld (eq_head_w_ld_16),
1243 .csrbus_wr_data (csrbus_wr_data),
1244 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_16)
1245 );
1246
1247//----- Entry 17
1248dmu_imu_eqs_csr_eq_head_entry eq_head_17
1249 (
1250 // synopsys translate_off
1251 .omni_ld (omni_ld_17),
1252 .omni_data (omni_data_17),
1253 // synopsys translate_on
1254 .clk (clk),
1255 .rst_l (rst_l),
1256 .w_ld (eq_head_w_ld_17),
1257 .csrbus_wr_data (csrbus_wr_data),
1258 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_17)
1259 );
1260
1261//----- Entry 18
1262dmu_imu_eqs_csr_eq_head_entry eq_head_18
1263 (
1264 // synopsys translate_off
1265 .omni_ld (omni_ld_18),
1266 .omni_data (omni_data_18),
1267 // synopsys translate_on
1268 .clk (clk),
1269 .rst_l (rst_l),
1270 .w_ld (eq_head_w_ld_18),
1271 .csrbus_wr_data (csrbus_wr_data),
1272 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_18)
1273 );
1274
1275//----- Entry 19
1276dmu_imu_eqs_csr_eq_head_entry eq_head_19
1277 (
1278 // synopsys translate_off
1279 .omni_ld (omni_ld_19),
1280 .omni_data (omni_data_19),
1281 // synopsys translate_on
1282 .clk (clk),
1283 .rst_l (rst_l),
1284 .w_ld (eq_head_w_ld_19),
1285 .csrbus_wr_data (csrbus_wr_data),
1286 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_19)
1287 );
1288
1289//----- Entry 20
1290dmu_imu_eqs_csr_eq_head_entry eq_head_20
1291 (
1292 // synopsys translate_off
1293 .omni_ld (omni_ld_20),
1294 .omni_data (omni_data_20),
1295 // synopsys translate_on
1296 .clk (clk),
1297 .rst_l (rst_l),
1298 .w_ld (eq_head_w_ld_20),
1299 .csrbus_wr_data (csrbus_wr_data),
1300 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_20)
1301 );
1302
1303//----- Entry 21
1304dmu_imu_eqs_csr_eq_head_entry eq_head_21
1305 (
1306 // synopsys translate_off
1307 .omni_ld (omni_ld_21),
1308 .omni_data (omni_data_21),
1309 // synopsys translate_on
1310 .clk (clk),
1311 .rst_l (rst_l),
1312 .w_ld (eq_head_w_ld_21),
1313 .csrbus_wr_data (csrbus_wr_data),
1314 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_21)
1315 );
1316
1317//----- Entry 22
1318dmu_imu_eqs_csr_eq_head_entry eq_head_22
1319 (
1320 // synopsys translate_off
1321 .omni_ld (omni_ld_22),
1322 .omni_data (omni_data_22),
1323 // synopsys translate_on
1324 .clk (clk),
1325 .rst_l (rst_l),
1326 .w_ld (eq_head_w_ld_22),
1327 .csrbus_wr_data (csrbus_wr_data),
1328 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_22)
1329 );
1330
1331//----- Entry 23
1332dmu_imu_eqs_csr_eq_head_entry eq_head_23
1333 (
1334 // synopsys translate_off
1335 .omni_ld (omni_ld_23),
1336 .omni_data (omni_data_23),
1337 // synopsys translate_on
1338 .clk (clk),
1339 .rst_l (rst_l),
1340 .w_ld (eq_head_w_ld_23),
1341 .csrbus_wr_data (csrbus_wr_data),
1342 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_23)
1343 );
1344
1345//----- Entry 24
1346dmu_imu_eqs_csr_eq_head_entry eq_head_24
1347 (
1348 // synopsys translate_off
1349 .omni_ld (omni_ld_24),
1350 .omni_data (omni_data_24),
1351 // synopsys translate_on
1352 .clk (clk),
1353 .rst_l (rst_l),
1354 .w_ld (eq_head_w_ld_24),
1355 .csrbus_wr_data (csrbus_wr_data),
1356 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_24)
1357 );
1358
1359//----- Entry 25
1360dmu_imu_eqs_csr_eq_head_entry eq_head_25
1361 (
1362 // synopsys translate_off
1363 .omni_ld (omni_ld_25),
1364 .omni_data (omni_data_25),
1365 // synopsys translate_on
1366 .clk (clk),
1367 .rst_l (rst_l),
1368 .w_ld (eq_head_w_ld_25),
1369 .csrbus_wr_data (csrbus_wr_data),
1370 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_25)
1371 );
1372
1373//----- Entry 26
1374dmu_imu_eqs_csr_eq_head_entry eq_head_26
1375 (
1376 // synopsys translate_off
1377 .omni_ld (omni_ld_26),
1378 .omni_data (omni_data_26),
1379 // synopsys translate_on
1380 .clk (clk),
1381 .rst_l (rst_l),
1382 .w_ld (eq_head_w_ld_26),
1383 .csrbus_wr_data (csrbus_wr_data),
1384 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_26)
1385 );
1386
1387//----- Entry 27
1388dmu_imu_eqs_csr_eq_head_entry eq_head_27
1389 (
1390 // synopsys translate_off
1391 .omni_ld (omni_ld_27),
1392 .omni_data (omni_data_27),
1393 // synopsys translate_on
1394 .clk (clk),
1395 .rst_l (rst_l),
1396 .w_ld (eq_head_w_ld_27),
1397 .csrbus_wr_data (csrbus_wr_data),
1398 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_27)
1399 );
1400
1401//----- Entry 28
1402dmu_imu_eqs_csr_eq_head_entry eq_head_28
1403 (
1404 // synopsys translate_off
1405 .omni_ld (omni_ld_28),
1406 .omni_data (omni_data_28),
1407 // synopsys translate_on
1408 .clk (clk),
1409 .rst_l (rst_l),
1410 .w_ld (eq_head_w_ld_28),
1411 .csrbus_wr_data (csrbus_wr_data),
1412 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_28)
1413 );
1414
1415//----- Entry 29
1416dmu_imu_eqs_csr_eq_head_entry eq_head_29
1417 (
1418 // synopsys translate_off
1419 .omni_ld (omni_ld_29),
1420 .omni_data (omni_data_29),
1421 // synopsys translate_on
1422 .clk (clk),
1423 .rst_l (rst_l),
1424 .w_ld (eq_head_w_ld_29),
1425 .csrbus_wr_data (csrbus_wr_data),
1426 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_29)
1427 );
1428
1429//----- Entry 30
1430dmu_imu_eqs_csr_eq_head_entry eq_head_30
1431 (
1432 // synopsys translate_off
1433 .omni_ld (omni_ld_30),
1434 .omni_data (omni_data_30),
1435 // synopsys translate_on
1436 .clk (clk),
1437 .rst_l (rst_l),
1438 .w_ld (eq_head_w_ld_30),
1439 .csrbus_wr_data (csrbus_wr_data),
1440 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_30)
1441 );
1442
1443//----- Entry 31
1444dmu_imu_eqs_csr_eq_head_entry eq_head_31
1445 (
1446 // synopsys translate_off
1447 .omni_ld (omni_ld_31),
1448 .omni_data (omni_data_31),
1449 // synopsys translate_on
1450 .clk (clk),
1451 .rst_l (rst_l),
1452 .w_ld (eq_head_w_ld_31),
1453 .csrbus_wr_data (csrbus_wr_data),
1454 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_31)
1455 );
1456
1457//----- Entry 32
1458dmu_imu_eqs_csr_eq_head_entry eq_head_32
1459 (
1460 // synopsys translate_off
1461 .omni_ld (omni_ld_32),
1462 .omni_data (omni_data_32),
1463 // synopsys translate_on
1464 .clk (clk),
1465 .rst_l (rst_l),
1466 .w_ld (eq_head_w_ld_32),
1467 .csrbus_wr_data (csrbus_wr_data),
1468 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_32)
1469 );
1470
1471//----- Entry 33
1472dmu_imu_eqs_csr_eq_head_entry eq_head_33
1473 (
1474 // synopsys translate_off
1475 .omni_ld (omni_ld_33),
1476 .omni_data (omni_data_33),
1477 // synopsys translate_on
1478 .clk (clk),
1479 .rst_l (rst_l),
1480 .w_ld (eq_head_w_ld_33),
1481 .csrbus_wr_data (csrbus_wr_data),
1482 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_33)
1483 );
1484
1485//----- Entry 34
1486dmu_imu_eqs_csr_eq_head_entry eq_head_34
1487 (
1488 // synopsys translate_off
1489 .omni_ld (omni_ld_34),
1490 .omni_data (omni_data_34),
1491 // synopsys translate_on
1492 .clk (clk),
1493 .rst_l (rst_l),
1494 .w_ld (eq_head_w_ld_34),
1495 .csrbus_wr_data (csrbus_wr_data),
1496 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_34)
1497 );
1498
1499//----- Entry 35
1500dmu_imu_eqs_csr_eq_head_entry eq_head_35
1501 (
1502 // synopsys translate_off
1503 .omni_ld (omni_ld_35),
1504 .omni_data (omni_data_35),
1505 // synopsys translate_on
1506 .clk (clk),
1507 .rst_l (rst_l),
1508 .w_ld (eq_head_w_ld_35),
1509 .csrbus_wr_data (csrbus_wr_data),
1510 .eq_head_csrbus_read_data (eq_head_csrbus_read_data_35)
1511 );
1512
1513endmodule // dmu_imu_eqs_csr_eq_head
Full OpenSPARC design & verification tarball including full HDL.