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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_eqs_csr_eq_head_entry.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_eqs_csr_eq_head_entry.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
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20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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22// For the avoidance of doubt, and except that if any non-GPL license
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24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_eqs_csr_eq_head_entry
36 (
37 // synopsys translate_off
38 omni_ld,
39 omni_data,
40 // synopsys translate_on
41 clk,
42 rst_l,
43 w_ld,
44 csrbus_wr_data,
45 eq_head_csrbus_read_data
46 );
47
48//====================================================================
49// Polarity declarations
50//====================================================================
51// synopsys translate_off
52 input omni_ld; // Omni load
53// vlint flag_input_port_not_connected off
54 input [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH - 1:0] omni_data; // Omni write
55 // data
56// synopsys translate_on
57// vlint flag_input_port_not_connected on
58input clk; // Clock signal
59input rst_l; // Reset signal
60input w_ld; // SW load
61// vlint flag_input_port_not_connected off
62input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
63// vlint flag_input_port_not_connected on
64output [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data;
65 // SW read data
66
67//====================================================================
68// Type declarations
69//====================================================================
70// synopsys translate_off
71 wire omni_ld; // Omni load
72// vlint flag_dangling_net_within_module off
73// vlint flag_net_has_no_load off
74 wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH - 1:0] omni_data; // Omni write
75 // data
76// synopsys translate_on
77// vlint flag_dangling_net_within_module on
78// vlint flag_net_has_no_load on
79wire clk; // Clock signal
80wire rst_l; // Reset signal
81wire w_ld; // SW load
82// vlint flag_dangling_net_within_module off
83// vlint flag_net_has_no_load off
84wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
85// vlint flag_dangling_net_within_module on
86// vlint flag_net_has_no_load on
87wire [`FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH-1:0] eq_head_csrbus_read_data;
88 // SW read data
89
90//====================================================================
91// Logic
92//====================================================================
93
94//----- Reset values
95// verilint 531 off
96wire [6:0] reset_head = 7'h0;
97// verilint 531 on
98
99//----- Active high reset wires
100wire rst_l_active_high = ~rst_l;
101
102//====================================================
103// Instantiation of flops
104//====================================================
105
106// bit 0
107csr_sw csr_sw_0
108 (
109 // synopsys translate_off
110 .omni_ld (omni_ld),
111 .omni_data (omni_data[0]),
112 .omni_rw_alias (1'b1),
113 .omni_rw1c_alias (1'b0),
114 .omni_rw1s_alias (1'b0),
115 // synopsys translate_on
116 .rst (rst_l_active_high),
117 .rst_val (reset_head[0]),
118 .csr_ld (w_ld),
119 .csr_data (csrbus_wr_data[0]),
120 .rw_alias (1'b1),
121 .rw1c_alias (1'b0),
122 .rw1s_alias (1'b0),
123 .hw_ld (1'b0),
124 .hw_data (1'b0),
125 .cp (clk),
126 .q (eq_head_csrbus_read_data[0])
127 );
128
129// bit 1
130csr_sw csr_sw_1
131 (
132 // synopsys translate_off
133 .omni_ld (omni_ld),
134 .omni_data (omni_data[1]),
135 .omni_rw_alias (1'b1),
136 .omni_rw1c_alias (1'b0),
137 .omni_rw1s_alias (1'b0),
138 // synopsys translate_on
139 .rst (rst_l_active_high),
140 .rst_val (reset_head[1]),
141 .csr_ld (w_ld),
142 .csr_data (csrbus_wr_data[1]),
143 .rw_alias (1'b1),
144 .rw1c_alias (1'b0),
145 .rw1s_alias (1'b0),
146 .hw_ld (1'b0),
147 .hw_data (1'b0),
148 .cp (clk),
149 .q (eq_head_csrbus_read_data[1])
150 );
151
152// bit 2
153csr_sw csr_sw_2
154 (
155 // synopsys translate_off
156 .omni_ld (omni_ld),
157 .omni_data (omni_data[2]),
158 .omni_rw_alias (1'b1),
159 .omni_rw1c_alias (1'b0),
160 .omni_rw1s_alias (1'b0),
161 // synopsys translate_on
162 .rst (rst_l_active_high),
163 .rst_val (reset_head[2]),
164 .csr_ld (w_ld),
165 .csr_data (csrbus_wr_data[2]),
166 .rw_alias (1'b1),
167 .rw1c_alias (1'b0),
168 .rw1s_alias (1'b0),
169 .hw_ld (1'b0),
170 .hw_data (1'b0),
171 .cp (clk),
172 .q (eq_head_csrbus_read_data[2])
173 );
174
175// bit 3
176csr_sw csr_sw_3
177 (
178 // synopsys translate_off
179 .omni_ld (omni_ld),
180 .omni_data (omni_data[3]),
181 .omni_rw_alias (1'b1),
182 .omni_rw1c_alias (1'b0),
183 .omni_rw1s_alias (1'b0),
184 // synopsys translate_on
185 .rst (rst_l_active_high),
186 .rst_val (reset_head[3]),
187 .csr_ld (w_ld),
188 .csr_data (csrbus_wr_data[3]),
189 .rw_alias (1'b1),
190 .rw1c_alias (1'b0),
191 .rw1s_alias (1'b0),
192 .hw_ld (1'b0),
193 .hw_data (1'b0),
194 .cp (clk),
195 .q (eq_head_csrbus_read_data[3])
196 );
197
198// bit 4
199csr_sw csr_sw_4
200 (
201 // synopsys translate_off
202 .omni_ld (omni_ld),
203 .omni_data (omni_data[4]),
204 .omni_rw_alias (1'b1),
205 .omni_rw1c_alias (1'b0),
206 .omni_rw1s_alias (1'b0),
207 // synopsys translate_on
208 .rst (rst_l_active_high),
209 .rst_val (reset_head[4]),
210 .csr_ld (w_ld),
211 .csr_data (csrbus_wr_data[4]),
212 .rw_alias (1'b1),
213 .rw1c_alias (1'b0),
214 .rw1s_alias (1'b0),
215 .hw_ld (1'b0),
216 .hw_data (1'b0),
217 .cp (clk),
218 .q (eq_head_csrbus_read_data[4])
219 );
220
221// bit 5
222csr_sw csr_sw_5
223 (
224 // synopsys translate_off
225 .omni_ld (omni_ld),
226 .omni_data (omni_data[5]),
227 .omni_rw_alias (1'b1),
228 .omni_rw1c_alias (1'b0),
229 .omni_rw1s_alias (1'b0),
230 // synopsys translate_on
231 .rst (rst_l_active_high),
232 .rst_val (reset_head[5]),
233 .csr_ld (w_ld),
234 .csr_data (csrbus_wr_data[5]),
235 .rw_alias (1'b1),
236 .rw1c_alias (1'b0),
237 .rw1s_alias (1'b0),
238 .hw_ld (1'b0),
239 .hw_data (1'b0),
240 .cp (clk),
241 .q (eq_head_csrbus_read_data[5])
242 );
243
244// bit 6
245csr_sw csr_sw_6
246 (
247 // synopsys translate_off
248 .omni_ld (omni_ld),
249 .omni_data (omni_data[6]),
250 .omni_rw_alias (1'b1),
251 .omni_rw1c_alias (1'b0),
252 .omni_rw1s_alias (1'b0),
253 // synopsys translate_on
254 .rst (rst_l_active_high),
255 .rst_val (reset_head[6]),
256 .csr_ld (w_ld),
257 .csr_data (csrbus_wr_data[6]),
258 .rw_alias (1'b1),
259 .rw1c_alias (1'b0),
260 .rw1s_alias (1'b0),
261 .hw_ld (1'b0),
262 .hw_data (1'b0),
263 .cp (clk),
264 .q (eq_head_csrbus_read_data[6])
265 );
266
267assign eq_head_csrbus_read_data[7] = 1'b0; // bit 7
268assign eq_head_csrbus_read_data[8] = 1'b0; // bit 8
269assign eq_head_csrbus_read_data[9] = 1'b0; // bit 9
270assign eq_head_csrbus_read_data[10] = 1'b0; // bit 10
271assign eq_head_csrbus_read_data[11] = 1'b0; // bit 11
272assign eq_head_csrbus_read_data[12] = 1'b0; // bit 12
273assign eq_head_csrbus_read_data[13] = 1'b0; // bit 13
274assign eq_head_csrbus_read_data[14] = 1'b0; // bit 14
275assign eq_head_csrbus_read_data[15] = 1'b0; // bit 15
276assign eq_head_csrbus_read_data[16] = 1'b0; // bit 16
277assign eq_head_csrbus_read_data[17] = 1'b0; // bit 17
278assign eq_head_csrbus_read_data[18] = 1'b0; // bit 18
279assign eq_head_csrbus_read_data[19] = 1'b0; // bit 19
280assign eq_head_csrbus_read_data[20] = 1'b0; // bit 20
281assign eq_head_csrbus_read_data[21] = 1'b0; // bit 21
282assign eq_head_csrbus_read_data[22] = 1'b0; // bit 22
283assign eq_head_csrbus_read_data[23] = 1'b0; // bit 23
284assign eq_head_csrbus_read_data[24] = 1'b0; // bit 24
285assign eq_head_csrbus_read_data[25] = 1'b0; // bit 25
286assign eq_head_csrbus_read_data[26] = 1'b0; // bit 26
287assign eq_head_csrbus_read_data[27] = 1'b0; // bit 27
288assign eq_head_csrbus_read_data[28] = 1'b0; // bit 28
289assign eq_head_csrbus_read_data[29] = 1'b0; // bit 29
290assign eq_head_csrbus_read_data[30] = 1'b0; // bit 30
291assign eq_head_csrbus_read_data[31] = 1'b0; // bit 31
292assign eq_head_csrbus_read_data[32] = 1'b0; // bit 32
293assign eq_head_csrbus_read_data[33] = 1'b0; // bit 33
294assign eq_head_csrbus_read_data[34] = 1'b0; // bit 34
295assign eq_head_csrbus_read_data[35] = 1'b0; // bit 35
296assign eq_head_csrbus_read_data[36] = 1'b0; // bit 36
297assign eq_head_csrbus_read_data[37] = 1'b0; // bit 37
298assign eq_head_csrbus_read_data[38] = 1'b0; // bit 38
299assign eq_head_csrbus_read_data[39] = 1'b0; // bit 39
300assign eq_head_csrbus_read_data[40] = 1'b0; // bit 40
301assign eq_head_csrbus_read_data[41] = 1'b0; // bit 41
302assign eq_head_csrbus_read_data[42] = 1'b0; // bit 42
303assign eq_head_csrbus_read_data[43] = 1'b0; // bit 43
304assign eq_head_csrbus_read_data[44] = 1'b0; // bit 44
305assign eq_head_csrbus_read_data[45] = 1'b0; // bit 45
306assign eq_head_csrbus_read_data[46] = 1'b0; // bit 46
307assign eq_head_csrbus_read_data[47] = 1'b0; // bit 47
308assign eq_head_csrbus_read_data[48] = 1'b0; // bit 48
309assign eq_head_csrbus_read_data[49] = 1'b0; // bit 49
310assign eq_head_csrbus_read_data[50] = 1'b0; // bit 50
311assign eq_head_csrbus_read_data[51] = 1'b0; // bit 51
312assign eq_head_csrbus_read_data[52] = 1'b0; // bit 52
313assign eq_head_csrbus_read_data[53] = 1'b0; // bit 53
314assign eq_head_csrbus_read_data[54] = 1'b0; // bit 54
315assign eq_head_csrbus_read_data[55] = 1'b0; // bit 55
316assign eq_head_csrbus_read_data[56] = 1'b0; // bit 56
317assign eq_head_csrbus_read_data[57] = 1'b0; // bit 57
318assign eq_head_csrbus_read_data[58] = 1'b0; // bit 58
319assign eq_head_csrbus_read_data[59] = 1'b0; // bit 59
320assign eq_head_csrbus_read_data[60] = 1'b0; // bit 60
321assign eq_head_csrbus_read_data[61] = 1'b0; // bit 61
322assign eq_head_csrbus_read_data[62] = 1'b0; // bit 62
323assign eq_head_csrbus_read_data[63] = 1'b0; // bit 63
324
325endmodule // dmu_imu_eqs_csr_eq_head_entry
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