[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_gcs.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_imu_gcs.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_imu_gcs (

		// Clock and Reset 

		clk, 
		rst_l,
		
		// Mondo Requests Comming from each of the 4 group controllers 
		    
		iss2gcs_gc_0_mdo_needed,
		iss2gcs_gc_1_mdo_needed,
		iss2gcs_gc_2_mdo_needed,
		iss2gcs_gc_3_mdo_needed,

		// ISS lookup request signals

		gcs2iss_tid_req,
		gcs2iss_tid_sel,
		gcs2iss_mdo_pending, 
			
		// ISS lookup response signals
	
		iss2gcs_tid_ack, 
		iss2gcs_tid, 
		iss2gcs_mondo_mode,
		
		// Static Counter Limit from CSR
				
		iss2gcs_counter_limit,
				
		// Interface for Mondo Reply Status 

		rss2gcs_rply,
		rss2gcs_id, 
		rss2gcs_valid, 

		// LRM Mondo Enqueue Interface 

		im2rm_mdo_enq,
		im2rm_mdo, 
		
		
		// Debug Ports 
		
		dbg2gcs_dbg_sel_a,
		dbg2gcs_dbg_sel_b,
		gcs2dbg_dbg_a,
		gcs2dbg_dbg_b,
		
		// Idle checkers 
		
		gcs2dbg_idle 
		
		);
		
//############################################################################
//				PORT DECLARATIONS
//############################################################################

  //------------------------------------------------------------------------
  //  Clock and Reset Signals      
  //------------------------------------------------------------------------

  input         clk; 
  input         rst_l; 
  
  //------------------------------------------------------------------------
  // Mondo Requests Comming from each of the 4 group controllers      
  //------------------------------------------------------------------------

  input [63:0]  iss2gcs_gc_0_mdo_needed;  //Requests to issue and interrupt from GC 0   
  input [63:0]  iss2gcs_gc_1_mdo_needed;  //Requests to issue and interrupt from GC 1 
  input [63:0]  iss2gcs_gc_2_mdo_needed;  //Requests to issue and interrupt from GC 2  
  input [63:0]  iss2gcs_gc_3_mdo_needed;  //Requests to issue and interrupt from GC 3 
  
  //------------------------------------------------------------------------
  // ISS lookup request signals
  //------------------------------------------------------------------------
  
  output        gcs2iss_tid_req;        // Request to ISS for TID for accepted mondo
  output [5:0]  gcs2iss_tid_sel;	// Select for the TID output mux
  output [63:0] gcs2iss_mdo_pending;    // ID of mondo that was accecpted

  //------------------------------------------------------------------------
  // ISS lookup response signals
  //------------------------------------------------------------------------
  input         iss2gcs_tid_ack;  	// ACK Qualifier for tid of mondo	
  input  [5:0]  iss2gcs_tid;           	// TID of mondo 
  input 	iss2gcs_mondo_mode;     // Mode of the modo 
 
  //-----------------------------------------------------
  // Static Counter Limit from CSR
  //-----------------------------------------------------
    
  input [24:0]  iss2gcs_counter_limit; 		// COunter Limit fo rthe retry counter 
 
  //-----------------------------------------------------
  // Interface for Mondo Reply Status 
  //-----------------------------------------------------
  
  input	  	rss2gcs_rply; 		// Reply type from RSS ack =1 nack =0
  input [1:0]	rss2gcs_id; 		// Group controller ID for response
  input 	rss2gcs_valid; 		// Valid signal to validate respose
  
  //-----------------------------------------------------
  // Interface for to LRM for Mondo Records
  //-----------------------------------------------------
  
  output        			im2rm_mdo_enq;    	//Enqueue signal for mondo record
  output [`FIRE_DLC_MQR_REC_WDTH-1:0] 	im2rm_mdo;         	// Mondo data 

  //------------------------------------------------------------------------
  // Debug Ports   
  //------------------------------------------------------------------------

  input [2:0] 					dbg2gcs_dbg_sel_a;
  input [2:0] 					dbg2gcs_dbg_sel_b;
  output   [`FIRE_DEBUG_WDTH-1:0]		gcs2dbg_dbg_a;
  output   [`FIRE_DEBUG_WDTH-1:0]		gcs2dbg_dbg_b;

  //------------------------------------------------------------------------
  // Idle Checkers  
  //------------------------------------------------------------------------
  output					gcs2dbg_idle; 
  
//############################################################################
//				SIGNAL DECLARATIONS
//############################################################################  
 
  //------------------------
  //  Wires 
  //------------------------
  
  wire       gc_0_req, gc_1_req, gc_2_req, gc_3_req; 
  wire [5:0] gc_0_ino, gc_1_ino, gc_2_ino, gc_3_ino; 
  wire       gc_0_gnt, gc_1_gnt, gc_2_gnt, gc_3_gnt; 
  wire  [`FIRE_DEBUG_WDTH-1:0]   gc_0_fsm_dbg, gc_1_fsm_dbg, gc_2_fsm_dbg, gc_3_fsm_dbg; 
  wire  [`FIRE_DEBUG_WDTH-1:0]  csm_fsm_dbg; 
  
  wire [5:0] gc_arb_ino;  
  wire [1:0] gc_arb_id;  
  
  wire 	     next_arb; 
  wire 	     gc_arb_valid; 

  //**************************************************
  // Registers that Are Not Flops 
  //**************************************************
 
  reg   [`FIRE_DEBUG_WDTH-1:0] 			n_dbg_a;
  reg   [`FIRE_DEBUG_WDTH-1:0] 			n_dbg_b;

  
  //**************************************************
  // Registers that Are Flops 
  //**************************************************
 
  reg   [`FIRE_DEBUG_WDTH-1:0] 			dbg_a;
  reg   [`FIRE_DEBUG_WDTH-1:0] 			dbg_b;

//############################################################################
//		    		COMBINATIONAL LOGIC
//############################################################################
//-----------------------------------------------------
//  Debug Ports  
//-----------------------------------------------------  

always @ (dbg2gcs_dbg_sel_a or gc_0_fsm_dbg or gc_1_fsm_dbg or gc_2_fsm_dbg or
	  gc_3_fsm_dbg or csm_fsm_dbg or gc_arb_ino or im2rm_mdo_enq or im2rm_mdo) 
  begin
    case (dbg2gcs_dbg_sel_a) // synopsys infer_mux
      3'b000: n_dbg_a = gc_0_fsm_dbg;
      3'b001: n_dbg_a = gc_1_fsm_dbg;
      3'b010: n_dbg_a = gc_2_fsm_dbg;
      3'b011: n_dbg_a = gc_3_fsm_dbg;
      3'b100: n_dbg_a = csm_fsm_dbg;
      3'b101: n_dbg_a = {2'h0, gc_arb_ino[5:0]};
      3'b110: n_dbg_a = {im2rm_mdo_enq, im2rm_mdo[6:0]};
      3'b111: n_dbg_a = {im2rm_mdo_enq, im2rm_mdo[13:7]};
    endcase
  end

always @ (dbg2gcs_dbg_sel_b or gc_0_fsm_dbg or gc_1_fsm_dbg or gc_2_fsm_dbg or
	  gc_3_fsm_dbg or csm_fsm_dbg or gc_arb_ino or im2rm_mdo_enq or im2rm_mdo) 
  begin
    case (dbg2gcs_dbg_sel_b) // synopsys infer_mux
      3'b000: n_dbg_b = gc_0_fsm_dbg;
      3'b001: n_dbg_b = gc_1_fsm_dbg;
      3'b010: n_dbg_b = gc_2_fsm_dbg;
      3'b011: n_dbg_b = gc_3_fsm_dbg;
      3'b100: n_dbg_b = csm_fsm_dbg;
      3'b101: n_dbg_b = {2'h0, gc_arb_ino[5:0]};
      3'b110: n_dbg_b = {im2rm_mdo_enq, im2rm_mdo[6:0]};
      3'b111: n_dbg_b = {im2rm_mdo_enq, im2rm_mdo[13:7]};
    endcase
  end

  
always @ (posedge clk)
     begin 
      if (!rst_l) begin
      dbg_a <= 8'b0;
      dbg_b <= 8'b0;
      end
      else begin
      dbg_a <= n_dbg_a;
      dbg_b <= n_dbg_b;
     end   
     end   
   

assign gcs2dbg_dbg_a = dbg_a; 
assign gcs2dbg_dbg_b = dbg_b; 

 //------------------------------------------------------------------------
  // Idle Checkers  
  //------------------------------------------------------------------------
 assign gcs2dbg_idle =  ~gc_0_fsm_dbg[7] & ~gc_0_fsm_dbg[6] &
			~gc_1_fsm_dbg[7] & ~gc_1_fsm_dbg[6] &
			~gc_2_fsm_dbg[7] & ~gc_2_fsm_dbg[6] &
			~gc_3_fsm_dbg[7] & ~gc_3_fsm_dbg[6] &
			~csm_fsm_dbg[5]  & ~csm_fsm_dbg[4];			
			 

//############################################################################
//		    		MODULE INSTANTIATIONS
//############################################################################    

 dmu_imu_gcs_gc gc_0 (

		.clk  (clk), 
		.rst_l  (rst_l),
		
		.int_req_vec  (iss2gcs_gc_0_mdo_needed),
		
		.gcs_req  (gc_0_req),
		.gcs_ino  (gc_0_ino), 
		.gcs_gnt  (gc_0_gnt), 
		
		.rss2gcs_rply  (rss2gcs_rply),
		.rss2gcs_id  (rss2gcs_id ), 
		.rss2gcs_valid  (rss2gcs_valid), 
		
		.iss2gcs_counter_limit  (iss2gcs_counter_limit), 
				
		.static_gc_id  (2'b00),
		
		.fsm_dbg (gc_0_fsm_dbg)
		
		);
		

 dmu_imu_gcs_gc gc_1 (

		.clk  (clk), 
		.rst_l  (rst_l),
		
		.int_req_vec  (iss2gcs_gc_1_mdo_needed),
		
		.gcs_req  (gc_1_req),
		.gcs_ino  (gc_1_ino), 
		.gcs_gnt  (gc_1_gnt), 
		
		.rss2gcs_rply  (rss2gcs_rply),
		.rss2gcs_id  (rss2gcs_id ), 
		.rss2gcs_valid  (rss2gcs_valid), 
		
		.iss2gcs_counter_limit  (iss2gcs_counter_limit), 
				
		.static_gc_id  (2'b01),
		
		.fsm_dbg (gc_1_fsm_dbg)
		
		);
		

 dmu_imu_gcs_gc gc_2 (

		.clk  (clk), 
		.rst_l  (rst_l),
		
		.int_req_vec  (iss2gcs_gc_2_mdo_needed),
		
		.gcs_req  (gc_2_req),
		.gcs_ino  (gc_2_ino), 
		.gcs_gnt  (gc_2_gnt), 
		
		.rss2gcs_rply  (rss2gcs_rply),
		.rss2gcs_id  (rss2gcs_id ), 
		.rss2gcs_valid  (rss2gcs_valid), 
		
		.iss2gcs_counter_limit  (iss2gcs_counter_limit), 
				
		.static_gc_id  (2'b10),
		
		.fsm_dbg (gc_2_fsm_dbg)
		
		);
		

 dmu_imu_gcs_gc gc_3 (

		.clk  (clk), 
		.rst_l  (rst_l),
		
		.int_req_vec  (iss2gcs_gc_3_mdo_needed),
		
		.gcs_req  (gc_3_req),
		.gcs_ino  (gc_3_ino), 
		.gcs_gnt  (gc_3_gnt), 
		
		.rss2gcs_rply  (rss2gcs_rply),
		.rss2gcs_id  (rss2gcs_id ), 
		.rss2gcs_valid  (rss2gcs_valid), 
		
		.iss2gcs_counter_limit  (iss2gcs_counter_limit), 
				
		.static_gc_id  (2'b11),
		
		.fsm_dbg (gc_3_fsm_dbg)
		
		);
		

 dmu_imu_gcs_arb arb (

		.clk     (clk), 
		.rst_l   (rst_l),
	
		.gc_0_req  (gc_0_req),
		.gc_0_ino  (gc_0_ino), 
		.gc_0_gnt  (gc_0_gnt), 

		.gc_1_req  (gc_1_req),
		.gc_1_ino  (gc_1_ino), 
		.gc_1_gnt  (gc_1_gnt), 

		.gc_2_req  (gc_2_req),
		.gc_2_ino  (gc_2_ino), 
		.gc_2_gnt  (gc_2_gnt), 


		.gc_3_req  (gc_3_req),
		.gc_3_ino  (gc_3_ino), 
		.gc_3_gnt  (gc_3_gnt), 


                .next_arb   (next_arb), 

                .gc_arb_valid (gc_arb_valid), 
                .gc_arb_ino   (gc_arb_ino),
                .gc_arb_id    (gc_arb_id)
		
		);


 dmu_imu_gcs_csm csm(

		.clk			(clk), 
		.rst_l			(rst_l), 
		
		.gcs2iss_tid_req	(gcs2iss_tid_req),
		.gcs2iss_tid_sel	(gcs2iss_tid_sel),

		.gcs2iss_mdo_pending	(gcs2iss_mdo_pending),
		.iss2gcs_tid_ack	(iss2gcs_tid_ack), 
		.iss2gcs_tid		(iss2gcs_tid), 		
		.iss2gcs_mondo_mode	(iss2gcs_mondo_mode),

                .next_arb		(next_arb), 
		
              	.gc_arb_valid		(gc_arb_valid), 
              	.gc_arb_ino		(gc_arb_ino),
              	.gc_arb_id		(gc_arb_id),


		.im2rm_mdo_enq		(im2rm_mdo_enq),
		.im2rm_mdo		(im2rm_mdo),
		
		.fsm_dbg 		(csm_fsm_dbg)

		);


endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_imu_gcs.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_imu_gcs (
	36
	37	// Clock and Reset
	38
	39	clk,
	40	rst_l,
	41
	42	// Mondo Requests Comming from each of the 4 group controllers
	43
	44	iss2gcs_gc_0_mdo_needed,
	45	iss2gcs_gc_1_mdo_needed,
	46	iss2gcs_gc_2_mdo_needed,
	47	iss2gcs_gc_3_mdo_needed,
	48
	49	// ISS lookup request signals
	50
	51	gcs2iss_tid_req,
	52	gcs2iss_tid_sel,
	53	gcs2iss_mdo_pending,
	54
	55	// ISS lookup response signals
	56
	57	iss2gcs_tid_ack,
	58	iss2gcs_tid,
	59	iss2gcs_mondo_mode,
	60
	61	// Static Counter Limit from CSR
	62
	63	iss2gcs_counter_limit,
	64
65	// Interface for Mondo Reply Status
66
67	rss2gcs_rply,
68	rss2gcs_id,
69	rss2gcs_valid,
70
71	// LRM Mondo Enqueue Interface
72
73	im2rm_mdo_enq,
74	im2rm_mdo,
75
76
77	// Debug Ports
78
79	dbg2gcs_dbg_sel_a,
80	dbg2gcs_dbg_sel_b,
81	gcs2dbg_dbg_a,
82	gcs2dbg_dbg_b,
83
84	// Idle checkers
85
86	gcs2dbg_idle
87
88	);
89
90	//############################################################################
91	// PORT DECLARATIONS
92	//############################################################################
93
94	//------------------------------------------------------------------------
95	// Clock and Reset Signals
96	//------------------------------------------------------------------------
97
98	input clk;
99	input rst_l;
100
101	//------------------------------------------------------------------------
102	// Mondo Requests Comming from each of the 4 group controllers
103	//------------------------------------------------------------------------
104
105	input [63:0] iss2gcs_gc_0_mdo_needed; //Requests to issue and interrupt from GC 0
106	input [63:0] iss2gcs_gc_1_mdo_needed; //Requests to issue and interrupt from GC 1
107	input [63:0] iss2gcs_gc_2_mdo_needed; //Requests to issue and interrupt from GC 2
108	input [63:0] iss2gcs_gc_3_mdo_needed; //Requests to issue and interrupt from GC 3
109
110	//------------------------------------------------------------------------
111	// ISS lookup request signals
112	//------------------------------------------------------------------------
113
114	output gcs2iss_tid_req; // Request to ISS for TID for accepted mondo
115	output [5:0] gcs2iss_tid_sel; // Select for the TID output mux
116	output [63:0] gcs2iss_mdo_pending; // ID of mondo that was accecpted
117
118	//------------------------------------------------------------------------
119	// ISS lookup response signals
120	//------------------------------------------------------------------------
121	input iss2gcs_tid_ack; // ACK Qualifier for tid of mondo
122	input [5:0] iss2gcs_tid; // TID of mondo
123	input iss2gcs_mondo_mode; // Mode of the modo
124
125	//-----------------------------------------------------
126	// Static Counter Limit from CSR
127	//-----------------------------------------------------
128
129	input [24:0] iss2gcs_counter_limit; // COunter Limit fo rthe retry counter
130
131	//-----------------------------------------------------
132	// Interface for Mondo Reply Status
133	//-----------------------------------------------------
134
135	input rss2gcs_rply; // Reply type from RSS ack =1 nack =0
136	input [1:0] rss2gcs_id; // Group controller ID for response
137	input rss2gcs_valid; // Valid signal to validate respose
138
139	//-----------------------------------------------------
140	// Interface for to LRM for Mondo Records
141	//-----------------------------------------------------
142
143	output im2rm_mdo_enq; //Enqueue signal for mondo record
144	output [`FIRE_DLC_MQR_REC_WDTH-1:0] im2rm_mdo; // Mondo data
145
146	//------------------------------------------------------------------------
147	// Debug Ports
148	//------------------------------------------------------------------------
149
150	input [2:0] dbg2gcs_dbg_sel_a;
151	input [2:0] dbg2gcs_dbg_sel_b;
152	output [`FIRE_DEBUG_WDTH-1:0] gcs2dbg_dbg_a;
153	output [`FIRE_DEBUG_WDTH-1:0] gcs2dbg_dbg_b;
154
155	//------------------------------------------------------------------------
156	// Idle Checkers
157	//------------------------------------------------------------------------
158	output gcs2dbg_idle;
159
160	//############################################################################
161	// SIGNAL DECLARATIONS
162	//############################################################################
163
164	//------------------------
165	// Wires
166	//------------------------
167
168	wire gc_0_req, gc_1_req, gc_2_req, gc_3_req;
169	wire [5:0] gc_0_ino, gc_1_ino, gc_2_ino, gc_3_ino;
170	wire gc_0_gnt, gc_1_gnt, gc_2_gnt, gc_3_gnt;
171	wire [`FIRE_DEBUG_WDTH-1:0] gc_0_fsm_dbg, gc_1_fsm_dbg, gc_2_fsm_dbg, gc_3_fsm_dbg;
172	wire [`FIRE_DEBUG_WDTH-1:0] csm_fsm_dbg;
173
174	wire [5:0] gc_arb_ino;
175	wire [1:0] gc_arb_id;
176
177	wire next_arb;
178	wire gc_arb_valid;
179
180	//**************************************************
181	// Registers that Are Not Flops
182	//**************************************************
183
184	reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_a;
185	reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_b;
186
187
188	//**************************************************
189	// Registers that Are Flops
190	//**************************************************
191
192	reg [`FIRE_DEBUG_WDTH-1:0] dbg_a;
193	reg [`FIRE_DEBUG_WDTH-1:0] dbg_b;
194
195	//############################################################################
196	// COMBINATIONAL LOGIC
197	//############################################################################
198	//-----------------------------------------------------
199	// Debug Ports
200	//-----------------------------------------------------
201
202	always @ (dbg2gcs_dbg_sel_a or gc_0_fsm_dbg or gc_1_fsm_dbg or gc_2_fsm_dbg or
203	gc_3_fsm_dbg or csm_fsm_dbg or gc_arb_ino or im2rm_mdo_enq or im2rm_mdo)
204	begin
205	case (dbg2gcs_dbg_sel_a) // synopsys infer_mux
206	3'b000: n_dbg_a = gc_0_fsm_dbg;
207	3'b001: n_dbg_a = gc_1_fsm_dbg;
208	3'b010: n_dbg_a = gc_2_fsm_dbg;
209	3'b011: n_dbg_a = gc_3_fsm_dbg;
210	3'b100: n_dbg_a = csm_fsm_dbg;
211	3'b101: n_dbg_a = {2'h0, gc_arb_ino[5:0]};
212	3'b110: n_dbg_a = {im2rm_mdo_enq, im2rm_mdo[6:0]};
213	3'b111: n_dbg_a = {im2rm_mdo_enq, im2rm_mdo[13:7]};
214	endcase
215	end
216
217	always @ (dbg2gcs_dbg_sel_b or gc_0_fsm_dbg or gc_1_fsm_dbg or gc_2_fsm_dbg or
218	gc_3_fsm_dbg or csm_fsm_dbg or gc_arb_ino or im2rm_mdo_enq or im2rm_mdo)
219	begin
220	case (dbg2gcs_dbg_sel_b) // synopsys infer_mux
221	3'b000: n_dbg_b = gc_0_fsm_dbg;
222	3'b001: n_dbg_b = gc_1_fsm_dbg;
223	3'b010: n_dbg_b = gc_2_fsm_dbg;
224	3'b011: n_dbg_b = gc_3_fsm_dbg;
225	3'b100: n_dbg_b = csm_fsm_dbg;
226	3'b101: n_dbg_b = {2'h0, gc_arb_ino[5:0]};
227	3'b110: n_dbg_b = {im2rm_mdo_enq, im2rm_mdo[6:0]};
228	3'b111: n_dbg_b = {im2rm_mdo_enq, im2rm_mdo[13:7]};
229	endcase
230	end
231
232
233	always @ (posedge clk)
234	begin
235	if (!rst_l) begin
236	dbg_a <= 8'b0;
237	dbg_b <= 8'b0;
238	end
239	else begin
240	dbg_a <= n_dbg_a;
241	dbg_b <= n_dbg_b;
242	end
243	end
244
245
246	assign gcs2dbg_dbg_a = dbg_a;
247	assign gcs2dbg_dbg_b = dbg_b;
248
249	//------------------------------------------------------------------------
250	// Idle Checkers
251	//------------------------------------------------------------------------
252	assign gcs2dbg_idle = ~gc_0_fsm_dbg[7] & ~gc_0_fsm_dbg[6] &
253	~gc_1_fsm_dbg[7] & ~gc_1_fsm_dbg[6] &
254	~gc_2_fsm_dbg[7] & ~gc_2_fsm_dbg[6] &
255	~gc_3_fsm_dbg[7] & ~gc_3_fsm_dbg[6] &
256	~csm_fsm_dbg[5] & ~csm_fsm_dbg[4];
257
258
259
260	//############################################################################
261	// MODULE INSTANTIATIONS
262	//############################################################################
263
264	dmu_imu_gcs_gc gc_0 (
265
266	.clk (clk),
267	.rst_l (rst_l),
268
269	.int_req_vec (iss2gcs_gc_0_mdo_needed),
270
271	.gcs_req (gc_0_req),
272	.gcs_ino (gc_0_ino),
273	.gcs_gnt (gc_0_gnt),
274
275	.rss2gcs_rply (rss2gcs_rply),
276	.rss2gcs_id (rss2gcs_id ),
277	.rss2gcs_valid (rss2gcs_valid),
278
279	.iss2gcs_counter_limit (iss2gcs_counter_limit),
280
281	.static_gc_id (2'b00),
282
283	.fsm_dbg (gc_0_fsm_dbg)
284
285	);
286
287
288	dmu_imu_gcs_gc gc_1 (
289
290	.clk (clk),
291	.rst_l (rst_l),
292
293	.int_req_vec (iss2gcs_gc_1_mdo_needed),
294
295	.gcs_req (gc_1_req),
296	.gcs_ino (gc_1_ino),
297	.gcs_gnt (gc_1_gnt),
298
299	.rss2gcs_rply (rss2gcs_rply),
300	.rss2gcs_id (rss2gcs_id ),
301	.rss2gcs_valid (rss2gcs_valid),
302
303	.iss2gcs_counter_limit (iss2gcs_counter_limit),
304
305	.static_gc_id (2'b01),
306
307	.fsm_dbg (gc_1_fsm_dbg)
308
309	);
310
311
312
313	dmu_imu_gcs_gc gc_2 (
314
315	.clk (clk),
316	.rst_l (rst_l),
317
318	.int_req_vec (iss2gcs_gc_2_mdo_needed),
319
320	.gcs_req (gc_2_req),
321	.gcs_ino (gc_2_ino),
322	.gcs_gnt (gc_2_gnt),
323
324	.rss2gcs_rply (rss2gcs_rply),
325	.rss2gcs_id (rss2gcs_id ),
326	.rss2gcs_valid (rss2gcs_valid),
327
328	.iss2gcs_counter_limit (iss2gcs_counter_limit),
329
330	.static_gc_id (2'b10),
331
332	.fsm_dbg (gc_2_fsm_dbg)
333
334	);
335
336
337
338	dmu_imu_gcs_gc gc_3 (
339
340	.clk (clk),
341	.rst_l (rst_l),
342
343	.int_req_vec (iss2gcs_gc_3_mdo_needed),
344
345	.gcs_req (gc_3_req),
346	.gcs_ino (gc_3_ino),
347	.gcs_gnt (gc_3_gnt),
348
349	.rss2gcs_rply (rss2gcs_rply),
350	.rss2gcs_id (rss2gcs_id ),
351	.rss2gcs_valid (rss2gcs_valid),
352
353	.iss2gcs_counter_limit (iss2gcs_counter_limit),
354
355	.static_gc_id (2'b11),
356
357	.fsm_dbg (gc_3_fsm_dbg)
358
359	);
360
361
362	dmu_imu_gcs_arb arb (
363
364	.clk (clk),
365	.rst_l (rst_l),
366
367	.gc_0_req (gc_0_req),
368	.gc_0_ino (gc_0_ino),
369	.gc_0_gnt (gc_0_gnt),
370
371	.gc_1_req (gc_1_req),
372	.gc_1_ino (gc_1_ino),
373	.gc_1_gnt (gc_1_gnt),
374
375	.gc_2_req (gc_2_req),
376	.gc_2_ino (gc_2_ino),
377	.gc_2_gnt (gc_2_gnt),
378
379
380	.gc_3_req (gc_3_req),
381	.gc_3_ino (gc_3_ino),
382	.gc_3_gnt (gc_3_gnt),
383
384
385	.next_arb (next_arb),
386
387	.gc_arb_valid (gc_arb_valid),
388	.gc_arb_ino (gc_arb_ino),
389	.gc_arb_id (gc_arb_id)
390
391	);
392
393
394
395	dmu_imu_gcs_csm csm(
396
397	.clk (clk),
398	.rst_l (rst_l),
399
400	.gcs2iss_tid_req (gcs2iss_tid_req),
401	.gcs2iss_tid_sel (gcs2iss_tid_sel),
402
403	.gcs2iss_mdo_pending (gcs2iss_mdo_pending),
404	.iss2gcs_tid_ack (iss2gcs_tid_ack),
405	.iss2gcs_tid (iss2gcs_tid),
406	.iss2gcs_mondo_mode (iss2gcs_mondo_mode),
407
408	.next_arb (next_arb),
409
410	.gc_arb_valid (gc_arb_valid),
411	.gc_arb_ino (gc_arb_ino),
412	.gc_arb_id (gc_arb_id),
413
414
415	.im2rm_mdo_enq (im2rm_mdo_enq),
416	.im2rm_mdo (im2rm_mdo),
417
418	.fsm_dbg (csm_fsm_dbg)
419
420	);
421
422
423
424
425
426
427	endmodule