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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_ics_defines.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dmu_imu_ics_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`ifdef FIRE_DLC_IMU_ICS_DEFINES
39`else
40`define FIRE_DLC_IMU_ICS_DEFINES
41
42`define FIRE_DLC_IMU_ICS_INSTANCE_ID_VALUE_A 1'h0
43`define FIRE_DLC_IMU_ICS_INSTANCE_ID_VALUE_B 1'h1
44
45//-------------------------------------------------------
46//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_error_log_en_reg
47//-------------------------------------------------------
48
49`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_HW_ADDR 27'b000000011000110001000000000
50`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ERROR_LOG_EN_REG_ADDR 30'b000000011000110001000000000000
51`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ERROR_LOG_EN_REG_HW_ADDR 27'b000000011100110001000000000
52`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ERROR_LOG_EN_REG_ADDR 30'b000000011100110001000000000000
53
54`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH 64
55`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_DEPTH 1
56`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SLC 63:0
57`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_INT_SLC 63:0
58`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_POSITION 0
59`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_LOW_ADDR_WIDTH 0
60`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_ADDR_RANGE 26:0
61`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000111111111111111
62`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
63`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000111111111111111
64`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
65`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
66`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
67`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
68`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_RMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
69`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111000000000000000
70`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
71`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000111111111111111
72`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_INTERNAL_REG 1
73`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_ZERO_TIME_OMNI 1
74`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NUM_FIELDS 11
75`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_FID 0
76`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_SLC 14:10
77`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_WIDTH 5
78`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC 4:0
79`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_POSITION 10
80`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000111110000000000
81`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
82`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_POR_VALUE 5'b11111
83`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_FID 1
84`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_SLC 9:9
85`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_WIDTH 1
86`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_INT_SLC 0:0
87`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_POSITION 9
88`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
89`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
90`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_OVER_LOG_EN_POR_VALUE 1'b1
91`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_FID 2
92`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_SLC 8:8
93`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_WIDTH 1
94`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_INT_SLC 0:0
95`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_POSITION 8
96`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
97`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
98`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_EQ_NOT_EN_LOG_EN_POR_VALUE 1'b1
99`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_FID 3
100`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_SLC 7:7
101`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_WIDTH 1
102`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_INT_SLC 0:0
103`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_POSITION 7
104`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
105`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
106`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_MAL_ERR_LOG_EN_POR_VALUE 1'b1
107`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_FID 4
108`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_SLC 6:6
109`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_WIDTH 1
110`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_INT_SLC 0:0
111`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_POSITION 6
112`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
113`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
114`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_PAR_ERR_LOG_EN_POR_VALUE 1'b1
115`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_FID 5
116`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_SLC 5:5
117`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_WIDTH 1
118`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_INT_SLC 0:0
119`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_POSITION 5
120`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
121`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
122`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMEACK_MES_NOT_EN_LOG_EN_POR_VALUE 1'b1
123`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_FID 6
124`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_SLC 4:4
125`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_WIDTH 1
126`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_INT_SLC 0:0
127`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_POSITION 4
128`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
129`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
130`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_PMPME_MES_NOT_EN_LOG_EN_POR_VALUE 1'b1
131`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_FID 7
132`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_SLC 3:3
133`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_WIDTH 1
134`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_INT_SLC 0:0
135`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_POSITION 3
136`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
137`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
138`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_FATAL_MES_NOT_EN_LOG_EN_POR_VALUE 1'b1
139`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_FID 8
140`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_SLC 2:2
141`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_WIDTH 1
142`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_INT_SLC 0:0
143`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_POSITION 2
144`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
145`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
146`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_NONFATAL_MES_NOT_EN_LOG_EN_POR_VALUE 1'b1
147`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_FID 9
148`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_SLC 1:1
149`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_WIDTH 1
150`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_INT_SLC 0:0
151`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_POSITION 1
152`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
153`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
154`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_COR_MES_NOT_EN_LOG_EN_POR_VALUE 1'b1
155`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_FID 10
156`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_SLC 0:0
157`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_WIDTH 1
158`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_INT_SLC 0:0
159`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_POSITION 0
160`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
161`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
162`define FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_MSI_NOT_EN_LOG_EN_POR_VALUE 1'b1
163
164//-------------------------------------------------------
165//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_int_en_reg
166//-------------------------------------------------------
167
168`define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_HW_ADDR 27'b000000011000110001000000001
169`define FIRE_DLC_IMU_ICS_CSR_A_IMU_INT_EN_REG_ADDR 30'b000000011000110001000000001000
170`define FIRE_DLC_IMU_ICS_CSR_B_IMU_INT_EN_REG_HW_ADDR 27'b000000011100110001000000001
171`define FIRE_DLC_IMU_ICS_CSR_B_IMU_INT_EN_REG_ADDR 30'b000000011100110001000000001000
172
173`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WIDTH 64
174`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_DEPTH 1
175`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SLC 63:0
176`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_INT_SLC 63:0
177`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_POSITION 0
178`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_LOW_ADDR_WIDTH 0
179`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_ADDR_RANGE 26:0
180`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_READ_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
181`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
182`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WRITE_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
183`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
184`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
185`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
186`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
187`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_RMASK 64'b0000000000000000011111111111111100000000000000000111111111111111
188`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_RESERVED_BIT_MASK 64'b1111111111111111100000000000000011111111111111111000000000000000
189`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
190`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
191`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_INTERNAL_REG 1
192`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_ZERO_TIME_OMNI 1
193`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NUM_FIELDS 22
194`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_FID 0
195`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_SLC 46:42
196`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_WIDTH 5
197`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_INT_SLC 4:0
198`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_POSITION 42
199`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_FMASK 64'b0000000000000000011111000000000000000000000000000000000000000000
200`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
201`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_S_INT_EN_POR_VALUE 5'b00000
202`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_FID 1
203`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_SLC 41:41
204`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_WIDTH 1
205`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_INT_SLC 0:0
206`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_POSITION 41
207`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
208`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
209`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_S_INT_EN_POR_VALUE 1'b0
210`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_FID 2
211`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_SLC 40:40
212`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_WIDTH 1
213`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_INT_SLC 0:0
214`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_POSITION 40
215`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
216`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
217`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_S_INT_EN_POR_VALUE 1'b0
218`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_FID 3
219`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_SLC 39:39
220`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_WIDTH 1
221`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_INT_SLC 0:0
222`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_POSITION 39
223`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
224`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
225`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_S_INT_EN_POR_VALUE 1'b0
226`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_FID 4
227`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_SLC 38:38
228`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_WIDTH 1
229`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_INT_SLC 0:0
230`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_POSITION 38
231`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
232`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
233`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_S_INT_EN_POR_VALUE 1'b0
234`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_FID 5
235`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_SLC 37:37
236`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_WIDTH 1
237`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_INT_SLC 0:0
238`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_POSITION 37
239`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
240`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
241`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_S_INT_EN_POR_VALUE 1'b0
242`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_FID 6
243`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_SLC 36:36
244`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_WIDTH 1
245`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_INT_SLC 0:0
246`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_POSITION 36
247`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
248`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
249`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_S_INT_EN_POR_VALUE 1'b0
250`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_FID 7
251`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_SLC 35:35
252`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_WIDTH 1
253`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_INT_SLC 0:0
254`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_POSITION 35
255`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_FMASK 64'b0000000000000000000000000000100000000000000000000000000000000000
256`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
257`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_S_INT_EN_POR_VALUE 1'b0
258`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_FID 8
259`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_SLC 34:34
260`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_WIDTH 1
261`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_INT_SLC 0:0
262`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_POSITION 34
263`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
264`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
265`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_S_INT_EN_POR_VALUE 1'b0
266`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_FID 9
267`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_SLC 33:33
268`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_WIDTH 1
269`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_INT_SLC 0:0
270`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_POSITION 33
271`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
272`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
273`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_S_INT_EN_POR_VALUE 1'b0
274`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_FID 10
275`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_SLC 32:32
276`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_WIDTH 1
277`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_INT_SLC 0:0
278`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_POSITION 32
279`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
280`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
281`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_S_INT_EN_POR_VALUE 1'b0
282`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_FID 11
283`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_SLC 14:10
284`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_WIDTH 5
285`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_INT_SLC 4:0
286`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_POSITION 10
287`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000111110000000000
288`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
289`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_SPARE_P_INT_EN_POR_VALUE 5'b00000
290`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_FID 12
291`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_SLC 9:9
292`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_WIDTH 1
293`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_INT_SLC 0:0
294`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_POSITION 9
295`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
296`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
297`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_OVER_P_INT_EN_POR_VALUE 1'b0
298`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_FID 13
299`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_SLC 8:8
300`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_WIDTH 1
301`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_INT_SLC 0:0
302`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_POSITION 8
303`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
304`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
305`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_EQ_NOT_EN_P_INT_EN_POR_VALUE 1'b0
306`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_FID 14
307`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_SLC 7:7
308`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_WIDTH 1
309`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_INT_SLC 0:0
310`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_POSITION 7
311`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
312`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
313`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_MAL_ERR_P_INT_EN_POR_VALUE 1'b0
314`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_FID 15
315`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_SLC 6:6
316`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_WIDTH 1
317`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_INT_SLC 0:0
318`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_POSITION 6
319`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
320`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
321`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_PAR_ERR_P_INT_EN_POR_VALUE 1'b0
322`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_FID 16
323`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_SLC 5:5
324`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_WIDTH 1
325`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_INT_SLC 0:0
326`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_POSITION 5
327`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
328`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
329`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMEACK_MES_NOT_EN_P_INT_EN_POR_VALUE 1'b0
330`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_FID 17
331`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_SLC 4:4
332`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_WIDTH 1
333`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_INT_SLC 0:0
334`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_POSITION 4
335`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
336`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
337`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_PMPME_MES_NOT_EN_P_INT_EN_POR_VALUE 1'b0
338`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_FID 18
339`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_SLC 3:3
340`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_WIDTH 1
341`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_INT_SLC 0:0
342`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_POSITION 3
343`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
344`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
345`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_FATAL_MES_NOT_EN_P_INT_EN_POR_VALUE 1'b0
346`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_FID 19
347`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_SLC 2:2
348`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_WIDTH 1
349`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_INT_SLC 0:0
350`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_POSITION 2
351`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
352`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
353`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_NONFATAL_MES_NOT_EN_P_INT_EN_POR_VALUE 1'b0
354`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_FID 20
355`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_SLC 1:1
356`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_WIDTH 1
357`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_INT_SLC 0:0
358`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_POSITION 1
359`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
360`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
361`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_COR_MES_NOT_EN_P_INT_EN_POR_VALUE 1'b0
362`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_FID 21
363`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_SLC 0:0
364`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_WIDTH 1
365`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_INT_SLC 0:0
366`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_POSITION 0
367`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
368`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
369`define FIRE_DLC_IMU_ICS_CSR_IMU_INT_EN_REG_MSI_NOT_EN_P_INT_EN_POR_VALUE 1'b0
370
371//-------------------------------------------------------
372//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_enabled_error_status_reg
373//-------------------------------------------------------
374
375`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_HW_ADDR 27'b000000011000110001000000010
376`define FIRE_DLC_IMU_ICS_CSR_A_IMU_ENABLED_ERROR_STATUS_REG_ADDR 30'b000000011000110001000000010000
377`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ENABLED_ERROR_STATUS_REG_HW_ADDR 27'b000000011100110001000000010
378`define FIRE_DLC_IMU_ICS_CSR_B_IMU_ENABLED_ERROR_STATUS_REG_ADDR 30'b000000011100110001000000010000
379
380`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_WIDTH 64
381`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_DEPTH 1
382`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SLC 63:0
383`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_INT_SLC 63:0
384`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_POSITION 0
385`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_LOW_ADDR_WIDTH 0
386`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_ADDR_RANGE 26:0
387`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_READ_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
388`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_READ_ONLY_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
389`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
390`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
391`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
392`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
393`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
394`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_RMASK 64'b0000000000000000011111111111111100000000000000000111111111111111
395`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_RESERVED_BIT_MASK 64'b1111111111111111100000000000000011111111111111111000000000000000
396`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_HW_LD_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
397`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
398`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_INTERNAL_REG 0
399`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EXTERNAL_DECODE_REG 1
400`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_ZERO_TIME_OMNI 0
401`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NUM_FIELDS 22
402`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_FID 0
403`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_SLC 46:42
404`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_WIDTH 5
405`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_INT_SLC 4:0
406`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_POSITION 42
407`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_FMASK 64'b0000000000000000011111000000000000000000000000000000000000000000
408`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_HW_LD_MASK 64'b0000000000000000011111000000000000000000000000000000000000000000
409`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_S_POR_VALUE 5'b00000
410`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_FID 1
411`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_SLC 41:41
412`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_WIDTH 1
413`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_INT_SLC 0:0
414`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_POSITION 41
415`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
416`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_HW_LD_MASK 64'b0000000000000000000000100000000000000000000000000000000000000000
417`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_S_POR_VALUE 1'b0
418`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_FID 2
419`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_SLC 40:40
420`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_WIDTH 1
421`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_INT_SLC 0:0
422`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_POSITION 40
423`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
424`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000010000000000000000000000000000000000000000
425`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_S_POR_VALUE 1'b0
426`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_FID 3
427`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_SLC 39:39
428`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_WIDTH 1
429`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_INT_SLC 0:0
430`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_POSITION 39
431`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
432`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
433`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_S_POR_VALUE 1'b0
434`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_FID 4
435`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_SLC 38:38
436`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_WIDTH 1
437`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_INT_SLC 0:0
438`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_POSITION 38
439`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
440`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
441`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_S_POR_VALUE 1'b0
442`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_FID 5
443`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_SLC 37:37
444`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_WIDTH 1
445`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_INT_SLC 0:0
446`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_POSITION 37
447`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
448`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
449`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_S_POR_VALUE 1'b0
450`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_FID 6
451`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_SLC 36:36
452`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_WIDTH 1
453`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_INT_SLC 0:0
454`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_POSITION 36
455`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
456`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
457`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_S_POR_VALUE 1'b0
458`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_FID 7
459`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_SLC 35:35
460`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_WIDTH 1
461`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_INT_SLC 0:0
462`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_POSITION 35
463`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000100000000000000000000000000000000000
464`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000100000000000000000000000000000000000
465`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_S_POR_VALUE 1'b0
466`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_FID 8
467`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_SLC 34:34
468`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_WIDTH 1
469`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_INT_SLC 0:0
470`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_POSITION 34
471`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
472`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000010000000000000000000000000000000000
473`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_S_POR_VALUE 1'b0
474`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_FID 9
475`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_SLC 33:33
476`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_WIDTH 1
477`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_INT_SLC 0:0
478`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_POSITION 33
479`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
480`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000001000000000000000000000000000000000
481`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_S_POR_VALUE 1'b0
482`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_FID 10
483`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_SLC 32:32
484`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_WIDTH 1
485`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_INT_SLC 0:0
486`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_POSITION 32
487`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
488`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000000100000000000000000000000000000000
489`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_S_POR_VALUE 1'b0
490`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_FID 11
491`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_SLC 14:10
492`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_WIDTH 5
493`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_INT_SLC 4:0
494`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_POSITION 10
495`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_FMASK 64'b0000000000000000000000000000000000000000000000000111110000000000
496`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000111110000000000
497`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_SPARE_P_POR_VALUE 5'b00000
498`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_FID 12
499`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_SLC 9:9
500`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_WIDTH 1
501`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_INT_SLC 0:0
502`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_POSITION 9
503`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
504`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
505`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_OVER_P_POR_VALUE 1'b0
506`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_FID 13
507`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_SLC 8:8
508`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_WIDTH 1
509`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_INT_SLC 0:0
510`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_POSITION 8
511`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
512`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
513`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_EQ_NOT_EN_P_POR_VALUE 1'b0
514`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_FID 14
515`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_SLC 7:7
516`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_WIDTH 1
517`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_INT_SLC 0:0
518`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_POSITION 7
519`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
520`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
521`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_MAL_ERR_P_POR_VALUE 1'b0
522`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_FID 15
523`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_SLC 6:6
524`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_WIDTH 1
525`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_INT_SLC 0:0
526`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_POSITION 6
527`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
528`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
529`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_PAR_ERR_P_POR_VALUE 1'b0
530`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_FID 16
531`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_SLC 5:5
532`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_WIDTH 1
533`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_INT_SLC 0:0
534`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_POSITION 5
535`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
536`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
537`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMEACK_MES_NOT_EN_P_POR_VALUE 1'b0
538`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_FID 17
539`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_SLC 4:4
540`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_WIDTH 1
541`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_INT_SLC 0:0
542`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_POSITION 4
543`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
544`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
545`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_PMPME_MES_NOT_EN_P_POR_VALUE 1'b0
546`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_FID 18
547`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_SLC 3:3
548`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_WIDTH 1
549`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_INT_SLC 0:0
550`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_POSITION 3
551`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
552`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
553`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_FATAL_MES_NOT_EN_P_POR_VALUE 1'b0
554`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_FID 19
555`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_SLC 2:2
556`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_WIDTH 1
557`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_INT_SLC 0:0
558`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_POSITION 2
559`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
560`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
561`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_NONFATAL_MES_NOT_EN_P_POR_VALUE 1'b0
562`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_FID 20
563`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_SLC 1:1
564`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_WIDTH 1
565`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_INT_SLC 0:0
566`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_POSITION 1
567`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
568`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
569`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_COR_MES_NOT_EN_P_POR_VALUE 1'b0
570`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_FID 21
571`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_SLC 0:0
572`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_WIDTH 1
573`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_INT_SLC 0:0
574`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_POSITION 0
575`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
576`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
577`define FIRE_DLC_IMU_ICS_CSR_IMU_ENABLED_ERROR_STATUS_REG_MSI_NOT_EN_P_POR_VALUE 1'b0
578
579//-------------------------------------------------------
580//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_logged_error_status_reg_rw1c_alias
581//-------------------------------------------------------
582
583`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_ADDR 27'b000000011000110001000000011
584`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR 30'b000000011000110001000000011000
585`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_ADDR 27'b000000011100110001000000011
586`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR 30'b000000011100110001000000011000
587
588`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH 64
589`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_DEPTH 1
590`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SLC 63:0
591`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_INT_SLC 63:0
592`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POSITION 0
593`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_LOW_ADDR_WIDTH 0
594`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ADDR_RANGE 26:0
595`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_READ_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
596`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
597`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
598`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
599`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
600`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_CLEAR_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
601`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
602`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_RMASK 64'b0000000000000000011111111111111100000000000000000111111111111111
603`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_RESERVED_BIT_MASK 64'b1111111111111111100000000000000011111111111111111000000000000000
604`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_HW_LD_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
605`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
606`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_INTERNAL_REG 1
607`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_ZERO_TIME_OMNI 1
608`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NUM_FIELDS 22
609`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_FID 0
610`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_SLC 46:42
611`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_WIDTH 5
612`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC 4:0
613`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_POSITION 42
614`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_FMASK 64'b0000000000000000011111000000000000000000000000000000000000000000
615`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_HW_LD_MASK 64'b0000000000000000011111000000000000000000000000000000000000000000
616`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_POR_VALUE 5'b00000
617`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_FID 1
618`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_SLC 41:41
619`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_WIDTH 1
620`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_INT_SLC 0:0
621`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_POSITION 41
622`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
623`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_HW_LD_MASK 64'b0000000000000000000000100000000000000000000000000000000000000000
624`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_S_POR_VALUE 1'b0
625`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_FID 2
626`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_SLC 40:40
627`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_WIDTH 1
628`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_INT_SLC 0:0
629`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_POSITION 40
630`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
631`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000010000000000000000000000000000000000000000
632`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_S_POR_VALUE 1'b0
633`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_FID 3
634`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_SLC 39:39
635`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_WIDTH 1
636`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_INT_SLC 0:0
637`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_POSITION 39
638`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
639`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
640`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_S_POR_VALUE 1'b0
641`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_FID 4
642`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_SLC 38:38
643`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_WIDTH 1
644`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_INT_SLC 0:0
645`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_POSITION 38
646`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
647`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
648`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_S_POR_VALUE 1'b0
649`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_FID 5
650`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_SLC 37:37
651`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_WIDTH 1
652`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_INT_SLC 0:0
653`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_POSITION 37
654`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
655`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
656`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_S_POR_VALUE 1'b0
657`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_FID 6
658`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_SLC 36:36
659`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_WIDTH 1
660`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_INT_SLC 0:0
661`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_POSITION 36
662`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
663`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
664`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_S_POR_VALUE 1'b0
665`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_FID 7
666`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_SLC 35:35
667`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_WIDTH 1
668`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_INT_SLC 0:0
669`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_POSITION 35
670`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000100000000000000000000000000000000000
671`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000100000000000000000000000000000000000
672`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_S_POR_VALUE 1'b0
673`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_FID 8
674`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_SLC 34:34
675`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_WIDTH 1
676`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_INT_SLC 0:0
677`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_POSITION 34
678`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
679`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000010000000000000000000000000000000000
680`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_S_POR_VALUE 1'b0
681`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_FID 9
682`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_SLC 33:33
683`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_WIDTH 1
684`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_INT_SLC 0:0
685`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_POSITION 33
686`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
687`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000001000000000000000000000000000000000
688`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_S_POR_VALUE 1'b0
689`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_FID 10
690`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_SLC 32:32
691`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_WIDTH 1
692`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_INT_SLC 0:0
693`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_POSITION 32
694`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
695`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000000100000000000000000000000000000000
696`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_S_POR_VALUE 1'b0
697`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_FID 11
698`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_SLC 14:10
699`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_WIDTH 5
700`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC 4:0
701`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_POSITION 10
702`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_FMASK 64'b0000000000000000000000000000000000000000000000000111110000000000
703`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000111110000000000
704`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_POR_VALUE 5'b00000
705`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_FID 12
706`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_SLC 9:9
707`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_WIDTH 1
708`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_INT_SLC 0:0
709`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_POSITION 9
710`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
711`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
712`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_OVER_P_POR_VALUE 1'b0
713`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_FID 13
714`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_SLC 8:8
715`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_WIDTH 1
716`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_INT_SLC 0:0
717`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_POSITION 8
718`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
719`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
720`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_EQ_NOT_EN_P_POR_VALUE 1'b0
721`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_FID 14
722`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_SLC 7:7
723`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_WIDTH 1
724`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_INT_SLC 0:0
725`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_POSITION 7
726`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
727`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
728`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_MAL_ERR_P_POR_VALUE 1'b0
729`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_FID 15
730`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_SLC 6:6
731`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_WIDTH 1
732`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_INT_SLC 0:0
733`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_POSITION 6
734`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
735`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
736`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_PAR_ERR_P_POR_VALUE 1'b0
737`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_FID 16
738`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_SLC 5:5
739`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_WIDTH 1
740`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_INT_SLC 0:0
741`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_POSITION 5
742`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
743`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
744`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMEACK_MES_NOT_EN_P_POR_VALUE 1'b0
745`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_FID 17
746`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_SLC 4:4
747`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_WIDTH 1
748`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_INT_SLC 0:0
749`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_POSITION 4
750`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
751`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
752`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_PMPME_MES_NOT_EN_P_POR_VALUE 1'b0
753`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_FID 18
754`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_SLC 3:3
755`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_WIDTH 1
756`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_INT_SLC 0:0
757`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_POSITION 3
758`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
759`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
760`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_FATAL_MES_NOT_EN_P_POR_VALUE 1'b0
761`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_FID 19
762`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_SLC 2:2
763`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_WIDTH 1
764`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_INT_SLC 0:0
765`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_POSITION 2
766`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
767`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
768`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_NONFATAL_MES_NOT_EN_P_POR_VALUE 1'b0
769`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_FID 20
770`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_SLC 1:1
771`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_WIDTH 1
772`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_INT_SLC 0:0
773`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_POSITION 1
774`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
775`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
776`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_COR_MES_NOT_EN_P_POR_VALUE 1'b0
777`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_FID 21
778`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_SLC 0:0
779`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_WIDTH 1
780`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_INT_SLC 0:0
781`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_POSITION 0
782`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
783`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
784`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_MSI_NOT_EN_P_POR_VALUE 1'b0
785
786//-------------------------------------------------------
787//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_logged_error_status_reg_rw1s_alias
788//-------------------------------------------------------
789
790`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_ADDR 27'b000000011000110001000000100
791`define FIRE_DLC_IMU_ICS_CSR_A_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR 30'b000000011000110001000000100000
792`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_ADDR 27'b000000011100110001000000100
793`define FIRE_DLC_IMU_ICS_CSR_B_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR 30'b000000011100110001000000100000
794
795`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WIDTH 64
796`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_DEPTH 1
797`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SLC 63:0
798`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_INT_SLC 63:0
799`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POSITION 0
800`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_LOW_ADDR_WIDTH 0
801`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ADDR_RANGE 26:0
802`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_READ_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
803`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
804`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
805`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
806`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SET_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
807`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
808`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
809`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_RMASK 64'b0000000000000000011111111111111100000000000000000111111111111111
810`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_RESERVED_BIT_MASK 64'b1111111111111111100000000000000011111111111111111000000000000000
811`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_HW_LD_MASK 64'b0000000000000000011111111111111100000000000000000111111111111111
812`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
813`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_INTERNAL_REG 1
814`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_ZERO_TIME_OMNI 1
815`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NUM_FIELDS 22
816`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_FID 0
817`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_SLC 46:42
818`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_WIDTH 5
819`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_INT_SLC 4:0
820`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_POSITION 42
821`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_FMASK 64'b0000000000000000011111000000000000000000000000000000000000000000
822`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_HW_LD_MASK 64'b0000000000000000011111000000000000000000000000000000000000000000
823`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_S_POR_VALUE 5'b00000
824`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_FID 1
825`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_SLC 41:41
826`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_WIDTH 1
827`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_INT_SLC 0:0
828`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_POSITION 41
829`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
830`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_HW_LD_MASK 64'b0000000000000000000000100000000000000000000000000000000000000000
831`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_S_POR_VALUE 1'b0
832`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_FID 2
833`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_SLC 40:40
834`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_WIDTH 1
835`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_INT_SLC 0:0
836`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_POSITION 40
837`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
838`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000010000000000000000000000000000000000000000
839`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_S_POR_VALUE 1'b0
840`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_FID 3
841`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_SLC 39:39
842`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_WIDTH 1
843`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_INT_SLC 0:0
844`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_POSITION 39
845`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
846`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
847`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_S_POR_VALUE 1'b0
848`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_FID 4
849`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_SLC 38:38
850`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_WIDTH 1
851`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_INT_SLC 0:0
852`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_POSITION 38
853`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
854`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
855`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_S_POR_VALUE 1'b0
856`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_FID 5
857`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_SLC 37:37
858`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_WIDTH 1
859`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_INT_SLC 0:0
860`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_POSITION 37
861`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
862`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
863`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_S_POR_VALUE 1'b0
864`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_FID 6
865`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_SLC 36:36
866`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_WIDTH 1
867`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_INT_SLC 0:0
868`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_POSITION 36
869`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
870`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
871`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_S_POR_VALUE 1'b0
872`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_FID 7
873`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_SLC 35:35
874`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_WIDTH 1
875`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_INT_SLC 0:0
876`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_POSITION 35
877`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000100000000000000000000000000000000000
878`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000100000000000000000000000000000000000
879`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_S_POR_VALUE 1'b0
880`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_FID 8
881`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_SLC 34:34
882`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_WIDTH 1
883`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_INT_SLC 0:0
884`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_POSITION 34
885`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
886`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000010000000000000000000000000000000000
887`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_S_POR_VALUE 1'b0
888`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_FID 9
889`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_SLC 33:33
890`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_WIDTH 1
891`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_INT_SLC 0:0
892`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_POSITION 33
893`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
894`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000001000000000000000000000000000000000
895`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_S_POR_VALUE 1'b0
896`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_FID 10
897`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_SLC 32:32
898`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_WIDTH 1
899`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_INT_SLC 0:0
900`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_POSITION 32
901`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
902`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_HW_LD_MASK 64'b0000000000000000000000000000000100000000000000000000000000000000
903`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_S_POR_VALUE 1'b0
904`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_FID 11
905`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_SLC 14:10
906`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_WIDTH 5
907`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_INT_SLC 4:0
908`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_POSITION 10
909`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_FMASK 64'b0000000000000000000000000000000000000000000000000111110000000000
910`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000111110000000000
911`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_SPARE_P_POR_VALUE 5'b00000
912`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_FID 12
913`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_SLC 9:9
914`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_WIDTH 1
915`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_INT_SLC 0:0
916`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_POSITION 9
917`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
918`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
919`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_OVER_P_POR_VALUE 1'b0
920`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_FID 13
921`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_SLC 8:8
922`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_WIDTH 1
923`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_INT_SLC 0:0
924`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_POSITION 8
925`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
926`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
927`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_EQ_NOT_EN_P_POR_VALUE 1'b0
928`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_FID 14
929`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_SLC 7:7
930`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_WIDTH 1
931`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_INT_SLC 0:0
932`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_POSITION 7
933`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
934`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
935`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_MAL_ERR_P_POR_VALUE 1'b0
936`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_FID 15
937`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_SLC 6:6
938`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_WIDTH 1
939`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_INT_SLC 0:0
940`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_POSITION 6
941`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
942`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
943`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_PAR_ERR_P_POR_VALUE 1'b0
944`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_FID 16
945`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_SLC 5:5
946`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_WIDTH 1
947`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_INT_SLC 0:0
948`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_POSITION 5
949`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
950`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
951`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMEACK_MES_NOT_EN_P_POR_VALUE 1'b0
952`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_FID 17
953`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_SLC 4:4
954`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_WIDTH 1
955`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_INT_SLC 0:0
956`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_POSITION 4
957`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
958`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
959`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_PMPME_MES_NOT_EN_P_POR_VALUE 1'b0
960`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_FID 18
961`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_SLC 3:3
962`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_WIDTH 1
963`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_INT_SLC 0:0
964`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_POSITION 3
965`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
966`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
967`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_FATAL_MES_NOT_EN_P_POR_VALUE 1'b0
968`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_FID 19
969`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_SLC 2:2
970`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_WIDTH 1
971`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_INT_SLC 0:0
972`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_POSITION 2
973`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
974`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
975`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_NONFATAL_MES_NOT_EN_P_POR_VALUE 1'b0
976`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_FID 20
977`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_SLC 1:1
978`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_WIDTH 1
979`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_INT_SLC 0:0
980`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_POSITION 1
981`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
982`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
983`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_COR_MES_NOT_EN_P_POR_VALUE 1'b0
984`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_FID 21
985`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_SLC 0:0
986`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_WIDTH 1
987`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_INT_SLC 0:0
988`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_POSITION 0
989`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
990`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
991`define FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1S_ALIAS_MSI_NOT_EN_P_POR_VALUE 1'b0
992
993//-------------------------------------------------------
994//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_rds_error_log_reg
995//-------------------------------------------------------
996
997`define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_HW_ADDR 27'b000000011000110001000000101
998`define FIRE_DLC_IMU_ICS_CSR_A_IMU_RDS_ERROR_LOG_REG_ADDR 30'b000000011000110001000000101000
999`define FIRE_DLC_IMU_ICS_CSR_B_IMU_RDS_ERROR_LOG_REG_HW_ADDR 27'b000000011100110001000000101
1000`define FIRE_DLC_IMU_ICS_CSR_B_IMU_RDS_ERROR_LOG_REG_ADDR 30'b000000011100110001000000101000
1001
1002`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WIDTH 64
1003`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_DEPTH 1
1004`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_SLC 63:0
1005`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_INT_SLC 63:0
1006`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_POSITION 0
1007`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LOW_ADDR_WIDTH 0
1008`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_ADDR_RANGE 26:0
1009`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1010`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1011`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1012`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1013`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1014`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1015`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1016`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1017`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1018`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1019`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1020`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_INTERNAL_REG 1
1021`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_ZERO_TIME_OMNI 1
1022`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_NUM_FIELDS 6
1023`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_FID 0
1024`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_SLC 63:58
1025`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_WIDTH 6
1026`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_INT_SLC 5:0
1027`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_POSITION 58
1028`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_FMASK 64'b1111110000000000000000000000000000000000000000000000000000000000
1029`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_HW_LD_MASK 64'b1111110000000000000000000000000000000000000000000000000000000000
1030`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TYPE_POR_VALUE 6'b000000
1031`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_FID 1
1032`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_SLC 57:48
1033`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_WIDTH 10
1034`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_INT_SLC 9:0
1035`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_POSITION 48
1036`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_FMASK 64'b0000001111111111000000000000000000000000000000000000000000000000
1037`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_HW_LD_MASK 64'b0000001111111111000000000000000000000000000000000000000000000000
1038`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_LENGTH_POR_VALUE 10'b0000000000
1039`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_FID 2
1040`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_SLC 47:32
1041`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_WIDTH 16
1042`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_INT_SLC 15:0
1043`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_POSITION 32
1044`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_FMASK 64'b0000000000000000111111111111111100000000000000000000000000000000
1045`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_HW_LD_MASK 64'b0000000000000000111111111111111100000000000000000000000000000000
1046`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_REQ_ID_POR_VALUE 16'b0000000000000000
1047`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_FID 3
1048`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_SLC 31:24
1049`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_WIDTH 8
1050`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_INT_SLC 7:0
1051`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_POSITION 24
1052`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_FMASK 64'b0000000000000000000000000000000011111111000000000000000000000000
1053`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_HW_LD_MASK 64'b0000000000000000000000000000000011111111000000000000000000000000
1054`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_TLP_TAG_POR_VALUE 8'b00000000
1055`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_FID 4
1056`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_SLC 23:16
1057`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_WIDTH 8
1058`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_INT_SLC 7:0
1059`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_POSITION 16
1060`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
1061`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000111111110000000000000000
1062`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_BE_MESS_CODE_POR_VALUE 8'b00000000
1063`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_FID 5
1064`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_SLC 15:0
1065`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_WIDTH 16
1066`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_INT_SLC 15:0
1067`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_POSITION 0
1068`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1069`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1070`define FIRE_DLC_IMU_ICS_CSR_IMU_RDS_ERROR_LOG_REG_MSI_DATA_POR_VALUE 16'b0000000000000000
1071
1072//-------------------------------------------------------
1073//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_scs_error_log_reg
1074//-------------------------------------------------------
1075
1076`define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_HW_ADDR 27'b000000011000110001000000110
1077`define FIRE_DLC_IMU_ICS_CSR_A_IMU_SCS_ERROR_LOG_REG_ADDR 30'b000000011000110001000000110000
1078`define FIRE_DLC_IMU_ICS_CSR_B_IMU_SCS_ERROR_LOG_REG_HW_ADDR 27'b000000011100110001000000110
1079`define FIRE_DLC_IMU_ICS_CSR_B_IMU_SCS_ERROR_LOG_REG_ADDR 30'b000000011100110001000000110000
1080
1081`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WIDTH 64
1082`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_DEPTH 1
1083`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_SLC 63:0
1084`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_INT_SLC 63:0
1085`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_POSITION 0
1086`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LOW_ADDR_WIDTH 0
1087`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_ADDR_RANGE 26:0
1088`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111110000000000111111
1089`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1090`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WRITE_MASK 64'b1111111111111111111111111111111111111111111111110000000000111111
1091`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1092`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1093`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1094`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1095`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_RMASK 64'b1111111111111111111111111111111111111111111111110000000000111111
1096`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000001111111111000000
1097`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111110000000000111111
1098`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1099`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_INTERNAL_REG 1
1100`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_ZERO_TIME_OMNI 1
1101`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_NUM_FIELDS 6
1102`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_FID 0
1103`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_SLC 63:58
1104`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_WIDTH 6
1105`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_INT_SLC 5:0
1106`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_POSITION 58
1107`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_FMASK 64'b1111110000000000000000000000000000000000000000000000000000000000
1108`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_HW_LD_MASK 64'b1111110000000000000000000000000000000000000000000000000000000000
1109`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TYPE_POR_VALUE 6'b000000
1110`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_FID 1
1111`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_SLC 57:48
1112`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_WIDTH 10
1113`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_INT_SLC 9:0
1114`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_POSITION 48
1115`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_FMASK 64'b0000001111111111000000000000000000000000000000000000000000000000
1116`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_HW_LD_MASK 64'b0000001111111111000000000000000000000000000000000000000000000000
1117`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_LENGTH_POR_VALUE 10'b0000000000
1118`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_FID 2
1119`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_SLC 47:32
1120`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_WIDTH 16
1121`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_INT_SLC 15:0
1122`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_POSITION 32
1123`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_FMASK 64'b0000000000000000111111111111111100000000000000000000000000000000
1124`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_HW_LD_MASK 64'b0000000000000000111111111111111100000000000000000000000000000000
1125`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_REQ_ID_POR_VALUE 16'b0000000000000000
1126`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_FID 3
1127`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_SLC 31:24
1128`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_WIDTH 8
1129`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_INT_SLC 7:0
1130`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_POSITION 24
1131`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_FMASK 64'b0000000000000000000000000000000011111111000000000000000000000000
1132`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_HW_LD_MASK 64'b0000000000000000000000000000000011111111000000000000000000000000
1133`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_TLP_TAG_POR_VALUE 8'b00000000
1134`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_FID 4
1135`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_SLC 23:16
1136`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_WIDTH 8
1137`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_INT_SLC 7:0
1138`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_POSITION 16
1139`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
1140`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000111111110000000000000000
1141`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_BE_MESS_CODE_POR_VALUE 8'b00000000
1142`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_FID 5
1143`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_SLC 5:0
1144`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_WIDTH 6
1145`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_INT_SLC 5:0
1146`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_POSITION 0
1147`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1148`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1149`define FIRE_DLC_IMU_ICS_CSR_IMU_SCS_ERROR_LOG_REG_EQ_NUM_POR_VALUE 6'b000000
1150
1151//-------------------------------------------------------
1152//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_eqs_error_log_reg
1153//-------------------------------------------------------
1154
1155`define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_HW_ADDR 27'b000000011000110001000000111
1156`define FIRE_DLC_IMU_ICS_CSR_A_IMU_EQS_ERROR_LOG_REG_ADDR 30'b000000011000110001000000111000
1157`define FIRE_DLC_IMU_ICS_CSR_B_IMU_EQS_ERROR_LOG_REG_HW_ADDR 27'b000000011100110001000000111
1158`define FIRE_DLC_IMU_ICS_CSR_B_IMU_EQS_ERROR_LOG_REG_ADDR 30'b000000011100110001000000111000
1159
1160`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH 64
1161`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_DEPTH 1
1162`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_SLC 63:0
1163`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_INT_SLC 63:0
1164`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_POSITION 0
1165`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_LOW_ADDR_WIDTH 0
1166`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_ADDR_RANGE 26:0
1167`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1168`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1169`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1170`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1171`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1172`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1173`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1174`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1175`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111000000
1176`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1177`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1178`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_INTERNAL_REG 1
1179`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_ZERO_TIME_OMNI 1
1180`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_NUM_FIELDS 1
1181`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_FID 0
1182`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_SLC 5:0
1183`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_WIDTH 6
1184`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_INT_SLC 5:0
1185`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_POSITION 0
1186`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1187`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1188`define FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_EQ_NUM_POR_VALUE 6'b000000
1189
1190//-------------------------------------------------------
1191//----- Variable definitions for register fire_dlc_imu_ics_csr_dmc_interrupt_mask_reg
1192//-------------------------------------------------------
1193
1194`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_HW_ADDR 27'b000000011000110001100000000
1195`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_MASK_REG_ADDR 30'b000000011000110001100000000000
1196`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_MASK_REG_HW_ADDR 27'b000000011100110001100000000
1197`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_MASK_REG_ADDR 30'b000000011100110001100000000000
1198
1199`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_WIDTH 64
1200`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEPTH 1
1201`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_SLC 63:0
1202`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_INT_SLC 63:0
1203`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_POSITION 0
1204`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_LOW_ADDR_WIDTH 0
1205`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_ADDR_RANGE 26:0
1206`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_READ_MASK 64'b1100000000000000000000000000000000000000000000000000000000000011
1207`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1208`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_WRITE_MASK 64'b1100000000000000000000000000000000000000000000000000000000000011
1209`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1210`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1211`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1212`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1213`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_RMASK 64'b1100000000000000000000000000000000000000000000000000000000000011
1214`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_RESERVED_BIT_MASK 64'b0011111111111111111111111111111111111111111111111111111111111100
1215`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1216`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1217`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_INTERNAL_REG 1
1218`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_ZERO_TIME_OMNI 1
1219`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_NUM_FIELDS 4
1220`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_FID 0
1221`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_SLC 63:63
1222`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_WIDTH 1
1223`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_INT_SLC 0:0
1224`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_POSITION 63
1225`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000
1226`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1227`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DMC_POR_VALUE 1'b0
1228`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_FID 1
1229`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_SLC 62:62
1230`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_WIDTH 1
1231`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_INT_SLC 0:0
1232`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_POSITION 62
1233`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_FMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
1234`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1235`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_DEBUG_TRIG_EN_POR_VALUE 1'b0
1236`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_FID 2
1237`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_SLC 1:1
1238`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_WIDTH 1
1239`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_INT_SLC 0:0
1240`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_POSITION 1
1241`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1242`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1243`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_MMU_POR_VALUE 1'b0
1244`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_FID 3
1245`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_SLC 0:0
1246`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_WIDTH 1
1247`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_INT_SLC 0:0
1248`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_POSITION 0
1249`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1250`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1251`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_MASK_REG_IMU_POR_VALUE 1'b0
1252
1253//-------------------------------------------------------
1254//----- Variable definitions for register fire_dlc_imu_ics_csr_dmc_interrupt_status_reg
1255//-------------------------------------------------------
1256
1257`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_HW_ADDR 27'b000000011000110001100000001
1258`define FIRE_DLC_IMU_ICS_CSR_A_DMC_INTERRUPT_STATUS_REG_ADDR 30'b000000011000110001100000001000
1259`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_STATUS_REG_HW_ADDR 27'b000000011100110001100000001
1260`define FIRE_DLC_IMU_ICS_CSR_B_DMC_INTERRUPT_STATUS_REG_ADDR 30'b000000011100110001100000001000
1261
1262`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_WIDTH 64
1263`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_DEPTH 1
1264`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_SLC 63:0
1265`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_INT_SLC 63:0
1266`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_POSITION 0
1267`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_LOW_ADDR_WIDTH 0
1268`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_ADDR_RANGE 26:0
1269`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
1270`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
1271`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1272`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1273`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1274`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1275`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1276`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011
1277`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
1278`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1279`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1280`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_INTERNAL_REG 0
1281`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_EXTERNAL_DECODE_REG 1
1282`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_ZERO_TIME_OMNI 0
1283`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_NUM_FIELDS 2
1284`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_FID 0
1285`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_SLC 1:1
1286`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_WIDTH 1
1287`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_INT_SLC 0:0
1288`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_POSITION 1
1289`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1290`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1291`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_MMU_POR_VALUE 1'b0
1292`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_FID 1
1293`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_SLC 0:0
1294`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_WIDTH 1
1295`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_INT_SLC 0:0
1296`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_POSITION 0
1297`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1298`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1299`define FIRE_DLC_IMU_ICS_CSR_DMC_INTERRUPT_STATUS_REG_IMU_POR_VALUE 1'b0
1300
1301//-------------------------------------------------------
1302//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_perf_cntrl
1303//-------------------------------------------------------
1304
1305`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_HW_ADDR 27'b000000011000110010000000000
1306`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNTRL_ADDR 30'b000000011000110010000000000000
1307`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNTRL_HW_ADDR 27'b000000011100110010000000000
1308`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNTRL_ADDR 30'b000000011100110010000000000000
1309
1310`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WIDTH 64
1311`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_DEPTH 1
1312`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SLC 63:0
1313`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_INT_SLC 63:0
1314`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_POSITION 0
1315`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_LOW_ADDR_WIDTH 0
1316`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_ADDR_RANGE 26:0
1317`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1318`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1319`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1320`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1321`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1322`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1323`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1324`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1325`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
1326`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1327`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1328`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_INTERNAL_REG 1
1329`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_ZERO_TIME_OMNI 1
1330`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_NUM_FIELDS 2
1331`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_FID 0
1332`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_SLC 15:8
1333`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_WIDTH 8
1334`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_INT_SLC 7:0
1335`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_POSITION 8
1336`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
1337`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1338`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL1_POR_VALUE 8'b00000000
1339`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_FID 1
1340`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_SLC 7:0
1341`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_WIDTH 8
1342`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_INT_SLC 7:0
1343`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_POSITION 0
1344`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
1345`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1346`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNTRL_SEL0_POR_VALUE 8'b00000000
1347
1348//-------------------------------------------------------
1349//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_perf_cnt0
1350//-------------------------------------------------------
1351
1352`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_HW_ADDR 27'b000000011000110010000000001
1353`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT0_ADDR 30'b000000011000110010000000001000
1354`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT0_HW_ADDR 27'b000000011100110010000000001
1355`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT0_ADDR 30'b000000011100110010000000001000
1356
1357`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_WIDTH 64
1358`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_DEPTH 1
1359`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_SLC 63:0
1360`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_INT_SLC 63:0
1361`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_POSITION 0
1362`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_LOW_ADDR_WIDTH 0
1363`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_ADDR_RANGE 26:0
1364`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1365`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1366`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1367`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1368`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1369`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1370`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1371`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1372`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1373`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1374`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1375`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_INTERNAL_REG 1
1376`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_ZERO_TIME_OMNI 1
1377`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_NUM_FIELDS 1
1378`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_FID 0
1379`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_SLC 63:0
1380`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_WIDTH 64
1381`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_INT_SLC 63:0
1382`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_POSITION 0
1383`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1384`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1385`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT0_CNT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1386
1387//-------------------------------------------------------
1388//----- Variable definitions for register fire_dlc_imu_ics_csr_imu_perf_cnt1
1389//-------------------------------------------------------
1390
1391`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_HW_ADDR 27'b000000011000110010000000010
1392`define FIRE_DLC_IMU_ICS_CSR_A_IMU_PERF_CNT1_ADDR 30'b000000011000110010000000010000
1393`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT1_HW_ADDR 27'b000000011100110010000000010
1394`define FIRE_DLC_IMU_ICS_CSR_B_IMU_PERF_CNT1_ADDR 30'b000000011100110010000000010000
1395
1396`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_WIDTH 64
1397`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_DEPTH 1
1398`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_SLC 63:0
1399`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_INT_SLC 63:0
1400`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_POSITION 0
1401`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_LOW_ADDR_WIDTH 0
1402`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_ADDR_RANGE 26:0
1403`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1404`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1405`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1406`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1407`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1408`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1409`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1410`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1411`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1412`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1413`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1414`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_INTERNAL_REG 1
1415`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_ZERO_TIME_OMNI 1
1416`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_NUM_FIELDS 1
1417`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_FID 0
1418`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_SLC 63:0
1419`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_WIDTH 64
1420`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_INT_SLC 63:0
1421`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_POSITION 0
1422`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1423`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1424`define FIRE_DLC_IMU_ICS_CSR_IMU_PERF_CNT1_CNT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1425
1426//-------------------------------------------------------
1427//----- Variable definitions for register fire_dlc_imu_ics_csr_msi_32_addr_reg
1428//-------------------------------------------------------
1429
1430`define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_HW_ADDR 27'b000000011000110100000000000
1431`define FIRE_DLC_IMU_ICS_CSR_A_MSI_32_ADDR_REG_ADDR 30'b000000011000110100000000000000
1432`define FIRE_DLC_IMU_ICS_CSR_B_MSI_32_ADDR_REG_HW_ADDR 27'b000000011100110100000000000
1433`define FIRE_DLC_IMU_ICS_CSR_B_MSI_32_ADDR_REG_ADDR 30'b000000011100110100000000000000
1434
1435`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WIDTH 64
1436`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_DEPTH 1
1437`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_SLC 63:0
1438`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_INT_SLC 63:0
1439`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_POSITION 0
1440`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_LOW_ADDR_WIDTH 0
1441`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_RANGE 26:0
1442`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_READ_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
1443`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1444`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WRITE_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
1445`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1446`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1447`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1448`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1449`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_RMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
1450`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000001111111111111111
1451`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1452`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1453`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_INTERNAL_REG 1
1454`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ZERO_TIME_OMNI 1
1455`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_NUM_FIELDS 1
1456`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_FID 0
1457`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_SLC 31:16
1458`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_WIDTH 16
1459`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_INT_SLC 15:0
1460`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_POSITION 16
1461`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
1462`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1463`define FIRE_DLC_IMU_ICS_CSR_MSI_32_ADDR_REG_ADDR_POR_VALUE 16'b0000000000000000
1464
1465//-------------------------------------------------------
1466//----- Variable definitions for register fire_dlc_imu_ics_csr_msi_64_addr_reg
1467//-------------------------------------------------------
1468
1469`define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_HW_ADDR 27'b000000011000110100000000001
1470`define FIRE_DLC_IMU_ICS_CSR_A_MSI_64_ADDR_REG_ADDR 30'b000000011000110100000000001000
1471`define FIRE_DLC_IMU_ICS_CSR_B_MSI_64_ADDR_REG_HW_ADDR 27'b000000011100110100000000001
1472`define FIRE_DLC_IMU_ICS_CSR_B_MSI_64_ADDR_REG_ADDR 30'b000000011100110100000000001000
1473
1474`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WIDTH 64
1475`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_DEPTH 1
1476`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_SLC 63:0
1477`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_INT_SLC 63:0
1478`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_POSITION 0
1479`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_LOW_ADDR_WIDTH 0
1480`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_RANGE 26:0
1481`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
1482`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1483`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WRITE_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
1484`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1485`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1486`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1487`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1488`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_RMASK 64'b1111111111111111111111111111111111111111111111110000000000000000
1489`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1490`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1491`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1492`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_INTERNAL_REG 1
1493`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ZERO_TIME_OMNI 1
1494`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_NUM_FIELDS 1
1495`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_FID 0
1496`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_SLC 63:16
1497`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_WIDTH 48
1498`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_INT_SLC 47:0
1499`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_POSITION 16
1500`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_FMASK 64'b1111111111111111111111111111111111111111111111110000000000000000
1501`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1502`define FIRE_DLC_IMU_ICS_CSR_MSI_64_ADDR_REG_ADDR_POR_VALUE 48'b000000000000000000000000000000000000000000000000
1503
1504//-------------------------------------------------------
1505//----- Variable definitions for register fire_dlc_imu_ics_csr_mem_64_pcie_offset_reg
1506//-------------------------------------------------------
1507
1508`define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_HW_ADDR 27'b000000011000110100000000011
1509`define FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR 30'b000000011000110100000000011000
1510`define FIRE_DLC_IMU_ICS_CSR_B_MEM_64_PCIE_OFFSET_REG_HW_ADDR 27'b000000011100110100000000011
1511`define FIRE_DLC_IMU_ICS_CSR_B_MEM_64_PCIE_OFFSET_REG_ADDR 30'b000000011100110100000000011000
1512
1513`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH 64
1514`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_DEPTH 1
1515`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SLC 63:0
1516`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_INT_SLC 63:0
1517`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_POSITION 0
1518`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_LOW_ADDR_WIDTH 0
1519`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_RANGE 26:0
1520`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1521`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1522`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1523`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1524`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1525`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1526`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1527`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1528`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1529`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000111111111111111100000000
1530`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1531`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_INTERNAL_REG 1
1532`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ZERO_TIME_OMNI 1
1533`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_NUM_FIELDS 11
1534`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_FID 0
1535`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_SLC 63:24
1536`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_WIDTH 40
1537`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_INT_SLC 39:0
1538`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_POSITION 24
1539`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_FMASK 64'b1111111111111111111111111111111111111111000000000000000000000000
1540`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1541`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_ADDR_POR_VALUE 40'b0000000000000000000000000000000000000000
1542`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_FID 1
1543`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_SLC 23:23
1544`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_WIDTH 1
1545`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_INT_SLC 0:0
1546`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_POSITION 23
1547`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_FMASK 64'b0000000000000000000000000000000000000000100000000000000000000000
1548`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_HW_LD_MASK 64'b0000000000000000000000000000000000000000100000000000000000000000
1549`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_7_POR_VALUE 1'b0
1550`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_FID 2
1551`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_SLC 22:22
1552`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_WIDTH 1
1553`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_INT_SLC 0:0
1554`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_POSITION 22
1555`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_FMASK 64'b0000000000000000000000000000000000000000010000000000000000000000
1556`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_HW_LD_MASK 64'b0000000000000000000000000000000000000000010000000000000000000000
1557`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_6_POR_VALUE 1'b0
1558`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_FID 3
1559`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_SLC 21:21
1560`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_WIDTH 1
1561`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_INT_SLC 0:0
1562`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_POSITION 21
1563`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_FMASK 64'b0000000000000000000000000000000000000000001000000000000000000000
1564`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_HW_LD_MASK 64'b0000000000000000000000000000000000000000001000000000000000000000
1565`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_5_POR_VALUE 1'b0
1566`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_FID 4
1567`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_SLC 20:20
1568`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_WIDTH 1
1569`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_INT_SLC 0:0
1570`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_POSITION 20
1571`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1572`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1573`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_4_POR_VALUE 1'b0
1574`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_FID 5
1575`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_SLC 19:19
1576`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_WIDTH 1
1577`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_INT_SLC 0:0
1578`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_POSITION 19
1579`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
1580`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000010000000000000000000
1581`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_3_POR_VALUE 1'b0
1582`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_FID 6
1583`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_SLC 18:18
1584`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_WIDTH 1
1585`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_INT_SLC 0:0
1586`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_POSITION 18
1587`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1588`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1589`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_2_POR_VALUE 1'b0
1590`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_FID 7
1591`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_SLC 17:17
1592`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_WIDTH 1
1593`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_INT_SLC 0:0
1594`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_POSITION 17
1595`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1596`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1597`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_1_POR_VALUE 1'b0
1598`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_FID 8
1599`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_SLC 16:16
1600`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_WIDTH 1
1601`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_INT_SLC 0:0
1602`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_POSITION 16
1603`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1604`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1605`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_LOAD_0_POR_VALUE 1'b0
1606`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_FID 9
1607`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_SLC 15:8
1608`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_WIDTH 8
1609`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC 7:0
1610`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_POSITION 8
1611`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
1612`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111100000000
1613`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_POR_VALUE 8'b00000000
1614`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_FID 10
1615`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_SLC 7:0
1616`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_WIDTH 8
1617`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_INT_SLC 7:0
1618`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_POSITION 0
1619`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
1620`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1621`define FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_STATUS_POR_VALUE 8'b00000000
1622
1623
1624`endif
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