Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_rds_mess_addr_decode.v
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2//
3// OpenSPARC T2 Processor File: dmu_imu_rds_mess_addr_decode.v
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35module dmu_imu_rds_mess_addr_decode
36 (
37 clk,
38 rst_l,
39 daemon_csrbus_valid,
40 daemon_csrbus_addr,
41 csrbus_src_bus,
42 daemon_csrbus_wr,
43 daemon_csrbus_wr_out,
44 daemon_csrbus_wr_data,
45 daemon_csrbus_wr_data_out,
46 daemon_csrbus_mapped,
47 csrbus_acc_vio,
48 daemon_transaction_in_progress,
49 instance_id,
50 daemon_csrbus_done,
51 err_cor_mapping_select_pulse,
52 err_nonfatal_mapping_select_pulse,
53 err_fatal_mapping_select_pulse,
54 pm_pme_mapping_select_pulse,
55 pme_to_ack_mapping_select_pulse
56 );
57
58//====================================================================
59// Polarity declarations
60//====================================================================
61input clk; // Clock signal
62input rst_l; // Reset
63input daemon_csrbus_valid; // Daemon_Valid
64input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
65input [1:0] csrbus_src_bus; // Source bus
66input daemon_csrbus_wr; // Read/Write signal
67output daemon_csrbus_wr_out; // Read/Write signal
68input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
69output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
70output daemon_csrbus_mapped; // mapped
71output csrbus_acc_vio; // acc_vio
72input daemon_transaction_in_progress; // daemon_transaction_in_progress
73input instance_id; // Instance ID
74output daemon_csrbus_done; // Operation is done
75output err_cor_mapping_select_pulse; // select signal
76output err_nonfatal_mapping_select_pulse; // select signal
77output err_fatal_mapping_select_pulse; // select signal
78output pm_pme_mapping_select_pulse; // select signal
79output pme_to_ack_mapping_select_pulse; // select signal
80
81//====================================================================
82// Type declarations
83//====================================================================
84wire clk; // Clock signal
85wire rst_l; // Reset
86wire daemon_csrbus_valid; // Daemon_Valid
87wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
88wire [1:0] csrbus_src_bus; // Source bus
89wire daemon_csrbus_wr; // Read/Write signal
90reg daemon_csrbus_wr_out; // Read/Write signal
91wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
92reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
93wire daemon_csrbus_mapped; // mapped
94wire csrbus_acc_vio; // acc_vio
95wire daemon_transaction_in_progress; // daemon_transaction_in_progress
96wire instance_id; // Instance ID
97wire daemon_csrbus_done; // Operation is done
98reg err_cor_mapping_select_pulse; // select signal
99reg err_nonfatal_mapping_select_pulse; // select signal
100reg err_fatal_mapping_select_pulse; // select signal
101reg pm_pme_mapping_select_pulse; // select signal
102reg pme_to_ack_mapping_select_pulse; // select signal
103
104
105//====================================================================
106// Clocked valid
107//====================================================================
108reg clocked_valid;
109reg clocked_valid_pulse;
110always @(posedge clk)
111 begin
112 if(~rst_l)
113 begin
114 clocked_valid <= 1'b0;
115 clocked_valid_pulse <= 1'b0;
116 end
117 else
118 begin
119 clocked_valid <= daemon_csrbus_valid;
120 clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid;
121 end
122 end
123
124//====================================================================
125// Address Decode
126//====================================================================
127reg err_cor_mapping_addr_decoded;
128reg err_nonfatal_mapping_addr_decoded;
129reg err_fatal_mapping_addr_decoded;
130reg pm_pme_mapping_addr_decoded;
131reg pme_to_ack_mapping_addr_decoded;
132
133always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id)
134 begin
135 if (~daemon_csrbus_valid)
136 begin
137 err_cor_mapping_addr_decoded = 1'b0;
138 err_nonfatal_mapping_addr_decoded = 1'b0;
139 err_fatal_mapping_addr_decoded = 1'b0;
140 pm_pme_mapping_addr_decoded = 1'b0;
141 pme_to_ack_mapping_addr_decoded = 1'b0;
142 end
143 else
144 case (instance_id)
145
146 `FIRE_DLC_IMU_RDS_MESS_INSTANCE_ID_VALUE_A:
147 begin
148 err_cor_mapping_addr_decoded =
149 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_COR_MAPPING_HW_ADDR;
150 err_nonfatal_mapping_addr_decoded =
151 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_NONFATAL_MAPPING_HW_ADDR;
152 err_fatal_mapping_addr_decoded =
153 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_A_ERR_FATAL_MAPPING_HW_ADDR;
154 pm_pme_mapping_addr_decoded =
155 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_A_PM_PME_MAPPING_HW_ADDR;
156 pme_to_ack_mapping_addr_decoded =
157 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_A_PME_TO_ACK_MAPPING_HW_ADDR;
158 end
159
160 `FIRE_DLC_IMU_RDS_MESS_INSTANCE_ID_VALUE_B:
161 begin
162 err_cor_mapping_addr_decoded =
163 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_B_ERR_COR_MAPPING_HW_ADDR;
164 err_nonfatal_mapping_addr_decoded =
165 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_B_ERR_NONFATAL_MAPPING_HW_ADDR;
166 err_fatal_mapping_addr_decoded =
167 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_B_ERR_FATAL_MAPPING_HW_ADDR;
168 pm_pme_mapping_addr_decoded =
169 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_B_PM_PME_MAPPING_HW_ADDR;
170 pme_to_ack_mapping_addr_decoded =
171 daemon_csrbus_addr[26:0] == `FIRE_DLC_IMU_RDS_MESS_CSR_B_PME_TO_ACK_MAPPING_HW_ADDR;
172 end
173
174 default:
175 begin
176 err_cor_mapping_addr_decoded = 1'b0;
177 err_nonfatal_mapping_addr_decoded = 1'b0;
178 err_fatal_mapping_addr_decoded = 1'b0;
179 pm_pme_mapping_addr_decoded = 1'b0;
180 pme_to_ack_mapping_addr_decoded = 1'b0;
181// vlint flag_system_call off
182 // synopsys translate_off
183 if(daemon_csrbus_valid)
184 begin // axis tbcall_region
185`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_mess_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_imu_rds_mess_csr is bad"); `endif
186 end // end of tbcall_region
187 // synopsys translate_on
188// vlint flag_system_call on
189 end
190 endcase
191 end
192
193//====================================================================
194// Register violations
195//====================================================================
196//----- reg_acc_vio: err_cor_mapping
197reg err_cor_mapping_acc_vio;
198always @(csrbus_src_bus or daemon_csrbus_wr or
199 err_cor_mapping_addr_decoded or
200 daemon_transaction_in_progress)
201 begin
202 if (daemon_transaction_in_progress | ~err_cor_mapping_addr_decoded)
203 err_cor_mapping_acc_vio = 1'b0;
204 else
205 case ({csrbus_src_bus, daemon_csrbus_wr})
206 // reads
207 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
208 err_cor_mapping_acc_vio = 1'b0;
209 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
210 err_cor_mapping_acc_vio = 1'b0;
211 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
212 err_cor_mapping_acc_vio = 1'b0;
213 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
214 err_cor_mapping_acc_vio = 1'b0;
215 // writes
216 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
217 err_cor_mapping_acc_vio = 1'b0;
218 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
219 err_cor_mapping_acc_vio = 1'b0;
220 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
221 err_cor_mapping_acc_vio = 1'b0;
222 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
223 err_cor_mapping_acc_vio = 1'b0;
224
225 default:
226 begin
227 err_cor_mapping_acc_vio = 1'b0;
228 begin // axis tbcall_region
229 // vlint flag_system_call off
230 // synopsys translate_off
231`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_mess_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_mess_csr_a_err_cor_mapping"); `endif
232 // synopsys translate_on
233 // vlint flag_system_call on
234 end // end of tbcall_region
235 end
236 endcase
237 end
238//----- reg_acc_vio: err_nonfatal_mapping
239reg err_nonfatal_mapping_acc_vio;
240always @(csrbus_src_bus or daemon_csrbus_wr or
241 err_nonfatal_mapping_addr_decoded or
242 daemon_transaction_in_progress)
243 begin
244 if (daemon_transaction_in_progress | ~err_nonfatal_mapping_addr_decoded)
245 err_nonfatal_mapping_acc_vio = 1'b0;
246 else
247 case ({csrbus_src_bus, daemon_csrbus_wr})
248 // reads
249 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
250 err_nonfatal_mapping_acc_vio = 1'b0;
251 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
252 err_nonfatal_mapping_acc_vio = 1'b0;
253 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
254 err_nonfatal_mapping_acc_vio = 1'b0;
255 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
256 err_nonfatal_mapping_acc_vio = 1'b0;
257 // writes
258 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
259 err_nonfatal_mapping_acc_vio = 1'b0;
260 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
261 err_nonfatal_mapping_acc_vio = 1'b0;
262 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
263 err_nonfatal_mapping_acc_vio = 1'b0;
264 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
265 err_nonfatal_mapping_acc_vio = 1'b0;
266
267 default:
268 begin
269 err_nonfatal_mapping_acc_vio = 1'b0;
270 begin // axis tbcall_region
271 // vlint flag_system_call off
272 // synopsys translate_off
273`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_mess_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_mess_csr_a_err_nonfatal_mapping"); `endif
274 // synopsys translate_on
275 // vlint flag_system_call on
276 end // end of tbcall_region
277 end
278 endcase
279 end
280//----- reg_acc_vio: err_fatal_mapping
281reg err_fatal_mapping_acc_vio;
282always @(csrbus_src_bus or daemon_csrbus_wr or
283 err_fatal_mapping_addr_decoded or
284 daemon_transaction_in_progress)
285 begin
286 if (daemon_transaction_in_progress | ~err_fatal_mapping_addr_decoded)
287 err_fatal_mapping_acc_vio = 1'b0;
288 else
289 case ({csrbus_src_bus, daemon_csrbus_wr})
290 // reads
291 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
292 err_fatal_mapping_acc_vio = 1'b0;
293 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
294 err_fatal_mapping_acc_vio = 1'b0;
295 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
296 err_fatal_mapping_acc_vio = 1'b0;
297 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
298 err_fatal_mapping_acc_vio = 1'b0;
299 // writes
300 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
301 err_fatal_mapping_acc_vio = 1'b0;
302 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
303 err_fatal_mapping_acc_vio = 1'b0;
304 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
305 err_fatal_mapping_acc_vio = 1'b0;
306 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
307 err_fatal_mapping_acc_vio = 1'b0;
308
309 default:
310 begin
311 err_fatal_mapping_acc_vio = 1'b0;
312 begin // axis tbcall_region
313 // vlint flag_system_call off
314 // synopsys translate_off
315`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_mess_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_mess_csr_a_err_fatal_mapping"); `endif
316 // synopsys translate_on
317 // vlint flag_system_call on
318 end // end of tbcall_region
319 end
320 endcase
321 end
322//----- reg_acc_vio: pm_pme_mapping
323reg pm_pme_mapping_acc_vio;
324always @(csrbus_src_bus or daemon_csrbus_wr or
325 pm_pme_mapping_addr_decoded or
326 daemon_transaction_in_progress)
327 begin
328 if (daemon_transaction_in_progress | ~pm_pme_mapping_addr_decoded)
329 pm_pme_mapping_acc_vio = 1'b0;
330 else
331 case ({csrbus_src_bus, daemon_csrbus_wr})
332 // reads
333 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
334 pm_pme_mapping_acc_vio = 1'b0;
335 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
336 pm_pme_mapping_acc_vio = 1'b0;
337 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
338 pm_pme_mapping_acc_vio = 1'b0;
339 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
340 pm_pme_mapping_acc_vio = 1'b0;
341 // writes
342 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
343 pm_pme_mapping_acc_vio = 1'b0;
344 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
345 pm_pme_mapping_acc_vio = 1'b0;
346 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
347 pm_pme_mapping_acc_vio = 1'b0;
348 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
349 pm_pme_mapping_acc_vio = 1'b0;
350
351 default:
352 begin
353 pm_pme_mapping_acc_vio = 1'b0;
354 begin // axis tbcall_region
355 // vlint flag_system_call off
356 // synopsys translate_off
357`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_mess_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_mess_csr_a_pm_pme_mapping"); `endif
358 // synopsys translate_on
359 // vlint flag_system_call on
360 end // end of tbcall_region
361 end
362 endcase
363 end
364//----- reg_acc_vio: pme_to_ack_mapping
365reg pme_to_ack_mapping_acc_vio;
366always @(csrbus_src_bus or daemon_csrbus_wr or
367 pme_to_ack_mapping_addr_decoded or
368 daemon_transaction_in_progress)
369 begin
370 if (daemon_transaction_in_progress | ~pme_to_ack_mapping_addr_decoded)
371 pme_to_ack_mapping_acc_vio = 1'b0;
372 else
373 case ({csrbus_src_bus, daemon_csrbus_wr})
374 // reads
375 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
376 pme_to_ack_mapping_acc_vio = 1'b0;
377 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
378 pme_to_ack_mapping_acc_vio = 1'b0;
379 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
380 pme_to_ack_mapping_acc_vio = 1'b0;
381 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
382 pme_to_ack_mapping_acc_vio = 1'b0;
383 // writes
384 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
385 pme_to_ack_mapping_acc_vio = 1'b0;
386 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
387 pme_to_ack_mapping_acc_vio = 1'b0;
388 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
389 pme_to_ack_mapping_acc_vio = 1'b0;
390 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
391 pme_to_ack_mapping_acc_vio = 1'b0;
392
393 default:
394 begin
395 pme_to_ack_mapping_acc_vio = 1'b0;
396 begin // axis tbcall_region
397 // vlint flag_system_call off
398 // synopsys translate_off
399`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_imu_rds_mess_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_imu_rds_mess_csr_a_pme_to_ack_mapping"); `endif
400 // synopsys translate_on
401 // vlint flag_system_call on
402 end // end of tbcall_region
403 end
404 endcase
405 end
406
407//====================================================================
408// Status: daemon_csrbus_mapped / csrbus_acc_vio
409//====================================================================
410//----- OUTPUT: daemon_csrbus_mapped
411assign daemon_csrbus_mapped = clocked_valid_pulse &
412 (
413 err_cor_mapping_addr_decoded |
414 err_nonfatal_mapping_addr_decoded |
415 err_fatal_mapping_addr_decoded |
416 pm_pme_mapping_addr_decoded |
417 pme_to_ack_mapping_addr_decoded
418 );
419
420
421// daemon_csrbus_mapped gets asserted after fixed number of cycles
422// after daemon_csrbus_valid become high
423/* 0in assert_together -name mapped_after_valid
424 -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1))
425 -follower $0in_rising_edge(daemon_csrbus_mapped)
426 -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid")
427 -module dmu_imu_rds_mess_addr_decode
428 -clock clk
429 -active $0in_rising_edge(daemon_csrbus_mapped)
430*/
431
432// daemon_csrbus_mapped is a pulse
433/* 0in assert_timer -name daemon_csrbus_mapped_pulse
434 -var daemon_csrbus_mapped -max 1
435 -message "daemon_csrbus_mapped pulse length is not 1"
436 -module dmu_imu_rds_mess_addr_decode
437 -clock clk
438*/
439//----- OUTPUT: csrbus_acc_vio
440assign csrbus_acc_vio = clocked_valid_pulse &
441 err_cor_mapping_acc_vio |
442 err_nonfatal_mapping_acc_vio |
443 err_fatal_mapping_acc_vio |
444 pm_pme_mapping_acc_vio |
445 pme_to_ack_mapping_acc_vio;
446
447//====================================================================
448// Select
449//====================================================================
450always @(posedge clk)
451 begin
452 if(~rst_l)
453 begin
454 err_cor_mapping_select_pulse <= 1'b0;
455 err_nonfatal_mapping_select_pulse <= 1'b0;
456 err_fatal_mapping_select_pulse <= 1'b0;
457 pm_pme_mapping_select_pulse <= 1'b0;
458 pme_to_ack_mapping_select_pulse <= 1'b0;
459 end
460 else
461 begin
462 err_cor_mapping_select_pulse <=
463 ~err_cor_mapping_acc_vio &
464 clocked_valid_pulse &
465 err_cor_mapping_addr_decoded;
466
467 err_nonfatal_mapping_select_pulse <=
468 ~err_nonfatal_mapping_acc_vio &
469 clocked_valid_pulse &
470 err_nonfatal_mapping_addr_decoded;
471
472 err_fatal_mapping_select_pulse <=
473 ~err_fatal_mapping_acc_vio &
474 clocked_valid_pulse &
475 err_fatal_mapping_addr_decoded;
476
477 pm_pme_mapping_select_pulse <=
478 ~pm_pme_mapping_acc_vio &
479 clocked_valid_pulse &
480 pm_pme_mapping_addr_decoded;
481
482 pme_to_ack_mapping_select_pulse <=
483 ~pme_to_ack_mapping_acc_vio &
484 clocked_valid_pulse &
485 pme_to_ack_mapping_addr_decoded;
486
487 end
488 end
489
490//====================================================================
491// daemon_csrbus_wr / daemon_csrbus_wr_data
492//====================================================================
493always @(posedge clk)
494 begin
495 if(~rst_l)
496 begin
497 daemon_csrbus_wr_out <= 1'b0;
498 daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0;
499 end
500 else
501 begin
502 daemon_csrbus_wr_out <= daemon_csrbus_wr;
503 daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data;
504 end
505 end
506
507//====================================================================
508// Cycle Counter: Used for ExtReadTiming / ExtWriteTiming
509//====================================================================
510
511//====================================================================
512// OUTPUT: daemon_csrbus_done (pipelining)
513//====================================================================
514//----- DONE for internal/extern registers
515reg stage_1_daemon_csrbus_done_internal_0;
516reg stage_2_daemon_csrbus_done_internal_0;
517
518always @(posedge clk)
519 begin
520 if(~rst_l)
521 begin
522 stage_1_daemon_csrbus_done_internal_0 <= 1'b0;
523 end
524 else
525 begin
526 stage_1_daemon_csrbus_done_internal_0 <=
527 err_cor_mapping_select_pulse |
528 err_nonfatal_mapping_select_pulse |
529 err_fatal_mapping_select_pulse |
530 pm_pme_mapping_select_pulse |
531 pme_to_ack_mapping_select_pulse;
532 end
533 if(~rst_l)
534 begin
535 stage_2_daemon_csrbus_done_internal_0 <= 1'b0;
536 end
537 else
538 begin
539 stage_2_daemon_csrbus_done_internal_0 <=
540 stage_1_daemon_csrbus_done_internal_0;
541 end
542 end
543
544//----- OUTPUT: daemon_csrbus_done
545assign daemon_csrbus_done = daemon_csrbus_valid &
546 (
547 stage_2_daemon_csrbus_done_internal_0
548 );
549
550// daemon_csrbus_done gets asserted only when csrbus_valid is high
551/* 0in assert -name daemon_csrbus_done_high
552 -var daemon_csrbus_valid -active daemon_csrbus_done
553 -message "csrbus_done got asserted while csrbus_valid is low"
554 -module dmu_imu_rds_mess_addr_decode
555 -clock clk
556*/
557
558// daemon_csrbus_done is a pulse
559/* 0in assert_timer -name daemon_csrbus_done_pulse
560 -var daemon_csrbus_done -max 1
561 -message "csrbus_done pulse length is not 1"
562 -module dmu_imu_rds_mess_addr_decode
563 -clock clk
564*/
565
566endmodule // dmu_imu_rds_mess_addr_decode