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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_addr_decode.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_mmu_csr_addr_decode.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_mmu_csr_addr_decode
36 (
37 clk,
38 rst_l,
39 daemon_csrbus_valid,
40 daemon_csrbus_addr,
41 csrbus_src_bus,
42 daemon_csrbus_wr,
43 daemon_csrbus_wr_out,
44 daemon_csrbus_wr_data,
45 daemon_csrbus_wr_data_out,
46 daemon_csrbus_mapped,
47 csrbus_acc_vio,
48 daemon_transaction_in_progress,
49 instance_id,
50 daemon_csrbus_done,
51 stage_mux_only_ext_done_0_out,
52 ctl_select_pulse,
53 tsb_select_pulse,
54 fsh_select_pulse,
55 inv_select,
56 log_select_pulse,
57 int_en_select_pulse,
58 en_err_select,
59 err_select_pulse,
60 err_rw1c_alias,
61 err_rw1s_alias,
62 flta_select_pulse,
63 flts_select_pulse,
64 prfc_select_pulse,
65 prf0_select_pulse,
66 prf1_select_pulse,
67 vtb_select,
68 vtb_hw_acc_jtag_rd,
69 vtb_hw_acc_jtag_wr,
70 vtb_hw_acc_pio_slow_rd,
71 vtb_hw_acc_pio_slow_wr,
72 vtb_hw_acc_pio_med_rd,
73 vtb_hw_acc_pio_med_wr,
74 vtb_hw_acc_pio_fast_rd,
75 vtb_hw_acc_pio_fast_wr,
76 ptb_select,
77 ptb_hw_acc_jtag_rd,
78 ptb_hw_acc_jtag_wr,
79 ptb_hw_acc_pio_slow_rd,
80 ptb_hw_acc_pio_slow_wr,
81 ptb_hw_acc_pio_med_rd,
82 ptb_hw_acc_pio_med_wr,
83 ptb_hw_acc_pio_fast_rd,
84 ptb_hw_acc_pio_fast_wr,
85 tdb_select,
86 tdb_hw_acc_jtag_rd,
87 tdb_hw_acc_jtag_wr,
88 tdb_hw_acc_pio_slow_rd,
89 tdb_hw_acc_pio_slow_wr,
90 tdb_hw_acc_pio_med_rd,
91 tdb_hw_acc_pio_med_wr,
92 tdb_hw_acc_pio_fast_rd,
93 tdb_hw_acc_pio_fast_wr,
94 dev2iotsb_select,
95 dev2iotsb_hw_acc_jtag_rd,
96 dev2iotsb_hw_acc_jtag_wr,
97 dev2iotsb_hw_acc_pio_slow_rd,
98 dev2iotsb_hw_acc_pio_slow_wr,
99 dev2iotsb_hw_acc_pio_med_rd,
100 dev2iotsb_hw_acc_pio_med_wr,
101 dev2iotsb_hw_acc_pio_fast_rd,
102 dev2iotsb_hw_acc_pio_fast_wr,
103 IotsbDesc_select,
104 IotsbDesc_hw_acc_jtag_rd,
105 IotsbDesc_hw_acc_jtag_wr,
106 IotsbDesc_hw_acc_pio_slow_rd,
107 IotsbDesc_hw_acc_pio_slow_wr,
108 IotsbDesc_hw_acc_pio_med_rd,
109 IotsbDesc_hw_acc_pio_med_wr,
110 IotsbDesc_hw_acc_pio_fast_rd,
111 IotsbDesc_hw_acc_pio_fast_wr
112 );
113
114//====================================================================
115// Polarity declarations
116//====================================================================
117input clk; // Clock signal
118input rst_l; // Reset
119input daemon_csrbus_valid; // Daemon_Valid
120input [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
121input [1:0] csrbus_src_bus; // Source bus
122input daemon_csrbus_wr; // Read/Write signal
123output daemon_csrbus_wr_out; // Read/Write signal
124input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
125output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
126output daemon_csrbus_mapped; // mapped
127output csrbus_acc_vio; // acc_vio
128input daemon_transaction_in_progress; // daemon_transaction_in_progress
129input instance_id; // Instance ID
130output daemon_csrbus_done; // Operation is done
131input stage_mux_only_ext_done_0_out; // Operation is done
132output ctl_select_pulse; // select signal
133output tsb_select_pulse; // select signal
134output fsh_select_pulse; // select signal
135output inv_select; // select signal
136output log_select_pulse; // select signal
137output int_en_select_pulse; // select signal
138output en_err_select; // select signal
139output err_select_pulse; // select signal
140output err_rw1c_alias; // alias signal
141output err_rw1s_alias; // alias signal
142output flta_select_pulse; // select signal
143output flts_select_pulse; // select signal
144output prfc_select_pulse; // select signal
145output prf0_select_pulse; // select signal
146output prf1_select_pulse; // select signal
147output vtb_select; // select signal
148input vtb_hw_acc_jtag_rd; // This signal enables reading of register vtb by
149 // jtag.
150input vtb_hw_acc_jtag_wr; // This signal enables writing of register vtb by
151 // jtag.
152input vtb_hw_acc_pio_slow_rd; // This signal enables reading of register vtb
153 // by pio_slow.
154input vtb_hw_acc_pio_slow_wr; // This signal enables writing of register vtb
155 // by pio_slow.
156input vtb_hw_acc_pio_med_rd; // This signal enables reading of register vtb by
157 // pio_med.
158input vtb_hw_acc_pio_med_wr; // This signal enables writing of register vtb by
159 // pio_med.
160input vtb_hw_acc_pio_fast_rd; // This signal enables reading of register vtb
161 // by pio_fast.
162input vtb_hw_acc_pio_fast_wr; // This signal enables writing of register vtb
163 // by pio_fast.
164output ptb_select; // select signal
165input ptb_hw_acc_jtag_rd; // This signal enables reading of register ptb by
166 // jtag.
167input ptb_hw_acc_jtag_wr; // This signal enables writing of register ptb by
168 // jtag.
169input ptb_hw_acc_pio_slow_rd; // This signal enables reading of register ptb
170 // by pio_slow.
171input ptb_hw_acc_pio_slow_wr; // This signal enables writing of register ptb
172 // by pio_slow.
173input ptb_hw_acc_pio_med_rd; // This signal enables reading of register ptb by
174 // pio_med.
175input ptb_hw_acc_pio_med_wr; // This signal enables writing of register ptb by
176 // pio_med.
177input ptb_hw_acc_pio_fast_rd; // This signal enables reading of register ptb
178 // by pio_fast.
179input ptb_hw_acc_pio_fast_wr; // This signal enables writing of register ptb
180 // by pio_fast.
181output tdb_select; // select signal
182input tdb_hw_acc_jtag_rd; // This signal enables reading of register tdb by
183 // jtag.
184input tdb_hw_acc_jtag_wr; // This signal enables writing of register tdb by
185 // jtag.
186input tdb_hw_acc_pio_slow_rd; // This signal enables reading of register tdb
187 // by pio_slow.
188input tdb_hw_acc_pio_slow_wr; // This signal enables writing of register tdb
189 // by pio_slow.
190input tdb_hw_acc_pio_med_rd; // This signal enables reading of register tdb by
191 // pio_med.
192input tdb_hw_acc_pio_med_wr; // This signal enables writing of register tdb by
193 // pio_med.
194input tdb_hw_acc_pio_fast_rd; // This signal enables reading of register tdb
195 // by pio_fast.
196input tdb_hw_acc_pio_fast_wr; // This signal enables writing of register tdb
197 // by pio_fast.
198output dev2iotsb_select; // select signal
199input dev2iotsb_hw_acc_jtag_rd; // This signal enables reading of register
200 // dev2iotsb by jtag.
201input dev2iotsb_hw_acc_jtag_wr; // This signal enables writing of register
202 // dev2iotsb by jtag.
203input dev2iotsb_hw_acc_pio_slow_rd; // This signal enables reading of register
204 // dev2iotsb by pio_slow.
205input dev2iotsb_hw_acc_pio_slow_wr; // This signal enables writing of register
206 // dev2iotsb by pio_slow.
207input dev2iotsb_hw_acc_pio_med_rd; // This signal enables reading of register
208 // dev2iotsb by pio_med.
209input dev2iotsb_hw_acc_pio_med_wr; // This signal enables writing of register
210 // dev2iotsb by pio_med.
211input dev2iotsb_hw_acc_pio_fast_rd; // This signal enables reading of register
212 // dev2iotsb by pio_fast.
213input dev2iotsb_hw_acc_pio_fast_wr; // This signal enables writing of register
214 // dev2iotsb by pio_fast.
215output IotsbDesc_select; // select signal
216input IotsbDesc_hw_acc_jtag_rd; // This signal enables reading of register
217 // IotsbDesc by jtag.
218input IotsbDesc_hw_acc_jtag_wr; // This signal enables writing of register
219 // IotsbDesc by jtag.
220input IotsbDesc_hw_acc_pio_slow_rd; // This signal enables reading of register
221 // IotsbDesc by pio_slow.
222input IotsbDesc_hw_acc_pio_slow_wr; // This signal enables writing of register
223 // IotsbDesc by pio_slow.
224input IotsbDesc_hw_acc_pio_med_rd; // This signal enables reading of register
225 // IotsbDesc by pio_med.
226input IotsbDesc_hw_acc_pio_med_wr; // This signal enables writing of register
227 // IotsbDesc by pio_med.
228input IotsbDesc_hw_acc_pio_fast_rd; // This signal enables reading of register
229 // IotsbDesc by pio_fast.
230input IotsbDesc_hw_acc_pio_fast_wr; // This signal enables writing of register
231 // IotsbDesc by pio_fast.
232
233//====================================================================
234// Type declarations
235//====================================================================
236wire clk; // Clock signal
237wire rst_l; // Reset
238wire daemon_csrbus_valid; // Daemon_Valid
239wire [`FIRE_CSRBUS_ADDR_WIDTH - 1:0] daemon_csrbus_addr; // Daemon_Addr
240wire [1:0] csrbus_src_bus; // Source bus
241wire daemon_csrbus_wr; // Read/Write signal
242reg daemon_csrbus_wr_out; // Read/Write signal
243wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data; // Write data
244reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // Write data
245wire daemon_csrbus_mapped; // mapped
246wire csrbus_acc_vio; // acc_vio
247wire daemon_transaction_in_progress; // daemon_transaction_in_progress
248wire instance_id; // Instance ID
249wire daemon_csrbus_done; // Operation is done
250wire stage_mux_only_ext_done_0_out; // Operation is done
251reg ctl_select_pulse; // select signal
252reg tsb_select_pulse; // select signal
253reg fsh_select_pulse; // select signal
254reg inv_select; // select signal
255reg log_select_pulse; // select signal
256reg int_en_select_pulse; // select signal
257reg en_err_select; // select signal
258reg err_select_pulse; // select signal
259wire err_rw1c_alias; // alias signal
260wire err_rw1s_alias; // alias signal
261reg flta_select_pulse; // select signal
262reg flts_select_pulse; // select signal
263reg prfc_select_pulse; // select signal
264reg prf0_select_pulse; // select signal
265reg prf1_select_pulse; // select signal
266reg vtb_select; // select signal
267wire vtb_hw_acc_jtag_rd; // This signal enables reading of register vtb by
268 // jtag.
269wire vtb_hw_acc_jtag_wr; // This signal enables writing of register vtb by
270 // jtag.
271wire vtb_hw_acc_pio_slow_rd; // This signal enables reading of register vtb by
272 // pio_slow.
273wire vtb_hw_acc_pio_slow_wr; // This signal enables writing of register vtb by
274 // pio_slow.
275wire vtb_hw_acc_pio_med_rd; // This signal enables reading of register vtb by
276 // pio_med.
277wire vtb_hw_acc_pio_med_wr; // This signal enables writing of register vtb by
278 // pio_med.
279wire vtb_hw_acc_pio_fast_rd; // This signal enables reading of register vtb by
280 // pio_fast.
281wire vtb_hw_acc_pio_fast_wr; // This signal enables writing of register vtb by
282 // pio_fast.
283reg ptb_select; // select signal
284wire ptb_hw_acc_jtag_rd; // This signal enables reading of register ptb by
285 // jtag.
286wire ptb_hw_acc_jtag_wr; // This signal enables writing of register ptb by
287 // jtag.
288wire ptb_hw_acc_pio_slow_rd; // This signal enables reading of register ptb by
289 // pio_slow.
290wire ptb_hw_acc_pio_slow_wr; // This signal enables writing of register ptb by
291 // pio_slow.
292wire ptb_hw_acc_pio_med_rd; // This signal enables reading of register ptb by
293 // pio_med.
294wire ptb_hw_acc_pio_med_wr; // This signal enables writing of register ptb by
295 // pio_med.
296wire ptb_hw_acc_pio_fast_rd; // This signal enables reading of register ptb by
297 // pio_fast.
298wire ptb_hw_acc_pio_fast_wr; // This signal enables writing of register ptb by
299 // pio_fast.
300reg tdb_select; // select signal
301wire tdb_hw_acc_jtag_rd; // This signal enables reading of register tdb by
302 // jtag.
303wire tdb_hw_acc_jtag_wr; // This signal enables writing of register tdb by
304 // jtag.
305wire tdb_hw_acc_pio_slow_rd; // This signal enables reading of register tdb by
306 // pio_slow.
307wire tdb_hw_acc_pio_slow_wr; // This signal enables writing of register tdb by
308 // pio_slow.
309wire tdb_hw_acc_pio_med_rd; // This signal enables reading of register tdb by
310 // pio_med.
311wire tdb_hw_acc_pio_med_wr; // This signal enables writing of register tdb by
312 // pio_med.
313wire tdb_hw_acc_pio_fast_rd; // This signal enables reading of register tdb by
314 // pio_fast.
315wire tdb_hw_acc_pio_fast_wr; // This signal enables writing of register tdb by
316 // pio_fast.
317reg dev2iotsb_select; // select signal
318wire dev2iotsb_hw_acc_jtag_rd; // This signal enables reading of register
319 // dev2iotsb by jtag.
320wire dev2iotsb_hw_acc_jtag_wr; // This signal enables writing of register
321 // dev2iotsb by jtag.
322wire dev2iotsb_hw_acc_pio_slow_rd; // This signal enables reading of register
323 // dev2iotsb by pio_slow.
324wire dev2iotsb_hw_acc_pio_slow_wr; // This signal enables writing of register
325 // dev2iotsb by pio_slow.
326wire dev2iotsb_hw_acc_pio_med_rd; // This signal enables reading of register
327 // dev2iotsb by pio_med.
328wire dev2iotsb_hw_acc_pio_med_wr; // This signal enables writing of register
329 // dev2iotsb by pio_med.
330wire dev2iotsb_hw_acc_pio_fast_rd; // This signal enables reading of register
331 // dev2iotsb by pio_fast.
332wire dev2iotsb_hw_acc_pio_fast_wr; // This signal enables writing of register
333 // dev2iotsb by pio_fast.
334reg IotsbDesc_select; // select signal
335wire IotsbDesc_hw_acc_jtag_rd; // This signal enables reading of register
336 // IotsbDesc by jtag.
337wire IotsbDesc_hw_acc_jtag_wr; // This signal enables writing of register
338 // IotsbDesc by jtag.
339wire IotsbDesc_hw_acc_pio_slow_rd; // This signal enables reading of register
340 // IotsbDesc by pio_slow.
341wire IotsbDesc_hw_acc_pio_slow_wr; // This signal enables writing of register
342 // IotsbDesc by pio_slow.
343wire IotsbDesc_hw_acc_pio_med_rd; // This signal enables reading of register
344 // IotsbDesc by pio_med.
345wire IotsbDesc_hw_acc_pio_med_wr; // This signal enables writing of register
346 // IotsbDesc by pio_med.
347wire IotsbDesc_hw_acc_pio_fast_rd; // This signal enables reading of register
348 // IotsbDesc by pio_fast.
349wire IotsbDesc_hw_acc_pio_fast_wr; // This signal enables writing of register
350 // IotsbDesc by pio_fast.
351
352
353//====================================================================
354// Clocked valid
355//====================================================================
356reg clocked_valid;
357reg clocked_valid_pulse;
358always @(posedge clk)
359 begin
360 if(~rst_l)
361 begin
362 clocked_valid <= 1'b0;
363 clocked_valid_pulse <= 1'b0;
364 end
365 else
366 begin
367 clocked_valid <= daemon_csrbus_valid;
368 clocked_valid_pulse <= daemon_csrbus_valid & ~clocked_valid;
369 end
370 end
371
372//====================================================================
373// Address Decode
374//====================================================================
375reg ctl_addr_decoded;
376reg tsb_addr_decoded;
377reg fsh_addr_decoded;
378reg inv_addr_decoded;
379reg log_addr_decoded;
380reg int_en_addr_decoded;
381reg en_err_addr_decoded;
382reg err_rw1c_alias_addr_decoded;
383reg err_rw1s_alias_addr_decoded;
384reg flta_addr_decoded;
385reg flts_addr_decoded;
386reg prfc_addr_decoded;
387reg prf0_addr_decoded;
388reg prf1_addr_decoded;
389reg vtb_addr_decoded;
390reg ptb_addr_decoded;
391reg tdb_addr_decoded;
392reg dev2iotsb_addr_decoded;
393reg IotsbDesc_addr_decoded;
394
395always @(daemon_csrbus_addr or daemon_csrbus_valid or instance_id)
396 begin
397 if (~daemon_csrbus_valid)
398 begin
399 ctl_addr_decoded = 1'b0;
400 tsb_addr_decoded = 1'b0;
401 fsh_addr_decoded = 1'b0;
402 inv_addr_decoded = 1'b0;
403 log_addr_decoded = 1'b0;
404 int_en_addr_decoded = 1'b0;
405 en_err_addr_decoded = 1'b0;
406 err_rw1c_alias_addr_decoded = 1'b0;
407 err_rw1s_alias_addr_decoded = 1'b0;
408 flta_addr_decoded = 1'b0;
409 flts_addr_decoded = 1'b0;
410 prfc_addr_decoded = 1'b0;
411 prf0_addr_decoded = 1'b0;
412 prf1_addr_decoded = 1'b0;
413 vtb_addr_decoded = 1'b0;
414 ptb_addr_decoded = 1'b0;
415 tdb_addr_decoded = 1'b0;
416 dev2iotsb_addr_decoded = 1'b0;
417 IotsbDesc_addr_decoded = 1'b0;
418 end
419 else
420 case (instance_id)
421
422 `FIRE_DLC_MMU_CSR_INSTANCE_ID_VALUE_A:
423 begin
424 ctl_addr_decoded =
425 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_CTL_HW_ADDR;
426 tsb_addr_decoded =
427 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_TSB_HW_ADDR;
428 fsh_addr_decoded =
429 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_FSH_HW_ADDR;
430 inv_addr_decoded =
431 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_INV_HW_ADDR;
432 log_addr_decoded =
433 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_LOG_HW_ADDR;
434 int_en_addr_decoded =
435 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_INT_EN_HW_ADDR;
436 en_err_addr_decoded =
437 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_EN_ERR_HW_ADDR;
438 err_rw1c_alias_addr_decoded =
439 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_HW_ADDR;
440 err_rw1s_alias_addr_decoded =
441 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_HW_ADDR;
442 flta_addr_decoded =
443 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_FLTA_HW_ADDR;
444 flts_addr_decoded =
445 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_FLTS_HW_ADDR;
446 prfc_addr_decoded =
447 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_PRFC_HW_ADDR;
448 prf0_addr_decoded =
449 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_PRF0_HW_ADDR;
450 prf1_addr_decoded =
451 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_A_PRF1_HW_ADDR;
452 vtb_addr_decoded =
453 {6'b0,daemon_csrbus_addr[26:6]} ==
454 `FIRE_DLC_MMU_CSR_A_VTB_HW_ADDR >>
455 `FIRE_DLC_MMU_CSR_VTB_LOW_ADDR_WIDTH;
456 ptb_addr_decoded =
457 {6'b0,daemon_csrbus_addr[26:6]} ==
458 `FIRE_DLC_MMU_CSR_A_PTB_HW_ADDR >>
459 `FIRE_DLC_MMU_CSR_PTB_LOW_ADDR_WIDTH;
460 tdb_addr_decoded =
461 {9'b0,daemon_csrbus_addr[26:9]} ==
462 `FIRE_DLC_MMU_CSR_A_TDB_HW_ADDR >>
463 `FIRE_DLC_MMU_CSR_TDB_LOW_ADDR_WIDTH;
464 dev2iotsb_addr_decoded =
465 {4'b0,daemon_csrbus_addr[26:4]} ==
466 `FIRE_DLC_MMU_CSR_A_DEV2IOTSB_HW_ADDR >>
467 `FIRE_DLC_MMU_CSR_DEV2IOTSB_LOW_ADDR_WIDTH;
468 IotsbDesc_addr_decoded =
469 {5'b0,daemon_csrbus_addr[26:5]} ==
470 `FIRE_DLC_MMU_CSR_A_IOTSBDESC_HW_ADDR >>
471 `FIRE_DLC_MMU_CSR_IOTSBDESC_LOW_ADDR_WIDTH;
472 end
473
474 `FIRE_DLC_MMU_CSR_INSTANCE_ID_VALUE_B:
475 begin
476 ctl_addr_decoded =
477 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_CTL_HW_ADDR;
478 tsb_addr_decoded =
479 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_TSB_HW_ADDR;
480 fsh_addr_decoded =
481 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_FSH_HW_ADDR;
482 inv_addr_decoded =
483 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_INV_HW_ADDR;
484 log_addr_decoded =
485 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_LOG_HW_ADDR;
486 int_en_addr_decoded =
487 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_INT_EN_HW_ADDR;
488 en_err_addr_decoded =
489 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_EN_ERR_HW_ADDR;
490 err_rw1c_alias_addr_decoded =
491 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_ERR_RW1C_ALIAS_HW_ADDR;
492 err_rw1s_alias_addr_decoded =
493 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_ERR_RW1S_ALIAS_HW_ADDR;
494 flta_addr_decoded =
495 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_FLTA_HW_ADDR;
496 flts_addr_decoded =
497 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_FLTS_HW_ADDR;
498 prfc_addr_decoded =
499 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_PRFC_HW_ADDR;
500 prf0_addr_decoded =
501 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_PRF0_HW_ADDR;
502 prf1_addr_decoded =
503 daemon_csrbus_addr[26:0] == `FIRE_DLC_MMU_CSR_B_PRF1_HW_ADDR;
504 vtb_addr_decoded =
505 {6'b0,daemon_csrbus_addr[26:6]} ==
506 `FIRE_DLC_MMU_CSR_B_VTB_HW_ADDR >>
507 `FIRE_DLC_MMU_CSR_VTB_LOW_ADDR_WIDTH;
508 ptb_addr_decoded =
509 {6'b0,daemon_csrbus_addr[26:6]} ==
510 `FIRE_DLC_MMU_CSR_B_PTB_HW_ADDR >>
511 `FIRE_DLC_MMU_CSR_PTB_LOW_ADDR_WIDTH;
512 tdb_addr_decoded =
513 {9'b0,daemon_csrbus_addr[26:9]} ==
514 `FIRE_DLC_MMU_CSR_B_TDB_HW_ADDR >>
515 `FIRE_DLC_MMU_CSR_TDB_LOW_ADDR_WIDTH;
516 dev2iotsb_addr_decoded =
517 {4'b0,daemon_csrbus_addr[26:4]} ==
518 `FIRE_DLC_MMU_CSR_B_DEV2IOTSB_HW_ADDR >>
519 `FIRE_DLC_MMU_CSR_DEV2IOTSB_LOW_ADDR_WIDTH;
520 IotsbDesc_addr_decoded =
521 {5'b0,daemon_csrbus_addr[26:5]} ==
522 `FIRE_DLC_MMU_CSR_B_IOTSBDESC_HW_ADDR >>
523 `FIRE_DLC_MMU_CSR_IOTSBDESC_LOW_ADDR_WIDTH;
524 end
525
526 default:
527 begin
528 ctl_addr_decoded = 1'b0;
529 tsb_addr_decoded = 1'b0;
530 fsh_addr_decoded = 1'b0;
531 inv_addr_decoded = 1'b0;
532 log_addr_decoded = 1'b0;
533 int_en_addr_decoded = 1'b0;
534 en_err_addr_decoded = 1'b0;
535 err_rw1s_alias_addr_decoded = 1'b0;
536 err_rw1c_alias_addr_decoded = 1'b0;
537 flta_addr_decoded = 1'b0;
538 flts_addr_decoded = 1'b0;
539 prfc_addr_decoded = 1'b0;
540 prf0_addr_decoded = 1'b0;
541 prf1_addr_decoded = 1'b0;
542 vtb_addr_decoded = 1'b0;
543 ptb_addr_decoded = 1'b0;
544 tdb_addr_decoded = 1'b0;
545 dev2iotsb_addr_decoded = 1'b0;
546 IotsbDesc_addr_decoded = 1'b0;
547// vlint flag_system_call off
548 // synopsys translate_off
549 if(daemon_csrbus_valid)
550 begin // axis tbcall_region
551`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"ERROR: Instance ID for module dmu_mmu_csr_csr is bad"); `endif
552 end // end of tbcall_region
553 // synopsys translate_on
554// vlint flag_system_call on
555 end
556 endcase
557 end
558
559//====================================================================
560// Register violations
561//====================================================================
562//----- reg_acc_vio: ctl
563reg ctl_acc_vio;
564always @(csrbus_src_bus or daemon_csrbus_wr or
565 ctl_addr_decoded or
566 daemon_transaction_in_progress)
567 begin
568 if (daemon_transaction_in_progress | ~ctl_addr_decoded)
569 ctl_acc_vio = 1'b0;
570 else
571 case ({csrbus_src_bus, daemon_csrbus_wr})
572 // reads
573 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
574 ctl_acc_vio = 1'b0;
575 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
576 ctl_acc_vio = 1'b0;
577 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
578 ctl_acc_vio = 1'b0;
579 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
580 ctl_acc_vio = 1'b0;
581 // writes
582 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
583 ctl_acc_vio = 1'b0;
584 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
585 ctl_acc_vio = 1'b0;
586 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
587 ctl_acc_vio = 1'b0;
588 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
589 ctl_acc_vio = 1'b0;
590
591 default:
592 begin
593 ctl_acc_vio = 1'b0;
594 begin // axis tbcall_region
595 // vlint flag_system_call off
596 // synopsys translate_off
597`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_ctl"); `endif
598 // synopsys translate_on
599 // vlint flag_system_call on
600 end // end of tbcall_region
601 end
602 endcase
603 end
604//----- reg_acc_vio: tsb
605reg tsb_acc_vio;
606always @(csrbus_src_bus or daemon_csrbus_wr or
607 tsb_addr_decoded or
608 daemon_transaction_in_progress)
609 begin
610 if (daemon_transaction_in_progress | ~tsb_addr_decoded)
611 tsb_acc_vio = 1'b0;
612 else
613 case ({csrbus_src_bus, daemon_csrbus_wr})
614 // reads
615 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
616 tsb_acc_vio = 1'b0;
617 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
618 tsb_acc_vio = 1'b0;
619 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
620 tsb_acc_vio = 1'b0;
621 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
622 tsb_acc_vio = 1'b0;
623 // writes
624 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
625 tsb_acc_vio = 1'b0;
626 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
627 tsb_acc_vio = 1'b0;
628 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
629 tsb_acc_vio = 1'b0;
630 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
631 tsb_acc_vio = 1'b0;
632
633 default:
634 begin
635 tsb_acc_vio = 1'b0;
636 begin // axis tbcall_region
637 // vlint flag_system_call off
638 // synopsys translate_off
639`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_tsb"); `endif
640 // synopsys translate_on
641 // vlint flag_system_call on
642 end // end of tbcall_region
643 end
644 endcase
645 end
646//----- reg_acc_vio: fsh
647reg fsh_acc_vio;
648always @(csrbus_src_bus or daemon_csrbus_wr or
649 fsh_addr_decoded or
650 daemon_transaction_in_progress)
651 begin
652 if (daemon_transaction_in_progress | ~fsh_addr_decoded)
653 fsh_acc_vio = 1'b0;
654 else
655 case ({csrbus_src_bus, daemon_csrbus_wr})
656 // reads
657 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
658 fsh_acc_vio = 1'b0;
659 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
660 fsh_acc_vio = 1'b0;
661 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
662 fsh_acc_vio = 1'b0;
663 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
664 fsh_acc_vio = 1'b0;
665 // writes
666 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
667 fsh_acc_vio = 1'b0;
668 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
669 fsh_acc_vio = 1'b0;
670 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
671 fsh_acc_vio = 1'b0;
672 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
673 fsh_acc_vio = 1'b0;
674
675 default:
676 begin
677 fsh_acc_vio = 1'b0;
678 begin // axis tbcall_region
679 // vlint flag_system_call off
680 // synopsys translate_off
681`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_fsh"); `endif
682 // synopsys translate_on
683 // vlint flag_system_call on
684 end // end of tbcall_region
685 end
686 endcase
687 end
688//----- reg_acc_vio: inv
689reg inv_acc_vio;
690always @(csrbus_src_bus or daemon_csrbus_wr or
691 inv_addr_decoded or
692 daemon_transaction_in_progress)
693 begin
694 if (daemon_transaction_in_progress | ~inv_addr_decoded)
695 inv_acc_vio = 1'b0;
696 else
697 case ({csrbus_src_bus, daemon_csrbus_wr})
698 // reads
699 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
700 inv_acc_vio = 1'b0;
701 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
702 inv_acc_vio = 1'b0;
703 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
704 inv_acc_vio = 1'b0;
705 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
706 inv_acc_vio = 1'b0;
707 // writes
708 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
709 inv_acc_vio = 1'b0;
710 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
711 inv_acc_vio = 1'b0;
712 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
713 inv_acc_vio = 1'b0;
714 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
715 inv_acc_vio = 1'b0;
716
717 default:
718 begin
719 inv_acc_vio = 1'b0;
720 begin // axis tbcall_region
721 // vlint flag_system_call off
722 // synopsys translate_off
723`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_inv"); `endif
724 // synopsys translate_on
725 // vlint flag_system_call on
726 end // end of tbcall_region
727 end
728 endcase
729 end
730//----- reg_acc_vio: log
731reg log_acc_vio;
732always @(csrbus_src_bus or daemon_csrbus_wr or
733 log_addr_decoded or
734 daemon_transaction_in_progress)
735 begin
736 if (daemon_transaction_in_progress | ~log_addr_decoded)
737 log_acc_vio = 1'b0;
738 else
739 case ({csrbus_src_bus, daemon_csrbus_wr})
740 // reads
741 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
742 log_acc_vio = 1'b0;
743 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
744 log_acc_vio = 1'b0;
745 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
746 log_acc_vio = 1'b0;
747 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
748 log_acc_vio = 1'b0;
749 // writes
750 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
751 log_acc_vio = 1'b0;
752 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
753 log_acc_vio = 1'b0;
754 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
755 log_acc_vio = 1'b0;
756 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
757 log_acc_vio = 1'b0;
758
759 default:
760 begin
761 log_acc_vio = 1'b0;
762 begin // axis tbcall_region
763 // vlint flag_system_call off
764 // synopsys translate_off
765`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_log"); `endif
766 // synopsys translate_on
767 // vlint flag_system_call on
768 end // end of tbcall_region
769 end
770 endcase
771 end
772//----- reg_acc_vio: int_en
773reg int_en_acc_vio;
774always @(csrbus_src_bus or daemon_csrbus_wr or
775 int_en_addr_decoded or
776 daemon_transaction_in_progress)
777 begin
778 if (daemon_transaction_in_progress | ~int_en_addr_decoded)
779 int_en_acc_vio = 1'b0;
780 else
781 case ({csrbus_src_bus, daemon_csrbus_wr})
782 // reads
783 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
784 int_en_acc_vio = 1'b0;
785 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
786 int_en_acc_vio = 1'b0;
787 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
788 int_en_acc_vio = 1'b0;
789 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
790 int_en_acc_vio = 1'b0;
791 // writes
792 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
793 int_en_acc_vio = 1'b0;
794 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
795 int_en_acc_vio = 1'b0;
796 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
797 int_en_acc_vio = 1'b0;
798 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
799 int_en_acc_vio = 1'b0;
800
801 default:
802 begin
803 int_en_acc_vio = 1'b0;
804 begin // axis tbcall_region
805 // vlint flag_system_call off
806 // synopsys translate_off
807`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_int_en"); `endif
808 // synopsys translate_on
809 // vlint flag_system_call on
810 end // end of tbcall_region
811 end
812 endcase
813 end
814//----- reg_acc_vio: en_err
815reg en_err_acc_vio;
816always @(csrbus_src_bus or daemon_csrbus_wr or
817 en_err_addr_decoded or
818 daemon_transaction_in_progress)
819 begin
820 if (daemon_transaction_in_progress | ~en_err_addr_decoded)
821 en_err_acc_vio = 1'b0;
822 else
823 case ({csrbus_src_bus, daemon_csrbus_wr})
824 // reads
825 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
826 en_err_acc_vio = 1'b0;
827 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
828 en_err_acc_vio = 1'b0;
829 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
830 en_err_acc_vio = 1'b0;
831 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
832 en_err_acc_vio = 1'b0;
833 // writes
834 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
835 en_err_acc_vio = 1'b0;
836 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
837 en_err_acc_vio = 1'b0;
838 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
839 en_err_acc_vio = 1'b0;
840 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
841 en_err_acc_vio = 1'b0;
842
843 default:
844 begin
845 en_err_acc_vio = 1'b0;
846 begin // axis tbcall_region
847 // vlint flag_system_call off
848 // synopsys translate_off
849`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_en_err"); `endif
850 // synopsys translate_on
851 // vlint flag_system_call on
852 end // end of tbcall_region
853 end
854 endcase
855 end
856//----- reg_acc_vio: err
857reg err_acc_vio;
858always @(csrbus_src_bus or daemon_csrbus_wr or
859 err_rw1c_alias_addr_decoded or
860 err_rw1s_alias_addr_decoded or
861 daemon_transaction_in_progress)
862 begin
863 if (daemon_transaction_in_progress |
864 ~ (err_rw1c_alias_addr_decoded | err_rw1s_alias_addr_decoded))
865 err_acc_vio = 1'b0;
866 else
867 case ({csrbus_src_bus, daemon_csrbus_wr})
868 // reads
869 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
870 err_acc_vio = 1'b0;
871 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
872 err_acc_vio = 1'b0;
873 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
874 err_acc_vio = 1'b0;
875 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
876 err_acc_vio = 1'b0;
877 // writes
878 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
879 err_acc_vio = 1'b0;
880 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
881 err_acc_vio = 1'b0;
882 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
883 err_acc_vio = 1'b0;
884 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
885 err_acc_vio = 1'b0;
886
887 default:
888 begin
889 err_acc_vio = 1'b0;
890 begin // axis tbcall_region
891 // vlint flag_system_call off
892 // synopsys translate_off
893`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_err_rw1c_alias"); `endif
894 // synopsys translate_on
895 // vlint flag_system_call on
896 end // end of tbcall_region
897 end
898 endcase
899 end
900//----- reg_acc_vio: flta
901reg flta_acc_vio;
902always @(csrbus_src_bus or daemon_csrbus_wr or
903 flta_addr_decoded or
904 daemon_transaction_in_progress)
905 begin
906 if (daemon_transaction_in_progress | ~flta_addr_decoded)
907 flta_acc_vio = 1'b0;
908 else
909 case ({csrbus_src_bus, daemon_csrbus_wr})
910 // reads
911 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
912 flta_acc_vio = 1'b0;
913 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
914 flta_acc_vio = 1'b0;
915 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
916 flta_acc_vio = 1'b0;
917 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
918 flta_acc_vio = 1'b0;
919 // writes
920 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
921 flta_acc_vio = 1'b0;
922 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
923 flta_acc_vio = 1'b0;
924 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
925 flta_acc_vio = 1'b0;
926 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
927 flta_acc_vio = 1'b0;
928
929 default:
930 begin
931 flta_acc_vio = 1'b0;
932 begin // axis tbcall_region
933 // vlint flag_system_call off
934 // synopsys translate_off
935`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_flta"); `endif
936 // synopsys translate_on
937 // vlint flag_system_call on
938 end // end of tbcall_region
939 end
940 endcase
941 end
942//----- reg_acc_vio: flts
943reg flts_acc_vio;
944always @(csrbus_src_bus or daemon_csrbus_wr or
945 flts_addr_decoded or
946 daemon_transaction_in_progress)
947 begin
948 if (daemon_transaction_in_progress | ~flts_addr_decoded)
949 flts_acc_vio = 1'b0;
950 else
951 case ({csrbus_src_bus, daemon_csrbus_wr})
952 // reads
953 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
954 flts_acc_vio = 1'b0;
955 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
956 flts_acc_vio = 1'b0;
957 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
958 flts_acc_vio = 1'b0;
959 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
960 flts_acc_vio = 1'b0;
961 // writes
962 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
963 flts_acc_vio = 1'b0;
964 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
965 flts_acc_vio = 1'b0;
966 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
967 flts_acc_vio = 1'b0;
968 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
969 flts_acc_vio = 1'b0;
970
971 default:
972 begin
973 flts_acc_vio = 1'b0;
974 begin // axis tbcall_region
975 // vlint flag_system_call off
976 // synopsys translate_off
977`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_flts"); `endif
978 // synopsys translate_on
979 // vlint flag_system_call on
980 end // end of tbcall_region
981 end
982 endcase
983 end
984//----- reg_acc_vio: prfc
985reg prfc_acc_vio;
986always @(csrbus_src_bus or daemon_csrbus_wr or
987 prfc_addr_decoded or
988 daemon_transaction_in_progress)
989 begin
990 if (daemon_transaction_in_progress | ~prfc_addr_decoded)
991 prfc_acc_vio = 1'b0;
992 else
993 case ({csrbus_src_bus, daemon_csrbus_wr})
994 // reads
995 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
996 prfc_acc_vio = 1'b0;
997 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
998 prfc_acc_vio = 1'b0;
999 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1000 prfc_acc_vio = 1'b0;
1001 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1002 prfc_acc_vio = 1'b0;
1003 // writes
1004 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1005 prfc_acc_vio = 1'b0;
1006 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1007 prfc_acc_vio = 1'b0;
1008 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1009 prfc_acc_vio = 1'b0;
1010 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1011 prfc_acc_vio = 1'b0;
1012
1013 default:
1014 begin
1015 prfc_acc_vio = 1'b0;
1016 begin // axis tbcall_region
1017 // vlint flag_system_call off
1018 // synopsys translate_off
1019`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_prfc"); `endif
1020 // synopsys translate_on
1021 // vlint flag_system_call on
1022 end // end of tbcall_region
1023 end
1024 endcase
1025 end
1026//----- reg_acc_vio: prf0
1027reg prf0_acc_vio;
1028always @(csrbus_src_bus or daemon_csrbus_wr or
1029 prf0_addr_decoded or
1030 daemon_transaction_in_progress)
1031 begin
1032 if (daemon_transaction_in_progress | ~prf0_addr_decoded)
1033 prf0_acc_vio = 1'b0;
1034 else
1035 case ({csrbus_src_bus, daemon_csrbus_wr})
1036 // reads
1037 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
1038 prf0_acc_vio = 1'b0;
1039 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
1040 prf0_acc_vio = 1'b0;
1041 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1042 prf0_acc_vio = 1'b0;
1043 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1044 prf0_acc_vio = 1'b0;
1045 // writes
1046 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1047 prf0_acc_vio = 1'b0;
1048 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1049 prf0_acc_vio = 1'b0;
1050 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1051 prf0_acc_vio = 1'b0;
1052 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1053 prf0_acc_vio = 1'b0;
1054
1055 default:
1056 begin
1057 prf0_acc_vio = 1'b0;
1058 begin // axis tbcall_region
1059 // vlint flag_system_call off
1060 // synopsys translate_off
1061`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_prf0"); `endif
1062 // synopsys translate_on
1063 // vlint flag_system_call on
1064 end // end of tbcall_region
1065 end
1066 endcase
1067 end
1068//----- reg_acc_vio: prf1
1069reg prf1_acc_vio;
1070always @(csrbus_src_bus or daemon_csrbus_wr or
1071 prf1_addr_decoded or
1072 daemon_transaction_in_progress)
1073 begin
1074 if (daemon_transaction_in_progress | ~prf1_addr_decoded)
1075 prf1_acc_vio = 1'b0;
1076 else
1077 case ({csrbus_src_bus, daemon_csrbus_wr})
1078 // reads
1079 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
1080 prf1_acc_vio = 1'b0;
1081 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
1082 prf1_acc_vio = 1'b0;
1083 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1084 prf1_acc_vio = 1'b0;
1085 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1086 prf1_acc_vio = 1'b0;
1087 // writes
1088 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1089 prf1_acc_vio = 1'b0;
1090 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1091 prf1_acc_vio = 1'b0;
1092 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1093 prf1_acc_vio = 1'b0;
1094 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1095 prf1_acc_vio = 1'b0;
1096
1097 default:
1098 begin
1099 prf1_acc_vio = 1'b0;
1100 begin // axis tbcall_region
1101 // vlint flag_system_call off
1102 // synopsys translate_off
1103`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_prf1"); `endif
1104 // synopsys translate_on
1105 // vlint flag_system_call on
1106 end // end of tbcall_region
1107 end
1108 endcase
1109 end
1110//----- reg_acc_vio: vtb
1111reg vtb_acc_vio;
1112always @(csrbus_src_bus or daemon_csrbus_wr or
1113 vtb_addr_decoded or
1114 daemon_transaction_in_progress or vtb_hw_acc_jtag_rd or
1115 vtb_hw_acc_jtag_wr or vtb_hw_acc_pio_slow_rd or
1116 vtb_hw_acc_pio_slow_wr or vtb_hw_acc_pio_med_rd or
1117 vtb_hw_acc_pio_med_wr or vtb_hw_acc_pio_fast_rd or
1118 vtb_hw_acc_pio_fast_wr)
1119 begin
1120 if (daemon_transaction_in_progress | ~vtb_addr_decoded)
1121 vtb_acc_vio = 1'b0;
1122 else
1123 case ({csrbus_src_bus, daemon_csrbus_wr})
1124 // reads
1125 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
1126 vtb_acc_vio = ~vtb_hw_acc_jtag_rd;
1127 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
1128 vtb_acc_vio = ~vtb_hw_acc_pio_slow_rd;
1129 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1130 vtb_acc_vio = ~vtb_hw_acc_pio_med_rd;
1131 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1132 vtb_acc_vio = ~vtb_hw_acc_pio_fast_rd;
1133 // writes
1134 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1135 vtb_acc_vio = ~vtb_hw_acc_jtag_wr;
1136 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1137 vtb_acc_vio = ~vtb_hw_acc_pio_slow_wr;
1138 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1139 vtb_acc_vio = ~vtb_hw_acc_pio_med_wr;
1140 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1141 vtb_acc_vio = ~vtb_hw_acc_pio_fast_wr;
1142
1143 default:
1144 begin
1145 vtb_acc_vio = 1'b0;
1146 begin // axis tbcall_region
1147 // vlint flag_system_call off
1148 // synopsys translate_off
1149`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_vtb"); `endif
1150 // synopsys translate_on
1151 // vlint flag_system_call on
1152 end // end of tbcall_region
1153 end
1154 endcase
1155 end
1156//----- reg_acc_vio: ptb
1157reg ptb_acc_vio;
1158always @(csrbus_src_bus or daemon_csrbus_wr or
1159 ptb_addr_decoded or
1160 daemon_transaction_in_progress or ptb_hw_acc_jtag_rd or
1161 ptb_hw_acc_jtag_wr or ptb_hw_acc_pio_slow_rd or
1162 ptb_hw_acc_pio_slow_wr or ptb_hw_acc_pio_med_rd or
1163 ptb_hw_acc_pio_med_wr or ptb_hw_acc_pio_fast_rd or
1164 ptb_hw_acc_pio_fast_wr)
1165 begin
1166 if (daemon_transaction_in_progress | ~ptb_addr_decoded)
1167 ptb_acc_vio = 1'b0;
1168 else
1169 case ({csrbus_src_bus, daemon_csrbus_wr})
1170 // reads
1171 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
1172 ptb_acc_vio = ~ptb_hw_acc_jtag_rd;
1173 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
1174 ptb_acc_vio = ~ptb_hw_acc_pio_slow_rd;
1175 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1176 ptb_acc_vio = ~ptb_hw_acc_pio_med_rd;
1177 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1178 ptb_acc_vio = ~ptb_hw_acc_pio_fast_rd;
1179 // writes
1180 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1181 ptb_acc_vio = ~ptb_hw_acc_jtag_wr;
1182 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1183 ptb_acc_vio = ~ptb_hw_acc_pio_slow_wr;
1184 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1185 ptb_acc_vio = ~ptb_hw_acc_pio_med_wr;
1186 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1187 ptb_acc_vio = ~ptb_hw_acc_pio_fast_wr;
1188
1189 default:
1190 begin
1191 ptb_acc_vio = 1'b0;
1192 begin // axis tbcall_region
1193 // vlint flag_system_call off
1194 // synopsys translate_off
1195`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_ptb"); `endif
1196 // synopsys translate_on
1197 // vlint flag_system_call on
1198 end // end of tbcall_region
1199 end
1200 endcase
1201 end
1202//----- reg_acc_vio: tdb
1203reg tdb_acc_vio;
1204always @(csrbus_src_bus or daemon_csrbus_wr or
1205 tdb_addr_decoded or
1206 daemon_transaction_in_progress or tdb_hw_acc_jtag_rd or
1207 tdb_hw_acc_jtag_wr or tdb_hw_acc_pio_slow_rd or
1208 tdb_hw_acc_pio_slow_wr or tdb_hw_acc_pio_med_rd or
1209 tdb_hw_acc_pio_med_wr or tdb_hw_acc_pio_fast_rd or
1210 tdb_hw_acc_pio_fast_wr)
1211 begin
1212 if (daemon_transaction_in_progress | ~tdb_addr_decoded)
1213 tdb_acc_vio = 1'b0;
1214 else
1215 case ({csrbus_src_bus, daemon_csrbus_wr})
1216 // reads
1217 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
1218 tdb_acc_vio = ~tdb_hw_acc_jtag_rd;
1219 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
1220 tdb_acc_vio = ~tdb_hw_acc_pio_slow_rd;
1221 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1222 tdb_acc_vio = ~tdb_hw_acc_pio_med_rd;
1223 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1224 tdb_acc_vio = ~tdb_hw_acc_pio_fast_rd;
1225 // writes
1226 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1227 tdb_acc_vio = ~tdb_hw_acc_jtag_wr;
1228 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1229 tdb_acc_vio = ~tdb_hw_acc_pio_slow_wr;
1230 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1231 tdb_acc_vio = ~tdb_hw_acc_pio_med_wr;
1232 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1233 tdb_acc_vio = ~tdb_hw_acc_pio_fast_wr;
1234
1235 default:
1236 begin
1237 tdb_acc_vio = 1'b0;
1238 begin // axis tbcall_region
1239 // vlint flag_system_call off
1240 // synopsys translate_off
1241`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_tdb"); `endif
1242 // synopsys translate_on
1243 // vlint flag_system_call on
1244 end // end of tbcall_region
1245 end
1246 endcase
1247 end
1248//----- reg_acc_vio: dev2iotsb
1249reg dev2iotsb_acc_vio;
1250always @(csrbus_src_bus or daemon_csrbus_wr or
1251 dev2iotsb_addr_decoded or
1252 daemon_transaction_in_progress or dev2iotsb_hw_acc_jtag_rd or
1253 dev2iotsb_hw_acc_jtag_wr or dev2iotsb_hw_acc_pio_slow_rd or
1254 dev2iotsb_hw_acc_pio_slow_wr or dev2iotsb_hw_acc_pio_med_rd or
1255 dev2iotsb_hw_acc_pio_med_wr or dev2iotsb_hw_acc_pio_fast_rd or
1256 dev2iotsb_hw_acc_pio_fast_wr)
1257 begin
1258 if (daemon_transaction_in_progress | ~dev2iotsb_addr_decoded)
1259 dev2iotsb_acc_vio = 1'b0;
1260 else
1261 case ({csrbus_src_bus, daemon_csrbus_wr})
1262 // reads
1263 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
1264 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_jtag_rd;
1265 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
1266 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_pio_slow_rd;
1267 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1268 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_pio_med_rd;
1269 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1270 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_pio_fast_rd;
1271 // writes
1272 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1273 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_jtag_wr;
1274 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1275 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_pio_slow_wr;
1276 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1277 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_pio_med_wr;
1278 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1279 dev2iotsb_acc_vio = ~dev2iotsb_hw_acc_pio_fast_wr;
1280
1281 default:
1282 begin
1283 dev2iotsb_acc_vio = 1'b0;
1284 begin // axis tbcall_region
1285 // vlint flag_system_call off
1286 // synopsys translate_off
1287`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_dev2iotsb"); `endif
1288 // synopsys translate_on
1289 // vlint flag_system_call on
1290 end // end of tbcall_region
1291 end
1292 endcase
1293 end
1294//----- reg_acc_vio: IotsbDesc
1295reg IotsbDesc_acc_vio;
1296always @(csrbus_src_bus or daemon_csrbus_wr or
1297 IotsbDesc_addr_decoded or
1298 daemon_transaction_in_progress or IotsbDesc_hw_acc_jtag_rd or
1299 IotsbDesc_hw_acc_jtag_wr or IotsbDesc_hw_acc_pio_slow_rd or
1300 IotsbDesc_hw_acc_pio_slow_wr or IotsbDesc_hw_acc_pio_med_rd or
1301 IotsbDesc_hw_acc_pio_med_wr or IotsbDesc_hw_acc_pio_fast_rd or
1302 IotsbDesc_hw_acc_pio_fast_wr)
1303 begin
1304 if (daemon_transaction_in_progress | ~IotsbDesc_addr_decoded)
1305 IotsbDesc_acc_vio = 1'b0;
1306 else
1307 case ({csrbus_src_bus, daemon_csrbus_wr})
1308 // reads
1309 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b0}:
1310 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_jtag_rd;
1311 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b0}:
1312 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_pio_slow_rd;
1313 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b0}:
1314 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_pio_med_rd;
1315 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b0}:
1316 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_pio_fast_rd;
1317 // writes
1318 {`FIRE_CSRBUS_SRC_BUS_ENC_JTAG, 1'b1}:
1319 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_jtag_wr;
1320 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_SLOW, 1'b1}:
1321 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_pio_slow_wr;
1322 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_MED, 1'b1}:
1323 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_pio_med_wr;
1324 {`FIRE_CSRBUS_SRC_BUS_ENC_PIO_FAST, 1'b1}:
1325 IotsbDesc_acc_vio = ~IotsbDesc_hw_acc_pio_fast_wr;
1326
1327 default:
1328 begin
1329 IotsbDesc_acc_vio = 1'b0;
1330 begin // axis tbcall_region
1331 // vlint flag_system_call off
1332 // synopsys translate_off
1333`ifdef PR_ERROR if ($time > 1 && rst_l) `PR_ERROR("dmu_mmu_csr_addr_decode",`MON_ERROR,"acc_vio: default case of dmu_mmu_csr_a_IotsbDesc"); `endif
1334 // synopsys translate_on
1335 // vlint flag_system_call on
1336 end // end of tbcall_region
1337 end
1338 endcase
1339 end
1340
1341//====================================================================
1342// Status: daemon_csrbus_mapped / csrbus_acc_vio
1343//====================================================================
1344//----- OUTPUT: daemon_csrbus_mapped
1345assign daemon_csrbus_mapped = clocked_valid_pulse &
1346 (
1347 ctl_addr_decoded |
1348 tsb_addr_decoded |
1349 fsh_addr_decoded |
1350 inv_addr_decoded |
1351 log_addr_decoded |
1352 int_en_addr_decoded |
1353 en_err_addr_decoded |
1354 err_rw1s_alias_addr_decoded |
1355 err_rw1c_alias_addr_decoded |
1356 flta_addr_decoded |
1357 flts_addr_decoded |
1358 prfc_addr_decoded |
1359 prf0_addr_decoded |
1360 prf1_addr_decoded |
1361 vtb_addr_decoded |
1362 ptb_addr_decoded |
1363 tdb_addr_decoded |
1364 dev2iotsb_addr_decoded |
1365 IotsbDesc_addr_decoded
1366 );
1367
1368
1369// daemon_csrbus_mapped gets asserted after fixed number of cycles
1370// after daemon_csrbus_valid become high
1371/* 0in assert_together -name mapped_after_valid
1372 -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 1))
1373 -follower $0in_rising_edge(daemon_csrbus_mapped)
1374 -message ("daemon_csrbus_mapped was not asserted 1 clock cycles from csrbus_valid")
1375 -module dmu_mmu_csr_addr_decode
1376 -clock clk
1377 -active $0in_rising_edge(daemon_csrbus_mapped)
1378*/
1379
1380// daemon_csrbus_mapped is a pulse
1381/* 0in assert_timer -name daemon_csrbus_mapped_pulse
1382 -var daemon_csrbus_mapped -max 1
1383 -message "daemon_csrbus_mapped pulse length is not 1"
1384 -module dmu_mmu_csr_addr_decode
1385 -clock clk
1386*/
1387//----- OUTPUT: csrbus_acc_vio
1388assign csrbus_acc_vio = clocked_valid_pulse &
1389 ctl_acc_vio |
1390 tsb_acc_vio |
1391 fsh_acc_vio |
1392 inv_acc_vio |
1393 log_acc_vio |
1394 int_en_acc_vio |
1395 en_err_acc_vio |
1396 err_acc_vio |
1397 flta_acc_vio |
1398 flts_acc_vio |
1399 prfc_acc_vio |
1400 prf0_acc_vio |
1401 prf1_acc_vio |
1402 vtb_acc_vio |
1403 ptb_acc_vio |
1404 tdb_acc_vio |
1405 dev2iotsb_acc_vio |
1406 IotsbDesc_acc_vio;
1407
1408//====================================================================
1409// Select
1410//====================================================================
1411always @(posedge clk)
1412 begin
1413 if(~rst_l)
1414 begin
1415 ctl_select_pulse <= 1'b0;
1416 tsb_select_pulse <= 1'b0;
1417 fsh_select_pulse <= 1'b0;
1418 inv_select <= 1'b0;
1419 log_select_pulse <= 1'b0;
1420 int_en_select_pulse <= 1'b0;
1421 en_err_select <= 1'b0;
1422 err_select_pulse <= 1'b0;
1423 flta_select_pulse <= 1'b0;
1424 flts_select_pulse <= 1'b0;
1425 prfc_select_pulse <= 1'b0;
1426 prf0_select_pulse <= 1'b0;
1427 prf1_select_pulse <= 1'b0;
1428 vtb_select <= 1'b0;
1429 ptb_select <= 1'b0;
1430 tdb_select <= 1'b0;
1431 dev2iotsb_select <= 1'b0;
1432 IotsbDesc_select <= 1'b0;
1433 end
1434 else
1435 begin
1436 ctl_select_pulse <=
1437 ~ctl_acc_vio &
1438 clocked_valid_pulse &
1439 ctl_addr_decoded;
1440
1441 tsb_select_pulse <=
1442 ~tsb_acc_vio &
1443 clocked_valid_pulse &
1444 tsb_addr_decoded;
1445
1446 fsh_select_pulse <=
1447 ~fsh_acc_vio &
1448 clocked_valid_pulse &
1449 fsh_addr_decoded;
1450
1451 inv_select <=
1452 ~inv_acc_vio &
1453 inv_addr_decoded;
1454
1455 log_select_pulse <=
1456 ~log_acc_vio &
1457 clocked_valid_pulse &
1458 log_addr_decoded;
1459
1460 int_en_select_pulse <=
1461 ~int_en_acc_vio &
1462 clocked_valid_pulse &
1463 int_en_addr_decoded;
1464
1465 en_err_select <=
1466 ~en_err_acc_vio &
1467 en_err_addr_decoded;
1468
1469 err_select_pulse <=
1470 ~err_acc_vio &
1471 clocked_valid_pulse &
1472 (
1473 err_rw1c_alias_addr_decoded |
1474 err_rw1s_alias_addr_decoded
1475 );
1476
1477 flta_select_pulse <=
1478 ~flta_acc_vio &
1479 clocked_valid_pulse &
1480 flta_addr_decoded;
1481
1482 flts_select_pulse <=
1483 ~flts_acc_vio &
1484 clocked_valid_pulse &
1485 flts_addr_decoded;
1486
1487 prfc_select_pulse <=
1488 ~prfc_acc_vio &
1489 clocked_valid_pulse &
1490 prfc_addr_decoded;
1491
1492 prf0_select_pulse <=
1493 ~prf0_acc_vio &
1494 clocked_valid_pulse &
1495 prf0_addr_decoded;
1496
1497 prf1_select_pulse <=
1498 ~prf1_acc_vio &
1499 clocked_valid_pulse &
1500 prf1_addr_decoded;
1501
1502 vtb_select <=
1503 ~ vtb_acc_vio &
1504 vtb_addr_decoded;
1505
1506 ptb_select <=
1507 ~ ptb_acc_vio &
1508 ptb_addr_decoded;
1509
1510 tdb_select <=
1511 ~ tdb_acc_vio &
1512 tdb_addr_decoded;
1513
1514 dev2iotsb_select <=
1515 ~ dev2iotsb_acc_vio &
1516 dev2iotsb_addr_decoded;
1517
1518 IotsbDesc_select <=
1519 ~ IotsbDesc_acc_vio &
1520 IotsbDesc_addr_decoded;
1521
1522 end
1523 end
1524
1525//====================================================================
1526// daemon_csrbus_wr / daemon_csrbus_wr_data
1527//====================================================================
1528always @(posedge clk)
1529 begin
1530 if(~rst_l)
1531 begin
1532 daemon_csrbus_wr_out <= 1'b0;
1533 daemon_csrbus_wr_data_out <= `FIRE_CSRBUS_DATA_WIDTH'b0;
1534 end
1535 else
1536 begin
1537 daemon_csrbus_wr_out <= daemon_csrbus_wr;
1538 daemon_csrbus_wr_data_out <= daemon_csrbus_wr_data;
1539 end
1540 end
1541
1542//====================================================================
1543// Cycle Counter: Used for ExtReadTiming / ExtWriteTiming
1544//====================================================================
1545reg [1:0] dcm_cycle_counter;
1546
1547reg daemon_csrbus_valid_p1; //Delaying
1548reg daemon_csrbus_valid_p2; //Delaying
1549reg daemon_csrbus_valid_p3; //Delaying
1550
1551always @(posedge clk)
1552 begin
1553 if(~rst_l)
1554 begin
1555 daemon_csrbus_valid_p1 <= 1'b0;
1556 daemon_csrbus_valid_p2 <= 1'b0;
1557 daemon_csrbus_valid_p3 <= 1'b0;
1558
1559 dcm_cycle_counter <= 2'b0;
1560 end
1561 else
1562 begin
1563 daemon_csrbus_valid_p1 <= daemon_csrbus_valid;
1564 daemon_csrbus_valid_p2 <= daemon_csrbus_valid & daemon_csrbus_valid_p1;
1565 daemon_csrbus_valid_p3 <= daemon_csrbus_valid & daemon_csrbus_valid_p2;
1566
1567 if(~daemon_csrbus_valid)
1568 dcm_cycle_counter <= 2'b0;
1569 else if(daemon_csrbus_valid_p3 & dcm_cycle_counter != 2'd3)
1570 dcm_cycle_counter <= dcm_cycle_counter + 2'b1;
1571 else
1572 dcm_cycle_counter <= dcm_cycle_counter;
1573 end
1574 end
1575
1576wire vtb_read_ext_done =
1577 dcm_cycle_counter == 2'd1 &
1578 ~ daemon_csrbus_wr &
1579 vtb_select;
1580
1581// vtb_read_ext_done gets asserted after a given # of
1582// cycles after daemon_csrbus_valid
1583/* 0in assert_together -name vtb_read_ext_done_after_daemon_csrbus_valid
1584 -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 4))
1585 -follower $0in_rising_edge(vtb_read_ext_done)
1586 -message ("vtb_read_ext_done was not asserted 4 clock cycles from daemon_csrbus_valid")
1587 -module dmu_mmu_csr_addr_decode
1588 -clock clk
1589 -active (vtb_select & !daemon_csrbus_wr)
1590*/
1591
1592wire ptb_read_ext_done =
1593 dcm_cycle_counter == 2'd1 &
1594 ~ daemon_csrbus_wr &
1595 ptb_select;
1596
1597// ptb_read_ext_done gets asserted after a given # of
1598// cycles after daemon_csrbus_valid
1599/* 0in assert_together -name ptb_read_ext_done_after_daemon_csrbus_valid
1600 -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 4))
1601 -follower $0in_rising_edge(ptb_read_ext_done)
1602 -message ("ptb_read_ext_done was not asserted 4 clock cycles from daemon_csrbus_valid")
1603 -module dmu_mmu_csr_addr_decode
1604 -clock clk
1605 -active (ptb_select & !daemon_csrbus_wr)
1606*/
1607
1608wire tdb_read_ext_done =
1609 dcm_cycle_counter == 2'd2 &
1610 ~ daemon_csrbus_wr &
1611 tdb_select;
1612
1613// tdb_read_ext_done gets asserted after a given # of
1614// cycles after daemon_csrbus_valid
1615/* 0in assert_together -name tdb_read_ext_done_after_daemon_csrbus_valid
1616 -leader $0in_rising_edge($0in_delay(daemon_csrbus_valid, 5))
1617 -follower $0in_rising_edge(tdb_read_ext_done)
1618 -message ("tdb_read_ext_done was not asserted 5 clock cycles from daemon_csrbus_valid")
1619 -module dmu_mmu_csr_addr_decode
1620 -clock clk
1621 -active (tdb_select & !daemon_csrbus_wr)
1622*/
1623
1624
1625//====================================================================
1626// Alias
1627//====================================================================
1628assign err_rw1c_alias=
1629 err_rw1c_alias_addr_decoded;
1630
1631assign err_rw1s_alias=
1632 err_rw1s_alias_addr_decoded;
1633
1634
1635//====================================================================
1636// OUTPUT: daemon_csrbus_done (pipelining)
1637//====================================================================
1638//----- DONE for internal/extern registers
1639reg stage_1_daemon_csrbus_done_internal_0;
1640reg stage_1_daemon_csrbus_done_internal_1;
1641reg stage_2_daemon_csrbus_done_internal_0;
1642reg stage_3_daemon_csrbus_done_internal_0;
1643reg stage_4_daemon_csrbus_done_internal_0;
1644
1645always @(posedge clk)
1646 begin
1647 if(~rst_l)
1648 begin
1649 stage_1_daemon_csrbus_done_internal_0 <= 1'b0;
1650 stage_1_daemon_csrbus_done_internal_1 <= 1'b0;
1651 end
1652 else
1653 begin
1654 stage_1_daemon_csrbus_done_internal_0 <=
1655 ctl_select_pulse |
1656 tsb_select_pulse |
1657 fsh_select_pulse |
1658 log_select_pulse |
1659 int_en_select_pulse |
1660 err_select_pulse |
1661 flta_select_pulse |
1662 flts_select_pulse |
1663 prfc_select_pulse |
1664 prf0_select_pulse |
1665 prf1_select_pulse |
1666 inv_select & clocked_valid_pulse |
1667 en_err_select & clocked_valid_pulse |
1668 vtb_select & clocked_valid_pulse & daemon_csrbus_wr |
1669 ptb_select & clocked_valid_pulse & daemon_csrbus_wr;
1670 stage_1_daemon_csrbus_done_internal_1 <=
1671 tdb_select & clocked_valid_pulse & daemon_csrbus_wr;
1672 end
1673 if(~rst_l)
1674 begin
1675 stage_2_daemon_csrbus_done_internal_0 <= 1'b0;
1676 end
1677 else
1678 begin
1679 stage_2_daemon_csrbus_done_internal_0 <=
1680 stage_1_daemon_csrbus_done_internal_0 |
1681 stage_1_daemon_csrbus_done_internal_1;
1682 end
1683 if(~rst_l)
1684 begin
1685 stage_3_daemon_csrbus_done_internal_0 <= 1'b0;
1686 end
1687 else
1688 begin
1689 stage_3_daemon_csrbus_done_internal_0 <=
1690 stage_2_daemon_csrbus_done_internal_0;
1691 end
1692 if(~rst_l)
1693 begin
1694 stage_4_daemon_csrbus_done_internal_0 <= 1'b0;
1695 end
1696 else
1697 begin
1698 stage_4_daemon_csrbus_done_internal_0 <=
1699 stage_3_daemon_csrbus_done_internal_0;
1700 end
1701 end
1702
1703//----- DONE for extern registers from cycle_counter
1704reg stage_1_daemon_csrbus_done_cycle_counter_0;
1705reg stage_2_daemon_csrbus_done_cycle_counter_0;
1706
1707always @(posedge clk)
1708 begin
1709 if(~rst_l)
1710 begin
1711 stage_1_daemon_csrbus_done_cycle_counter_0 <= 1'b0;
1712 end
1713 else
1714 begin
1715 stage_1_daemon_csrbus_done_cycle_counter_0 <=
1716 vtb_read_ext_done |
1717 ptb_read_ext_done |
1718 tdb_read_ext_done;
1719 end
1720 if(~rst_l)
1721 begin
1722 stage_2_daemon_csrbus_done_cycle_counter_0 <= 1'b0;
1723 end
1724 else
1725 begin
1726 stage_2_daemon_csrbus_done_cycle_counter_0 <=
1727 stage_1_daemon_csrbus_done_cycle_counter_0;
1728 end
1729 end
1730
1731//----- OUTPUT: daemon_csrbus_done
1732assign daemon_csrbus_done = daemon_csrbus_valid &
1733 (
1734 stage_4_daemon_csrbus_done_internal_0 |
1735 stage_2_daemon_csrbus_done_cycle_counter_0 |
1736 stage_mux_only_ext_done_0_out
1737 );
1738
1739// daemon_csrbus_done gets asserted only when csrbus_valid is high
1740/* 0in assert -name daemon_csrbus_done_high
1741 -var daemon_csrbus_valid -active daemon_csrbus_done
1742 -message "csrbus_done got asserted while csrbus_valid is low"
1743 -module dmu_mmu_csr_addr_decode
1744 -clock clk
1745*/
1746
1747// daemon_csrbus_done is a pulse
1748/* 0in assert_timer -name daemon_csrbus_done_pulse
1749 -var daemon_csrbus_done -max 1
1750 -message "csrbus_done pulse length is not 1"
1751 -module dmu_mmu_csr_addr_decode
1752 -clock clk
1753*/
1754
1755endmodule // dmu_mmu_csr_addr_decode
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