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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_err_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_csr_err_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | omni_rw1c_alias, | |
41 | omni_rw1s_alias, | |
42 | // synopsys translate_on | |
43 | clk, | |
44 | por_l, | |
45 | w_ld, | |
46 | csrbus_wr_data, | |
47 | rw1c_alias, | |
48 | rw1s_alias, | |
49 | err_csrbus_read_data, | |
50 | err_hw_set | |
51 | ); | |
52 | ||
53 | //==================================================================== | |
54 | // Polarity declarations | |
55 | //==================================================================== | |
56 | // synopsys translate_off | |
57 | input omni_ld; // Omni load | |
58 | // vlint flag_input_port_not_connected off | |
59 | input [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH - 1:0] omni_data; | |
60 | // Omni write data | |
61 | // vlint flag_input_port_not_connected on | |
62 | input omni_rw1c_alias; // Omni load type: write-one-to-clear | |
63 | input omni_rw1s_alias; // Omni load type: write-one-to-set | |
64 | // synopsys translate_on | |
65 | input clk; // Clock signal | |
66 | input por_l; // Reset signal | |
67 | input w_ld; // SW load | |
68 | // vlint flag_input_port_not_connected off | |
69 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
70 | // vlint flag_input_port_not_connected on | |
71 | input rw1c_alias; // SW load type: write-one-to-clear | |
72 | input rw1s_alias; // SW load type: write-one-to-set | |
73 | output [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_csrbus_read_data; | |
74 | // SW read data | |
75 | // vlint flag_input_port_not_connected off | |
76 | input [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH -1:0] err_hw_set; // Hardware | |
77 | // set signal | |
78 | // for err. | |
79 | // When set | |
80 | // err will be | |
81 | // set to one. | |
82 | // vlint flag_input_port_not_connected on | |
83 | ||
84 | //==================================================================== | |
85 | // Type declarations | |
86 | //==================================================================== | |
87 | // synopsys translate_off | |
88 | wire omni_ld; // Omni load | |
89 | // vlint flag_dangling_net_within_module off | |
90 | // vlint flag_net_has_no_load off | |
91 | wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH - 1:0] omni_data; // Omni write | |
92 | // data | |
93 | // vlint flag_dangling_net_within_module on | |
94 | // vlint flag_net_has_no_load on | |
95 | wire omni_rw1c_alias; // Omni load type: write-one-to-clear | |
96 | wire omni_rw1s_alias; // Omni load type: write-one-to-set | |
97 | // synopsys translate_on | |
98 | wire clk; // Clock signal | |
99 | wire por_l; // Reset signal | |
100 | wire w_ld; // SW load | |
101 | // vlint flag_dangling_net_within_module off | |
102 | // vlint flag_net_has_no_load off | |
103 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
104 | // vlint flag_dangling_net_within_module on | |
105 | // vlint flag_net_has_no_load on | |
106 | wire rw1c_alias; // SW load type: write-one-to-clear | |
107 | wire rw1s_alias; // SW load type: write-one-to-set | |
108 | wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH-1:0] err_csrbus_read_data; | |
109 | // SW read data | |
110 | // vlint flag_dangling_net_within_module off | |
111 | // vlint flag_net_has_no_load off | |
112 | wire [`FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH -1:0] err_hw_set; // Hardware set | |
113 | // signal for | |
114 | // err. When set | |
115 | // err will be | |
116 | // set to one. | |
117 | // vlint flag_dangling_net_within_module on | |
118 | // vlint flag_net_has_no_load on | |
119 | ||
120 | //==================================================================== | |
121 | // Logic | |
122 | //==================================================================== | |
123 | ||
124 | //----- Reset values | |
125 | // verilint 531 off | |
126 | wire [0:0] reset_sun4v_key_err_s = 1'h0; | |
127 | wire [0:0] reset_sun4v_va_adj_uf_s = 1'h0; | |
128 | wire [0:0] reset_sun4v_va_oor_s = 1'h0; | |
129 | wire [0:0] reset_iotsbdesc_dpe_s = 1'h0; | |
130 | wire [0:0] reset_iotsbdesc_inv_s = 1'h0; | |
131 | wire [0:0] reset_tbw_dpe_s = 1'h0; | |
132 | wire [0:0] reset_tbw_err_s = 1'h0; | |
133 | wire [0:0] reset_tbw_ude_s = 1'h0; | |
134 | wire [0:0] reset_tbw_dme_s = 1'h0; | |
135 | wire [0:0] reset_spare3_s = 1'h0; | |
136 | wire [0:0] reset_spare2_s = 1'h0; | |
137 | wire [0:0] reset_ttc_cae_s = 1'h0; | |
138 | wire [0:0] reset_ttc_dpe_s = 1'h0; | |
139 | wire [0:0] reset_tte_prt_s = 1'h0; | |
140 | wire [0:0] reset_tte_inv_s = 1'h0; | |
141 | wire [0:0] reset_trn_oor_s = 1'h0; | |
142 | wire [0:0] reset_trn_err_s = 1'h0; | |
143 | wire [0:0] reset_spare1_s = 1'h0; | |
144 | wire [0:0] reset_spare0_s = 1'h0; | |
145 | wire [0:0] reset_byp_oor_s = 1'h0; | |
146 | wire [0:0] reset_byp_err_s = 1'h0; | |
147 | wire [0:0] reset_sun4v_key_err_p = 1'h0; | |
148 | wire [0:0] reset_sun4v_va_adj_uf_p = 1'h0; | |
149 | wire [0:0] reset_sun4v_va_oor_p = 1'h0; | |
150 | wire [0:0] reset_iotsbdesc_dpe_p = 1'h0; | |
151 | wire [0:0] reset_iotsbdesc_inv_p = 1'h0; | |
152 | wire [0:0] reset_tbw_dpe_p = 1'h0; | |
153 | wire [0:0] reset_tbw_err_p = 1'h0; | |
154 | wire [0:0] reset_tbw_ude_p = 1'h0; | |
155 | wire [0:0] reset_tbw_dme_p = 1'h0; | |
156 | wire [0:0] reset_spare3_p = 1'h0; | |
157 | wire [0:0] reset_spare2_p = 1'h0; | |
158 | wire [0:0] reset_ttc_cae_p = 1'h0; | |
159 | wire [0:0] reset_ttc_dpe_p = 1'h0; | |
160 | wire [0:0] reset_tte_prt_p = 1'h0; | |
161 | wire [0:0] reset_tte_inv_p = 1'h0; | |
162 | wire [0:0] reset_trn_oor_p = 1'h0; | |
163 | wire [0:0] reset_trn_err_p = 1'h0; | |
164 | wire [0:0] reset_spare1_p = 1'h0; | |
165 | wire [0:0] reset_spare0_p = 1'h0; | |
166 | wire [0:0] reset_byp_oor_p = 1'h0; | |
167 | wire [0:0] reset_byp_err_p = 1'h0; | |
168 | // verilint 531 on | |
169 | ||
170 | //----- Active high reset wires | |
171 | wire por_l_active_high = ~por_l; | |
172 | ||
173 | //==================================================== | |
174 | // Instantiation of flops | |
175 | //==================================================== | |
176 | ||
177 | // bit 0 | |
178 | csr_sw csr_sw_0 | |
179 | ( | |
180 | // synopsys translate_off | |
181 | .omni_ld (omni_ld), | |
182 | .omni_data (omni_data[0]), | |
183 | .omni_rw_alias (1'b0), | |
184 | .omni_rw1c_alias (omni_rw1c_alias), | |
185 | .omni_rw1s_alias (omni_rw1s_alias), | |
186 | // synopsys translate_on | |
187 | .rst (por_l_active_high), | |
188 | .rst_val (reset_byp_err_p[0]), | |
189 | .csr_ld (w_ld), | |
190 | .csr_data (csrbus_wr_data[0]), | |
191 | .rw_alias (1'b0), | |
192 | .rw1c_alias (rw1c_alias), | |
193 | .rw1s_alias (rw1s_alias), | |
194 | .hw_ld (err_hw_set[0]), | |
195 | .hw_data (1'b1), | |
196 | .cp (clk), | |
197 | .q (err_csrbus_read_data[0]) | |
198 | ); | |
199 | ||
200 | // bit 1 | |
201 | csr_sw csr_sw_1 | |
202 | ( | |
203 | // synopsys translate_off | |
204 | .omni_ld (omni_ld), | |
205 | .omni_data (omni_data[1]), | |
206 | .omni_rw_alias (1'b0), | |
207 | .omni_rw1c_alias (omni_rw1c_alias), | |
208 | .omni_rw1s_alias (omni_rw1s_alias), | |
209 | // synopsys translate_on | |
210 | .rst (por_l_active_high), | |
211 | .rst_val (reset_byp_oor_p[0]), | |
212 | .csr_ld (w_ld), | |
213 | .csr_data (csrbus_wr_data[1]), | |
214 | .rw_alias (1'b0), | |
215 | .rw1c_alias (rw1c_alias), | |
216 | .rw1s_alias (rw1s_alias), | |
217 | .hw_ld (err_hw_set[1]), | |
218 | .hw_data (1'b1), | |
219 | .cp (clk), | |
220 | .q (err_csrbus_read_data[1]) | |
221 | ); | |
222 | ||
223 | // bit 2 | |
224 | csr_sw csr_sw_2 | |
225 | ( | |
226 | // synopsys translate_off | |
227 | .omni_ld (omni_ld), | |
228 | .omni_data (omni_data[2]), | |
229 | .omni_rw_alias (1'b0), | |
230 | .omni_rw1c_alias (omni_rw1c_alias), | |
231 | .omni_rw1s_alias (omni_rw1s_alias), | |
232 | // synopsys translate_on | |
233 | .rst (por_l_active_high), | |
234 | .rst_val (reset_spare0_p[0]), | |
235 | .csr_ld (w_ld), | |
236 | .csr_data (csrbus_wr_data[2]), | |
237 | .rw_alias (1'b0), | |
238 | .rw1c_alias (rw1c_alias), | |
239 | .rw1s_alias (rw1s_alias), | |
240 | .hw_ld (err_hw_set[2]), | |
241 | .hw_data (1'b1), | |
242 | .cp (clk), | |
243 | .q (err_csrbus_read_data[2]) | |
244 | ); | |
245 | ||
246 | // bit 3 | |
247 | csr_sw csr_sw_3 | |
248 | ( | |
249 | // synopsys translate_off | |
250 | .omni_ld (omni_ld), | |
251 | .omni_data (omni_data[3]), | |
252 | .omni_rw_alias (1'b0), | |
253 | .omni_rw1c_alias (omni_rw1c_alias), | |
254 | .omni_rw1s_alias (omni_rw1s_alias), | |
255 | // synopsys translate_on | |
256 | .rst (por_l_active_high), | |
257 | .rst_val (reset_spare1_p[0]), | |
258 | .csr_ld (w_ld), | |
259 | .csr_data (csrbus_wr_data[3]), | |
260 | .rw_alias (1'b0), | |
261 | .rw1c_alias (rw1c_alias), | |
262 | .rw1s_alias (rw1s_alias), | |
263 | .hw_ld (err_hw_set[3]), | |
264 | .hw_data (1'b1), | |
265 | .cp (clk), | |
266 | .q (err_csrbus_read_data[3]) | |
267 | ); | |
268 | ||
269 | // bit 4 | |
270 | csr_sw csr_sw_4 | |
271 | ( | |
272 | // synopsys translate_off | |
273 | .omni_ld (omni_ld), | |
274 | .omni_data (omni_data[4]), | |
275 | .omni_rw_alias (1'b0), | |
276 | .omni_rw1c_alias (omni_rw1c_alias), | |
277 | .omni_rw1s_alias (omni_rw1s_alias), | |
278 | // synopsys translate_on | |
279 | .rst (por_l_active_high), | |
280 | .rst_val (reset_trn_err_p[0]), | |
281 | .csr_ld (w_ld), | |
282 | .csr_data (csrbus_wr_data[4]), | |
283 | .rw_alias (1'b0), | |
284 | .rw1c_alias (rw1c_alias), | |
285 | .rw1s_alias (rw1s_alias), | |
286 | .hw_ld (err_hw_set[4]), | |
287 | .hw_data (1'b1), | |
288 | .cp (clk), | |
289 | .q (err_csrbus_read_data[4]) | |
290 | ); | |
291 | ||
292 | // bit 5 | |
293 | csr_sw csr_sw_5 | |
294 | ( | |
295 | // synopsys translate_off | |
296 | .omni_ld (omni_ld), | |
297 | .omni_data (omni_data[5]), | |
298 | .omni_rw_alias (1'b0), | |
299 | .omni_rw1c_alias (omni_rw1c_alias), | |
300 | .omni_rw1s_alias (omni_rw1s_alias), | |
301 | // synopsys translate_on | |
302 | .rst (por_l_active_high), | |
303 | .rst_val (reset_trn_oor_p[0]), | |
304 | .csr_ld (w_ld), | |
305 | .csr_data (csrbus_wr_data[5]), | |
306 | .rw_alias (1'b0), | |
307 | .rw1c_alias (rw1c_alias), | |
308 | .rw1s_alias (rw1s_alias), | |
309 | .hw_ld (err_hw_set[5]), | |
310 | .hw_data (1'b1), | |
311 | .cp (clk), | |
312 | .q (err_csrbus_read_data[5]) | |
313 | ); | |
314 | ||
315 | // bit 6 | |
316 | csr_sw csr_sw_6 | |
317 | ( | |
318 | // synopsys translate_off | |
319 | .omni_ld (omni_ld), | |
320 | .omni_data (omni_data[6]), | |
321 | .omni_rw_alias (1'b0), | |
322 | .omni_rw1c_alias (omni_rw1c_alias), | |
323 | .omni_rw1s_alias (omni_rw1s_alias), | |
324 | // synopsys translate_on | |
325 | .rst (por_l_active_high), | |
326 | .rst_val (reset_tte_inv_p[0]), | |
327 | .csr_ld (w_ld), | |
328 | .csr_data (csrbus_wr_data[6]), | |
329 | .rw_alias (1'b0), | |
330 | .rw1c_alias (rw1c_alias), | |
331 | .rw1s_alias (rw1s_alias), | |
332 | .hw_ld (err_hw_set[6]), | |
333 | .hw_data (1'b1), | |
334 | .cp (clk), | |
335 | .q (err_csrbus_read_data[6]) | |
336 | ); | |
337 | ||
338 | // bit 7 | |
339 | csr_sw csr_sw_7 | |
340 | ( | |
341 | // synopsys translate_off | |
342 | .omni_ld (omni_ld), | |
343 | .omni_data (omni_data[7]), | |
344 | .omni_rw_alias (1'b0), | |
345 | .omni_rw1c_alias (omni_rw1c_alias), | |
346 | .omni_rw1s_alias (omni_rw1s_alias), | |
347 | // synopsys translate_on | |
348 | .rst (por_l_active_high), | |
349 | .rst_val (reset_tte_prt_p[0]), | |
350 | .csr_ld (w_ld), | |
351 | .csr_data (csrbus_wr_data[7]), | |
352 | .rw_alias (1'b0), | |
353 | .rw1c_alias (rw1c_alias), | |
354 | .rw1s_alias (rw1s_alias), | |
355 | .hw_ld (err_hw_set[7]), | |
356 | .hw_data (1'b1), | |
357 | .cp (clk), | |
358 | .q (err_csrbus_read_data[7]) | |
359 | ); | |
360 | ||
361 | // bit 8 | |
362 | csr_sw csr_sw_8 | |
363 | ( | |
364 | // synopsys translate_off | |
365 | .omni_ld (omni_ld), | |
366 | .omni_data (omni_data[8]), | |
367 | .omni_rw_alias (1'b0), | |
368 | .omni_rw1c_alias (omni_rw1c_alias), | |
369 | .omni_rw1s_alias (omni_rw1s_alias), | |
370 | // synopsys translate_on | |
371 | .rst (por_l_active_high), | |
372 | .rst_val (reset_ttc_dpe_p[0]), | |
373 | .csr_ld (w_ld), | |
374 | .csr_data (csrbus_wr_data[8]), | |
375 | .rw_alias (1'b0), | |
376 | .rw1c_alias (rw1c_alias), | |
377 | .rw1s_alias (rw1s_alias), | |
378 | .hw_ld (err_hw_set[8]), | |
379 | .hw_data (1'b1), | |
380 | .cp (clk), | |
381 | .q (err_csrbus_read_data[8]) | |
382 | ); | |
383 | ||
384 | // bit 9 | |
385 | csr_sw csr_sw_9 | |
386 | ( | |
387 | // synopsys translate_off | |
388 | .omni_ld (omni_ld), | |
389 | .omni_data (omni_data[9]), | |
390 | .omni_rw_alias (1'b0), | |
391 | .omni_rw1c_alias (omni_rw1c_alias), | |
392 | .omni_rw1s_alias (omni_rw1s_alias), | |
393 | // synopsys translate_on | |
394 | .rst (por_l_active_high), | |
395 | .rst_val (reset_ttc_cae_p[0]), | |
396 | .csr_ld (w_ld), | |
397 | .csr_data (csrbus_wr_data[9]), | |
398 | .rw_alias (1'b0), | |
399 | .rw1c_alias (rw1c_alias), | |
400 | .rw1s_alias (rw1s_alias), | |
401 | .hw_ld (err_hw_set[9]), | |
402 | .hw_data (1'b1), | |
403 | .cp (clk), | |
404 | .q (err_csrbus_read_data[9]) | |
405 | ); | |
406 | ||
407 | // bit 10 | |
408 | csr_sw csr_sw_10 | |
409 | ( | |
410 | // synopsys translate_off | |
411 | .omni_ld (omni_ld), | |
412 | .omni_data (omni_data[10]), | |
413 | .omni_rw_alias (1'b0), | |
414 | .omni_rw1c_alias (omni_rw1c_alias), | |
415 | .omni_rw1s_alias (omni_rw1s_alias), | |
416 | // synopsys translate_on | |
417 | .rst (por_l_active_high), | |
418 | .rst_val (reset_spare2_p[0]), | |
419 | .csr_ld (w_ld), | |
420 | .csr_data (csrbus_wr_data[10]), | |
421 | .rw_alias (1'b0), | |
422 | .rw1c_alias (rw1c_alias), | |
423 | .rw1s_alias (rw1s_alias), | |
424 | .hw_ld (err_hw_set[10]), | |
425 | .hw_data (1'b1), | |
426 | .cp (clk), | |
427 | .q (err_csrbus_read_data[10]) | |
428 | ); | |
429 | ||
430 | // bit 11 | |
431 | csr_sw csr_sw_11 | |
432 | ( | |
433 | // synopsys translate_off | |
434 | .omni_ld (omni_ld), | |
435 | .omni_data (omni_data[11]), | |
436 | .omni_rw_alias (1'b0), | |
437 | .omni_rw1c_alias (omni_rw1c_alias), | |
438 | .omni_rw1s_alias (omni_rw1s_alias), | |
439 | // synopsys translate_on | |
440 | .rst (por_l_active_high), | |
441 | .rst_val (reset_spare3_p[0]), | |
442 | .csr_ld (w_ld), | |
443 | .csr_data (csrbus_wr_data[11]), | |
444 | .rw_alias (1'b0), | |
445 | .rw1c_alias (rw1c_alias), | |
446 | .rw1s_alias (rw1s_alias), | |
447 | .hw_ld (err_hw_set[11]), | |
448 | .hw_data (1'b1), | |
449 | .cp (clk), | |
450 | .q (err_csrbus_read_data[11]) | |
451 | ); | |
452 | ||
453 | // bit 12 | |
454 | csr_sw csr_sw_12 | |
455 | ( | |
456 | // synopsys translate_off | |
457 | .omni_ld (omni_ld), | |
458 | .omni_data (omni_data[12]), | |
459 | .omni_rw_alias (1'b0), | |
460 | .omni_rw1c_alias (omni_rw1c_alias), | |
461 | .omni_rw1s_alias (omni_rw1s_alias), | |
462 | // synopsys translate_on | |
463 | .rst (por_l_active_high), | |
464 | .rst_val (reset_tbw_dme_p[0]), | |
465 | .csr_ld (w_ld), | |
466 | .csr_data (csrbus_wr_data[12]), | |
467 | .rw_alias (1'b0), | |
468 | .rw1c_alias (rw1c_alias), | |
469 | .rw1s_alias (rw1s_alias), | |
470 | .hw_ld (err_hw_set[12]), | |
471 | .hw_data (1'b1), | |
472 | .cp (clk), | |
473 | .q (err_csrbus_read_data[12]) | |
474 | ); | |
475 | ||
476 | // bit 13 | |
477 | csr_sw csr_sw_13 | |
478 | ( | |
479 | // synopsys translate_off | |
480 | .omni_ld (omni_ld), | |
481 | .omni_data (omni_data[13]), | |
482 | .omni_rw_alias (1'b0), | |
483 | .omni_rw1c_alias (omni_rw1c_alias), | |
484 | .omni_rw1s_alias (omni_rw1s_alias), | |
485 | // synopsys translate_on | |
486 | .rst (por_l_active_high), | |
487 | .rst_val (reset_tbw_ude_p[0]), | |
488 | .csr_ld (w_ld), | |
489 | .csr_data (csrbus_wr_data[13]), | |
490 | .rw_alias (1'b0), | |
491 | .rw1c_alias (rw1c_alias), | |
492 | .rw1s_alias (rw1s_alias), | |
493 | .hw_ld (err_hw_set[13]), | |
494 | .hw_data (1'b1), | |
495 | .cp (clk), | |
496 | .q (err_csrbus_read_data[13]) | |
497 | ); | |
498 | ||
499 | // bit 14 | |
500 | csr_sw csr_sw_14 | |
501 | ( | |
502 | // synopsys translate_off | |
503 | .omni_ld (omni_ld), | |
504 | .omni_data (omni_data[14]), | |
505 | .omni_rw_alias (1'b0), | |
506 | .omni_rw1c_alias (omni_rw1c_alias), | |
507 | .omni_rw1s_alias (omni_rw1s_alias), | |
508 | // synopsys translate_on | |
509 | .rst (por_l_active_high), | |
510 | .rst_val (reset_tbw_err_p[0]), | |
511 | .csr_ld (w_ld), | |
512 | .csr_data (csrbus_wr_data[14]), | |
513 | .rw_alias (1'b0), | |
514 | .rw1c_alias (rw1c_alias), | |
515 | .rw1s_alias (rw1s_alias), | |
516 | .hw_ld (err_hw_set[14]), | |
517 | .hw_data (1'b1), | |
518 | .cp (clk), | |
519 | .q (err_csrbus_read_data[14]) | |
520 | ); | |
521 | ||
522 | // bit 15 | |
523 | csr_sw csr_sw_15 | |
524 | ( | |
525 | // synopsys translate_off | |
526 | .omni_ld (omni_ld), | |
527 | .omni_data (omni_data[15]), | |
528 | .omni_rw_alias (1'b0), | |
529 | .omni_rw1c_alias (omni_rw1c_alias), | |
530 | .omni_rw1s_alias (omni_rw1s_alias), | |
531 | // synopsys translate_on | |
532 | .rst (por_l_active_high), | |
533 | .rst_val (reset_tbw_dpe_p[0]), | |
534 | .csr_ld (w_ld), | |
535 | .csr_data (csrbus_wr_data[15]), | |
536 | .rw_alias (1'b0), | |
537 | .rw1c_alias (rw1c_alias), | |
538 | .rw1s_alias (rw1s_alias), | |
539 | .hw_ld (err_hw_set[15]), | |
540 | .hw_data (1'b1), | |
541 | .cp (clk), | |
542 | .q (err_csrbus_read_data[15]) | |
543 | ); | |
544 | ||
545 | // bit 16 | |
546 | csr_sw csr_sw_16 | |
547 | ( | |
548 | // synopsys translate_off | |
549 | .omni_ld (omni_ld), | |
550 | .omni_data (omni_data[16]), | |
551 | .omni_rw_alias (1'b0), | |
552 | .omni_rw1c_alias (omni_rw1c_alias), | |
553 | .omni_rw1s_alias (omni_rw1s_alias), | |
554 | // synopsys translate_on | |
555 | .rst (por_l_active_high), | |
556 | .rst_val (reset_iotsbdesc_inv_p[0]), | |
557 | .csr_ld (w_ld), | |
558 | .csr_data (csrbus_wr_data[16]), | |
559 | .rw_alias (1'b0), | |
560 | .rw1c_alias (rw1c_alias), | |
561 | .rw1s_alias (rw1s_alias), | |
562 | .hw_ld (err_hw_set[16]), | |
563 | .hw_data (1'b1), | |
564 | .cp (clk), | |
565 | .q (err_csrbus_read_data[16]) | |
566 | ); | |
567 | ||
568 | // bit 17 | |
569 | csr_sw csr_sw_17 | |
570 | ( | |
571 | // synopsys translate_off | |
572 | .omni_ld (omni_ld), | |
573 | .omni_data (omni_data[17]), | |
574 | .omni_rw_alias (1'b0), | |
575 | .omni_rw1c_alias (omni_rw1c_alias), | |
576 | .omni_rw1s_alias (omni_rw1s_alias), | |
577 | // synopsys translate_on | |
578 | .rst (por_l_active_high), | |
579 | .rst_val (reset_iotsbdesc_dpe_p[0]), | |
580 | .csr_ld (w_ld), | |
581 | .csr_data (csrbus_wr_data[17]), | |
582 | .rw_alias (1'b0), | |
583 | .rw1c_alias (rw1c_alias), | |
584 | .rw1s_alias (rw1s_alias), | |
585 | .hw_ld (err_hw_set[17]), | |
586 | .hw_data (1'b1), | |
587 | .cp (clk), | |
588 | .q (err_csrbus_read_data[17]) | |
589 | ); | |
590 | ||
591 | // bit 18 | |
592 | csr_sw csr_sw_18 | |
593 | ( | |
594 | // synopsys translate_off | |
595 | .omni_ld (omni_ld), | |
596 | .omni_data (omni_data[18]), | |
597 | .omni_rw_alias (1'b0), | |
598 | .omni_rw1c_alias (omni_rw1c_alias), | |
599 | .omni_rw1s_alias (omni_rw1s_alias), | |
600 | // synopsys translate_on | |
601 | .rst (por_l_active_high), | |
602 | .rst_val (reset_sun4v_va_oor_p[0]), | |
603 | .csr_ld (w_ld), | |
604 | .csr_data (csrbus_wr_data[18]), | |
605 | .rw_alias (1'b0), | |
606 | .rw1c_alias (rw1c_alias), | |
607 | .rw1s_alias (rw1s_alias), | |
608 | .hw_ld (err_hw_set[18]), | |
609 | .hw_data (1'b1), | |
610 | .cp (clk), | |
611 | .q (err_csrbus_read_data[18]) | |
612 | ); | |
613 | ||
614 | // bit 19 | |
615 | csr_sw csr_sw_19 | |
616 | ( | |
617 | // synopsys translate_off | |
618 | .omni_ld (omni_ld), | |
619 | .omni_data (omni_data[19]), | |
620 | .omni_rw_alias (1'b0), | |
621 | .omni_rw1c_alias (omni_rw1c_alias), | |
622 | .omni_rw1s_alias (omni_rw1s_alias), | |
623 | // synopsys translate_on | |
624 | .rst (por_l_active_high), | |
625 | .rst_val (reset_sun4v_va_adj_uf_p[0]), | |
626 | .csr_ld (w_ld), | |
627 | .csr_data (csrbus_wr_data[19]), | |
628 | .rw_alias (1'b0), | |
629 | .rw1c_alias (rw1c_alias), | |
630 | .rw1s_alias (rw1s_alias), | |
631 | .hw_ld (err_hw_set[19]), | |
632 | .hw_data (1'b1), | |
633 | .cp (clk), | |
634 | .q (err_csrbus_read_data[19]) | |
635 | ); | |
636 | ||
637 | // bit 20 | |
638 | csr_sw csr_sw_20 | |
639 | ( | |
640 | // synopsys translate_off | |
641 | .omni_ld (omni_ld), | |
642 | .omni_data (omni_data[20]), | |
643 | .omni_rw_alias (1'b0), | |
644 | .omni_rw1c_alias (omni_rw1c_alias), | |
645 | .omni_rw1s_alias (omni_rw1s_alias), | |
646 | // synopsys translate_on | |
647 | .rst (por_l_active_high), | |
648 | .rst_val (reset_sun4v_key_err_p[0]), | |
649 | .csr_ld (w_ld), | |
650 | .csr_data (csrbus_wr_data[20]), | |
651 | .rw_alias (1'b0), | |
652 | .rw1c_alias (rw1c_alias), | |
653 | .rw1s_alias (rw1s_alias), | |
654 | .hw_ld (err_hw_set[20]), | |
655 | .hw_data (1'b1), | |
656 | .cp (clk), | |
657 | .q (err_csrbus_read_data[20]) | |
658 | ); | |
659 | ||
660 | assign err_csrbus_read_data[21] = 1'b0; // bit 21 | |
661 | assign err_csrbus_read_data[22] = 1'b0; // bit 22 | |
662 | assign err_csrbus_read_data[23] = 1'b0; // bit 23 | |
663 | assign err_csrbus_read_data[24] = 1'b0; // bit 24 | |
664 | assign err_csrbus_read_data[25] = 1'b0; // bit 25 | |
665 | assign err_csrbus_read_data[26] = 1'b0; // bit 26 | |
666 | assign err_csrbus_read_data[27] = 1'b0; // bit 27 | |
667 | assign err_csrbus_read_data[28] = 1'b0; // bit 28 | |
668 | assign err_csrbus_read_data[29] = 1'b0; // bit 29 | |
669 | assign err_csrbus_read_data[30] = 1'b0; // bit 30 | |
670 | assign err_csrbus_read_data[31] = 1'b0; // bit 31 | |
671 | // bit 32 | |
672 | csr_sw csr_sw_32 | |
673 | ( | |
674 | // synopsys translate_off | |
675 | .omni_ld (omni_ld), | |
676 | .omni_data (omni_data[32]), | |
677 | .omni_rw_alias (1'b0), | |
678 | .omni_rw1c_alias (omni_rw1c_alias), | |
679 | .omni_rw1s_alias (omni_rw1s_alias), | |
680 | // synopsys translate_on | |
681 | .rst (por_l_active_high), | |
682 | .rst_val (reset_byp_err_s[0]), | |
683 | .csr_ld (w_ld), | |
684 | .csr_data (csrbus_wr_data[32]), | |
685 | .rw_alias (1'b0), | |
686 | .rw1c_alias (rw1c_alias), | |
687 | .rw1s_alias (rw1s_alias), | |
688 | .hw_ld (err_hw_set[32]), | |
689 | .hw_data (1'b1), | |
690 | .cp (clk), | |
691 | .q (err_csrbus_read_data[32]) | |
692 | ); | |
693 | ||
694 | // bit 33 | |
695 | csr_sw csr_sw_33 | |
696 | ( | |
697 | // synopsys translate_off | |
698 | .omni_ld (omni_ld), | |
699 | .omni_data (omni_data[33]), | |
700 | .omni_rw_alias (1'b0), | |
701 | .omni_rw1c_alias (omni_rw1c_alias), | |
702 | .omni_rw1s_alias (omni_rw1s_alias), | |
703 | // synopsys translate_on | |
704 | .rst (por_l_active_high), | |
705 | .rst_val (reset_byp_oor_s[0]), | |
706 | .csr_ld (w_ld), | |
707 | .csr_data (csrbus_wr_data[33]), | |
708 | .rw_alias (1'b0), | |
709 | .rw1c_alias (rw1c_alias), | |
710 | .rw1s_alias (rw1s_alias), | |
711 | .hw_ld (err_hw_set[33]), | |
712 | .hw_data (1'b1), | |
713 | .cp (clk), | |
714 | .q (err_csrbus_read_data[33]) | |
715 | ); | |
716 | ||
717 | // bit 34 | |
718 | csr_sw csr_sw_34 | |
719 | ( | |
720 | // synopsys translate_off | |
721 | .omni_ld (omni_ld), | |
722 | .omni_data (omni_data[34]), | |
723 | .omni_rw_alias (1'b0), | |
724 | .omni_rw1c_alias (omni_rw1c_alias), | |
725 | .omni_rw1s_alias (omni_rw1s_alias), | |
726 | // synopsys translate_on | |
727 | .rst (por_l_active_high), | |
728 | .rst_val (reset_spare0_s[0]), | |
729 | .csr_ld (w_ld), | |
730 | .csr_data (csrbus_wr_data[34]), | |
731 | .rw_alias (1'b0), | |
732 | .rw1c_alias (rw1c_alias), | |
733 | .rw1s_alias (rw1s_alias), | |
734 | .hw_ld (err_hw_set[34]), | |
735 | .hw_data (1'b1), | |
736 | .cp (clk), | |
737 | .q (err_csrbus_read_data[34]) | |
738 | ); | |
739 | ||
740 | // bit 35 | |
741 | csr_sw csr_sw_35 | |
742 | ( | |
743 | // synopsys translate_off | |
744 | .omni_ld (omni_ld), | |
745 | .omni_data (omni_data[35]), | |
746 | .omni_rw_alias (1'b0), | |
747 | .omni_rw1c_alias (omni_rw1c_alias), | |
748 | .omni_rw1s_alias (omni_rw1s_alias), | |
749 | // synopsys translate_on | |
750 | .rst (por_l_active_high), | |
751 | .rst_val (reset_spare1_s[0]), | |
752 | .csr_ld (w_ld), | |
753 | .csr_data (csrbus_wr_data[35]), | |
754 | .rw_alias (1'b0), | |
755 | .rw1c_alias (rw1c_alias), | |
756 | .rw1s_alias (rw1s_alias), | |
757 | .hw_ld (err_hw_set[35]), | |
758 | .hw_data (1'b1), | |
759 | .cp (clk), | |
760 | .q (err_csrbus_read_data[35]) | |
761 | ); | |
762 | ||
763 | // bit 36 | |
764 | csr_sw csr_sw_36 | |
765 | ( | |
766 | // synopsys translate_off | |
767 | .omni_ld (omni_ld), | |
768 | .omni_data (omni_data[36]), | |
769 | .omni_rw_alias (1'b0), | |
770 | .omni_rw1c_alias (omni_rw1c_alias), | |
771 | .omni_rw1s_alias (omni_rw1s_alias), | |
772 | // synopsys translate_on | |
773 | .rst (por_l_active_high), | |
774 | .rst_val (reset_trn_err_s[0]), | |
775 | .csr_ld (w_ld), | |
776 | .csr_data (csrbus_wr_data[36]), | |
777 | .rw_alias (1'b0), | |
778 | .rw1c_alias (rw1c_alias), | |
779 | .rw1s_alias (rw1s_alias), | |
780 | .hw_ld (err_hw_set[36]), | |
781 | .hw_data (1'b1), | |
782 | .cp (clk), | |
783 | .q (err_csrbus_read_data[36]) | |
784 | ); | |
785 | ||
786 | // bit 37 | |
787 | csr_sw csr_sw_37 | |
788 | ( | |
789 | // synopsys translate_off | |
790 | .omni_ld (omni_ld), | |
791 | .omni_data (omni_data[37]), | |
792 | .omni_rw_alias (1'b0), | |
793 | .omni_rw1c_alias (omni_rw1c_alias), | |
794 | .omni_rw1s_alias (omni_rw1s_alias), | |
795 | // synopsys translate_on | |
796 | .rst (por_l_active_high), | |
797 | .rst_val (reset_trn_oor_s[0]), | |
798 | .csr_ld (w_ld), | |
799 | .csr_data (csrbus_wr_data[37]), | |
800 | .rw_alias (1'b0), | |
801 | .rw1c_alias (rw1c_alias), | |
802 | .rw1s_alias (rw1s_alias), | |
803 | .hw_ld (err_hw_set[37]), | |
804 | .hw_data (1'b1), | |
805 | .cp (clk), | |
806 | .q (err_csrbus_read_data[37]) | |
807 | ); | |
808 | ||
809 | // bit 38 | |
810 | csr_sw csr_sw_38 | |
811 | ( | |
812 | // synopsys translate_off | |
813 | .omni_ld (omni_ld), | |
814 | .omni_data (omni_data[38]), | |
815 | .omni_rw_alias (1'b0), | |
816 | .omni_rw1c_alias (omni_rw1c_alias), | |
817 | .omni_rw1s_alias (omni_rw1s_alias), | |
818 | // synopsys translate_on | |
819 | .rst (por_l_active_high), | |
820 | .rst_val (reset_tte_inv_s[0]), | |
821 | .csr_ld (w_ld), | |
822 | .csr_data (csrbus_wr_data[38]), | |
823 | .rw_alias (1'b0), | |
824 | .rw1c_alias (rw1c_alias), | |
825 | .rw1s_alias (rw1s_alias), | |
826 | .hw_ld (err_hw_set[38]), | |
827 | .hw_data (1'b1), | |
828 | .cp (clk), | |
829 | .q (err_csrbus_read_data[38]) | |
830 | ); | |
831 | ||
832 | // bit 39 | |
833 | csr_sw csr_sw_39 | |
834 | ( | |
835 | // synopsys translate_off | |
836 | .omni_ld (omni_ld), | |
837 | .omni_data (omni_data[39]), | |
838 | .omni_rw_alias (1'b0), | |
839 | .omni_rw1c_alias (omni_rw1c_alias), | |
840 | .omni_rw1s_alias (omni_rw1s_alias), | |
841 | // synopsys translate_on | |
842 | .rst (por_l_active_high), | |
843 | .rst_val (reset_tte_prt_s[0]), | |
844 | .csr_ld (w_ld), | |
845 | .csr_data (csrbus_wr_data[39]), | |
846 | .rw_alias (1'b0), | |
847 | .rw1c_alias (rw1c_alias), | |
848 | .rw1s_alias (rw1s_alias), | |
849 | .hw_ld (err_hw_set[39]), | |
850 | .hw_data (1'b1), | |
851 | .cp (clk), | |
852 | .q (err_csrbus_read_data[39]) | |
853 | ); | |
854 | ||
855 | // bit 40 | |
856 | csr_sw csr_sw_40 | |
857 | ( | |
858 | // synopsys translate_off | |
859 | .omni_ld (omni_ld), | |
860 | .omni_data (omni_data[40]), | |
861 | .omni_rw_alias (1'b0), | |
862 | .omni_rw1c_alias (omni_rw1c_alias), | |
863 | .omni_rw1s_alias (omni_rw1s_alias), | |
864 | // synopsys translate_on | |
865 | .rst (por_l_active_high), | |
866 | .rst_val (reset_ttc_dpe_s[0]), | |
867 | .csr_ld (w_ld), | |
868 | .csr_data (csrbus_wr_data[40]), | |
869 | .rw_alias (1'b0), | |
870 | .rw1c_alias (rw1c_alias), | |
871 | .rw1s_alias (rw1s_alias), | |
872 | .hw_ld (err_hw_set[40]), | |
873 | .hw_data (1'b1), | |
874 | .cp (clk), | |
875 | .q (err_csrbus_read_data[40]) | |
876 | ); | |
877 | ||
878 | // bit 41 | |
879 | csr_sw csr_sw_41 | |
880 | ( | |
881 | // synopsys translate_off | |
882 | .omni_ld (omni_ld), | |
883 | .omni_data (omni_data[41]), | |
884 | .omni_rw_alias (1'b0), | |
885 | .omni_rw1c_alias (omni_rw1c_alias), | |
886 | .omni_rw1s_alias (omni_rw1s_alias), | |
887 | // synopsys translate_on | |
888 | .rst (por_l_active_high), | |
889 | .rst_val (reset_ttc_cae_s[0]), | |
890 | .csr_ld (w_ld), | |
891 | .csr_data (csrbus_wr_data[41]), | |
892 | .rw_alias (1'b0), | |
893 | .rw1c_alias (rw1c_alias), | |
894 | .rw1s_alias (rw1s_alias), | |
895 | .hw_ld (err_hw_set[41]), | |
896 | .hw_data (1'b1), | |
897 | .cp (clk), | |
898 | .q (err_csrbus_read_data[41]) | |
899 | ); | |
900 | ||
901 | // bit 42 | |
902 | csr_sw csr_sw_42 | |
903 | ( | |
904 | // synopsys translate_off | |
905 | .omni_ld (omni_ld), | |
906 | .omni_data (omni_data[42]), | |
907 | .omni_rw_alias (1'b0), | |
908 | .omni_rw1c_alias (omni_rw1c_alias), | |
909 | .omni_rw1s_alias (omni_rw1s_alias), | |
910 | // synopsys translate_on | |
911 | .rst (por_l_active_high), | |
912 | .rst_val (reset_spare2_s[0]), | |
913 | .csr_ld (w_ld), | |
914 | .csr_data (csrbus_wr_data[42]), | |
915 | .rw_alias (1'b0), | |
916 | .rw1c_alias (rw1c_alias), | |
917 | .rw1s_alias (rw1s_alias), | |
918 | .hw_ld (err_hw_set[42]), | |
919 | .hw_data (1'b1), | |
920 | .cp (clk), | |
921 | .q (err_csrbus_read_data[42]) | |
922 | ); | |
923 | ||
924 | // bit 43 | |
925 | csr_sw csr_sw_43 | |
926 | ( | |
927 | // synopsys translate_off | |
928 | .omni_ld (omni_ld), | |
929 | .omni_data (omni_data[43]), | |
930 | .omni_rw_alias (1'b0), | |
931 | .omni_rw1c_alias (omni_rw1c_alias), | |
932 | .omni_rw1s_alias (omni_rw1s_alias), | |
933 | // synopsys translate_on | |
934 | .rst (por_l_active_high), | |
935 | .rst_val (reset_spare3_s[0]), | |
936 | .csr_ld (w_ld), | |
937 | .csr_data (csrbus_wr_data[43]), | |
938 | .rw_alias (1'b0), | |
939 | .rw1c_alias (rw1c_alias), | |
940 | .rw1s_alias (rw1s_alias), | |
941 | .hw_ld (err_hw_set[43]), | |
942 | .hw_data (1'b1), | |
943 | .cp (clk), | |
944 | .q (err_csrbus_read_data[43]) | |
945 | ); | |
946 | ||
947 | // bit 44 | |
948 | csr_sw csr_sw_44 | |
949 | ( | |
950 | // synopsys translate_off | |
951 | .omni_ld (omni_ld), | |
952 | .omni_data (omni_data[44]), | |
953 | .omni_rw_alias (1'b0), | |
954 | .omni_rw1c_alias (omni_rw1c_alias), | |
955 | .omni_rw1s_alias (omni_rw1s_alias), | |
956 | // synopsys translate_on | |
957 | .rst (por_l_active_high), | |
958 | .rst_val (reset_tbw_dme_s[0]), | |
959 | .csr_ld (w_ld), | |
960 | .csr_data (csrbus_wr_data[44]), | |
961 | .rw_alias (1'b0), | |
962 | .rw1c_alias (rw1c_alias), | |
963 | .rw1s_alias (rw1s_alias), | |
964 | .hw_ld (err_hw_set[44]), | |
965 | .hw_data (1'b1), | |
966 | .cp (clk), | |
967 | .q (err_csrbus_read_data[44]) | |
968 | ); | |
969 | ||
970 | // bit 45 | |
971 | csr_sw csr_sw_45 | |
972 | ( | |
973 | // synopsys translate_off | |
974 | .omni_ld (omni_ld), | |
975 | .omni_data (omni_data[45]), | |
976 | .omni_rw_alias (1'b0), | |
977 | .omni_rw1c_alias (omni_rw1c_alias), | |
978 | .omni_rw1s_alias (omni_rw1s_alias), | |
979 | // synopsys translate_on | |
980 | .rst (por_l_active_high), | |
981 | .rst_val (reset_tbw_ude_s[0]), | |
982 | .csr_ld (w_ld), | |
983 | .csr_data (csrbus_wr_data[45]), | |
984 | .rw_alias (1'b0), | |
985 | .rw1c_alias (rw1c_alias), | |
986 | .rw1s_alias (rw1s_alias), | |
987 | .hw_ld (err_hw_set[45]), | |
988 | .hw_data (1'b1), | |
989 | .cp (clk), | |
990 | .q (err_csrbus_read_data[45]) | |
991 | ); | |
992 | ||
993 | // bit 46 | |
994 | csr_sw csr_sw_46 | |
995 | ( | |
996 | // synopsys translate_off | |
997 | .omni_ld (omni_ld), | |
998 | .omni_data (omni_data[46]), | |
999 | .omni_rw_alias (1'b0), | |
1000 | .omni_rw1c_alias (omni_rw1c_alias), | |
1001 | .omni_rw1s_alias (omni_rw1s_alias), | |
1002 | // synopsys translate_on | |
1003 | .rst (por_l_active_high), | |
1004 | .rst_val (reset_tbw_err_s[0]), | |
1005 | .csr_ld (w_ld), | |
1006 | .csr_data (csrbus_wr_data[46]), | |
1007 | .rw_alias (1'b0), | |
1008 | .rw1c_alias (rw1c_alias), | |
1009 | .rw1s_alias (rw1s_alias), | |
1010 | .hw_ld (err_hw_set[46]), | |
1011 | .hw_data (1'b1), | |
1012 | .cp (clk), | |
1013 | .q (err_csrbus_read_data[46]) | |
1014 | ); | |
1015 | ||
1016 | // bit 47 | |
1017 | csr_sw csr_sw_47 | |
1018 | ( | |
1019 | // synopsys translate_off | |
1020 | .omni_ld (omni_ld), | |
1021 | .omni_data (omni_data[47]), | |
1022 | .omni_rw_alias (1'b0), | |
1023 | .omni_rw1c_alias (omni_rw1c_alias), | |
1024 | .omni_rw1s_alias (omni_rw1s_alias), | |
1025 | // synopsys translate_on | |
1026 | .rst (por_l_active_high), | |
1027 | .rst_val (reset_tbw_dpe_s[0]), | |
1028 | .csr_ld (w_ld), | |
1029 | .csr_data (csrbus_wr_data[47]), | |
1030 | .rw_alias (1'b0), | |
1031 | .rw1c_alias (rw1c_alias), | |
1032 | .rw1s_alias (rw1s_alias), | |
1033 | .hw_ld (err_hw_set[47]), | |
1034 | .hw_data (1'b1), | |
1035 | .cp (clk), | |
1036 | .q (err_csrbus_read_data[47]) | |
1037 | ); | |
1038 | ||
1039 | // bit 48 | |
1040 | csr_sw csr_sw_48 | |
1041 | ( | |
1042 | // synopsys translate_off | |
1043 | .omni_ld (omni_ld), | |
1044 | .omni_data (omni_data[48]), | |
1045 | .omni_rw_alias (1'b0), | |
1046 | .omni_rw1c_alias (omni_rw1c_alias), | |
1047 | .omni_rw1s_alias (omni_rw1s_alias), | |
1048 | // synopsys translate_on | |
1049 | .rst (por_l_active_high), | |
1050 | .rst_val (reset_iotsbdesc_inv_s[0]), | |
1051 | .csr_ld (w_ld), | |
1052 | .csr_data (csrbus_wr_data[48]), | |
1053 | .rw_alias (1'b0), | |
1054 | .rw1c_alias (rw1c_alias), | |
1055 | .rw1s_alias (rw1s_alias), | |
1056 | .hw_ld (err_hw_set[48]), | |
1057 | .hw_data (1'b1), | |
1058 | .cp (clk), | |
1059 | .q (err_csrbus_read_data[48]) | |
1060 | ); | |
1061 | ||
1062 | // bit 49 | |
1063 | csr_sw csr_sw_49 | |
1064 | ( | |
1065 | // synopsys translate_off | |
1066 | .omni_ld (omni_ld), | |
1067 | .omni_data (omni_data[49]), | |
1068 | .omni_rw_alias (1'b0), | |
1069 | .omni_rw1c_alias (omni_rw1c_alias), | |
1070 | .omni_rw1s_alias (omni_rw1s_alias), | |
1071 | // synopsys translate_on | |
1072 | .rst (por_l_active_high), | |
1073 | .rst_val (reset_iotsbdesc_dpe_s[0]), | |
1074 | .csr_ld (w_ld), | |
1075 | .csr_data (csrbus_wr_data[49]), | |
1076 | .rw_alias (1'b0), | |
1077 | .rw1c_alias (rw1c_alias), | |
1078 | .rw1s_alias (rw1s_alias), | |
1079 | .hw_ld (err_hw_set[49]), | |
1080 | .hw_data (1'b1), | |
1081 | .cp (clk), | |
1082 | .q (err_csrbus_read_data[49]) | |
1083 | ); | |
1084 | ||
1085 | // bit 50 | |
1086 | csr_sw csr_sw_50 | |
1087 | ( | |
1088 | // synopsys translate_off | |
1089 | .omni_ld (omni_ld), | |
1090 | .omni_data (omni_data[50]), | |
1091 | .omni_rw_alias (1'b0), | |
1092 | .omni_rw1c_alias (omni_rw1c_alias), | |
1093 | .omni_rw1s_alias (omni_rw1s_alias), | |
1094 | // synopsys translate_on | |
1095 | .rst (por_l_active_high), | |
1096 | .rst_val (reset_sun4v_va_oor_s[0]), | |
1097 | .csr_ld (w_ld), | |
1098 | .csr_data (csrbus_wr_data[50]), | |
1099 | .rw_alias (1'b0), | |
1100 | .rw1c_alias (rw1c_alias), | |
1101 | .rw1s_alias (rw1s_alias), | |
1102 | .hw_ld (err_hw_set[50]), | |
1103 | .hw_data (1'b1), | |
1104 | .cp (clk), | |
1105 | .q (err_csrbus_read_data[50]) | |
1106 | ); | |
1107 | ||
1108 | // bit 51 | |
1109 | csr_sw csr_sw_51 | |
1110 | ( | |
1111 | // synopsys translate_off | |
1112 | .omni_ld (omni_ld), | |
1113 | .omni_data (omni_data[51]), | |
1114 | .omni_rw_alias (1'b0), | |
1115 | .omni_rw1c_alias (omni_rw1c_alias), | |
1116 | .omni_rw1s_alias (omni_rw1s_alias), | |
1117 | // synopsys translate_on | |
1118 | .rst (por_l_active_high), | |
1119 | .rst_val (reset_sun4v_va_adj_uf_s[0]), | |
1120 | .csr_ld (w_ld), | |
1121 | .csr_data (csrbus_wr_data[51]), | |
1122 | .rw_alias (1'b0), | |
1123 | .rw1c_alias (rw1c_alias), | |
1124 | .rw1s_alias (rw1s_alias), | |
1125 | .hw_ld (err_hw_set[51]), | |
1126 | .hw_data (1'b1), | |
1127 | .cp (clk), | |
1128 | .q (err_csrbus_read_data[51]) | |
1129 | ); | |
1130 | ||
1131 | // bit 52 | |
1132 | csr_sw csr_sw_52 | |
1133 | ( | |
1134 | // synopsys translate_off | |
1135 | .omni_ld (omni_ld), | |
1136 | .omni_data (omni_data[52]), | |
1137 | .omni_rw_alias (1'b0), | |
1138 | .omni_rw1c_alias (omni_rw1c_alias), | |
1139 | .omni_rw1s_alias (omni_rw1s_alias), | |
1140 | // synopsys translate_on | |
1141 | .rst (por_l_active_high), | |
1142 | .rst_val (reset_sun4v_key_err_s[0]), | |
1143 | .csr_ld (w_ld), | |
1144 | .csr_data (csrbus_wr_data[52]), | |
1145 | .rw_alias (1'b0), | |
1146 | .rw1c_alias (rw1c_alias), | |
1147 | .rw1s_alias (rw1s_alias), | |
1148 | .hw_ld (err_hw_set[52]), | |
1149 | .hw_data (1'b1), | |
1150 | .cp (clk), | |
1151 | .q (err_csrbus_read_data[52]) | |
1152 | ); | |
1153 | ||
1154 | assign err_csrbus_read_data[53] = 1'b0; // bit 53 | |
1155 | assign err_csrbus_read_data[54] = 1'b0; // bit 54 | |
1156 | assign err_csrbus_read_data[55] = 1'b0; // bit 55 | |
1157 | assign err_csrbus_read_data[56] = 1'b0; // bit 56 | |
1158 | assign err_csrbus_read_data[57] = 1'b0; // bit 57 | |
1159 | assign err_csrbus_read_data[58] = 1'b0; // bit 58 | |
1160 | assign err_csrbus_read_data[59] = 1'b0; // bit 59 | |
1161 | assign err_csrbus_read_data[60] = 1'b0; // bit 60 | |
1162 | assign err_csrbus_read_data[61] = 1'b0; // bit 61 | |
1163 | assign err_csrbus_read_data[62] = 1'b0; // bit 62 | |
1164 | assign err_csrbus_read_data[63] = 1'b0; // bit 63 | |
1165 | ||
1166 | endmodule // dmu_mmu_csr_err_entry |