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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_flta.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_csr_flta | |
36 | ( | |
37 | clk, | |
38 | por_l, | |
39 | flta_w_ld, | |
40 | csrbus_wr_data, | |
41 | flta_csrbus_read_data, | |
42 | flta_va_hw_ld, | |
43 | flta_va_hw_write | |
44 | ); | |
45 | ||
46 | //==================================================================== | |
47 | // Polarity declarations | |
48 | //==================================================================== | |
49 | input clk; // Clock | |
50 | input por_l; // Reset signal | |
51 | input flta_w_ld; // SW load bus | |
52 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
53 | output [`FIRE_DLC_MMU_CSR_FLTA_WIDTH-1:0] flta_csrbus_read_data; // SW read | |
54 | // data | |
55 | input flta_va_hw_ld; // Hardware load enable for flta_va. When set, <hw write | |
56 | // signal> will be loaded into flta. | |
57 | input [`FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC] flta_va_hw_write; // data bus for hw | |
58 | // loading of | |
59 | // flta_va. | |
60 | ||
61 | //==================================================================== | |
62 | // Type declarations | |
63 | //==================================================================== | |
64 | wire clk; // Clock | |
65 | wire por_l; // Reset signal | |
66 | wire flta_w_ld; // SW load bus | |
67 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
68 | wire [`FIRE_DLC_MMU_CSR_FLTA_WIDTH-1:0] flta_csrbus_read_data; // SW read data | |
69 | wire flta_va_hw_ld; // Hardware load enable for flta_va. When set, <hw write | |
70 | // signal> will be loaded into flta. | |
71 | wire [`FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC] flta_va_hw_write; // data bus for hw | |
72 | // loading of | |
73 | // flta_va. | |
74 | ||
75 | //==================================================================== | |
76 | // Logic | |
77 | //==================================================================== | |
78 | ||
79 | // synopsys translate_off | |
80 | // verilint 123 off | |
81 | // verilint 498 off | |
82 | reg omni_ld; | |
83 | reg [`FIRE_DLC_MMU_CSR_FLTA_WIDTH-1:0] omni_data; | |
84 | ||
85 | // vlint flag_unsynthesizable_initial off | |
86 | initial | |
87 | begin | |
88 | omni_ld = 1'b0; | |
89 | omni_data = `FIRE_DLC_MMU_CSR_FLTA_WIDTH'b0; | |
90 | end// vlint flag_unsynthesizable_initial on | |
91 | ||
92 | // verilint 123 on | |
93 | // verilint 498 on | |
94 | // synopsys translate_on | |
95 | ||
96 | //----- Hardware Data Out Mux Assignments | |
97 | ||
98 | //==================================================================== | |
99 | // Instantiation of entries | |
100 | //==================================================================== | |
101 | ||
102 | //----- Entry 0 | |
103 | dmu_mmu_csr_flta_entry flta_0 | |
104 | ( | |
105 | // synopsys translate_off | |
106 | .omni_ld (omni_ld), | |
107 | .omni_data (omni_data), | |
108 | // synopsys translate_on | |
109 | .clk (clk), | |
110 | .por_l (por_l), | |
111 | .w_ld (flta_w_ld), | |
112 | .csrbus_wr_data (csrbus_wr_data), | |
113 | .flta_csrbus_read_data (flta_csrbus_read_data), | |
114 | .flta_va_hw_ld (flta_va_hw_ld), | |
115 | .flta_va_hw_write (flta_va_hw_write) | |
116 | ); | |
117 | ||
118 | endmodule // dmu_mmu_csr_flta |