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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_int_en_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_mmu_csr_int_en_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | int_en_csrbus_read_data | |
46 | ); | |
47 | ||
48 | //==================================================================== | |
49 | // Polarity declarations | |
50 | //==================================================================== | |
51 | // synopsys translate_off | |
52 | input omni_ld; // Omni load | |
53 | // vlint flag_input_port_not_connected off | |
54 | input [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH - 1:0] omni_data; // Omni write data | |
55 | // synopsys translate_on | |
56 | // vlint flag_input_port_not_connected on | |
57 | input clk; // Clock signal | |
58 | input rst_l; // Reset signal | |
59 | input w_ld; // SW load | |
60 | // vlint flag_input_port_not_connected off | |
61 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
62 | // vlint flag_input_port_not_connected on | |
63 | output [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH-1:0] int_en_csrbus_read_data; | |
64 | // SW read data | |
65 | ||
66 | //==================================================================== | |
67 | // Type declarations | |
68 | //==================================================================== | |
69 | // synopsys translate_off | |
70 | wire omni_ld; // Omni load | |
71 | // vlint flag_dangling_net_within_module off | |
72 | // vlint flag_net_has_no_load off | |
73 | wire [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH - 1:0] omni_data; // Omni write data | |
74 | // synopsys translate_on | |
75 | // vlint flag_dangling_net_within_module on | |
76 | // vlint flag_net_has_no_load on | |
77 | wire clk; // Clock signal | |
78 | wire rst_l; // Reset signal | |
79 | wire w_ld; // SW load | |
80 | // vlint flag_dangling_net_within_module off | |
81 | // vlint flag_net_has_no_load off | |
82 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
83 | // vlint flag_dangling_net_within_module on | |
84 | // vlint flag_net_has_no_load on | |
85 | wire [`FIRE_DLC_MMU_CSR_INT_EN_WIDTH-1:0] int_en_csrbus_read_data; | |
86 | // SW read data | |
87 | ||
88 | //==================================================================== | |
89 | // Logic | |
90 | //==================================================================== | |
91 | ||
92 | //----- Reset values | |
93 | // verilint 531 off | |
94 | wire [20:0] reset_en_s = 21'h0; | |
95 | wire [20:0] reset_en_p = 21'h0; | |
96 | // verilint 531 on | |
97 | ||
98 | //----- Active high reset wires | |
99 | wire rst_l_active_high = ~rst_l; | |
100 | ||
101 | //==================================================== | |
102 | // Instantiation of flops | |
103 | //==================================================== | |
104 | ||
105 | // bit 0 | |
106 | csr_sw csr_sw_0 | |
107 | ( | |
108 | // synopsys translate_off | |
109 | .omni_ld (omni_ld), | |
110 | .omni_data (omni_data[0]), | |
111 | .omni_rw_alias (1'b1), | |
112 | .omni_rw1c_alias (1'b0), | |
113 | .omni_rw1s_alias (1'b0), | |
114 | // synopsys translate_on | |
115 | .rst (rst_l_active_high), | |
116 | .rst_val (reset_en_p[0]), | |
117 | .csr_ld (w_ld), | |
118 | .csr_data (csrbus_wr_data[0]), | |
119 | .rw_alias (1'b1), | |
120 | .rw1c_alias (1'b0), | |
121 | .rw1s_alias (1'b0), | |
122 | .hw_ld (1'b0), | |
123 | .hw_data (1'b0), | |
124 | .cp (clk), | |
125 | .q (int_en_csrbus_read_data[0]) | |
126 | ); | |
127 | ||
128 | // bit 1 | |
129 | csr_sw csr_sw_1 | |
130 | ( | |
131 | // synopsys translate_off | |
132 | .omni_ld (omni_ld), | |
133 | .omni_data (omni_data[1]), | |
134 | .omni_rw_alias (1'b1), | |
135 | .omni_rw1c_alias (1'b0), | |
136 | .omni_rw1s_alias (1'b0), | |
137 | // synopsys translate_on | |
138 | .rst (rst_l_active_high), | |
139 | .rst_val (reset_en_p[1]), | |
140 | .csr_ld (w_ld), | |
141 | .csr_data (csrbus_wr_data[1]), | |
142 | .rw_alias (1'b1), | |
143 | .rw1c_alias (1'b0), | |
144 | .rw1s_alias (1'b0), | |
145 | .hw_ld (1'b0), | |
146 | .hw_data (1'b0), | |
147 | .cp (clk), | |
148 | .q (int_en_csrbus_read_data[1]) | |
149 | ); | |
150 | ||
151 | // bit 2 | |
152 | csr_sw csr_sw_2 | |
153 | ( | |
154 | // synopsys translate_off | |
155 | .omni_ld (omni_ld), | |
156 | .omni_data (omni_data[2]), | |
157 | .omni_rw_alias (1'b1), | |
158 | .omni_rw1c_alias (1'b0), | |
159 | .omni_rw1s_alias (1'b0), | |
160 | // synopsys translate_on | |
161 | .rst (rst_l_active_high), | |
162 | .rst_val (reset_en_p[2]), | |
163 | .csr_ld (w_ld), | |
164 | .csr_data (csrbus_wr_data[2]), | |
165 | .rw_alias (1'b1), | |
166 | .rw1c_alias (1'b0), | |
167 | .rw1s_alias (1'b0), | |
168 | .hw_ld (1'b0), | |
169 | .hw_data (1'b0), | |
170 | .cp (clk), | |
171 | .q (int_en_csrbus_read_data[2]) | |
172 | ); | |
173 | ||
174 | // bit 3 | |
175 | csr_sw csr_sw_3 | |
176 | ( | |
177 | // synopsys translate_off | |
178 | .omni_ld (omni_ld), | |
179 | .omni_data (omni_data[3]), | |
180 | .omni_rw_alias (1'b1), | |
181 | .omni_rw1c_alias (1'b0), | |
182 | .omni_rw1s_alias (1'b0), | |
183 | // synopsys translate_on | |
184 | .rst (rst_l_active_high), | |
185 | .rst_val (reset_en_p[3]), | |
186 | .csr_ld (w_ld), | |
187 | .csr_data (csrbus_wr_data[3]), | |
188 | .rw_alias (1'b1), | |
189 | .rw1c_alias (1'b0), | |
190 | .rw1s_alias (1'b0), | |
191 | .hw_ld (1'b0), | |
192 | .hw_data (1'b0), | |
193 | .cp (clk), | |
194 | .q (int_en_csrbus_read_data[3]) | |
195 | ); | |
196 | ||
197 | // bit 4 | |
198 | csr_sw csr_sw_4 | |
199 | ( | |
200 | // synopsys translate_off | |
201 | .omni_ld (omni_ld), | |
202 | .omni_data (omni_data[4]), | |
203 | .omni_rw_alias (1'b1), | |
204 | .omni_rw1c_alias (1'b0), | |
205 | .omni_rw1s_alias (1'b0), | |
206 | // synopsys translate_on | |
207 | .rst (rst_l_active_high), | |
208 | .rst_val (reset_en_p[4]), | |
209 | .csr_ld (w_ld), | |
210 | .csr_data (csrbus_wr_data[4]), | |
211 | .rw_alias (1'b1), | |
212 | .rw1c_alias (1'b0), | |
213 | .rw1s_alias (1'b0), | |
214 | .hw_ld (1'b0), | |
215 | .hw_data (1'b0), | |
216 | .cp (clk), | |
217 | .q (int_en_csrbus_read_data[4]) | |
218 | ); | |
219 | ||
220 | // bit 5 | |
221 | csr_sw csr_sw_5 | |
222 | ( | |
223 | // synopsys translate_off | |
224 | .omni_ld (omni_ld), | |
225 | .omni_data (omni_data[5]), | |
226 | .omni_rw_alias (1'b1), | |
227 | .omni_rw1c_alias (1'b0), | |
228 | .omni_rw1s_alias (1'b0), | |
229 | // synopsys translate_on | |
230 | .rst (rst_l_active_high), | |
231 | .rst_val (reset_en_p[5]), | |
232 | .csr_ld (w_ld), | |
233 | .csr_data (csrbus_wr_data[5]), | |
234 | .rw_alias (1'b1), | |
235 | .rw1c_alias (1'b0), | |
236 | .rw1s_alias (1'b0), | |
237 | .hw_ld (1'b0), | |
238 | .hw_data (1'b0), | |
239 | .cp (clk), | |
240 | .q (int_en_csrbus_read_data[5]) | |
241 | ); | |
242 | ||
243 | // bit 6 | |
244 | csr_sw csr_sw_6 | |
245 | ( | |
246 | // synopsys translate_off | |
247 | .omni_ld (omni_ld), | |
248 | .omni_data (omni_data[6]), | |
249 | .omni_rw_alias (1'b1), | |
250 | .omni_rw1c_alias (1'b0), | |
251 | .omni_rw1s_alias (1'b0), | |
252 | // synopsys translate_on | |
253 | .rst (rst_l_active_high), | |
254 | .rst_val (reset_en_p[6]), | |
255 | .csr_ld (w_ld), | |
256 | .csr_data (csrbus_wr_data[6]), | |
257 | .rw_alias (1'b1), | |
258 | .rw1c_alias (1'b0), | |
259 | .rw1s_alias (1'b0), | |
260 | .hw_ld (1'b0), | |
261 | .hw_data (1'b0), | |
262 | .cp (clk), | |
263 | .q (int_en_csrbus_read_data[6]) | |
264 | ); | |
265 | ||
266 | // bit 7 | |
267 | csr_sw csr_sw_7 | |
268 | ( | |
269 | // synopsys translate_off | |
270 | .omni_ld (omni_ld), | |
271 | .omni_data (omni_data[7]), | |
272 | .omni_rw_alias (1'b1), | |
273 | .omni_rw1c_alias (1'b0), | |
274 | .omni_rw1s_alias (1'b0), | |
275 | // synopsys translate_on | |
276 | .rst (rst_l_active_high), | |
277 | .rst_val (reset_en_p[7]), | |
278 | .csr_ld (w_ld), | |
279 | .csr_data (csrbus_wr_data[7]), | |
280 | .rw_alias (1'b1), | |
281 | .rw1c_alias (1'b0), | |
282 | .rw1s_alias (1'b0), | |
283 | .hw_ld (1'b0), | |
284 | .hw_data (1'b0), | |
285 | .cp (clk), | |
286 | .q (int_en_csrbus_read_data[7]) | |
287 | ); | |
288 | ||
289 | // bit 8 | |
290 | csr_sw csr_sw_8 | |
291 | ( | |
292 | // synopsys translate_off | |
293 | .omni_ld (omni_ld), | |
294 | .omni_data (omni_data[8]), | |
295 | .omni_rw_alias (1'b1), | |
296 | .omni_rw1c_alias (1'b0), | |
297 | .omni_rw1s_alias (1'b0), | |
298 | // synopsys translate_on | |
299 | .rst (rst_l_active_high), | |
300 | .rst_val (reset_en_p[8]), | |
301 | .csr_ld (w_ld), | |
302 | .csr_data (csrbus_wr_data[8]), | |
303 | .rw_alias (1'b1), | |
304 | .rw1c_alias (1'b0), | |
305 | .rw1s_alias (1'b0), | |
306 | .hw_ld (1'b0), | |
307 | .hw_data (1'b0), | |
308 | .cp (clk), | |
309 | .q (int_en_csrbus_read_data[8]) | |
310 | ); | |
311 | ||
312 | // bit 9 | |
313 | csr_sw csr_sw_9 | |
314 | ( | |
315 | // synopsys translate_off | |
316 | .omni_ld (omni_ld), | |
317 | .omni_data (omni_data[9]), | |
318 | .omni_rw_alias (1'b1), | |
319 | .omni_rw1c_alias (1'b0), | |
320 | .omni_rw1s_alias (1'b0), | |
321 | // synopsys translate_on | |
322 | .rst (rst_l_active_high), | |
323 | .rst_val (reset_en_p[9]), | |
324 | .csr_ld (w_ld), | |
325 | .csr_data (csrbus_wr_data[9]), | |
326 | .rw_alias (1'b1), | |
327 | .rw1c_alias (1'b0), | |
328 | .rw1s_alias (1'b0), | |
329 | .hw_ld (1'b0), | |
330 | .hw_data (1'b0), | |
331 | .cp (clk), | |
332 | .q (int_en_csrbus_read_data[9]) | |
333 | ); | |
334 | ||
335 | // bit 10 | |
336 | csr_sw csr_sw_10 | |
337 | ( | |
338 | // synopsys translate_off | |
339 | .omni_ld (omni_ld), | |
340 | .omni_data (omni_data[10]), | |
341 | .omni_rw_alias (1'b1), | |
342 | .omni_rw1c_alias (1'b0), | |
343 | .omni_rw1s_alias (1'b0), | |
344 | // synopsys translate_on | |
345 | .rst (rst_l_active_high), | |
346 | .rst_val (reset_en_p[10]), | |
347 | .csr_ld (w_ld), | |
348 | .csr_data (csrbus_wr_data[10]), | |
349 | .rw_alias (1'b1), | |
350 | .rw1c_alias (1'b0), | |
351 | .rw1s_alias (1'b0), | |
352 | .hw_ld (1'b0), | |
353 | .hw_data (1'b0), | |
354 | .cp (clk), | |
355 | .q (int_en_csrbus_read_data[10]) | |
356 | ); | |
357 | ||
358 | // bit 11 | |
359 | csr_sw csr_sw_11 | |
360 | ( | |
361 | // synopsys translate_off | |
362 | .omni_ld (omni_ld), | |
363 | .omni_data (omni_data[11]), | |
364 | .omni_rw_alias (1'b1), | |
365 | .omni_rw1c_alias (1'b0), | |
366 | .omni_rw1s_alias (1'b0), | |
367 | // synopsys translate_on | |
368 | .rst (rst_l_active_high), | |
369 | .rst_val (reset_en_p[11]), | |
370 | .csr_ld (w_ld), | |
371 | .csr_data (csrbus_wr_data[11]), | |
372 | .rw_alias (1'b1), | |
373 | .rw1c_alias (1'b0), | |
374 | .rw1s_alias (1'b0), | |
375 | .hw_ld (1'b0), | |
376 | .hw_data (1'b0), | |
377 | .cp (clk), | |
378 | .q (int_en_csrbus_read_data[11]) | |
379 | ); | |
380 | ||
381 | // bit 12 | |
382 | csr_sw csr_sw_12 | |
383 | ( | |
384 | // synopsys translate_off | |
385 | .omni_ld (omni_ld), | |
386 | .omni_data (omni_data[12]), | |
387 | .omni_rw_alias (1'b1), | |
388 | .omni_rw1c_alias (1'b0), | |
389 | .omni_rw1s_alias (1'b0), | |
390 | // synopsys translate_on | |
391 | .rst (rst_l_active_high), | |
392 | .rst_val (reset_en_p[12]), | |
393 | .csr_ld (w_ld), | |
394 | .csr_data (csrbus_wr_data[12]), | |
395 | .rw_alias (1'b1), | |
396 | .rw1c_alias (1'b0), | |
397 | .rw1s_alias (1'b0), | |
398 | .hw_ld (1'b0), | |
399 | .hw_data (1'b0), | |
400 | .cp (clk), | |
401 | .q (int_en_csrbus_read_data[12]) | |
402 | ); | |
403 | ||
404 | // bit 13 | |
405 | csr_sw csr_sw_13 | |
406 | ( | |
407 | // synopsys translate_off | |
408 | .omni_ld (omni_ld), | |
409 | .omni_data (omni_data[13]), | |
410 | .omni_rw_alias (1'b1), | |
411 | .omni_rw1c_alias (1'b0), | |
412 | .omni_rw1s_alias (1'b0), | |
413 | // synopsys translate_on | |
414 | .rst (rst_l_active_high), | |
415 | .rst_val (reset_en_p[13]), | |
416 | .csr_ld (w_ld), | |
417 | .csr_data (csrbus_wr_data[13]), | |
418 | .rw_alias (1'b1), | |
419 | .rw1c_alias (1'b0), | |
420 | .rw1s_alias (1'b0), | |
421 | .hw_ld (1'b0), | |
422 | .hw_data (1'b0), | |
423 | .cp (clk), | |
424 | .q (int_en_csrbus_read_data[13]) | |
425 | ); | |
426 | ||
427 | // bit 14 | |
428 | csr_sw csr_sw_14 | |
429 | ( | |
430 | // synopsys translate_off | |
431 | .omni_ld (omni_ld), | |
432 | .omni_data (omni_data[14]), | |
433 | .omni_rw_alias (1'b1), | |
434 | .omni_rw1c_alias (1'b0), | |
435 | .omni_rw1s_alias (1'b0), | |
436 | // synopsys translate_on | |
437 | .rst (rst_l_active_high), | |
438 | .rst_val (reset_en_p[14]), | |
439 | .csr_ld (w_ld), | |
440 | .csr_data (csrbus_wr_data[14]), | |
441 | .rw_alias (1'b1), | |
442 | .rw1c_alias (1'b0), | |
443 | .rw1s_alias (1'b0), | |
444 | .hw_ld (1'b0), | |
445 | .hw_data (1'b0), | |
446 | .cp (clk), | |
447 | .q (int_en_csrbus_read_data[14]) | |
448 | ); | |
449 | ||
450 | // bit 15 | |
451 | csr_sw csr_sw_15 | |
452 | ( | |
453 | // synopsys translate_off | |
454 | .omni_ld (omni_ld), | |
455 | .omni_data (omni_data[15]), | |
456 | .omni_rw_alias (1'b1), | |
457 | .omni_rw1c_alias (1'b0), | |
458 | .omni_rw1s_alias (1'b0), | |
459 | // synopsys translate_on | |
460 | .rst (rst_l_active_high), | |
461 | .rst_val (reset_en_p[15]), | |
462 | .csr_ld (w_ld), | |
463 | .csr_data (csrbus_wr_data[15]), | |
464 | .rw_alias (1'b1), | |
465 | .rw1c_alias (1'b0), | |
466 | .rw1s_alias (1'b0), | |
467 | .hw_ld (1'b0), | |
468 | .hw_data (1'b0), | |
469 | .cp (clk), | |
470 | .q (int_en_csrbus_read_data[15]) | |
471 | ); | |
472 | ||
473 | // bit 16 | |
474 | csr_sw csr_sw_16 | |
475 | ( | |
476 | // synopsys translate_off | |
477 | .omni_ld (omni_ld), | |
478 | .omni_data (omni_data[16]), | |
479 | .omni_rw_alias (1'b1), | |
480 | .omni_rw1c_alias (1'b0), | |
481 | .omni_rw1s_alias (1'b0), | |
482 | // synopsys translate_on | |
483 | .rst (rst_l_active_high), | |
484 | .rst_val (reset_en_p[16]), | |
485 | .csr_ld (w_ld), | |
486 | .csr_data (csrbus_wr_data[16]), | |
487 | .rw_alias (1'b1), | |
488 | .rw1c_alias (1'b0), | |
489 | .rw1s_alias (1'b0), | |
490 | .hw_ld (1'b0), | |
491 | .hw_data (1'b0), | |
492 | .cp (clk), | |
493 | .q (int_en_csrbus_read_data[16]) | |
494 | ); | |
495 | ||
496 | // bit 17 | |
497 | csr_sw csr_sw_17 | |
498 | ( | |
499 | // synopsys translate_off | |
500 | .omni_ld (omni_ld), | |
501 | .omni_data (omni_data[17]), | |
502 | .omni_rw_alias (1'b1), | |
503 | .omni_rw1c_alias (1'b0), | |
504 | .omni_rw1s_alias (1'b0), | |
505 | // synopsys translate_on | |
506 | .rst (rst_l_active_high), | |
507 | .rst_val (reset_en_p[17]), | |
508 | .csr_ld (w_ld), | |
509 | .csr_data (csrbus_wr_data[17]), | |
510 | .rw_alias (1'b1), | |
511 | .rw1c_alias (1'b0), | |
512 | .rw1s_alias (1'b0), | |
513 | .hw_ld (1'b0), | |
514 | .hw_data (1'b0), | |
515 | .cp (clk), | |
516 | .q (int_en_csrbus_read_data[17]) | |
517 | ); | |
518 | ||
519 | // bit 18 | |
520 | csr_sw csr_sw_18 | |
521 | ( | |
522 | // synopsys translate_off | |
523 | .omni_ld (omni_ld), | |
524 | .omni_data (omni_data[18]), | |
525 | .omni_rw_alias (1'b1), | |
526 | .omni_rw1c_alias (1'b0), | |
527 | .omni_rw1s_alias (1'b0), | |
528 | // synopsys translate_on | |
529 | .rst (rst_l_active_high), | |
530 | .rst_val (reset_en_p[18]), | |
531 | .csr_ld (w_ld), | |
532 | .csr_data (csrbus_wr_data[18]), | |
533 | .rw_alias (1'b1), | |
534 | .rw1c_alias (1'b0), | |
535 | .rw1s_alias (1'b0), | |
536 | .hw_ld (1'b0), | |
537 | .hw_data (1'b0), | |
538 | .cp (clk), | |
539 | .q (int_en_csrbus_read_data[18]) | |
540 | ); | |
541 | ||
542 | // bit 19 | |
543 | csr_sw csr_sw_19 | |
544 | ( | |
545 | // synopsys translate_off | |
546 | .omni_ld (omni_ld), | |
547 | .omni_data (omni_data[19]), | |
548 | .omni_rw_alias (1'b1), | |
549 | .omni_rw1c_alias (1'b0), | |
550 | .omni_rw1s_alias (1'b0), | |
551 | // synopsys translate_on | |
552 | .rst (rst_l_active_high), | |
553 | .rst_val (reset_en_p[19]), | |
554 | .csr_ld (w_ld), | |
555 | .csr_data (csrbus_wr_data[19]), | |
556 | .rw_alias (1'b1), | |
557 | .rw1c_alias (1'b0), | |
558 | .rw1s_alias (1'b0), | |
559 | .hw_ld (1'b0), | |
560 | .hw_data (1'b0), | |
561 | .cp (clk), | |
562 | .q (int_en_csrbus_read_data[19]) | |
563 | ); | |
564 | ||
565 | // bit 20 | |
566 | csr_sw csr_sw_20 | |
567 | ( | |
568 | // synopsys translate_off | |
569 | .omni_ld (omni_ld), | |
570 | .omni_data (omni_data[20]), | |
571 | .omni_rw_alias (1'b1), | |
572 | .omni_rw1c_alias (1'b0), | |
573 | .omni_rw1s_alias (1'b0), | |
574 | // synopsys translate_on | |
575 | .rst (rst_l_active_high), | |
576 | .rst_val (reset_en_p[20]), | |
577 | .csr_ld (w_ld), | |
578 | .csr_data (csrbus_wr_data[20]), | |
579 | .rw_alias (1'b1), | |
580 | .rw1c_alias (1'b0), | |
581 | .rw1s_alias (1'b0), | |
582 | .hw_ld (1'b0), | |
583 | .hw_data (1'b0), | |
584 | .cp (clk), | |
585 | .q (int_en_csrbus_read_data[20]) | |
586 | ); | |
587 | ||
588 | assign int_en_csrbus_read_data[21] = 1'b0; // bit 21 | |
589 | assign int_en_csrbus_read_data[22] = 1'b0; // bit 22 | |
590 | assign int_en_csrbus_read_data[23] = 1'b0; // bit 23 | |
591 | assign int_en_csrbus_read_data[24] = 1'b0; // bit 24 | |
592 | assign int_en_csrbus_read_data[25] = 1'b0; // bit 25 | |
593 | assign int_en_csrbus_read_data[26] = 1'b0; // bit 26 | |
594 | assign int_en_csrbus_read_data[27] = 1'b0; // bit 27 | |
595 | assign int_en_csrbus_read_data[28] = 1'b0; // bit 28 | |
596 | assign int_en_csrbus_read_data[29] = 1'b0; // bit 29 | |
597 | assign int_en_csrbus_read_data[30] = 1'b0; // bit 30 | |
598 | assign int_en_csrbus_read_data[31] = 1'b0; // bit 31 | |
599 | // bit 32 | |
600 | csr_sw csr_sw_32 | |
601 | ( | |
602 | // synopsys translate_off | |
603 | .omni_ld (omni_ld), | |
604 | .omni_data (omni_data[32]), | |
605 | .omni_rw_alias (1'b1), | |
606 | .omni_rw1c_alias (1'b0), | |
607 | .omni_rw1s_alias (1'b0), | |
608 | // synopsys translate_on | |
609 | .rst (rst_l_active_high), | |
610 | .rst_val (reset_en_s[0]), | |
611 | .csr_ld (w_ld), | |
612 | .csr_data (csrbus_wr_data[32]), | |
613 | .rw_alias (1'b1), | |
614 | .rw1c_alias (1'b0), | |
615 | .rw1s_alias (1'b0), | |
616 | .hw_ld (1'b0), | |
617 | .hw_data (1'b0), | |
618 | .cp (clk), | |
619 | .q (int_en_csrbus_read_data[32]) | |
620 | ); | |
621 | ||
622 | // bit 33 | |
623 | csr_sw csr_sw_33 | |
624 | ( | |
625 | // synopsys translate_off | |
626 | .omni_ld (omni_ld), | |
627 | .omni_data (omni_data[33]), | |
628 | .omni_rw_alias (1'b1), | |
629 | .omni_rw1c_alias (1'b0), | |
630 | .omni_rw1s_alias (1'b0), | |
631 | // synopsys translate_on | |
632 | .rst (rst_l_active_high), | |
633 | .rst_val (reset_en_s[1]), | |
634 | .csr_ld (w_ld), | |
635 | .csr_data (csrbus_wr_data[33]), | |
636 | .rw_alias (1'b1), | |
637 | .rw1c_alias (1'b0), | |
638 | .rw1s_alias (1'b0), | |
639 | .hw_ld (1'b0), | |
640 | .hw_data (1'b0), | |
641 | .cp (clk), | |
642 | .q (int_en_csrbus_read_data[33]) | |
643 | ); | |
644 | ||
645 | // bit 34 | |
646 | csr_sw csr_sw_34 | |
647 | ( | |
648 | // synopsys translate_off | |
649 | .omni_ld (omni_ld), | |
650 | .omni_data (omni_data[34]), | |
651 | .omni_rw_alias (1'b1), | |
652 | .omni_rw1c_alias (1'b0), | |
653 | .omni_rw1s_alias (1'b0), | |
654 | // synopsys translate_on | |
655 | .rst (rst_l_active_high), | |
656 | .rst_val (reset_en_s[2]), | |
657 | .csr_ld (w_ld), | |
658 | .csr_data (csrbus_wr_data[34]), | |
659 | .rw_alias (1'b1), | |
660 | .rw1c_alias (1'b0), | |
661 | .rw1s_alias (1'b0), | |
662 | .hw_ld (1'b0), | |
663 | .hw_data (1'b0), | |
664 | .cp (clk), | |
665 | .q (int_en_csrbus_read_data[34]) | |
666 | ); | |
667 | ||
668 | // bit 35 | |
669 | csr_sw csr_sw_35 | |
670 | ( | |
671 | // synopsys translate_off | |
672 | .omni_ld (omni_ld), | |
673 | .omni_data (omni_data[35]), | |
674 | .omni_rw_alias (1'b1), | |
675 | .omni_rw1c_alias (1'b0), | |
676 | .omni_rw1s_alias (1'b0), | |
677 | // synopsys translate_on | |
678 | .rst (rst_l_active_high), | |
679 | .rst_val (reset_en_s[3]), | |
680 | .csr_ld (w_ld), | |
681 | .csr_data (csrbus_wr_data[35]), | |
682 | .rw_alias (1'b1), | |
683 | .rw1c_alias (1'b0), | |
684 | .rw1s_alias (1'b0), | |
685 | .hw_ld (1'b0), | |
686 | .hw_data (1'b0), | |
687 | .cp (clk), | |
688 | .q (int_en_csrbus_read_data[35]) | |
689 | ); | |
690 | ||
691 | // bit 36 | |
692 | csr_sw csr_sw_36 | |
693 | ( | |
694 | // synopsys translate_off | |
695 | .omni_ld (omni_ld), | |
696 | .omni_data (omni_data[36]), | |
697 | .omni_rw_alias (1'b1), | |
698 | .omni_rw1c_alias (1'b0), | |
699 | .omni_rw1s_alias (1'b0), | |
700 | // synopsys translate_on | |
701 | .rst (rst_l_active_high), | |
702 | .rst_val (reset_en_s[4]), | |
703 | .csr_ld (w_ld), | |
704 | .csr_data (csrbus_wr_data[36]), | |
705 | .rw_alias (1'b1), | |
706 | .rw1c_alias (1'b0), | |
707 | .rw1s_alias (1'b0), | |
708 | .hw_ld (1'b0), | |
709 | .hw_data (1'b0), | |
710 | .cp (clk), | |
711 | .q (int_en_csrbus_read_data[36]) | |
712 | ); | |
713 | ||
714 | // bit 37 | |
715 | csr_sw csr_sw_37 | |
716 | ( | |
717 | // synopsys translate_off | |
718 | .omni_ld (omni_ld), | |
719 | .omni_data (omni_data[37]), | |
720 | .omni_rw_alias (1'b1), | |
721 | .omni_rw1c_alias (1'b0), | |
722 | .omni_rw1s_alias (1'b0), | |
723 | // synopsys translate_on | |
724 | .rst (rst_l_active_high), | |
725 | .rst_val (reset_en_s[5]), | |
726 | .csr_ld (w_ld), | |
727 | .csr_data (csrbus_wr_data[37]), | |
728 | .rw_alias (1'b1), | |
729 | .rw1c_alias (1'b0), | |
730 | .rw1s_alias (1'b0), | |
731 | .hw_ld (1'b0), | |
732 | .hw_data (1'b0), | |
733 | .cp (clk), | |
734 | .q (int_en_csrbus_read_data[37]) | |
735 | ); | |
736 | ||
737 | // bit 38 | |
738 | csr_sw csr_sw_38 | |
739 | ( | |
740 | // synopsys translate_off | |
741 | .omni_ld (omni_ld), | |
742 | .omni_data (omni_data[38]), | |
743 | .omni_rw_alias (1'b1), | |
744 | .omni_rw1c_alias (1'b0), | |
745 | .omni_rw1s_alias (1'b0), | |
746 | // synopsys translate_on | |
747 | .rst (rst_l_active_high), | |
748 | .rst_val (reset_en_s[6]), | |
749 | .csr_ld (w_ld), | |
750 | .csr_data (csrbus_wr_data[38]), | |
751 | .rw_alias (1'b1), | |
752 | .rw1c_alias (1'b0), | |
753 | .rw1s_alias (1'b0), | |
754 | .hw_ld (1'b0), | |
755 | .hw_data (1'b0), | |
756 | .cp (clk), | |
757 | .q (int_en_csrbus_read_data[38]) | |
758 | ); | |
759 | ||
760 | // bit 39 | |
761 | csr_sw csr_sw_39 | |
762 | ( | |
763 | // synopsys translate_off | |
764 | .omni_ld (omni_ld), | |
765 | .omni_data (omni_data[39]), | |
766 | .omni_rw_alias (1'b1), | |
767 | .omni_rw1c_alias (1'b0), | |
768 | .omni_rw1s_alias (1'b0), | |
769 | // synopsys translate_on | |
770 | .rst (rst_l_active_high), | |
771 | .rst_val (reset_en_s[7]), | |
772 | .csr_ld (w_ld), | |
773 | .csr_data (csrbus_wr_data[39]), | |
774 | .rw_alias (1'b1), | |
775 | .rw1c_alias (1'b0), | |
776 | .rw1s_alias (1'b0), | |
777 | .hw_ld (1'b0), | |
778 | .hw_data (1'b0), | |
779 | .cp (clk), | |
780 | .q (int_en_csrbus_read_data[39]) | |
781 | ); | |
782 | ||
783 | // bit 40 | |
784 | csr_sw csr_sw_40 | |
785 | ( | |
786 | // synopsys translate_off | |
787 | .omni_ld (omni_ld), | |
788 | .omni_data (omni_data[40]), | |
789 | .omni_rw_alias (1'b1), | |
790 | .omni_rw1c_alias (1'b0), | |
791 | .omni_rw1s_alias (1'b0), | |
792 | // synopsys translate_on | |
793 | .rst (rst_l_active_high), | |
794 | .rst_val (reset_en_s[8]), | |
795 | .csr_ld (w_ld), | |
796 | .csr_data (csrbus_wr_data[40]), | |
797 | .rw_alias (1'b1), | |
798 | .rw1c_alias (1'b0), | |
799 | .rw1s_alias (1'b0), | |
800 | .hw_ld (1'b0), | |
801 | .hw_data (1'b0), | |
802 | .cp (clk), | |
803 | .q (int_en_csrbus_read_data[40]) | |
804 | ); | |
805 | ||
806 | // bit 41 | |
807 | csr_sw csr_sw_41 | |
808 | ( | |
809 | // synopsys translate_off | |
810 | .omni_ld (omni_ld), | |
811 | .omni_data (omni_data[41]), | |
812 | .omni_rw_alias (1'b1), | |
813 | .omni_rw1c_alias (1'b0), | |
814 | .omni_rw1s_alias (1'b0), | |
815 | // synopsys translate_on | |
816 | .rst (rst_l_active_high), | |
817 | .rst_val (reset_en_s[9]), | |
818 | .csr_ld (w_ld), | |
819 | .csr_data (csrbus_wr_data[41]), | |
820 | .rw_alias (1'b1), | |
821 | .rw1c_alias (1'b0), | |
822 | .rw1s_alias (1'b0), | |
823 | .hw_ld (1'b0), | |
824 | .hw_data (1'b0), | |
825 | .cp (clk), | |
826 | .q (int_en_csrbus_read_data[41]) | |
827 | ); | |
828 | ||
829 | // bit 42 | |
830 | csr_sw csr_sw_42 | |
831 | ( | |
832 | // synopsys translate_off | |
833 | .omni_ld (omni_ld), | |
834 | .omni_data (omni_data[42]), | |
835 | .omni_rw_alias (1'b1), | |
836 | .omni_rw1c_alias (1'b0), | |
837 | .omni_rw1s_alias (1'b0), | |
838 | // synopsys translate_on | |
839 | .rst (rst_l_active_high), | |
840 | .rst_val (reset_en_s[10]), | |
841 | .csr_ld (w_ld), | |
842 | .csr_data (csrbus_wr_data[42]), | |
843 | .rw_alias (1'b1), | |
844 | .rw1c_alias (1'b0), | |
845 | .rw1s_alias (1'b0), | |
846 | .hw_ld (1'b0), | |
847 | .hw_data (1'b0), | |
848 | .cp (clk), | |
849 | .q (int_en_csrbus_read_data[42]) | |
850 | ); | |
851 | ||
852 | // bit 43 | |
853 | csr_sw csr_sw_43 | |
854 | ( | |
855 | // synopsys translate_off | |
856 | .omni_ld (omni_ld), | |
857 | .omni_data (omni_data[43]), | |
858 | .omni_rw_alias (1'b1), | |
859 | .omni_rw1c_alias (1'b0), | |
860 | .omni_rw1s_alias (1'b0), | |
861 | // synopsys translate_on | |
862 | .rst (rst_l_active_high), | |
863 | .rst_val (reset_en_s[11]), | |
864 | .csr_ld (w_ld), | |
865 | .csr_data (csrbus_wr_data[43]), | |
866 | .rw_alias (1'b1), | |
867 | .rw1c_alias (1'b0), | |
868 | .rw1s_alias (1'b0), | |
869 | .hw_ld (1'b0), | |
870 | .hw_data (1'b0), | |
871 | .cp (clk), | |
872 | .q (int_en_csrbus_read_data[43]) | |
873 | ); | |
874 | ||
875 | // bit 44 | |
876 | csr_sw csr_sw_44 | |
877 | ( | |
878 | // synopsys translate_off | |
879 | .omni_ld (omni_ld), | |
880 | .omni_data (omni_data[44]), | |
881 | .omni_rw_alias (1'b1), | |
882 | .omni_rw1c_alias (1'b0), | |
883 | .omni_rw1s_alias (1'b0), | |
884 | // synopsys translate_on | |
885 | .rst (rst_l_active_high), | |
886 | .rst_val (reset_en_s[12]), | |
887 | .csr_ld (w_ld), | |
888 | .csr_data (csrbus_wr_data[44]), | |
889 | .rw_alias (1'b1), | |
890 | .rw1c_alias (1'b0), | |
891 | .rw1s_alias (1'b0), | |
892 | .hw_ld (1'b0), | |
893 | .hw_data (1'b0), | |
894 | .cp (clk), | |
895 | .q (int_en_csrbus_read_data[44]) | |
896 | ); | |
897 | ||
898 | // bit 45 | |
899 | csr_sw csr_sw_45 | |
900 | ( | |
901 | // synopsys translate_off | |
902 | .omni_ld (omni_ld), | |
903 | .omni_data (omni_data[45]), | |
904 | .omni_rw_alias (1'b1), | |
905 | .omni_rw1c_alias (1'b0), | |
906 | .omni_rw1s_alias (1'b0), | |
907 | // synopsys translate_on | |
908 | .rst (rst_l_active_high), | |
909 | .rst_val (reset_en_s[13]), | |
910 | .csr_ld (w_ld), | |
911 | .csr_data (csrbus_wr_data[45]), | |
912 | .rw_alias (1'b1), | |
913 | .rw1c_alias (1'b0), | |
914 | .rw1s_alias (1'b0), | |
915 | .hw_ld (1'b0), | |
916 | .hw_data (1'b0), | |
917 | .cp (clk), | |
918 | .q (int_en_csrbus_read_data[45]) | |
919 | ); | |
920 | ||
921 | // bit 46 | |
922 | csr_sw csr_sw_46 | |
923 | ( | |
924 | // synopsys translate_off | |
925 | .omni_ld (omni_ld), | |
926 | .omni_data (omni_data[46]), | |
927 | .omni_rw_alias (1'b1), | |
928 | .omni_rw1c_alias (1'b0), | |
929 | .omni_rw1s_alias (1'b0), | |
930 | // synopsys translate_on | |
931 | .rst (rst_l_active_high), | |
932 | .rst_val (reset_en_s[14]), | |
933 | .csr_ld (w_ld), | |
934 | .csr_data (csrbus_wr_data[46]), | |
935 | .rw_alias (1'b1), | |
936 | .rw1c_alias (1'b0), | |
937 | .rw1s_alias (1'b0), | |
938 | .hw_ld (1'b0), | |
939 | .hw_data (1'b0), | |
940 | .cp (clk), | |
941 | .q (int_en_csrbus_read_data[46]) | |
942 | ); | |
943 | ||
944 | // bit 47 | |
945 | csr_sw csr_sw_47 | |
946 | ( | |
947 | // synopsys translate_off | |
948 | .omni_ld (omni_ld), | |
949 | .omni_data (omni_data[47]), | |
950 | .omni_rw_alias (1'b1), | |
951 | .omni_rw1c_alias (1'b0), | |
952 | .omni_rw1s_alias (1'b0), | |
953 | // synopsys translate_on | |
954 | .rst (rst_l_active_high), | |
955 | .rst_val (reset_en_s[15]), | |
956 | .csr_ld (w_ld), | |
957 | .csr_data (csrbus_wr_data[47]), | |
958 | .rw_alias (1'b1), | |
959 | .rw1c_alias (1'b0), | |
960 | .rw1s_alias (1'b0), | |
961 | .hw_ld (1'b0), | |
962 | .hw_data (1'b0), | |
963 | .cp (clk), | |
964 | .q (int_en_csrbus_read_data[47]) | |
965 | ); | |
966 | ||
967 | // bit 48 | |
968 | csr_sw csr_sw_48 | |
969 | ( | |
970 | // synopsys translate_off | |
971 | .omni_ld (omni_ld), | |
972 | .omni_data (omni_data[48]), | |
973 | .omni_rw_alias (1'b1), | |
974 | .omni_rw1c_alias (1'b0), | |
975 | .omni_rw1s_alias (1'b0), | |
976 | // synopsys translate_on | |
977 | .rst (rst_l_active_high), | |
978 | .rst_val (reset_en_s[16]), | |
979 | .csr_ld (w_ld), | |
980 | .csr_data (csrbus_wr_data[48]), | |
981 | .rw_alias (1'b1), | |
982 | .rw1c_alias (1'b0), | |
983 | .rw1s_alias (1'b0), | |
984 | .hw_ld (1'b0), | |
985 | .hw_data (1'b0), | |
986 | .cp (clk), | |
987 | .q (int_en_csrbus_read_data[48]) | |
988 | ); | |
989 | ||
990 | // bit 49 | |
991 | csr_sw csr_sw_49 | |
992 | ( | |
993 | // synopsys translate_off | |
994 | .omni_ld (omni_ld), | |
995 | .omni_data (omni_data[49]), | |
996 | .omni_rw_alias (1'b1), | |
997 | .omni_rw1c_alias (1'b0), | |
998 | .omni_rw1s_alias (1'b0), | |
999 | // synopsys translate_on | |
1000 | .rst (rst_l_active_high), | |
1001 | .rst_val (reset_en_s[17]), | |
1002 | .csr_ld (w_ld), | |
1003 | .csr_data (csrbus_wr_data[49]), | |
1004 | .rw_alias (1'b1), | |
1005 | .rw1c_alias (1'b0), | |
1006 | .rw1s_alias (1'b0), | |
1007 | .hw_ld (1'b0), | |
1008 | .hw_data (1'b0), | |
1009 | .cp (clk), | |
1010 | .q (int_en_csrbus_read_data[49]) | |
1011 | ); | |
1012 | ||
1013 | // bit 50 | |
1014 | csr_sw csr_sw_50 | |
1015 | ( | |
1016 | // synopsys translate_off | |
1017 | .omni_ld (omni_ld), | |
1018 | .omni_data (omni_data[50]), | |
1019 | .omni_rw_alias (1'b1), | |
1020 | .omni_rw1c_alias (1'b0), | |
1021 | .omni_rw1s_alias (1'b0), | |
1022 | // synopsys translate_on | |
1023 | .rst (rst_l_active_high), | |
1024 | .rst_val (reset_en_s[18]), | |
1025 | .csr_ld (w_ld), | |
1026 | .csr_data (csrbus_wr_data[50]), | |
1027 | .rw_alias (1'b1), | |
1028 | .rw1c_alias (1'b0), | |
1029 | .rw1s_alias (1'b0), | |
1030 | .hw_ld (1'b0), | |
1031 | .hw_data (1'b0), | |
1032 | .cp (clk), | |
1033 | .q (int_en_csrbus_read_data[50]) | |
1034 | ); | |
1035 | ||
1036 | // bit 51 | |
1037 | csr_sw csr_sw_51 | |
1038 | ( | |
1039 | // synopsys translate_off | |
1040 | .omni_ld (omni_ld), | |
1041 | .omni_data (omni_data[51]), | |
1042 | .omni_rw_alias (1'b1), | |
1043 | .omni_rw1c_alias (1'b0), | |
1044 | .omni_rw1s_alias (1'b0), | |
1045 | // synopsys translate_on | |
1046 | .rst (rst_l_active_high), | |
1047 | .rst_val (reset_en_s[19]), | |
1048 | .csr_ld (w_ld), | |
1049 | .csr_data (csrbus_wr_data[51]), | |
1050 | .rw_alias (1'b1), | |
1051 | .rw1c_alias (1'b0), | |
1052 | .rw1s_alias (1'b0), | |
1053 | .hw_ld (1'b0), | |
1054 | .hw_data (1'b0), | |
1055 | .cp (clk), | |
1056 | .q (int_en_csrbus_read_data[51]) | |
1057 | ); | |
1058 | ||
1059 | // bit 52 | |
1060 | csr_sw csr_sw_52 | |
1061 | ( | |
1062 | // synopsys translate_off | |
1063 | .omni_ld (omni_ld), | |
1064 | .omni_data (omni_data[52]), | |
1065 | .omni_rw_alias (1'b1), | |
1066 | .omni_rw1c_alias (1'b0), | |
1067 | .omni_rw1s_alias (1'b0), | |
1068 | // synopsys translate_on | |
1069 | .rst (rst_l_active_high), | |
1070 | .rst_val (reset_en_s[20]), | |
1071 | .csr_ld (w_ld), | |
1072 | .csr_data (csrbus_wr_data[52]), | |
1073 | .rw_alias (1'b1), | |
1074 | .rw1c_alias (1'b0), | |
1075 | .rw1s_alias (1'b0), | |
1076 | .hw_ld (1'b0), | |
1077 | .hw_data (1'b0), | |
1078 | .cp (clk), | |
1079 | .q (int_en_csrbus_read_data[52]) | |
1080 | ); | |
1081 | ||
1082 | assign int_en_csrbus_read_data[53] = 1'b0; // bit 53 | |
1083 | assign int_en_csrbus_read_data[54] = 1'b0; // bit 54 | |
1084 | assign int_en_csrbus_read_data[55] = 1'b0; // bit 55 | |
1085 | assign int_en_csrbus_read_data[56] = 1'b0; // bit 56 | |
1086 | assign int_en_csrbus_read_data[57] = 1'b0; // bit 57 | |
1087 | assign int_en_csrbus_read_data[58] = 1'b0; // bit 58 | |
1088 | assign int_en_csrbus_read_data[59] = 1'b0; // bit 59 | |
1089 | assign int_en_csrbus_read_data[60] = 1'b0; // bit 60 | |
1090 | assign int_en_csrbus_read_data[61] = 1'b0; // bit 61 | |
1091 | assign int_en_csrbus_read_data[62] = 1'b0; // bit 62 | |
1092 | assign int_en_csrbus_read_data[63] = 1'b0; // bit 63 | |
1093 | ||
1094 | endmodule // dmu_mmu_csr_int_en_entry |