[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_log_entry.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_mmu_csr_log_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
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// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
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// ========== Copyright Header End ============================================
module dmu_mmu_csr_log_entry 
	(
	// synopsys translate_off
	  omni_ld,
	  omni_data,
	// synopsys translate_on
	clk,
	por_l,
	w_ld,
	csrbus_wr_data,
	log_csrbus_read_data
	);

//====================================================================
//     Polarity declarations
//====================================================================
// synopsys translate_off
  input  omni_ld;  // Omni load
// vlint flag_input_port_not_connected off
  input  [`FIRE_DLC_MMU_CSR_LOG_WIDTH - 1:0] omni_data;  // Omni write data
// synopsys translate_on
// vlint flag_input_port_not_connected on
input  clk;  // Clock signal
input  por_l;  // Reset signal
input  w_ld;  // SW load
// vlint flag_input_port_not_connected off
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_MMU_CSR_LOG_WIDTH-1:0] log_csrbus_read_data;  // SW read data

//====================================================================
//     Type declarations
//====================================================================
// synopsys translate_off
  wire omni_ld;  // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
  wire [`FIRE_DLC_MMU_CSR_LOG_WIDTH - 1:0] omni_data;  // Omni write data
// synopsys translate_on
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk;  // Clock signal
wire por_l;  // Reset signal
wire w_ld;  // SW load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_MMU_CSR_LOG_WIDTH-1:0] log_csrbus_read_data;  // SW read data

//====================================================================
//     Logic     
//====================================================================

//----- Reset values
// verilint 531 off
wire [20:0] reset_en = 21'h1FFFFF;
// verilint 531 on

//----- Active high reset wires 
wire por_l_active_high = ~por_l;

//====================================================
//     Instantiation of flops
//====================================================

// bit 0
csr_sw csr_sw_0
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[0]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[0]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[0])
	);

// bit 1
csr_sw csr_sw_1
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[1]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[1]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[1])
	);

// bit 2
csr_sw csr_sw_2
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[2]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[2]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[2])
	);

// bit 3
csr_sw csr_sw_3
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[3]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[3]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[3])
	);

// bit 4
csr_sw csr_sw_4
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[4]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[4]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[4]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[4])
	);

// bit 5
csr_sw csr_sw_5
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[5]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[5]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[5]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[5])
	);

// bit 6
csr_sw csr_sw_6
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[6]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[6]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[6]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[6])
	);

// bit 7
csr_sw csr_sw_7
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[7]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[7]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[7]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[7])
	);

// bit 8
csr_sw csr_sw_8
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[8]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[8]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[8]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[8])
	);

// bit 9
csr_sw csr_sw_9
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[9]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[9]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[9]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[9])
	);

// bit 10
csr_sw csr_sw_10
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[10]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[10]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[10]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[10])
	);

// bit 11
csr_sw csr_sw_11
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[11]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[11]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[11]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[11])
	);

// bit 12
csr_sw csr_sw_12
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[12]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[12]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[12]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[12])
	);

// bit 13
csr_sw csr_sw_13
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[13]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[13]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[13]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[13])
	);

// bit 14
csr_sw csr_sw_14
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[14]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[14]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[14]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[14])
	);

// bit 15
csr_sw csr_sw_15
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[15]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[15]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[15]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[15])
	);

// bit 16
csr_sw csr_sw_16
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[16]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[16]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[16]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[16])
	);

// bit 17
csr_sw csr_sw_17
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[17]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[17]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[17]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[17])
	);

// bit 18
csr_sw csr_sw_18
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[18]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[18]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[18]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[18])
	);

// bit 19
csr_sw csr_sw_19
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[19]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[19]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[19]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[19])
	);

// bit 20
csr_sw csr_sw_20
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[20]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_en[20]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[20]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (1'b0),
	.hw_data        (1'b0),
	.cp             (clk),
	.q              (log_csrbus_read_data[20])
	);

assign  log_csrbus_read_data[21] = 1'b0;  // bit 21
assign  log_csrbus_read_data[22] = 1'b0;  // bit 22
assign  log_csrbus_read_data[23] = 1'b0;  // bit 23
assign  log_csrbus_read_data[24] = 1'b0;  // bit 24
assign  log_csrbus_read_data[25] = 1'b0;  // bit 25
assign  log_csrbus_read_data[26] = 1'b0;  // bit 26
assign  log_csrbus_read_data[27] = 1'b0;  // bit 27
assign  log_csrbus_read_data[28] = 1'b0;  // bit 28
assign  log_csrbus_read_data[29] = 1'b0;  // bit 29
assign  log_csrbus_read_data[30] = 1'b0;  // bit 30
assign  log_csrbus_read_data[31] = 1'b0;  // bit 31
assign  log_csrbus_read_data[32] = 1'b0;  // bit 32
assign  log_csrbus_read_data[33] = 1'b0;  // bit 33
assign  log_csrbus_read_data[34] = 1'b0;  // bit 34
assign  log_csrbus_read_data[35] = 1'b0;  // bit 35
assign  log_csrbus_read_data[36] = 1'b0;  // bit 36
assign  log_csrbus_read_data[37] = 1'b0;  // bit 37
assign  log_csrbus_read_data[38] = 1'b0;  // bit 38
assign  log_csrbus_read_data[39] = 1'b0;  // bit 39
assign  log_csrbus_read_data[40] = 1'b0;  // bit 40
assign  log_csrbus_read_data[41] = 1'b0;  // bit 41
assign  log_csrbus_read_data[42] = 1'b0;  // bit 42
assign  log_csrbus_read_data[43] = 1'b0;  // bit 43
assign  log_csrbus_read_data[44] = 1'b0;  // bit 44
assign  log_csrbus_read_data[45] = 1'b0;  // bit 45
assign  log_csrbus_read_data[46] = 1'b0;  // bit 46
assign  log_csrbus_read_data[47] = 1'b0;  // bit 47
assign  log_csrbus_read_data[48] = 1'b0;  // bit 48
assign  log_csrbus_read_data[49] = 1'b0;  // bit 49
assign  log_csrbus_read_data[50] = 1'b0;  // bit 50
assign  log_csrbus_read_data[51] = 1'b0;  // bit 51
assign  log_csrbus_read_data[52] = 1'b0;  // bit 52
assign  log_csrbus_read_data[53] = 1'b0;  // bit 53
assign  log_csrbus_read_data[54] = 1'b0;  // bit 54
assign  log_csrbus_read_data[55] = 1'b0;  // bit 55
assign  log_csrbus_read_data[56] = 1'b0;  // bit 56
assign  log_csrbus_read_data[57] = 1'b0;  // bit 57
assign  log_csrbus_read_data[58] = 1'b0;  // bit 58
assign  log_csrbus_read_data[59] = 1'b0;  // bit 59
assign  log_csrbus_read_data[60] = 1'b0;  // bit 60
assign  log_csrbus_read_data[61] = 1'b0;  // bit 61
assign  log_csrbus_read_data[62] = 1'b0;  // bit 62
assign  log_csrbus_read_data[63] = 1'b0;  // bit 63

endmodule // dmu_mmu_csr_log_entry
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_mmu_csr_log_entry.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_mmu_csr_log_entry
	36	(
	37	// synopsys translate_off
	38	omni_ld,
	39	omni_data,
	40	// synopsys translate_on
	41	clk,
	42	por_l,
	43	w_ld,
	44	csrbus_wr_data,
	45	log_csrbus_read_data
	46	);
	47
	48	//====================================================================
	49	// Polarity declarations
	50	//====================================================================
	51	// synopsys translate_off
	52	input omni_ld; // Omni load
	53	// vlint flag_input_port_not_connected off
	54	input [`FIRE_DLC_MMU_CSR_LOG_WIDTH - 1:0] omni_data; // Omni write data
	55	// synopsys translate_on
	56	// vlint flag_input_port_not_connected on
	57	input clk; // Clock signal
	58	input por_l; // Reset signal
	59	input w_ld; // SW load
	60	// vlint flag_input_port_not_connected off
	61	input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
	62	// vlint flag_input_port_not_connected on
	63	output [`FIRE_DLC_MMU_CSR_LOG_WIDTH-1:0] log_csrbus_read_data; // SW read data
	64
65	//====================================================================
66	// Type declarations
67	//====================================================================
68	// synopsys translate_off
69	wire omni_ld; // Omni load
70	// vlint flag_dangling_net_within_module off
71	// vlint flag_net_has_no_load off
72	wire [`FIRE_DLC_MMU_CSR_LOG_WIDTH - 1:0] omni_data; // Omni write data
73	// synopsys translate_on
74	// vlint flag_dangling_net_within_module on
75	// vlint flag_net_has_no_load on
76	wire clk; // Clock signal
77	wire por_l; // Reset signal
78	wire w_ld; // SW load
79	// vlint flag_dangling_net_within_module off
80	// vlint flag_net_has_no_load off
81	wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
82	// vlint flag_dangling_net_within_module on
83	// vlint flag_net_has_no_load on
84	wire [`FIRE_DLC_MMU_CSR_LOG_WIDTH-1:0] log_csrbus_read_data; // SW read data
85
86	//====================================================================
87	// Logic
88	//====================================================================
89
90	//----- Reset values
91	// verilint 531 off
92	wire [20:0] reset_en = 21'h1FFFFF;
93	// verilint 531 on
94
95	//----- Active high reset wires
96	wire por_l_active_high = ~por_l;
97
98	//====================================================
99	// Instantiation of flops
100	//====================================================
101
102	// bit 0
103	csr_sw csr_sw_0
104	(
105	// synopsys translate_off
106	.omni_ld (omni_ld),
107	.omni_data (omni_data[0]),
108	.omni_rw_alias (1'b1),
109	.omni_rw1c_alias (1'b0),
110	.omni_rw1s_alias (1'b0),
111	// synopsys translate_on
112	.rst (por_l_active_high),
113	.rst_val (reset_en[0]),
114	.csr_ld (w_ld),
115	.csr_data (csrbus_wr_data[0]),
116	.rw_alias (1'b1),
117	.rw1c_alias (1'b0),
118	.rw1s_alias (1'b0),
119	.hw_ld (1'b0),
120	.hw_data (1'b0),
121	.cp (clk),
122	.q (log_csrbus_read_data[0])
123	);
124
125	// bit 1
126	csr_sw csr_sw_1
127	(
128	// synopsys translate_off
129	.omni_ld (omni_ld),
130	.omni_data (omni_data[1]),
131	.omni_rw_alias (1'b1),
132	.omni_rw1c_alias (1'b0),
133	.omni_rw1s_alias (1'b0),
134	// synopsys translate_on
135	.rst (por_l_active_high),
136	.rst_val (reset_en[1]),
137	.csr_ld (w_ld),
138	.csr_data (csrbus_wr_data[1]),
139	.rw_alias (1'b1),
140	.rw1c_alias (1'b0),
141	.rw1s_alias (1'b0),
142	.hw_ld (1'b0),
143	.hw_data (1'b0),
144	.cp (clk),
145	.q (log_csrbus_read_data[1])
146	);
147
148	// bit 2
149	csr_sw csr_sw_2
150	(
151	// synopsys translate_off
152	.omni_ld (omni_ld),
153	.omni_data (omni_data[2]),
154	.omni_rw_alias (1'b1),
155	.omni_rw1c_alias (1'b0),
156	.omni_rw1s_alias (1'b0),
157	// synopsys translate_on
158	.rst (por_l_active_high),
159	.rst_val (reset_en[2]),
160	.csr_ld (w_ld),
161	.csr_data (csrbus_wr_data[2]),
162	.rw_alias (1'b1),
163	.rw1c_alias (1'b0),
164	.rw1s_alias (1'b0),
165	.hw_ld (1'b0),
166	.hw_data (1'b0),
167	.cp (clk),
168	.q (log_csrbus_read_data[2])
169	);
170
171	// bit 3
172	csr_sw csr_sw_3
173	(
174	// synopsys translate_off
175	.omni_ld (omni_ld),
176	.omni_data (omni_data[3]),
177	.omni_rw_alias (1'b1),
178	.omni_rw1c_alias (1'b0),
179	.omni_rw1s_alias (1'b0),
180	// synopsys translate_on
181	.rst (por_l_active_high),
182	.rst_val (reset_en[3]),
183	.csr_ld (w_ld),
184	.csr_data (csrbus_wr_data[3]),
185	.rw_alias (1'b1),
186	.rw1c_alias (1'b0),
187	.rw1s_alias (1'b0),
188	.hw_ld (1'b0),
189	.hw_data (1'b0),
190	.cp (clk),
191	.q (log_csrbus_read_data[3])
192	);
193
194	// bit 4
195	csr_sw csr_sw_4
196	(
197	// synopsys translate_off
198	.omni_ld (omni_ld),
199	.omni_data (omni_data[4]),
200	.omni_rw_alias (1'b1),
201	.omni_rw1c_alias (1'b0),
202	.omni_rw1s_alias (1'b0),
203	// synopsys translate_on
204	.rst (por_l_active_high),
205	.rst_val (reset_en[4]),
206	.csr_ld (w_ld),
207	.csr_data (csrbus_wr_data[4]),
208	.rw_alias (1'b1),
209	.rw1c_alias (1'b0),
210	.rw1s_alias (1'b0),
211	.hw_ld (1'b0),
212	.hw_data (1'b0),
213	.cp (clk),
214	.q (log_csrbus_read_data[4])
215	);
216
217	// bit 5
218	csr_sw csr_sw_5
219	(
220	// synopsys translate_off
221	.omni_ld (omni_ld),
222	.omni_data (omni_data[5]),
223	.omni_rw_alias (1'b1),
224	.omni_rw1c_alias (1'b0),
225	.omni_rw1s_alias (1'b0),
226	// synopsys translate_on
227	.rst (por_l_active_high),
228	.rst_val (reset_en[5]),
229	.csr_ld (w_ld),
230	.csr_data (csrbus_wr_data[5]),
231	.rw_alias (1'b1),
232	.rw1c_alias (1'b0),
233	.rw1s_alias (1'b0),
234	.hw_ld (1'b0),
235	.hw_data (1'b0),
236	.cp (clk),
237	.q (log_csrbus_read_data[5])
238	);
239
240	// bit 6
241	csr_sw csr_sw_6
242	(
243	// synopsys translate_off
244	.omni_ld (omni_ld),
245	.omni_data (omni_data[6]),
246	.omni_rw_alias (1'b1),
247	.omni_rw1c_alias (1'b0),
248	.omni_rw1s_alias (1'b0),
249	// synopsys translate_on
250	.rst (por_l_active_high),
251	.rst_val (reset_en[6]),
252	.csr_ld (w_ld),
253	.csr_data (csrbus_wr_data[6]),
254	.rw_alias (1'b1),
255	.rw1c_alias (1'b0),
256	.rw1s_alias (1'b0),
257	.hw_ld (1'b0),
258	.hw_data (1'b0),
259	.cp (clk),
260	.q (log_csrbus_read_data[6])
261	);
262
263	// bit 7
264	csr_sw csr_sw_7
265	(
266	// synopsys translate_off
267	.omni_ld (omni_ld),
268	.omni_data (omni_data[7]),
269	.omni_rw_alias (1'b1),
270	.omni_rw1c_alias (1'b0),
271	.omni_rw1s_alias (1'b0),
272	// synopsys translate_on
273	.rst (por_l_active_high),
274	.rst_val (reset_en[7]),
275	.csr_ld (w_ld),
276	.csr_data (csrbus_wr_data[7]),
277	.rw_alias (1'b1),
278	.rw1c_alias (1'b0),
279	.rw1s_alias (1'b0),
280	.hw_ld (1'b0),
281	.hw_data (1'b0),
282	.cp (clk),
283	.q (log_csrbus_read_data[7])
284	);
285
286	// bit 8
287	csr_sw csr_sw_8
288	(
289	// synopsys translate_off
290	.omni_ld (omni_ld),
291	.omni_data (omni_data[8]),
292	.omni_rw_alias (1'b1),
293	.omni_rw1c_alias (1'b0),
294	.omni_rw1s_alias (1'b0),
295	// synopsys translate_on
296	.rst (por_l_active_high),
297	.rst_val (reset_en[8]),
298	.csr_ld (w_ld),
299	.csr_data (csrbus_wr_data[8]),
300	.rw_alias (1'b1),
301	.rw1c_alias (1'b0),
302	.rw1s_alias (1'b0),
303	.hw_ld (1'b0),
304	.hw_data (1'b0),
305	.cp (clk),
306	.q (log_csrbus_read_data[8])
307	);
308
309	// bit 9
310	csr_sw csr_sw_9
311	(
312	// synopsys translate_off
313	.omni_ld (omni_ld),
314	.omni_data (omni_data[9]),
315	.omni_rw_alias (1'b1),
316	.omni_rw1c_alias (1'b0),
317	.omni_rw1s_alias (1'b0),
318	// synopsys translate_on
319	.rst (por_l_active_high),
320	.rst_val (reset_en[9]),
321	.csr_ld (w_ld),
322	.csr_data (csrbus_wr_data[9]),
323	.rw_alias (1'b1),
324	.rw1c_alias (1'b0),
325	.rw1s_alias (1'b0),
326	.hw_ld (1'b0),
327	.hw_data (1'b0),
328	.cp (clk),
329	.q (log_csrbus_read_data[9])
330	);
331
332	// bit 10
333	csr_sw csr_sw_10
334	(
335	// synopsys translate_off
336	.omni_ld (omni_ld),
337	.omni_data (omni_data[10]),
338	.omni_rw_alias (1'b1),
339	.omni_rw1c_alias (1'b0),
340	.omni_rw1s_alias (1'b0),
341	// synopsys translate_on
342	.rst (por_l_active_high),
343	.rst_val (reset_en[10]),
344	.csr_ld (w_ld),
345	.csr_data (csrbus_wr_data[10]),
346	.rw_alias (1'b1),
347	.rw1c_alias (1'b0),
348	.rw1s_alias (1'b0),
349	.hw_ld (1'b0),
350	.hw_data (1'b0),
351	.cp (clk),
352	.q (log_csrbus_read_data[10])
353	);
354
355	// bit 11
356	csr_sw csr_sw_11
357	(
358	// synopsys translate_off
359	.omni_ld (omni_ld),
360	.omni_data (omni_data[11]),
361	.omni_rw_alias (1'b1),
362	.omni_rw1c_alias (1'b0),
363	.omni_rw1s_alias (1'b0),
364	// synopsys translate_on
365	.rst (por_l_active_high),
366	.rst_val (reset_en[11]),
367	.csr_ld (w_ld),
368	.csr_data (csrbus_wr_data[11]),
369	.rw_alias (1'b1),
370	.rw1c_alias (1'b0),
371	.rw1s_alias (1'b0),
372	.hw_ld (1'b0),
373	.hw_data (1'b0),
374	.cp (clk),
375	.q (log_csrbus_read_data[11])
376	);
377
378	// bit 12
379	csr_sw csr_sw_12
380	(
381	// synopsys translate_off
382	.omni_ld (omni_ld),
383	.omni_data (omni_data[12]),
384	.omni_rw_alias (1'b1),
385	.omni_rw1c_alias (1'b0),
386	.omni_rw1s_alias (1'b0),
387	// synopsys translate_on
388	.rst (por_l_active_high),
389	.rst_val (reset_en[12]),
390	.csr_ld (w_ld),
391	.csr_data (csrbus_wr_data[12]),
392	.rw_alias (1'b1),
393	.rw1c_alias (1'b0),
394	.rw1s_alias (1'b0),
395	.hw_ld (1'b0),
396	.hw_data (1'b0),
397	.cp (clk),
398	.q (log_csrbus_read_data[12])
399	);
400
401	// bit 13
402	csr_sw csr_sw_13
403	(
404	// synopsys translate_off
405	.omni_ld (omni_ld),
406	.omni_data (omni_data[13]),
407	.omni_rw_alias (1'b1),
408	.omni_rw1c_alias (1'b0),
409	.omni_rw1s_alias (1'b0),
410	// synopsys translate_on
411	.rst (por_l_active_high),
412	.rst_val (reset_en[13]),
413	.csr_ld (w_ld),
414	.csr_data (csrbus_wr_data[13]),
415	.rw_alias (1'b1),
416	.rw1c_alias (1'b0),
417	.rw1s_alias (1'b0),
418	.hw_ld (1'b0),
419	.hw_data (1'b0),
420	.cp (clk),
421	.q (log_csrbus_read_data[13])
422	);
423
424	// bit 14
425	csr_sw csr_sw_14
426	(
427	// synopsys translate_off
428	.omni_ld (omni_ld),
429	.omni_data (omni_data[14]),
430	.omni_rw_alias (1'b1),
431	.omni_rw1c_alias (1'b0),
432	.omni_rw1s_alias (1'b0),
433	// synopsys translate_on
434	.rst (por_l_active_high),
435	.rst_val (reset_en[14]),
436	.csr_ld (w_ld),
437	.csr_data (csrbus_wr_data[14]),
438	.rw_alias (1'b1),
439	.rw1c_alias (1'b0),
440	.rw1s_alias (1'b0),
441	.hw_ld (1'b0),
442	.hw_data (1'b0),
443	.cp (clk),
444	.q (log_csrbus_read_data[14])
445	);
446
447	// bit 15
448	csr_sw csr_sw_15
449	(
450	// synopsys translate_off
451	.omni_ld (omni_ld),
452	.omni_data (omni_data[15]),
453	.omni_rw_alias (1'b1),
454	.omni_rw1c_alias (1'b0),
455	.omni_rw1s_alias (1'b0),
456	// synopsys translate_on
457	.rst (por_l_active_high),
458	.rst_val (reset_en[15]),
459	.csr_ld (w_ld),
460	.csr_data (csrbus_wr_data[15]),
461	.rw_alias (1'b1),
462	.rw1c_alias (1'b0),
463	.rw1s_alias (1'b0),
464	.hw_ld (1'b0),
465	.hw_data (1'b0),
466	.cp (clk),
467	.q (log_csrbus_read_data[15])
468	);
469
470	// bit 16
471	csr_sw csr_sw_16
472	(
473	// synopsys translate_off
474	.omni_ld (omni_ld),
475	.omni_data (omni_data[16]),
476	.omni_rw_alias (1'b1),
477	.omni_rw1c_alias (1'b0),
478	.omni_rw1s_alias (1'b0),
479	// synopsys translate_on
480	.rst (por_l_active_high),
481	.rst_val (reset_en[16]),
482	.csr_ld (w_ld),
483	.csr_data (csrbus_wr_data[16]),
484	.rw_alias (1'b1),
485	.rw1c_alias (1'b0),
486	.rw1s_alias (1'b0),
487	.hw_ld (1'b0),
488	.hw_data (1'b0),
489	.cp (clk),
490	.q (log_csrbus_read_data[16])
491	);
492
493	// bit 17
494	csr_sw csr_sw_17
495	(
496	// synopsys translate_off
497	.omni_ld (omni_ld),
498	.omni_data (omni_data[17]),
499	.omni_rw_alias (1'b1),
500	.omni_rw1c_alias (1'b0),
501	.omni_rw1s_alias (1'b0),
502	// synopsys translate_on
503	.rst (por_l_active_high),
504	.rst_val (reset_en[17]),
505	.csr_ld (w_ld),
506	.csr_data (csrbus_wr_data[17]),
507	.rw_alias (1'b1),
508	.rw1c_alias (1'b0),
509	.rw1s_alias (1'b0),
510	.hw_ld (1'b0),
511	.hw_data (1'b0),
512	.cp (clk),
513	.q (log_csrbus_read_data[17])
514	);
515
516	// bit 18
517	csr_sw csr_sw_18
518	(
519	// synopsys translate_off
520	.omni_ld (omni_ld),
521	.omni_data (omni_data[18]),
522	.omni_rw_alias (1'b1),
523	.omni_rw1c_alias (1'b0),
524	.omni_rw1s_alias (1'b0),
525	// synopsys translate_on
526	.rst (por_l_active_high),
527	.rst_val (reset_en[18]),
528	.csr_ld (w_ld),
529	.csr_data (csrbus_wr_data[18]),
530	.rw_alias (1'b1),
531	.rw1c_alias (1'b0),
532	.rw1s_alias (1'b0),
533	.hw_ld (1'b0),
534	.hw_data (1'b0),
535	.cp (clk),
536	.q (log_csrbus_read_data[18])
537	);
538
539	// bit 19
540	csr_sw csr_sw_19
541	(
542	// synopsys translate_off
543	.omni_ld (omni_ld),
544	.omni_data (omni_data[19]),
545	.omni_rw_alias (1'b1),
546	.omni_rw1c_alias (1'b0),
547	.omni_rw1s_alias (1'b0),
548	// synopsys translate_on
549	.rst (por_l_active_high),
550	.rst_val (reset_en[19]),
551	.csr_ld (w_ld),
552	.csr_data (csrbus_wr_data[19]),
553	.rw_alias (1'b1),
554	.rw1c_alias (1'b0),
555	.rw1s_alias (1'b0),
556	.hw_ld (1'b0),
557	.hw_data (1'b0),
558	.cp (clk),
559	.q (log_csrbus_read_data[19])
560	);
561
562	// bit 20
563	csr_sw csr_sw_20
564	(
565	// synopsys translate_off
566	.omni_ld (omni_ld),
567	.omni_data (omni_data[20]),
568	.omni_rw_alias (1'b1),
569	.omni_rw1c_alias (1'b0),
570	.omni_rw1s_alias (1'b0),
571	// synopsys translate_on
572	.rst (por_l_active_high),
573	.rst_val (reset_en[20]),
574	.csr_ld (w_ld),
575	.csr_data (csrbus_wr_data[20]),
576	.rw_alias (1'b1),
577	.rw1c_alias (1'b0),
578	.rw1s_alias (1'b0),
579	.hw_ld (1'b0),
580	.hw_data (1'b0),
581	.cp (clk),
582	.q (log_csrbus_read_data[20])
583	);
584
585	assign log_csrbus_read_data[21] = 1'b0; // bit 21
586	assign log_csrbus_read_data[22] = 1'b0; // bit 22
587	assign log_csrbus_read_data[23] = 1'b0; // bit 23
588	assign log_csrbus_read_data[24] = 1'b0; // bit 24
589	assign log_csrbus_read_data[25] = 1'b0; // bit 25
590	assign log_csrbus_read_data[26] = 1'b0; // bit 26
591	assign log_csrbus_read_data[27] = 1'b0; // bit 27
592	assign log_csrbus_read_data[28] = 1'b0; // bit 28
593	assign log_csrbus_read_data[29] = 1'b0; // bit 29
594	assign log_csrbus_read_data[30] = 1'b0; // bit 30
595	assign log_csrbus_read_data[31] = 1'b0; // bit 31
596	assign log_csrbus_read_data[32] = 1'b0; // bit 32
597	assign log_csrbus_read_data[33] = 1'b0; // bit 33
598	assign log_csrbus_read_data[34] = 1'b0; // bit 34
599	assign log_csrbus_read_data[35] = 1'b0; // bit 35
600	assign log_csrbus_read_data[36] = 1'b0; // bit 36
601	assign log_csrbus_read_data[37] = 1'b0; // bit 37
602	assign log_csrbus_read_data[38] = 1'b0; // bit 38
603	assign log_csrbus_read_data[39] = 1'b0; // bit 39
604	assign log_csrbus_read_data[40] = 1'b0; // bit 40
605	assign log_csrbus_read_data[41] = 1'b0; // bit 41
606	assign log_csrbus_read_data[42] = 1'b0; // bit 42
607	assign log_csrbus_read_data[43] = 1'b0; // bit 43
608	assign log_csrbus_read_data[44] = 1'b0; // bit 44
609	assign log_csrbus_read_data[45] = 1'b0; // bit 45
610	assign log_csrbus_read_data[46] = 1'b0; // bit 46
611	assign log_csrbus_read_data[47] = 1'b0; // bit 47
612	assign log_csrbus_read_data[48] = 1'b0; // bit 48
613	assign log_csrbus_read_data[49] = 1'b0; // bit 49
614	assign log_csrbus_read_data[50] = 1'b0; // bit 50
615	assign log_csrbus_read_data[51] = 1'b0; // bit 51
616	assign log_csrbus_read_data[52] = 1'b0; // bit 52
617	assign log_csrbus_read_data[53] = 1'b0; // bit 53
618	assign log_csrbus_read_data[54] = 1'b0; // bit 54
619	assign log_csrbus_read_data[55] = 1'b0; // bit 55
620	assign log_csrbus_read_data[56] = 1'b0; // bit 56
621	assign log_csrbus_read_data[57] = 1'b0; // bit 57
622	assign log_csrbus_read_data[58] = 1'b0; // bit 58
623	assign log_csrbus_read_data[59] = 1'b0; // bit 59
624	assign log_csrbus_read_data[60] = 1'b0; // bit 60
625	assign log_csrbus_read_data[61] = 1'b0; // bit 61
626	assign log_csrbus_read_data[62] = 1'b0; // bit 62
627	assign log_csrbus_read_data[63] = 1'b0; // bit 63
628
629	endmodule // dmu_mmu_csr_log_entry