[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_tcb.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_mmu_tcb.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_mmu_tcb 
  (
   clk,				// clock
   rst_l,			// reset
   crb2tcb_tag,			// crb replacement tag
   csr2tcb_av,			// csr access violation
   csr2tcb_be,			// csr bypass enable
   csr2tcb_cm,			// csr cache mode
   csr2tcb_ds_a,		// csr debug select a
   csr2tcb_ds_b,		// csr debug select b
   csr2tcb_pd,			// csr processing disable
   csr2tcb_te,			// csr translation enable
   pab2tcb_err,			// pab errors
   ptb2tcb_hit,			// ptb physical tag hit
   rcb2tcb_ack, 		// rcb acknowledge
   rcb2tcb_err, 		// rcb error
   rcb2tcb_tag,			// rcb tag
   rcb2tcb_vld, 		// rcb valid
   tlb2tcb_hit,			// tlb virtual tag hit
   vab2tcb_err,			// vab errors
   vab2tcb_vld,			// vab valids
   vab2tcb_sun4v_va_oor,	// sun4v va out of range
   vab2tcb_4vor,		// sun4v out of range error
   vab2tcb_s4uf,		// sun4v underflow error
   qcb2tcb_hld,			// qcb hold
   qcb2tcb_vld,			// qcb valid
   vtb2tcb_hit,			// vtb hit
   tcb2crb_req,			// crb request
   tcb2csr_dbg_a,		// csr debug bus a
   tcb2csr_dbg_b,		// csr debug bus b
   tcb2csr_err, 		// csr errors
   tcb2csr_prf, 		// csr performance events
   tcb2csr_tcm,			// csr tablewalk cache mode
   tcb2csr_tip,			// csr tablewalk in progress
   tcb2csr_tpl,			// csr translation pipeline not empty
   tcb2pab_err,			// pab error
   tcb2pab_sel,			// pab select
   tcb2ptb_sel,			// ptb select
   tcb2ptb_vld,			// ptb valid
   tcb2ptb_wa,			// ptb write address
   tcb2ptb_we,			// ptb write enable
   tcb2qcb_hld,			// qcb hold
   tcb2qcb_vld,			// qcb valids
   tcb2rcb_req, 		// rcb request
   tcb2rcb_tag,			// rcb tag
   tcb2tdb_sel,			// tdb select
   tcb2tdb_wa,			// tdb write address
   tcb2tdb_we,			// tdb write enable
   tcb2tlb_dld,			// tlb data load
   tcb2tlb_hld,			// tlb holds
   tcb2tlb_ra,			// tlb read address
   tcb2tlb_ras,			// tlb read address select
   tcb2tlb_sel,			// tlb select
   tcb2tlb_tld,			// tlb tag load
   tcb2vab_hld,			// vab hold
   tcb2vtb_hld,			// vtb holds
   tcb2vtb_sel,			// vtb select
   tcb2vtb_tmv,			// vtb translation mode valid
   tcb2vtb_vld,			// vtb valid
   tcb2vtb_wa,			// vtb write address
   vaq2tcb_deq_en,
   tcb2vtb_we,			// vtb write enable
   tdb2tmc_kerr,		// tdb key error on ppn readout from tdb ram readout
   tlb2tmc_kerr,		// tdb key error on ppn readout from single entry tlb
   srq2tmc_ipe,			// iotsb parity error
   srq2tmc_ivld,		// iotsb valid bit and'ed with sun4v_mode
   sun4v_mode,			// 1= sun4v_mode
   srq2tmc_sun4v_pgsz_err	// 1 = sun4v_mode illegal page size
   );

// ----------------------------------------------------------------------------
// Ports
// ----------------------------------------------------------------------------
  input 		 		clk;
  input 		 		rst_l;

  input [`FIRE_DLC_MMU_TAG_PTR_BITS]	crb2tcb_tag;
  input 				csr2tcb_av;
  input 				csr2tcb_be;
  input [`FIRE_DLC_MMU_CSR_CM_BITS]	csr2tcb_cm;
  input [`FIRE_DLC_MMU_CSR_DS_BITS]	csr2tcb_ds_a;
  input [`FIRE_DLC_MMU_CSR_DS_BITS]	csr2tcb_ds_b;
  input 				csr2tcb_pd;
  input 				csr2tcb_te;
  input [`FIRE_DLC_MMU_PAB_ERR_BITS]	pab2tcb_err;
  input 				ptb2tcb_hit;
  input 				rcb2tcb_ack;
  input [`FIRE_DLC_MMU_RCB_ERR_BITS]	rcb2tcb_err;
  input [`FIRE_DLC_MMU_TAG_PTR_BITS]	rcb2tcb_tag;
  input 				rcb2tcb_vld;
  input 				tlb2tcb_hit;
  input [`FIRE_DLC_MMU_VAB_ERR_BITS]	vab2tcb_err;
  input [`FIRE_DLC_MMU_VAB_VLD_BITS]	vab2tcb_vld;
  input 				vab2tcb_sun4v_va_oor;
  input 				vab2tcb_4vor;
  input 				vab2tcb_s4uf;
  input 				qcb2tcb_hld;
  input 				qcb2tcb_vld;
  input 				vtb2tcb_hit;
  input 				vaq2tcb_deq_en;
  input 				tdb2tmc_kerr;
  input 				tlb2tmc_kerr;
  input 				srq2tmc_ipe;
  input 				srq2tmc_ivld;
  input 				sun4v_mode;
  input 				srq2tmc_sun4v_pgsz_err;

  output				tcb2crb_req;
  output [`FIRE_DBG_DATA_BITS]		tcb2csr_dbg_a;
  output [`FIRE_DBG_DATA_BITS]		tcb2csr_dbg_b;
  output [`FIRE_DLC_MMU_CSR_ERR_BITS]	tcb2csr_err;
  output [`FIRE_DLC_MMU_TCB_PRF_BITS]	tcb2csr_prf;
  output [`FIRE_DLC_MMU_CSR_CM_BITS]	tcb2csr_tcm;
  output				tcb2csr_tip;
  output				tcb2csr_tpl;
  output				tcb2pab_err;
  output				tcb2pab_sel;
  output				tcb2ptb_sel;
  output				tcb2ptb_vld;
  output [`FIRE_DLC_MMU_TAG_PTR_BITS]	tcb2ptb_wa;
  output				tcb2ptb_we;
  output				tcb2qcb_hld;
  output [`FIRE_DLC_MMU_PLS_DPTH:1]	tcb2qcb_vld;
  output				tcb2rcb_req;
  output [`FIRE_DLC_MMU_TAG_PTR_BITS]	tcb2rcb_tag;
  output				tcb2tdb_sel;
  output [`FIRE_DLC_MMU_TDB_PTR_BITS]	tcb2tdb_wa;
  output				tcb2tdb_we;
  output				tcb2tlb_dld;
  output				tcb2tlb_hld;
  output [`FILE_DLC_MMU_TTE_CNT_BITS]	tcb2tlb_ra;
  output				tcb2tlb_ras;
  output				tcb2tlb_sel;
  output				tcb2tlb_tld;
  output				tcb2vab_hld;
  output				tcb2vtb_hld;
  output				tcb2vtb_sel;
  output				tcb2vtb_tmv;
  output				tcb2vtb_vld;
  output [`FIRE_DLC_MMU_TAG_PTR_BITS]	tcb2vtb_wa;
  output				tcb2vtb_we;

// ----------------------------------------------------------------------------
// Variables
// ----------------------------------------------------------------------------
  wire					tcb2crb_req;
  wire [`FIRE_DBG_DATA_BITS]		tcb2csr_dbg_a;
  wire [`FIRE_DBG_DATA_BITS]		tcb2csr_dbg_b;
  wire [`FIRE_DLC_MMU_CSR_ERR_BITS]	tcb2csr_err;
  wire [`FIRE_DLC_MMU_TCB_PRF_BITS]	tcb2csr_prf;
  wire [`FIRE_DLC_MMU_CSR_CM_BITS]	tcb2csr_tcm;
  wire					tcb2csr_tip;
  wire					tcb2csr_tpl;
  wire					tcb2pab_err;
  wire					tcb2pab_sel;
  wire					tcb2ptb_sel;
  wire					tcb2ptb_vld;
  wire [`FIRE_DLC_MMU_TAG_PTR_BITS]	tcb2ptb_wa;
  wire					tcb2ptb_we;
  wire					tcb2qcb_hld;
  wire [`FIRE_DLC_MMU_PLS_DPTH:1]	tcb2qcb_vld;
  wire					tcb2rcb_req;
  wire [`FIRE_DLC_MMU_TAG_PTR_BITS]	tcb2rcb_tag;
  wire					tcb2tdb_sel;
  wire [`FIRE_DLC_MMU_TDB_PTR_BITS]	tcb2tdb_wa;
  wire					tcb2tdb_we;
  wire					tcb2tlb_dld;
  wire					tcb2tlb_hld;
  wire [`FILE_DLC_MMU_TTE_CNT_BITS]	tcb2tlb_ra;
  wire					tcb2tlb_ras;
  wire					tcb2tlb_sel;
  wire					tcb2tlb_tld;
  wire					tcb2vab_hld;
  wire					tcb2vtb_hld;
  wire					tcb2vtb_sel;
  wire					tcb2vtb_tmv;
  wire					tcb2vtb_vld;
  wire [`FIRE_DLC_MMU_TAG_PTR_BITS]	tcb2vtb_wa;
  wire					tcb2vtb_we;
  wire					tcc2tdc_cld;
  wire					tcc2tdc_req;
  wire [`FIRE_DLC_MMU_TAG_PTR_BITS]	tcc2tdc_tag;
  wire					tcc2tmc_ack;
  wire [`FIRE_DBG_DATA_BITS]		tcc2tmc_dbg;
  wire					tcc2tmc_vld;
  wire					tdc2tcc_ack;
  wire					tdc2tcc_err;
  wire [`FIRE_DBG_DATA_BITS]		tdc2tmc_dbg;
  wire [`FIRE_DLC_MMU_TDC_ERR_BITS]	tdc2tmc_err;
  wire					tmc2tcc_req;
  wire					srq2tmc_ivld;
  wire					sun4v_mode;

// ----------------------------------------------------------------------------
// Instantiations
// ----------------------------------------------------------------------------
  dmu_mmu_tcb_tcc tcc
    (
     .clk		(clk),
     .rst_l		(rst_l),
     .crb2tcb_tag	(crb2tcb_tag),
     .csr2tcb_cm	(csr2tcb_cm),
     .ptb2tcb_hit	(ptb2tcb_hit),
     .rcb2tcb_ack	(rcb2tcb_ack),
     .tdc2tcc_ack	(tdc2tcc_ack),
     .tdc2tcc_err	(tdc2tcc_err),
     .tmc2tcc_req	(tmc2tcc_req),
     .tcb2crb_req	(tcb2crb_req),
     .tcb2csr_tcm	(tcb2csr_tcm),
     .tcb2csr_tip	(tcb2csr_tip),
     .tcb2ptb_sel	(tcb2ptb_sel),
     .tcb2ptb_vld	(tcb2ptb_vld),
     .tcb2ptb_wa	(tcb2ptb_wa),
     .tcb2ptb_we	(tcb2ptb_we),
     .tcb2rcb_req	(tcb2rcb_req),
     .tcb2rcb_tag	(tcb2rcb_tag),
     .tcb2tdb_sel	(tcb2tdb_sel),
     .tcb2tlb_tld	(tcb2tlb_tld),
     .tcb2vtb_sel	(tcb2vtb_sel),
     .tcb2vtb_vld	(tcb2vtb_vld),
     .tcb2vtb_wa	(tcb2vtb_wa),
     .tcb2vtb_we	(tcb2vtb_we),
     .tcc2tdc_cld	(tcc2tdc_cld),
     .tcc2tdc_req	(tcc2tdc_req),
     .tcc2tdc_tag	(tcc2tdc_tag),
     .tcc2tmc_ack	(tcc2tmc_ack),
     .tcc2tmc_dbg	(tcc2tmc_dbg),
     .tcc2tmc_vld	(tcc2tmc_vld)
     );

  dmu_mmu_tcb_tdc tdc
    (
     .clk		(clk),
     .rst_l		(rst_l),
     .rcb2tcb_err	(rcb2tcb_err),
     .rcb2tcb_tag	(rcb2tcb_tag),
     .rcb2tcb_vld	(rcb2tcb_vld),
     .tcc2tdc_cld	(tcc2tdc_cld),
     .tcc2tdc_req	(tcc2tdc_req),
     .tcc2tdc_tag	(tcc2tdc_tag),
     .tcb2tdb_wa	(tcb2tdb_wa),
     .tcb2tdb_we	(tcb2tdb_we),
     .tcb2tlb_dld	(tcb2tlb_dld),
     .tcb2tlb_ra	(tcb2tlb_ra),
     .tcb2tlb_ras	(tcb2tlb_ras),
     .tdc2tcc_ack	(tdc2tcc_ack),
     .tdc2tcc_err	(tdc2tcc_err),
     .tdc2tmc_dbg	(tdc2tmc_dbg),
     .tdc2tmc_err	(tdc2tmc_err)
     );

  dmu_mmu_tcb_tmc tmc
    (
     .clk		(clk),
     .rst_l		(rst_l),
     .csr2tcb_av	(csr2tcb_av),
     .csr2tcb_be	(csr2tcb_be),
     .csr2tcb_cm	(csr2tcb_cm),
     .csr2tcb_ds_a	(csr2tcb_ds_a),
     .csr2tcb_ds_b	(csr2tcb_ds_b),
     .csr2tcb_pd	(csr2tcb_pd),
     .csr2tcb_te	(csr2tcb_te),
     .pab2tcb_err	(pab2tcb_err),
     .tlb2tcb_hit	(tlb2tcb_hit),
     .vab2tcb_err	(vab2tcb_err),
     .vab2tcb_vld	(vab2tcb_vld),
     .vab2tcb_sun4v_va_oor (vab2tcb_sun4v_va_oor),
     .vab2tcb_4vor	(vab2tcb_4vor),
     .vab2tcb_s4uf	(vab2tcb_s4uf),
     .qcb2tcb_hld	(qcb2tcb_hld),
     .qcb2tcb_vld	(qcb2tcb_vld),
     .vtb2tcb_hit	(vtb2tcb_hit),
     .tcc2tmc_ack	(tcc2tmc_ack),
     .tcc2tmc_dbg	(tcc2tmc_dbg),
     .tcc2tmc_vld	(tcc2tmc_vld),
     .tdc2tmc_dbg	(tdc2tmc_dbg),
     .tdc2tmc_err	(tdc2tmc_err),
     .tcb2csr_dbg_a	(tcb2csr_dbg_a),
     .tcb2csr_dbg_b	(tcb2csr_dbg_b),
     .tcb2csr_err	(tcb2csr_err),
     .tcb2csr_prf	(tcb2csr_prf),
     .tcb2csr_tpl	(tcb2csr_tpl),
     .tcb2pab_err	(tcb2pab_err),
     .tcb2pab_sel	(tcb2pab_sel),
     .tcb2qcb_hld	(tcb2qcb_hld),
     .tcb2qcb_vld	(tcb2qcb_vld),
     .tcb2tlb_hld	(tcb2tlb_hld),
     .tcb2tlb_sel	(tcb2tlb_sel),
     .tcb2vab_hld	(tcb2vab_hld),
     .tcb2vtb_hld	(tcb2vtb_hld),
     .tcb2vtb_tmv	(tcb2vtb_tmv),
     .vaq2tcb_deq_en    (vaq2tcb_deq_en),
     .tmc2tcc_req	(tmc2tcc_req),
     .tdb2tmc_kerr	(tdb2tmc_kerr),
     .tlb2tmc_kerr	(tlb2tmc_kerr),
     .srq2tmc_ipe	(srq2tmc_ipe),
     .srq2tmc_ivld	(srq2tmc_ivld),
     .sun4v_mode	(sun4v_mode),
     .srq2tmc_sun4v_pgsz_err	(srq2tmc_sun4v_pgsz_err)
     );

endmodule // dmu_mmu_tcb
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_mmu_tcb.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_mmu_tcb
	36	(
	37	clk, // clock
	38	rst_l, // reset
	39	crb2tcb_tag, // crb replacement tag
	40	csr2tcb_av, // csr access violation
	41	csr2tcb_be, // csr bypass enable
	42	csr2tcb_cm, // csr cache mode
	43	csr2tcb_ds_a, // csr debug select a
	44	csr2tcb_ds_b, // csr debug select b
	45	csr2tcb_pd, // csr processing disable
	46	csr2tcb_te, // csr translation enable
	47	pab2tcb_err, // pab errors
	48	ptb2tcb_hit, // ptb physical tag hit
	49	rcb2tcb_ack, // rcb acknowledge
	50	rcb2tcb_err, // rcb error
	51	rcb2tcb_tag, // rcb tag
	52	rcb2tcb_vld, // rcb valid
	53	tlb2tcb_hit, // tlb virtual tag hit
	54	vab2tcb_err, // vab errors
	55	vab2tcb_vld, // vab valids
	56	vab2tcb_sun4v_va_oor, // sun4v va out of range
	57	vab2tcb_4vor, // sun4v out of range error
	58	vab2tcb_s4uf, // sun4v underflow error
	59	qcb2tcb_hld, // qcb hold
	60	qcb2tcb_vld, // qcb valid
	61	vtb2tcb_hit, // vtb hit
	62	tcb2crb_req, // crb request
	63	tcb2csr_dbg_a, // csr debug bus a
	64	tcb2csr_dbg_b, // csr debug bus b
65	tcb2csr_err, // csr errors
66	tcb2csr_prf, // csr performance events
67	tcb2csr_tcm, // csr tablewalk cache mode
68	tcb2csr_tip, // csr tablewalk in progress
69	tcb2csr_tpl, // csr translation pipeline not empty
70	tcb2pab_err, // pab error
71	tcb2pab_sel, // pab select
72	tcb2ptb_sel, // ptb select
73	tcb2ptb_vld, // ptb valid
74	tcb2ptb_wa, // ptb write address
75	tcb2ptb_we, // ptb write enable
76	tcb2qcb_hld, // qcb hold
77	tcb2qcb_vld, // qcb valids
78	tcb2rcb_req, // rcb request
79	tcb2rcb_tag, // rcb tag
80	tcb2tdb_sel, // tdb select
81	tcb2tdb_wa, // tdb write address
82	tcb2tdb_we, // tdb write enable
83	tcb2tlb_dld, // tlb data load
84	tcb2tlb_hld, // tlb holds
85	tcb2tlb_ra, // tlb read address
86	tcb2tlb_ras, // tlb read address select
87	tcb2tlb_sel, // tlb select
88	tcb2tlb_tld, // tlb tag load
89	tcb2vab_hld, // vab hold
90	tcb2vtb_hld, // vtb holds
91	tcb2vtb_sel, // vtb select
92	tcb2vtb_tmv, // vtb translation mode valid
93	tcb2vtb_vld, // vtb valid
94	tcb2vtb_wa, // vtb write address
95	vaq2tcb_deq_en,
96	tcb2vtb_we, // vtb write enable
97	tdb2tmc_kerr, // tdb key error on ppn readout from tdb ram readout
98	tlb2tmc_kerr, // tdb key error on ppn readout from single entry tlb
99	srq2tmc_ipe, // iotsb parity error
100	srq2tmc_ivld, // iotsb valid bit and'ed with sun4v_mode
101	sun4v_mode, // 1= sun4v_mode
102	srq2tmc_sun4v_pgsz_err // 1 = sun4v_mode illegal page size
103	);
104
105	// ----------------------------------------------------------------------------
106	// Ports
107	// ----------------------------------------------------------------------------
108	input clk;
109	input rst_l;
110
111	input [`FIRE_DLC_MMU_TAG_PTR_BITS] crb2tcb_tag;
112	input csr2tcb_av;
113	input csr2tcb_be;
114	input [`FIRE_DLC_MMU_CSR_CM_BITS] csr2tcb_cm;
115	input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2tcb_ds_a;
116	input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2tcb_ds_b;
117	input csr2tcb_pd;
118	input csr2tcb_te;
119	input [`FIRE_DLC_MMU_PAB_ERR_BITS] pab2tcb_err;
120	input ptb2tcb_hit;
121	input rcb2tcb_ack;
122	input [`FIRE_DLC_MMU_RCB_ERR_BITS] rcb2tcb_err;
123	input [`FIRE_DLC_MMU_TAG_PTR_BITS] rcb2tcb_tag;
124	input rcb2tcb_vld;
125	input tlb2tcb_hit;
126	input [`FIRE_DLC_MMU_VAB_ERR_BITS] vab2tcb_err;
127	input [`FIRE_DLC_MMU_VAB_VLD_BITS] vab2tcb_vld;
128	input vab2tcb_sun4v_va_oor;
129	input vab2tcb_4vor;
130	input vab2tcb_s4uf;
131	input qcb2tcb_hld;
132	input qcb2tcb_vld;
133	input vtb2tcb_hit;
134	input vaq2tcb_deq_en;
135	input tdb2tmc_kerr;
136	input tlb2tmc_kerr;
137	input srq2tmc_ipe;
138	input srq2tmc_ivld;
139	input sun4v_mode;
140	input srq2tmc_sun4v_pgsz_err;
141
142	output tcb2crb_req;
143	output [`FIRE_DBG_DATA_BITS] tcb2csr_dbg_a;
144	output [`FIRE_DBG_DATA_BITS] tcb2csr_dbg_b;
145	output [`FIRE_DLC_MMU_CSR_ERR_BITS] tcb2csr_err;
146	output [`FIRE_DLC_MMU_TCB_PRF_BITS] tcb2csr_prf;
147	output [`FIRE_DLC_MMU_CSR_CM_BITS] tcb2csr_tcm;
148	output tcb2csr_tip;
149	output tcb2csr_tpl;
150	output tcb2pab_err;
151	output tcb2pab_sel;
152	output tcb2ptb_sel;
153	output tcb2ptb_vld;
154	output [`FIRE_DLC_MMU_TAG_PTR_BITS] tcb2ptb_wa;
155	output tcb2ptb_we;
156	output tcb2qcb_hld;
157	output [`FIRE_DLC_MMU_PLS_DPTH:1] tcb2qcb_vld;
158	output tcb2rcb_req;
159	output [`FIRE_DLC_MMU_TAG_PTR_BITS] tcb2rcb_tag;
160	output tcb2tdb_sel;
161	output [`FIRE_DLC_MMU_TDB_PTR_BITS] tcb2tdb_wa;
162	output tcb2tdb_we;
163	output tcb2tlb_dld;
164	output tcb2tlb_hld;
165	output [`FILE_DLC_MMU_TTE_CNT_BITS] tcb2tlb_ra;
166	output tcb2tlb_ras;
167	output tcb2tlb_sel;
168	output tcb2tlb_tld;
169	output tcb2vab_hld;
170	output tcb2vtb_hld;
171	output tcb2vtb_sel;
172	output tcb2vtb_tmv;
173	output tcb2vtb_vld;
174	output [`FIRE_DLC_MMU_TAG_PTR_BITS] tcb2vtb_wa;
175	output tcb2vtb_we;
176
177	// ----------------------------------------------------------------------------
178	// Variables
179	// ----------------------------------------------------------------------------
180	wire tcb2crb_req;
181	wire [`FIRE_DBG_DATA_BITS] tcb2csr_dbg_a;
182	wire [`FIRE_DBG_DATA_BITS] tcb2csr_dbg_b;
183	wire [`FIRE_DLC_MMU_CSR_ERR_BITS] tcb2csr_err;
184	wire [`FIRE_DLC_MMU_TCB_PRF_BITS] tcb2csr_prf;
185	wire [`FIRE_DLC_MMU_CSR_CM_BITS] tcb2csr_tcm;
186	wire tcb2csr_tip;
187	wire tcb2csr_tpl;
188	wire tcb2pab_err;
189	wire tcb2pab_sel;
190	wire tcb2ptb_sel;
191	wire tcb2ptb_vld;
192	wire [`FIRE_DLC_MMU_TAG_PTR_BITS] tcb2ptb_wa;
193	wire tcb2ptb_we;
194	wire tcb2qcb_hld;
195	wire [`FIRE_DLC_MMU_PLS_DPTH:1] tcb2qcb_vld;
196	wire tcb2rcb_req;
197	wire [`FIRE_DLC_MMU_TAG_PTR_BITS] tcb2rcb_tag;
198	wire tcb2tdb_sel;
199	wire [`FIRE_DLC_MMU_TDB_PTR_BITS] tcb2tdb_wa;
200	wire tcb2tdb_we;
201	wire tcb2tlb_dld;
202	wire tcb2tlb_hld;
203	wire [`FILE_DLC_MMU_TTE_CNT_BITS] tcb2tlb_ra;
204	wire tcb2tlb_ras;
205	wire tcb2tlb_sel;
206	wire tcb2tlb_tld;
207	wire tcb2vab_hld;
208	wire tcb2vtb_hld;
209	wire tcb2vtb_sel;
210	wire tcb2vtb_tmv;
211	wire tcb2vtb_vld;
212	wire [`FIRE_DLC_MMU_TAG_PTR_BITS] tcb2vtb_wa;
213	wire tcb2vtb_we;
214	wire tcc2tdc_cld;
215	wire tcc2tdc_req;
216	wire [`FIRE_DLC_MMU_TAG_PTR_BITS] tcc2tdc_tag;
217	wire tcc2tmc_ack;
218	wire [`FIRE_DBG_DATA_BITS] tcc2tmc_dbg;
219	wire tcc2tmc_vld;
220	wire tdc2tcc_ack;
221	wire tdc2tcc_err;
222	wire [`FIRE_DBG_DATA_BITS] tdc2tmc_dbg;
223	wire [`FIRE_DLC_MMU_TDC_ERR_BITS] tdc2tmc_err;
224	wire tmc2tcc_req;
225	wire srq2tmc_ivld;
226	wire sun4v_mode;
227
228	// ----------------------------------------------------------------------------
229	// Instantiations
230	// ----------------------------------------------------------------------------
231	dmu_mmu_tcb_tcc tcc
232	(
233	.clk (clk),
234	.rst_l (rst_l),
235	.crb2tcb_tag (crb2tcb_tag),
236	.csr2tcb_cm (csr2tcb_cm),
237	.ptb2tcb_hit (ptb2tcb_hit),
238	.rcb2tcb_ack (rcb2tcb_ack),
239	.tdc2tcc_ack (tdc2tcc_ack),
240	.tdc2tcc_err (tdc2tcc_err),
241	.tmc2tcc_req (tmc2tcc_req),
242	.tcb2crb_req (tcb2crb_req),
243	.tcb2csr_tcm (tcb2csr_tcm),
244	.tcb2csr_tip (tcb2csr_tip),
245	.tcb2ptb_sel (tcb2ptb_sel),
246	.tcb2ptb_vld (tcb2ptb_vld),
247	.tcb2ptb_wa (tcb2ptb_wa),
248	.tcb2ptb_we (tcb2ptb_we),
249	.tcb2rcb_req (tcb2rcb_req),
250	.tcb2rcb_tag (tcb2rcb_tag),
251	.tcb2tdb_sel (tcb2tdb_sel),
252	.tcb2tlb_tld (tcb2tlb_tld),
253	.tcb2vtb_sel (tcb2vtb_sel),
254	.tcb2vtb_vld (tcb2vtb_vld),
255	.tcb2vtb_wa (tcb2vtb_wa),
256	.tcb2vtb_we (tcb2vtb_we),
257	.tcc2tdc_cld (tcc2tdc_cld),
258	.tcc2tdc_req (tcc2tdc_req),
259	.tcc2tdc_tag (tcc2tdc_tag),
260	.tcc2tmc_ack (tcc2tmc_ack),
261	.tcc2tmc_dbg (tcc2tmc_dbg),
262	.tcc2tmc_vld (tcc2tmc_vld)
263	);
264
265	dmu_mmu_tcb_tdc tdc
266	(
267	.clk (clk),
268	.rst_l (rst_l),
269	.rcb2tcb_err (rcb2tcb_err),
270	.rcb2tcb_tag (rcb2tcb_tag),
271	.rcb2tcb_vld (rcb2tcb_vld),
272	.tcc2tdc_cld (tcc2tdc_cld),
273	.tcc2tdc_req (tcc2tdc_req),
274	.tcc2tdc_tag (tcc2tdc_tag),
275	.tcb2tdb_wa (tcb2tdb_wa),
276	.tcb2tdb_we (tcb2tdb_we),
277	.tcb2tlb_dld (tcb2tlb_dld),
278	.tcb2tlb_ra (tcb2tlb_ra),
279	.tcb2tlb_ras (tcb2tlb_ras),
280	.tdc2tcc_ack (tdc2tcc_ack),
281	.tdc2tcc_err (tdc2tcc_err),
282	.tdc2tmc_dbg (tdc2tmc_dbg),
283	.tdc2tmc_err (tdc2tmc_err)
284	);
285
286	dmu_mmu_tcb_tmc tmc
287	(
288	.clk (clk),
289	.rst_l (rst_l),
290	.csr2tcb_av (csr2tcb_av),
291	.csr2tcb_be (csr2tcb_be),
292	.csr2tcb_cm (csr2tcb_cm),
293	.csr2tcb_ds_a (csr2tcb_ds_a),
294	.csr2tcb_ds_b (csr2tcb_ds_b),
295	.csr2tcb_pd (csr2tcb_pd),
296	.csr2tcb_te (csr2tcb_te),
297	.pab2tcb_err (pab2tcb_err),
298	.tlb2tcb_hit (tlb2tcb_hit),
299	.vab2tcb_err (vab2tcb_err),
300	.vab2tcb_vld (vab2tcb_vld),
301	.vab2tcb_sun4v_va_oor (vab2tcb_sun4v_va_oor),
302	.vab2tcb_4vor (vab2tcb_4vor),
303	.vab2tcb_s4uf (vab2tcb_s4uf),
304	.qcb2tcb_hld (qcb2tcb_hld),
305	.qcb2tcb_vld (qcb2tcb_vld),
306	.vtb2tcb_hit (vtb2tcb_hit),
307	.tcc2tmc_ack (tcc2tmc_ack),
308	.tcc2tmc_dbg (tcc2tmc_dbg),
309	.tcc2tmc_vld (tcc2tmc_vld),
310	.tdc2tmc_dbg (tdc2tmc_dbg),
311	.tdc2tmc_err (tdc2tmc_err),
312	.tcb2csr_dbg_a (tcb2csr_dbg_a),
313	.tcb2csr_dbg_b (tcb2csr_dbg_b),
314	.tcb2csr_err (tcb2csr_err),
315	.tcb2csr_prf (tcb2csr_prf),
316	.tcb2csr_tpl (tcb2csr_tpl),
317	.tcb2pab_err (tcb2pab_err),
318	.tcb2pab_sel (tcb2pab_sel),
319	.tcb2qcb_hld (tcb2qcb_hld),
320	.tcb2qcb_vld (tcb2qcb_vld),
321	.tcb2tlb_hld (tcb2tlb_hld),
322	.tcb2tlb_sel (tcb2tlb_sel),
323	.tcb2vab_hld (tcb2vab_hld),
324	.tcb2vtb_hld (tcb2vtb_hld),
325	.tcb2vtb_tmv (tcb2vtb_tmv),
326	.vaq2tcb_deq_en (vaq2tcb_deq_en),
327	.tmc2tcc_req (tmc2tcc_req),
328	.tdb2tmc_kerr (tdb2tmc_kerr),
329	.tlb2tmc_kerr (tlb2tmc_kerr),
330	.srq2tmc_ipe (srq2tmc_ipe),
331	.srq2tmc_ivld (srq2tmc_ivld),
332	.sun4v_mode (sun4v_mode),
333	.srq2tmc_sun4v_pgsz_err (srq2tmc_sun4v_pgsz_err)
334	);
335
336	endmodule // dmu_mmu_tcb