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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_rmu.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_rmu ( | |
36 | clk, | |
37 | rst_l, | |
38 | ||
39 | // Core Level Signals - RMU <-> JBC interface | |
40 | ||
41 | d2j_p_wrack_tag, | |
42 | d2j_p_wrack_vld, | |
43 | ||
44 | // Core Level Signals - RMU <-> ILU interface | |
45 | ||
46 | y2k_rel_rcd, | |
47 | y2k_rel_enq, | |
48 | ||
49 | // EPE Record | |
50 | k2y_rcd, | |
51 | k2y_rcd_enq, | |
52 | y2k_rcd_deq, | |
53 | ||
54 | ||
55 | // TMU Interface | |
56 | ||
57 | // DIM Record | |
58 | tm2rm_rcd, | |
59 | tm2rm_rcd_enq, | |
60 | rm2tm_rcd_full, | |
61 | ||
62 | ||
63 | // IMU Interface | |
64 | ||
65 | // Interrupt In Record | |
66 | rm2im_rcd, | |
67 | rm2im_rcd_enq, | |
68 | ||
69 | // Interrupt Out Record | |
70 | im2rm_rcd, | |
71 | im2rm_rcd_enq, | |
72 | ||
73 | // Mondo ReQuest Record | |
74 | im2rm_mdo, | |
75 | im2rm_mdo_enq, | |
76 | ||
77 | // Mondo Reply record | |
78 | rm2im_rply, | |
79 | rm2im_rply_enq, | |
80 | ||
81 | // PIO mem64 offset Reg | |
82 | im2rm_mem64_offset_reg, | |
83 | ||
84 | ||
85 | // TSB Interface | |
86 | ||
87 | rm2ts_i_cmd_type, | |
88 | rm2ts_i_wr_data, | |
89 | rm2ts_i_req, | |
90 | ts2rm_i_gnt, | |
91 | ts2rm_i_full, | |
92 | ts2rm_i_n_trn, | |
93 | ||
94 | rm2ts_e_cmd_type, | |
95 | rm2ts_e_wr_data, | |
96 | rm2ts_e_trn, | |
97 | rm2ts_e_req, | |
98 | ts2rm_e_gnt, | |
99 | ts2rm_e_rd_data, | |
100 | ||
101 | ||
102 | // MMU Interface | |
103 | ||
104 | // SRM Record | |
105 | rm2mm_rcd, | |
106 | rm2mm_rcd_enq, | |
107 | mm2rm_rcd_full, | |
108 | ||
109 | ||
110 | // CMU Interface | |
111 | ||
112 | // Retire Record | |
113 | cm2rm_rcd, | |
114 | cm2rm_rcd_enq, | |
115 | rm2cm_rcd_full, | |
116 | ||
117 | ||
118 | // CLU Interface | |
119 | ||
120 | // DMA Rd Buffer Release Record | |
121 | rm2cl_bufrel, | |
122 | rm2cl_bufrel_enq, | |
123 | ||
124 | ||
125 | // CRU Interface | |
126 | ||
127 | // Fire's Programmable Reqid (PIO), CompletionID (DMA) | |
128 | cr2rm_req_id, | |
129 | ||
130 | // Debug Ports | |
131 | cr2rm_dbg_sel_a, | |
132 | cr2rm_dbg_sel_b, | |
133 | ||
134 | rm2cr_dbg_a, | |
135 | rm2cr_dbg_b, | |
136 | ||
137 | rm2crm_npwr_wrack | |
138 | ||
139 | ); | |
140 | ||
141 | ||
142 | ||
143 | //############################################################################ | |
144 | // PORT DECLARATIONS | |
145 | //############################################################################ | |
146 | ||
147 | //------------------------------------------------------------------------ | |
148 | // Clock and Reset Signals | |
149 | //------------------------------------------------------------------------ | |
150 | input clk; | |
151 | input rst_l; | |
152 | ||
153 | ||
154 | //------------------------------------------------------------------------ | |
155 | // JBC Interface | |
156 | //------------------------------------------------------------------------ | |
157 | ||
158 | // Copy of original JBC PIO request 4 bit tag - and corresponding valid signal | |
159 | output [`FIRE_D2J_P_WRACK_WDTH-1:0] d2j_p_wrack_tag; | |
160 | output d2j_p_wrack_vld; | |
161 | ||
162 | ||
163 | //------------------------------------------------------------------------ | |
164 | // ILU Interface | |
165 | //------------------------------------------------------------------------ | |
166 | ||
167 | // 9 bit Downbound Release Rcd from EIL - (PIO Cpl and DMA Rd buffer release) | |
168 | input [`FIRE_DLC_DRR_REC_WDTH-1:0] y2k_rel_rcd; | |
169 | input y2k_rel_enq; | |
170 | ||
171 | // Egress pipeline interface - EPE (Egress PEC record) (RRM to ILU) | |
172 | output [`FIRE_DLC_EPE_REC_WDTH-1:0] k2y_rcd; | |
173 | output k2y_rcd_enq; | |
174 | input y2k_rcd_deq; | |
175 | ||
176 | ||
177 | //------------------------------------------------------------------------ | |
178 | // TMU Interface | |
179 | //------------------------------------------------------------------------ | |
180 | ||
181 | // Ingress pipeline interface - DIM RECORD (DIM to LRM) | |
182 | input [`FIRE_DLC_DIM_REC_WDTH-1:0] tm2rm_rcd; | |
183 | input tm2rm_rcd_enq; | |
184 | output rm2tm_rcd_full; | |
185 | ||
186 | ||
187 | //------------------------------------------------------------------------ | |
188 | // CMU Interface | |
189 | //------------------------------------------------------------------------ | |
190 | ||
191 | // Egress pipeline interface - RETIRE RECORD (TCM to RRM) | |
192 | input [`FIRE_DLC_ERR_REC_WDTH-1:0] cm2rm_rcd; | |
193 | input cm2rm_rcd_enq; | |
194 | output rm2cm_rcd_full; | |
195 | ||
196 | ||
197 | //------------------------------------------------------------------------ | |
198 | // IMU Interface | |
199 | //------------------------------------------------------------------------ | |
200 | ||
201 | // INTERRUPT IN Record for IMU servicing (LRM to IMU) | |
202 | output [`FIRE_DLC_IIN_REC_WDTH-1:0] rm2im_rcd; | |
203 | output rm2im_rcd_enq; | |
204 | ||
205 | // INTERRUPT OUT Record - record processed by IMU (IMU to LRM) | |
206 | input [`FIRE_DLC_IOT_REC_WDTH-1:0] im2rm_rcd; | |
207 | input im2rm_rcd_enq; | |
208 | ||
209 | // Mondo ReQuest Record (IMU to LRM) | |
210 | input [`FIRE_DLC_MQR_REC_WDTH-1:0] im2rm_mdo; | |
211 | input im2rm_mdo_enq; | |
212 | ||
213 | // Mondo Reply Record (RRM to IMU) | |
214 | output [`FIRE_DLC_MRR_REC_WDTH-1:0] rm2im_rply; | |
215 | output rm2im_rply_enq; | |
216 | ||
217 | input [`FIRE_DLC_SCW_MEM64_WDTH-1:0] im2rm_mem64_offset_reg; // 40 bit field | |
218 | ||
219 | ||
220 | //------------------------------------------------------------------------ | |
221 | // TSB Interfacs | |
222 | //------------------------------------------------------------------------ | |
223 | ||
224 | // SRM <-> TSB interface (Ingress Pipeline) | |
225 | output [`FIRE_DLC_TSR_CMD_TYPE_WDTH-1:0] rm2ts_i_cmd_type; | |
226 | output [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] rm2ts_i_wr_data; | |
227 | output rm2ts_i_req; | |
228 | ||
229 | input ts2rm_i_gnt; | |
230 | input ts2rm_i_full; | |
231 | input [`FIRE_DLC_TSR_TRN_WDTH-1:0] ts2rm_i_n_trn; | |
232 | ||
233 | ||
234 | // RRM <-> TSB interface (Egress Pipeline) | |
235 | ||
236 | output [`FIRE_DLC_TSR_CMD_TYPE_WDTH-1:0] rm2ts_e_cmd_type; | |
237 | output [`FIRE_DLC_TSR_WR_DATA_WDTH-1:0] rm2ts_e_wr_data; | |
238 | output [`FIRE_DLC_TSR_TRN_WDTH-1:0] rm2ts_e_trn; | |
239 | output rm2ts_e_req; | |
240 | ||
241 | input ts2rm_e_gnt; | |
242 | input [`FIRE_DLC_TSR_RD_DATA_WDTH-1:0] ts2rm_e_rd_data; | |
243 | ||
244 | ||
245 | //------------------------------------------------------------------------ | |
246 | // MMU Interface | |
247 | //------------------------------------------------------------------------ | |
248 | ||
249 | // Ingress pipeline interface - SRM RECORD (SRM to MMU) | |
250 | ||
251 | output [`FIRE_DLC_SRM_WDTH-1:0] rm2mm_rcd; | |
252 | output rm2mm_rcd_enq; | |
253 | input mm2rm_rcd_full; | |
254 | ||
255 | ||
256 | //------------------------------------------------------------------------ | |
257 | // CLU Interface | |
258 | //------------------------------------------------------------------------ | |
259 | ||
260 | // DMA Rd Buffer Release Record - 5 bit DOU Buffer Release | |
261 | ||
262 | output [`FIRE_DLC_DOU_REL_WDTH-1:0] rm2cl_bufrel; | |
263 | output rm2cl_bufrel_enq; | |
264 | ||
265 | output rm2crm_npwr_wrack; | |
266 | ||
267 | ||
268 | //------------------------------------------------------------------------ | |
269 | // CRU Interface - Block Debug Level Selects and Output Ports | |
270 | //------------------------------------------------------------------------ | |
271 | ||
272 | // FIRE's 16 bit Prog. ReqID (PIO)-CplID (DMA) - was 16'b0 prior to P1731 | |
273 | input [`FIRE_PCIE_REQ_ID_WDTH-1:0] cr2rm_req_id; | |
274 | ||
275 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2rm_dbg_sel_a; // 6 bit select | |
276 | input [`FIRE_DLC_DEBUG_SEL_WDTH-1:0] cr2rm_dbg_sel_b; // 6 bit select | |
277 | ||
278 | output [`FIRE_DEBUG_WDTH-1:0] rm2cr_dbg_a; // 8 bit debug port | |
279 | output [`FIRE_DEBUG_WDTH-1:0] rm2cr_dbg_b; // 8 bit debug port | |
280 | ||
281 | ||
282 | //############################################################################ | |
283 | // PARAMETERS | |
284 | //############################################################################ | |
285 | ||
286 | ||
287 | //############################################################################ | |
288 | // SIGNAL DECLARATIONS | |
289 | //############################################################################ | |
290 | ||
291 | ||
292 | //************************************************** | |
293 | // Internal Sub-Block Wires | |
294 | //************************************************** | |
295 | ||
296 | // 4 bit (non-posted) PIO Transaction Credit Record Release | |
297 | ||
298 | wire [`FIRE_DLC_RMU_LRM_REL_WDTH-1:0] lrm2rrm_cpl; | |
299 | wire lrm2rrm_cpl_enq; | |
300 | ||
301 | // RRM Debug port wires | |
302 | wire [2:0] dbg2rrm_dbg_sel_a; // 3 bit select | |
303 | wire [2:0] dbg2rrm_dbg_sel_b; // 3 bit select | |
304 | wire [`FIRE_DEBUG_WDTH-1:0] rrm2dbg_dbg_a; // 8 bit debug port | |
305 | wire [`FIRE_DEBUG_WDTH-1:0] rrm2dbg_dbg_b; // 8 bit debug port | |
306 | ||
307 | ||
308 | // LRM Debug port wires | |
309 | wire [2:0] dbg2lrm_dbg_sel_a; // 3 bit select | |
310 | wire [2:0] dbg2lrm_dbg_sel_b; // 3 bit select | |
311 | wire [`FIRE_DEBUG_WDTH-1:0] lrm2dbg_dbg_a; // 8 bit debug port | |
312 | wire [`FIRE_DEBUG_WDTH-1:0] lrm2dbg_dbg_b; // 8 bit debug port | |
313 | ||
314 | ||
315 | //************************************************** | |
316 | // Registers that Are Not Flops | |
317 | //************************************************** | |
318 | ||
319 | ||
320 | //************************************************** | |
321 | // Registers that Are Flops | |
322 | //************************************************** | |
323 | ||
324 | ||
325 | //############################################################################ | |
326 | // ZERO IN CHECKERS | |
327 | //############################################################################ | |
328 | ||
329 | ||
330 | //############################################################################ | |
331 | // COMBINATIONAL LOGIC | |
332 | //############################################################################ | |
333 | ||
334 | ||
335 | //############################################################################ | |
336 | // SEQUENTIAL LOGIC | |
337 | //############################################################################ | |
338 | ||
339 | ||
340 | //############################################################################ | |
341 | // MODULE INSTANTIATIONS | |
342 | //############################################################################ | |
343 | ||
344 | ||
345 | ||
346 | dmu_rmu_rrm rrm( | |
347 | .clk (clk), | |
348 | .rst_l (rst_l), | |
349 | ||
350 | // Outputs to JBC Block - PIO credit release | |
351 | .d2j_p_wrack_tag (d2j_p_wrack_tag), | |
352 | .d2j_p_wrack_vld (d2j_p_wrack_vld), | |
353 | ||
354 | // Inputs from ILU (EIL) Block - Release Record for PIO Cpl/DMA Rd | |
355 | .y2k_rel_rcd (y2k_rel_rcd), | |
356 | .y2k_rel_enq (y2k_rel_enq), | |
357 | ||
358 | // Outputs to ILU - EPE Record (Egress PEC Record) | |
359 | .k2y_rcd (k2y_rcd), | |
360 | .k2y_rcd_enq (k2y_rcd_enq), | |
361 | ||
362 | // Input from ILU | |
363 | .y2k_rcd_deq (y2k_rcd_deq), | |
364 | ||
365 | // Outputs to IMU - Mondo Reply Record (RRM to IMU) | |
366 | .rm2im_rply (rm2im_rply), | |
367 | .rm2im_rply_enq (rm2im_rply_enq), | |
368 | ||
369 | // Input from IMU - Static CSR MEM64 Address Offset | |
370 | .im2rm_mem64_offset_reg (im2rm_mem64_offset_reg), | |
371 | ||
372 | // Outputs to TSB - Egress Pipeline | |
373 | .rm2ts_e_cmd_type (rm2ts_e_cmd_type), | |
374 | .rm2ts_e_wr_data (rm2ts_e_wr_data), | |
375 | .rm2ts_e_trn (rm2ts_e_trn), | |
376 | .rm2ts_e_req (rm2ts_e_req), | |
377 | ||
378 | // Inputs from TSB | |
379 | .ts2rm_e_gnt (ts2rm_e_gnt), | |
380 | .ts2rm_e_rd_data (ts2rm_e_rd_data), | |
381 | ||
382 | // Inputs from CMU - Retire Record (TCM to RRM) | |
383 | .cm2rm_rcd (cm2rm_rcd), | |
384 | .cm2rm_rcd_enq (cm2rm_rcd_enq), | |
385 | ||
386 | // Output to CMU | |
387 | .rm2cm_rcd_full (rm2cm_rcd_full), | |
388 | ||
389 | // Outputs to CLU | |
390 | .rm2cl_bufrel (rm2cl_bufrel), | |
391 | .rm2cl_bufrel_enq (rm2cl_bufrel_enq), | |
392 | ||
393 | // Input from CRU - static REQID (PIO)/ Completion ID (DMA) for EPE rcd | |
394 | .cr2rm_req_id (cr2rm_req_id), | |
395 | ||
396 | // Internal sub-block Inputs - PIO Transaction Credit Record | |
397 | .lrm2rrm_cpl (lrm2rrm_cpl), | |
398 | .lrm2rrm_cpl_enq (lrm2rrm_cpl_enq), | |
399 | ||
400 | // RRM Debug Ports - Inputs (Selects) | |
401 | .dbg2rrm_dbg_sel_a (dbg2rrm_dbg_sel_a), | |
402 | .dbg2rrm_dbg_sel_b (dbg2rrm_dbg_sel_b), | |
403 | ||
404 | // RRM Debug Ports - Onputs | |
405 | .rrm2dbg_dbg_a (rrm2dbg_dbg_a), | |
406 | .rrm2dbg_dbg_b (rrm2dbg_dbg_b), | |
407 | ||
408 | // | |
409 | .rm2crm_npwr_wrack (rm2crm_npwr_wrack) | |
410 | ); | |
411 | ||
412 | ||
413 | dmu_rmu_lrm lrm( | |
414 | .clk (clk), | |
415 | .rst_l (rst_l), | |
416 | ||
417 | // Inputs from TMU - DIM Record - Ingress Pipeline | |
418 | .tm2rm_rcd (tm2rm_rcd), | |
419 | .tm2rm_rcd_enq (tm2rm_rcd_enq), | |
420 | ||
421 | // Output to TMU - DIM Record Queue Full | |
422 | .rm2tm_rcd_full (rm2tm_rcd_full), | |
423 | ||
424 | // Outputs to IMU - Interrupt In Record for IMU Servicing | |
425 | .rm2im_rcd (rm2im_rcd), | |
426 | .rm2im_rcd_enq (rm2im_rcd_enq), | |
427 | ||
428 | // Inputs from IMU - Interrupt Out Record for Ingress Pipeline | |
429 | .im2rm_rcd (im2rm_rcd), | |
430 | .im2rm_rcd_enq (im2rm_rcd_enq), | |
431 | ||
432 | // Inputs from IMU (cont) - Mondo ReQuest Record | |
433 | .im2rm_mdo (im2rm_mdo), | |
434 | .im2rm_mdo_enq (im2rm_mdo_enq), | |
435 | ||
436 | // TSB Interface - Ingress Pipeline | |
437 | .rm2ts_i_cmd_type (rm2ts_i_cmd_type), | |
438 | .rm2ts_i_wr_data (rm2ts_i_wr_data), | |
439 | .rm2ts_i_req (rm2ts_i_req), | |
440 | ||
441 | // Inputs from TSB | |
442 | .ts2rm_i_gnt (ts2rm_i_gnt), | |
443 | .ts2rm_i_full (ts2rm_i_full), | |
444 | .ts2rm_i_n_trn (ts2rm_i_n_trn), | |
445 | ||
446 | // Outputs to MMU | |
447 | .rm2mm_rcd (rm2mm_rcd), | |
448 | .rm2mm_rcd_enq (rm2mm_rcd_enq), | |
449 | ||
450 | // Input from MMU | |
451 | .mm2rm_rcd_full (mm2rm_rcd_full), | |
452 | ||
453 | // Internal sub-block Outputs to RMU - PIO WR Release | |
454 | .lrm2rrm_cpl (lrm2rrm_cpl), | |
455 | .lrm2rrm_cpl_enq (lrm2rrm_cpl_enq), | |
456 | ||
457 | // LRM Debug Ports - Inputs (Selects) | |
458 | .dbg2lrm_dbg_sel_a (dbg2lrm_dbg_sel_a), | |
459 | .dbg2lrm_dbg_sel_b (dbg2lrm_dbg_sel_b), | |
460 | ||
461 | // LRM Debug Ports - Onputs | |
462 | .lrm2dbg_dbg_a (lrm2dbg_dbg_a), | |
463 | .lrm2dbg_dbg_b (lrm2dbg_dbg_b) | |
464 | ||
465 | ); | |
466 | ||
467 | ||
468 | dmu_rmu_dbg dbg( | |
469 | .clk (clk), | |
470 | .rst_l (rst_l), | |
471 | ||
472 | // Block Level Selects and Output Ports | |
473 | .cr2rm_dbg_sel_a (cr2rm_dbg_sel_a), | |
474 | .cr2rm_dbg_sel_b (cr2rm_dbg_sel_b), | |
475 | ||
476 | .rm2cr_dbg_a (rm2cr_dbg_a), | |
477 | .rm2cr_dbg_b (rm2cr_dbg_b), | |
478 | ||
479 | // Sub Block Selects and Output Ports | |
480 | // RRM sub block | |
481 | .dbg2rrm_dbg_sel_a (dbg2rrm_dbg_sel_a), | |
482 | .dbg2rrm_dbg_sel_b (dbg2rrm_dbg_sel_b), | |
483 | .rrm2dbg_dbg_a (rrm2dbg_dbg_a), | |
484 | .rrm2dbg_dbg_b (rrm2dbg_dbg_b), | |
485 | ||
486 | // LRM sub block | |
487 | .dbg2lrm_dbg_sel_a (dbg2lrm_dbg_sel_a), | |
488 | .dbg2lrm_dbg_sel_b (dbg2lrm_dbg_sel_b), | |
489 | .lrm2dbg_dbg_a (lrm2dbg_dbg_a), | |
490 | .lrm2dbg_dbg_b (lrm2dbg_dbg_b) | |
491 | ||
492 | ); | |
493 | ||
494 | ||
495 | endmodule |