Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | `timescale 1ns/10ps |
2 | ||
3 | module esr ( | |
4 | // Outputs | |
5 | XAUI0_AMUX, XAUI0_TX_N, XAUI0_TX_P, esr_mac_tclk_0, | |
6 | esr_mac_rclk_0, esr_mac_rxd0_0, esr_mac_rxd1_0, esr_mac_rxd2_0, | |
7 | esr_mac_rxd3_0, stciq_0, ststx0_0, ststx1_0, ststx2_0, ststx3_0, | |
8 | stsrx0_0, stsrx1_0, stsrx2_0, stsrx3_0, stspll_0, fdo_0, | |
9 | XAUI1_AMUX, XAUI1_TX_N, XAUI1_TX_P, esr_mac_tclk_1, | |
10 | esr_mac_rclk_1, esr_mac_rxd0_1, esr_mac_rxd1_1, esr_mac_rxd2_1, | |
11 | esr_mac_rxd3_1, stciq_1, ststx0_1, ststx1_1, ststx2_1, ststx3_1, | |
12 | stsrx0_1, stsrx1_1, stsrx2_1, stsrx3_1, stspll_1, fdo_1, | |
13 | esr_atpgq, | |
14 | // Inputs | |
15 | XAUI0_REFCLK_N, XAUI0_REFCLK_P, XAUI0_RX_N, XAUI0_RX_P, | |
16 | mac_esr_tclk_0, mac_esr_txd0_0, mac_esr_txd1_0, mac_esr_txd2_0, | |
17 | mac_esr_txd3_0, stcicfg_0, stciclk_0, stcid_0, rxbclkin_0, | |
18 | testclkr_0, testclkt_0, cfgtx0_0, cfgtx1_0, cfgtx2_0, cfgtx3_0, | |
19 | cfgrx0_0, cfgrx1_0, cfgrx2_0, cfgrx3_0, cfgpll_0, testcfg_0, | |
20 | fclk_0, fclrz_0, fdi_0, XAUI1_RX_N, XAUI1_RX_P, mac_esr_tclk_1, | |
21 | mac_esr_txd0_1, mac_esr_txd1_1, mac_esr_txd2_1, mac_esr_txd3_1, | |
22 | stcicfg_1, stciclk_1, stcid_1, rxbclkin_1, testclkr_1, testclkt_1, | |
23 | cfgtx0_1, cfgtx1_1, cfgtx2_1, cfgtx3_1, cfgrx0_1, cfgrx1_1, | |
24 | cfgrx2_1, cfgrx3_1, cfgpll_1, testcfg_1, fclk_1, fclrz_1, fdi_1, | |
25 | tcu_sbs_bsinitclk_0, tcu_sbs_bsinitclk_1, tcu_esr_atpgse_0, | |
26 | tcu_esr_atpgse_1, tcu_esr_atpgmode_0, tcu_esr_atpgmode_1, | |
27 | esr_atpgd, VDDT, VDDA, VDDD, VDDR, VSSA | |
28 | ); | |
29 | ||
30 | ||
31 | /* ---------------- serdes_0 ---------------------------------- */ | |
32 | output XAUI0_AMUX; // PAD | |
33 | output [3:0] XAUI0_TX_N; // PAD | |
34 | output [3:0] XAUI0_TX_P; // PAD | |
35 | input XAUI0_REFCLK_N; // PAD | |
36 | input XAUI0_REFCLK_P; // PAD | |
37 | input [3:0] XAUI0_RX_N; // PAD | |
38 | input [3:0] XAUI0_RX_P; // PAD | |
39 | output esr_mac_tclk_0; // to phy_clock | |
40 | output [3:0] esr_mac_rclk_0; // to phy_clock | |
41 | output [9:0] esr_mac_rxd0_0; // to sphy_dpath | |
42 | output [9:0] esr_mac_rxd1_0; // to sphy_dpath | |
43 | output [9:0] esr_mac_rxd2_0; // to sphy_dpath | |
44 | output [9:0] esr_mac_rxd3_0; // to sphy_dpath | |
45 | input [3:0] mac_esr_tclk_0; // from esr_mac_tclk leaf | |
46 | input [9:0] mac_esr_txd0_0; // from sphy_dpath | |
47 | input [9:0] mac_esr_txd1_0; // from sphy_dpath | |
48 | input [9:0] mac_esr_txd2_0; // from sphy_dpath | |
49 | input [9:0] mac_esr_txd3_0; // from sphy_dpath | |
50 | input [1:0] stcicfg_0; // serial test | |
51 | input stciclk_0; // serial test | |
52 | input stcid_0; // serial test | |
53 | output stciq_0; // serial test | |
54 | input [3:0] rxbclkin_0; // rxbclkin_0[3:0] <- esr_mac_rclk_0[3:0] at cpu level | |
55 | input testclkr_0; // from test logic | |
56 | input testclkt_0; // from test logic | |
57 | input [19:0] cfgtx0_0; // from hedwig | |
58 | input [19:0] cfgtx1_0; // from hedwig | |
59 | input [19:0] cfgtx2_0; // from hedwig | |
60 | input [19:0] cfgtx3_0; // from hedwig | |
61 | input [27:0] cfgrx0_0; // from hedwig | |
62 | input [27:0] cfgrx1_0; // from hedwig | |
63 | input [27:0] cfgrx2_0; // from hedwig | |
64 | input [27:0] cfgrx3_0; // from hedwig | |
65 | input [11:0] cfgpll_0; // from hedwig | |
66 | input [15:0] testcfg_0; // from hedwig | |
67 | input tcu_sbs_bsinitclk_0; | |
68 | input tcu_esr_atpgse_0; // TESTCFG[19] | |
69 | input [2:0] tcu_esr_atpgmode_0; // TESTCFG[18:16] | |
70 | output [3:0] ststx0_0; // to hedwig | |
71 | output [3:0] ststx1_0; // to hedwig | |
72 | output [3:0] ststx2_0; // to hedwig | |
73 | output [3:0] ststx3_0; // to hedwig | |
74 | output [7:0] stsrx0_0; // to hedwig | |
75 | output [7:0] stsrx1_0; // to hedwig | |
76 | output [7:0] stsrx2_0; // to hedwig | |
77 | output [7:0] stsrx3_0; // to hedwig | |
78 | output [3:0] stspll_0; // to hedwig | |
79 | output fdo_0; // efuse signal | |
80 | input fclk_0; // efuse signal | |
81 | input fclrz_0; // efuse signal | |
82 | input fdi_0; // efuse signal | |
83 | /* ---------------- serdes_1 ---------------------------------- */ | |
84 | output XAUI1_AMUX; // PAD | |
85 | output [3:0] XAUI1_TX_N; // PAD | |
86 | output [3:0] XAUI1_TX_P; // PAD | |
87 | input [3:0] XAUI1_RX_N; // PAD | |
88 | input [3:0] XAUI1_RX_P; // PAD | |
89 | output esr_mac_tclk_1; // to phy_clock | |
90 | output [3:0] esr_mac_rclk_1; // to phy_clock | |
91 | output [9:0] esr_mac_rxd0_1; // to sphy_dpath | |
92 | output [9:0] esr_mac_rxd1_1; // to sphy_dpath | |
93 | output [9:0] esr_mac_rxd2_1; // to sphy_dpath | |
94 | output [9:0] esr_mac_rxd3_1; // to sphy_dpath | |
95 | input [3:0] mac_esr_tclk_1; // from esr_mac_tclk leaf | |
96 | input [9:0] mac_esr_txd0_1; // from sphy_dpath | |
97 | input [9:0] mac_esr_txd1_1; // from sphy_dpath | |
98 | input [9:0] mac_esr_txd2_1; // from sphy_dpath | |
99 | input [9:0] mac_esr_txd3_1; // from sphy_dpath | |
100 | input [1:0] stcicfg_1; // serial test | |
101 | input stciclk_1; // serial test | |
102 | input stcid_1; // serial test | |
103 | output stciq_1; // serial test | |
104 | input [3:0] rxbclkin_1; // rxbclkin_1[3:0] <- esr_mac_rclk_1[3:0] at cpu level | |
105 | input testclkr_1; // from test logic | |
106 | input testclkt_1; // from test logic | |
107 | input [19:0] cfgtx0_1; // from hedwig | |
108 | input [19:0] cfgtx1_1; // from hedwig | |
109 | input [19:0] cfgtx2_1; // from hedwig | |
110 | input [19:0] cfgtx3_1; // from hedwig | |
111 | input [27:0] cfgrx0_1; // from hedwig | |
112 | input [27:0] cfgrx1_1; // from hedwig | |
113 | input [27:0] cfgrx2_1; // from hedwig | |
114 | input [27:0] cfgrx3_1; // from hedwig | |
115 | input [11:0] cfgpll_1; // from hedwig | |
116 | input [15:0] testcfg_1; // from hedwig | |
117 | input tcu_sbs_bsinitclk_1; | |
118 | input tcu_esr_atpgse_1; // TESTCFG[19] | |
119 | input [2:0] tcu_esr_atpgmode_1; // TESTCFG[18:16] | |
120 | output [3:0] ststx0_1; // to hedwig | |
121 | output [3:0] ststx1_1; // to hedwig | |
122 | output [3:0] ststx2_1; // to hedwig | |
123 | output [3:0] ststx3_1; // to hedwig | |
124 | output [7:0] stsrx0_1; // to hedwig | |
125 | output [7:0] stsrx1_1; // to hedwig | |
126 | output [7:0] stsrx2_1; // to hedwig | |
127 | output [7:0] stsrx3_1; // to hedwig | |
128 | output [3:0] stspll_1; // to hedwig | |
129 | output fdo_1; // efuse signal | |
130 | input fclk_1; // efuse signal | |
131 | input fclrz_1; // efuse signal | |
132 | input fdi_1; // efuse signal | |
133 | /* ---------------- common signals ---------------------------- */ | |
134 | input esr_atpgd; // ATPG M D_in | |
135 | output esr_atpgq; // ATPG TX Q_out | |
136 | // vlint flag_input_port_not_connected off | |
137 | input VDDT; // floating VDD. | |
138 | input VDDA; // floating VDD. | |
139 | input VDDD; // floating VDD. | |
140 | input VDDR; // floating VDD. | |
141 | input VSSA; // floating VSS. | |
142 | // vlint flag_input_port_not_connected on | |
143 | ||
144 | ||
145 | wire [3:0] XAUI0_TX_N; | |
146 | wire [3:0] XAUI0_TX_P; | |
147 | wire [3:0] XAUI0_RX_N; | |
148 | wire [3:0] XAUI0_RX_P; | |
149 | wire [3:0] XAUI1_TX_N; | |
150 | wire [3:0] XAUI1_TX_P; | |
151 | wire [3:0] XAUI1_RX_N; | |
152 | wire [3:0] XAUI1_RX_P; | |
153 | ||
154 | // ATPG signals | |
155 | // _s0 means serdes0, _s1 means serdes1 | |
156 | // naming rule: source_destination_serdes# | |
157 | // example: rb3_rb2_s0 means rx bit 3 to rx bit2 in serdes 0 | |
158 | wire atpgm_tb2_s0; | |
159 | wire rb3_rb0_s1,rb2_tb3_s0,rb1_tb1_s0,rb0_tb0_s0; | |
160 | wire tb3_rb3_s0,tb2_rb2_s0,tb1_atpgm_s0,tb0_rb1_s0; | |
161 | wire atpgm_tb2_s1; | |
162 | wire rb2_tb3_s1,rb1_tb1_s1,rb0_tb0_s1; | |
163 | wire tb3_rb3_s1,tb2_rb2_s1,tb1_atpgm_s1,tb0_rb1_s1; | |
164 | ||
165 | ||
166 | // vlint flag_dangling_net_within_module off | |
167 | // vlint flag_net_has_no_load off | |
168 | wire [1:0] rdll0_0; // for ti only. | |
169 | wire [1:0] rdll1_0; // for ti only. | |
170 | wire [1:0] rdll2_0; // for ti only. | |
171 | wire [1:0] rdll3_0; // for ti only. | |
172 | wire [3:0] rxbclklln_0; // for ti only. | |
173 | wire [3:0] rxbclkllp_0; // for ti only. | |
174 | wire [1:0] rdll0_1; // for ti only. | |
175 | wire [1:0] rdll1_1; // for ti only. | |
176 | wire [1:0] rdll2_1; // for ti only. | |
177 | wire [1:0] rdll3_1; // for ti only. | |
178 | wire [3:0] rxbclklln_1; // for ti only. | |
179 | wire [3:0] rxbclkllp_1; // for ti only. | |
180 | wire y; // single ended. let it float. | |
181 | wire txbclk3_0,txbclk2_0,txbclk1_0; | |
182 | wire txbclk3_1,txbclk2_1,txbclk1_1; | |
183 | // vlint flag_net_has_no_load on | |
184 | // vlint flag_dangling_net_within_module on | |
185 | ||
186 | // LJCB & RCD signals | |
187 | wire clkxaui; | |
188 | wire clkxauix; | |
189 | wire clkxaui_b_31; | |
190 | wire clkxaui_b_31x; | |
191 | wire clkxaui_b_29; | |
192 | wire clkxaui_b_29x; | |
193 | ||
194 | // vlint flag_dangling_net_within_module off | |
195 | // vlint flag_net_has_no_load off | |
196 | // vlint flag_input_port_not_connected off | |
197 | wire VDDT; // floating VDD. | |
198 | wire VDDA; // floating VDD. | |
199 | wire VDDD; // floating VDD. | |
200 | wire VDDR; // floating VDD. | |
201 | wire VSSA; // floating VDD. | |
202 | // vlint flag_input_port_not_connected on | |
203 | // vlint flag_net_has_no_load on | |
204 | // vlint flag_dangling_net_within_module on | |
205 | ||
206 | wire xaui_clk; | |
207 | clock_multiplier_10x clock_multiplier_10x (tb_top.cpu.XAUI0_REFCLK_P, xaui_clk); | |
208 | ||
209 | reg f_clk[3:0]; // fake clocks | |
210 | ||
211 | always @(posedge xaui_clk) begin | |
212 | f_clk[0] <= tb_top.cpu.XAUI0_REFCLK_P; | |
213 | f_clk[1] <= f_clk[0]; | |
214 | f_clk[2] <= f_clk[1]; | |
215 | f_clk[3] <= f_clk[2]; | |
216 | end | |
217 | ||
218 | assign esr_mac_tclk_0 = f_clk[3]; | |
219 | assign esr_mac_tclk_1 = f_clk[3]; | |
220 | assign esr_mac_rclk_0 = {4{f_clk[1]}}; | |
221 | assign esr_mac_rclk_1 = {4{f_clk[1]}}; | |
222 | ||
223 | assign stspll_0 = 4'b0001; | |
224 | assign stspll_1 = 4'b0001; | |
225 | ||
226 | assign ststx0_0 = 4'b0; | |
227 | assign ststx1_0 = 4'b0; | |
228 | assign ststx2_0 = 4'b0; | |
229 | assign ststx3_0 = 4'b0; | |
230 | assign stsrx0_0 = 8'b0; | |
231 | assign stsrx1_0 = 8'b0; | |
232 | assign stsrx2_0 = 8'b0; | |
233 | assign stsrx3_0 = 8'b0; | |
234 | ||
235 | ||
236 | assign ststx0_1 = 4'b0; | |
237 | assign ststx1_1 = 4'b0; | |
238 | assign ststx2_1 = 4'b0; | |
239 | assign ststx3_1 = 4'b0; | |
240 | assign stsrx0_1 = 8'b0; | |
241 | assign stsrx1_1 = 8'b0; | |
242 | assign stsrx2_1 = 8'b0; | |
243 | assign stsrx3_1 = 8'b0; | |
244 | ||
245 | xaui_port esr_0 ( | |
246 | .XAUI_AMUX (XAUI0_AMUX), | |
247 | .XAUI_RX_N ({XAUI0_RX_N[3],XAUI0_RX_N[2],XAUI0_RX_N[1],XAUI0_RX_N[0]}), | |
248 | .XAUI_RX_P ({XAUI0_RX_P[3],XAUI0_RX_P[2],XAUI0_RX_P[1],XAUI0_RX_P[0]}), | |
249 | .XAUI_TX_N ({XAUI0_TX_N[3],XAUI0_TX_N[2],XAUI0_TX_N[1],XAUI0_TX_N[0]}), | |
250 | .XAUI_TX_P ({XAUI0_TX_P[3],XAUI0_TX_P[2],XAUI0_TX_P[1],XAUI0_TX_P[0]}), | |
251 | .esr_mac_rxd0 (esr_mac_rxd0_0[9:0]), | |
252 | .esr_mac_rxd1 (esr_mac_rxd1_0[9:0]), | |
253 | .esr_mac_rxd2 (esr_mac_rxd2_0[9:0]), | |
254 | .esr_mac_rxd3 (esr_mac_rxd3_0[9:0]), | |
255 | .mac_esr_txd0 (mac_esr_txd0_0[9:0]), | |
256 | .mac_esr_txd1 (mac_esr_txd1_0[9:0]), | |
257 | .mac_esr_txd2 (mac_esr_txd2_0[9:0]), | |
258 | .mac_esr_txd3 (mac_esr_txd3_0[9:0]), | |
259 | .xaui_clk (xaui_clk), | |
260 | .mac_clk (tb_top.cpu.XAUI0_REFCLK_P), | |
261 | .reset (~tb_top.cpu.n2_clk_gl_cust.gl_rst_mac_c1b) ); | |
262 | ||
263 | ||
264 | xaui_port esr_1 ( | |
265 | .XAUI_AMUX (XAUI1_AMUX), | |
266 | .XAUI_RX_N ({XAUI1_RX_N[3],XAUI1_RX_N[2],XAUI1_RX_N[1],XAUI1_RX_N[0]}), | |
267 | .XAUI_RX_P ({XAUI1_RX_P[3],XAUI1_RX_P[2],XAUI1_RX_P[1],XAUI1_RX_P[0]}), | |
268 | .XAUI_TX_N ({XAUI1_TX_N[3],XAUI1_TX_N[2],XAUI1_TX_N[1],XAUI1_TX_N[0]}), | |
269 | .XAUI_TX_P ({XAUI1_TX_P[3],XAUI1_TX_P[2],XAUI1_TX_P[1],XAUI1_TX_P[0]}), | |
270 | .esr_mac_rxd0 (esr_mac_rxd0_1[9:0]), | |
271 | .esr_mac_rxd1 (esr_mac_rxd1_1[9:0]), | |
272 | .esr_mac_rxd2 (esr_mac_rxd2_1[9:0]), | |
273 | .esr_mac_rxd3 (esr_mac_rxd3_1[9:0]), | |
274 | .mac_esr_txd0 (mac_esr_txd0_1[9:0]), | |
275 | .mac_esr_txd1 (mac_esr_txd1_1[9:0]), | |
276 | .mac_esr_txd2 (mac_esr_txd2_1[9:0]), | |
277 | .mac_esr_txd3 (mac_esr_txd3_1[9:0]), | |
278 | .xaui_clk (xaui_clk), | |
279 | .mac_clk (tb_top.cpu.XAUI0_REFCLK_P), | |
280 | .reset (~tb_top.cpu.n2_clk_gl_cust.gl_rst_mac_c1b) ); | |
281 | ||
282 | ||
283 | ||
284 | ||
285 | // -------------- RCD instantiation -------------- | |
286 | // RCD Reference Clock Distribution | |
287 | U0 RCD_U0 | |
288 | ( | |
289 | // Outputs | |
290 | .clkxaui_b_31 (clkxaui_b_31), // P. serdes0 left-hand side | |
291 | .clkxaui_b_31x (clkxaui_b_31x), // N. serdes0 left-hand side | |
292 | .clkxaui_b_29 (clkxaui_b_29), // P. serdes1 right-hand side | |
293 | .clkxaui_b_29x (clkxaui_b_29x), // N. serdes1 right-hand side | |
294 | // Inputs | |
295 | .clkxaui (clkxaui), | |
296 | .clkxauix (clkxauix), | |
297 | .clkxaui_pwrdn (1'b0)); | |
298 | ||
299 | // -------------- LJCB instantiation -------------- | |
300 | U1 LJCB_U1 | |
301 | ( | |
302 | // Outputs | |
303 | .y (y), // Single ended. let it float. | |
304 | .yn (clkxauix), | |
305 | .yp (clkxaui), | |
306 | // Inputs | |
307 | .padn (XAUI0_REFCLK_N), | |
308 | .pad (XAUI0_REFCLK_P), | |
309 | .pwrdn (1'b0), | |
310 | .pwrdnse (1'b1)); | |
311 | ||
312 | ||
313 | endmodule // esr | |
314 | ||
315 | /*******************************************************************************************/ | |
316 | ||
317 | `timescale 1 ns / 1 ps | |
318 | module U1(padn, pad, pwrdn, pwrdnse, y, yn, yp); | |
319 | ||
320 | input padn; | |
321 | input pad; | |
322 | input pwrdn; | |
323 | input pwrdnse; | |
324 | output y; | |
325 | output yn; | |
326 | output yp; | |
327 | ||
328 | wire pad_ne_padn; | |
329 | wire pad_net; | |
330 | wire padn_net; | |
331 | wire yn_tmp; | |
332 | wire ynn_tmp; | |
333 | ||
334 | specify | |
335 | endspecify | |
336 | ||
337 | xor ti_xor_pri0(pad_ne_padn, pad, padn); | |
338 | bufif1 ti_buf_pri1(pad_net, pad, pad_ne_padn); | |
339 | bufif1 ti_buf_pri2(padn_net, padn, pad_ne_padn); | |
340 | or #(0) ti_or2_pri3(yp, pwrdn, pad_net); | |
341 | or ti_or2_pri4(yn_tmp, pwrdn, padn_net); | |
342 | buf #(0) ti_buf_pri5(yn, yn_tmp); | |
343 | or ti_or2_pri7(ynn_tmp, pwrdnse, yn_tmp); | |
344 | not #(0) ti_not_pri6(y, ynn_tmp); | |
345 | endmodule | |
346 | ||
347 | ||
348 | module U0 (clkxaui_b_31, clkxaui_b_31x, clkxaui_b_29, clkxaui_b_29x, clkxaui, clkxauix, clkxaui_pwrdn); | |
349 | ||
350 | output clkxaui_b_31; | |
351 | output clkxaui_b_31x; | |
352 | output clkxaui_b_29; | |
353 | output clkxaui_b_29x; | |
354 | input clkxaui; | |
355 | input clkxauix; | |
356 | input clkxaui_pwrdn; | |
357 | ||
358 | wire vdq_bottom2_1; | |
359 | wire cmlbias1_34p0; | |
360 | wire clkxaui_bb_3; | |
361 | wire clkxaui_bb_3x; | |
362 | wire pwrdnxaui_bb_3; | |
363 | wire cmlbias1_38p5; | |
364 | wire clkxaui_bb_4; | |
365 | wire clkxaui_bb_4x; | |
366 | wire pwrdnxaui_bb_4; | |
367 | wire cmlbias1_42p0; | |
368 | wire ninv_xaui_bb_3_pwrdnx; | |
369 | wire ninv_xaui_bb_4_pwrdnx; | |
370 | ||
371 | not esr_out_ninv_xaui_b_31(clkxaui_b_31, clkxaui_bb_3x); | |
372 | not esr_clkxaui_b_31x(clkxaui_b_31x, clkxaui_bb_3); | |
373 | or esr_ninv_xaui_bb_3(clkxaui_bb_3, clkxaui_pwrdn, clkxaui); | |
374 | or esr_clkxaui_bb_3x(clkxaui_bb_3x, clkxaui_pwrdn, clkxauix); | |
375 | not esr_ninv_xaui_bb_3_pwrdnx(ninv_xaui_bb_3_pwrdnx, clkxaui_pwrdn); | |
376 | not esr_pwrdnxaui_bb_3(pwrdnxaui_bb_3, ninv_xaui_bb_3_pwrdnx); | |
377 | or esr_ninv_xaui_bb_4(clkxaui_bb_4, clkxaui_pwrdn, clkxaui); | |
378 | or esr_clkxaui_bb_4x(clkxaui_bb_4x, clkxaui_pwrdn, clkxauix); | |
379 | not esr_ninv_xaui_bb_4_pwrdnx(ninv_xaui_bb_4_pwrdnx, clkxaui_pwrdn); | |
380 | not esr_pwrdnxaui_bb_4(pwrdnxaui_bb_4, ninv_xaui_bb_4_pwrdnx); | |
381 | not esr_out_ninv_xaui_b_29(clkxaui_b_29, clkxaui_bb_4x); | |
382 | not esr_clkxaui_b_29x(clkxaui_b_29x, clkxaui_bb_4); | |
383 | endmodule | |
384 |