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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / fsr_right / rtl / fsr_right.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fsr_right.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module fsr_right
36 (fsr4_mcu2_rd0,
37 fsr4_mcu2_rd1,
38 fsr4_mcu2_rd2,
39 fsr4_mcu2_rd3,
40 fsr4_mcu2_rd4,
41 fsr4_mcu2_rd5,
42 fsr4_mcu2_rd6,
43 fsr4_mcu2_rd7,
44 fsr4_mcu2_rd8,
45 fsr4_mcu2_rd9,
46 fsr4_mcu2_rd10,
47 fsr4_mcu2_rd11,
48 fsr4_mcu2_rd12,
49 fsr4_mcu2_rd13,
50 fsr4_mcu2_ststx_testfail,
51 fsr4_mcu2_stspll_lock,
52 fsr4_mcu2_stsrx_testfail,
53 fsr4_mcu2_stsrx_sync,
54 fsr4_mcu2_stsrx_losdtct,
55 fsr4_mcu2_stsrx_bsrxp,
56 fsr4_mcu2_stsrx_bsrxn,
57 fsr4_mcu2_rxbclk,
58 FBDIMM2A_TX_N,
59 FBDIMM2A_TX_P,
60 FBDIMM2A_AMUX,
61 fsr4_fdo,
62 fsr4_stciq,
63 mcu2_fsr4_cfgpll0,
64 mcu2_fsr4_cfgpll1,
65 mcu2_fsr4_cfgpll2,
66 mcu2_fsr4_cfgrx0,
67 mcu2_fsr4_cfgrx1,
68 mcu2_fsr4_cfgrx2,
69 mcu2_fsr4_cfgrx3,
70 mcu2_fsr4_cfgrx4,
71 mcu2_fsr4_cfgrx5,
72 mcu2_fsr4_cfgrx6,
73 mcu2_fsr4_cfgrx7,
74 mcu2_fsr4_cfgrx8,
75 mcu2_fsr4_cfgrx9,
76 mcu2_fsr4_cfgrx10,
77 mcu2_fsr4_cfgrx11,
78 mcu2_fsr4_cfgrx12,
79 mcu2_fsr4_cfgrx13,
80 mcu2_fsr4_cfgtx0,
81 mcu2_fsr4_cfgtx1,
82 mcu2_fsr4_cfgtx2,
83 mcu2_fsr4_cfgtx3,
84 mcu2_fsr4_cfgtx4,
85 mcu2_fsr4_cfgtx5,
86 mcu2_fsr4_cfgtx6,
87 mcu2_fsr4_cfgtx7,
88 mcu2_fsr4_cfgtx8,
89 mcu2_fsr4_cfgtx9,
90 mcu2_fsr4_testcfg0,
91 mcu2_fsr4_testcfg1,
92 mcu2_fsr4_testcfg2,
93 mcu2_fsr4_td0,
94 mcu2_fsr4_td1,
95 mcu2_fsr4_td2,
96 mcu2_fsr4_td3,
97 mcu2_fsr4_td4,
98 mcu2_fsr4_td5,
99 mcu2_fsr4_td6,
100 mcu2_fsr4_td7,
101 mcu2_fsr4_td8,
102 mcu2_fsr4_td9,
103 fsr4_stcicfg,
104 fsr4_txbclkin,
105 fsr4_rxbclkin,
106 fsr4_bsinitclk,
107 fsr4_fclk,
108 fsr4_fclrz,
109 fsr4_fdi,
110 FBDIMM2A_RX_N,
111 FBDIMM2A_RX_P,
112 fsr4_stciclk,
113 fsr4_stcid,
114 fsr4_testclkr,
115 fsr4_testclkt,
116 fsr5_mcu2_rd0,
117 fsr5_mcu2_rd1,
118 fsr5_mcu2_rd2,
119 fsr5_mcu2_rd3,
120 fsr5_mcu2_rd4,
121 fsr5_mcu2_rd5,
122 fsr5_mcu2_rd6,
123 fsr5_mcu2_rd7,
124 fsr5_mcu2_rd8,
125 fsr5_mcu2_rd9,
126 fsr5_mcu2_rd10,
127 fsr5_mcu2_rd11,
128 fsr5_mcu2_rd12,
129 fsr5_mcu2_rd13,
130 fsr5_mcu2_ststx_testfail,
131 fsr5_mcu2_stspll_lock,
132 fsr5_mcu2_stsrx_testfail,
133 fsr5_mcu2_stsrx_sync,
134 fsr5_mcu2_stsrx_losdtct,
135 fsr5_mcu2_stsrx_bsrxp,
136 fsr5_mcu2_stsrx_bsrxn,
137 fsr5_mcu2_rxbclk,
138 FBDIMM2B_TX_N,
139 FBDIMM2B_TX_P,
140 FBDIMM2B_AMUX,
141 fsr5_fdo,
142 fsr5_stciq,
143 mcu2_fsr5_cfgpll0,
144 mcu2_fsr5_cfgpll1,
145 mcu2_fsr5_cfgpll2,
146 mcu2_fsr5_cfgrx0,
147 mcu2_fsr5_cfgrx1,
148 mcu2_fsr5_cfgrx2,
149 mcu2_fsr5_cfgrx3,
150 mcu2_fsr5_cfgrx4,
151 mcu2_fsr5_cfgrx5,
152 mcu2_fsr5_cfgrx6,
153 mcu2_fsr5_cfgrx7,
154 mcu2_fsr5_cfgrx8,
155 mcu2_fsr5_cfgrx9,
156 mcu2_fsr5_cfgrx10,
157 mcu2_fsr5_cfgrx11,
158 mcu2_fsr5_cfgrx12,
159 mcu2_fsr5_cfgrx13,
160 mcu2_fsr5_cfgtx0,
161 mcu2_fsr5_cfgtx1,
162 mcu2_fsr5_cfgtx2,
163 mcu2_fsr5_cfgtx3,
164 mcu2_fsr5_cfgtx4,
165 mcu2_fsr5_cfgtx5,
166 mcu2_fsr5_cfgtx6,
167 mcu2_fsr5_cfgtx7,
168 mcu2_fsr5_cfgtx8,
169 mcu2_fsr5_cfgtx9,
170 mcu2_fsr5_testcfg0,
171 mcu2_fsr5_testcfg1,
172 mcu2_fsr5_testcfg2,
173 mcu2_fsr5_td0,
174 mcu2_fsr5_td1,
175 mcu2_fsr5_td2,
176 mcu2_fsr5_td3,
177 mcu2_fsr5_td4,
178 mcu2_fsr5_td5,
179 mcu2_fsr5_td6,
180 mcu2_fsr5_td7,
181 mcu2_fsr5_td8,
182 mcu2_fsr5_td9,
183 fsr5_stcicfg,
184 fsr5_txbclkin,
185 fsr5_rxbclkin,
186 fsr5_bsinitclk,
187 fsr5_fclk,
188 fsr5_fclrz,
189 fsr5_fdi,
190 FBDIMM2B_RX_N,
191 FBDIMM2B_RX_P,
192 fsr5_stciclk,
193 fsr5_stcid,
194 fsr5_testclkr,
195 fsr5_testclkt,
196 fsr6_mcu3_rd0,
197 fsr6_mcu3_rd1,
198 fsr6_mcu3_rd2,
199 fsr6_mcu3_rd3,
200 fsr6_mcu3_rd4,
201 fsr6_mcu3_rd5,
202 fsr6_mcu3_rd6,
203 fsr6_mcu3_rd7,
204 fsr6_mcu3_rd8,
205 fsr6_mcu3_rd9,
206 fsr6_mcu3_rd10,
207 fsr6_mcu3_rd11,
208 fsr6_mcu3_rd12,
209 fsr6_mcu3_rd13,
210 fsr6_mcu3_ststx_testfail,
211 fsr6_mcu3_stspll_lock,
212 fsr6_mcu3_stsrx_testfail,
213 fsr6_mcu3_stsrx_sync,
214 fsr6_mcu3_stsrx_losdtct,
215 fsr6_mcu3_stsrx_bsrxp,
216 fsr6_mcu3_stsrx_bsrxn,
217 fsr6_mcu3_rxbclk,
218 FBDIMM3A_TX_N,
219 FBDIMM3A_TX_P,
220 FBDIMM3A_AMUX,
221 fsr6_fdo,
222 fsr6_stciq,
223 mcu3_fsr6_cfgpll0,
224 mcu3_fsr6_cfgpll1,
225 mcu3_fsr6_cfgpll2,
226 mcu3_fsr6_cfgrx0,
227 mcu3_fsr6_cfgrx1,
228 mcu3_fsr6_cfgrx2,
229 mcu3_fsr6_cfgrx3,
230 mcu3_fsr6_cfgrx4,
231 mcu3_fsr6_cfgrx5,
232 mcu3_fsr6_cfgrx6,
233 mcu3_fsr6_cfgrx7,
234 mcu3_fsr6_cfgrx8,
235 mcu3_fsr6_cfgrx9,
236 mcu3_fsr6_cfgrx10,
237 mcu3_fsr6_cfgrx11,
238 mcu3_fsr6_cfgrx12,
239 mcu3_fsr6_cfgrx13,
240 mcu3_fsr6_cfgtx0,
241 mcu3_fsr6_cfgtx1,
242 mcu3_fsr6_cfgtx2,
243 mcu3_fsr6_cfgtx3,
244 mcu3_fsr6_cfgtx4,
245 mcu3_fsr6_cfgtx5,
246 mcu3_fsr6_cfgtx6,
247 mcu3_fsr6_cfgtx7,
248 mcu3_fsr6_cfgtx8,
249 mcu3_fsr6_cfgtx9,
250 mcu3_fsr6_testcfg0,
251 mcu3_fsr6_testcfg1,
252 mcu3_fsr6_testcfg2,
253 mcu3_fsr6_td0,
254 mcu3_fsr6_td1,
255 mcu3_fsr6_td2,
256 mcu3_fsr6_td3,
257 mcu3_fsr6_td4,
258 mcu3_fsr6_td5,
259 mcu3_fsr6_td6,
260 mcu3_fsr6_td7,
261 mcu3_fsr6_td8,
262 mcu3_fsr6_td9,
263 fsr6_stcicfg,
264 fsr6_txbclkin,
265 fsr6_rxbclkin,
266 fsr6_bsinitclk,
267 fsr6_fclk,
268 fsr6_fclrz,
269 fsr6_fdi,
270 FBDIMM3A_RX_N,
271 FBDIMM3A_RX_P,
272 fsr6_stciclk,
273 fsr6_stcid,
274 fsr6_testclkr,
275 fsr6_testclkt,
276 fsr_right_atpgd,
277 fsr_right_atpgq,
278 FBDIMM2_REFCLK_N,
279 FBDIMM2_REFCLK_P,
280 VDDA,
281 VDDD,
282 VDDR,
283 VDDT,
284 VSSA);
285
286 output [11:0] fsr4_mcu2_rd0;
287 output [11:0] fsr4_mcu2_rd1;
288 output [11:0] fsr4_mcu2_rd2;
289 output [11:0] fsr4_mcu2_rd3;
290 output [11:0] fsr4_mcu2_rd4;
291 output [11:0] fsr4_mcu2_rd5;
292 output [11:0] fsr4_mcu2_rd6;
293 output [11:0] fsr4_mcu2_rd7;
294 output [11:0] fsr4_mcu2_rd8;
295 output [11:0] fsr4_mcu2_rd9;
296 output [11:0] fsr4_mcu2_rd10;
297 output [11:0] fsr4_mcu2_rd11;
298 output [11:0] fsr4_mcu2_rd12;
299 output [11:0] fsr4_mcu2_rd13;
300 output [2:0] fsr4_mcu2_stspll_lock;
301 output [13:0] fsr4_mcu2_stsrx_testfail;
302 output [13:0] fsr4_mcu2_stsrx_sync;
303 output [13:0] fsr4_mcu2_stsrx_losdtct;
304 output [13:0] fsr4_mcu2_stsrx_bsrxp;
305 output [13:0] fsr4_mcu2_stsrx_bsrxn;
306 output [9:0] fsr4_mcu2_ststx_testfail;
307 output [13:0] fsr4_mcu2_rxbclk;
308 output [9:0] FBDIMM2A_TX_N;
309 output [9:0] FBDIMM2A_TX_P;
310 output [2:0] FBDIMM2A_AMUX;
311 output [2:0] fsr4_fdo;
312 output [2:0] fsr4_stciq;
313
314 input [6:0] mcu2_fsr4_cfgpll0;
315 input [6:0] mcu2_fsr4_cfgpll1;
316 input [6:0] mcu2_fsr4_cfgpll2;
317 input [19:0] mcu2_fsr4_cfgrx0;
318 input [19:0] mcu2_fsr4_cfgrx1;
319 input [19:0] mcu2_fsr4_cfgrx2;
320 input [19:0] mcu2_fsr4_cfgrx3;
321 input [19:0] mcu2_fsr4_cfgrx4;
322 input [19:0] mcu2_fsr4_cfgrx5;
323 input [19:0] mcu2_fsr4_cfgrx6;
324 input [19:0] mcu2_fsr4_cfgrx7;
325 input [19:0] mcu2_fsr4_cfgrx8;
326 input [19:0] mcu2_fsr4_cfgrx9;
327 input [19:0] mcu2_fsr4_cfgrx10;
328 input [19:0] mcu2_fsr4_cfgrx11;
329 input [19:0] mcu2_fsr4_cfgrx12;
330 input [19:0] mcu2_fsr4_cfgrx13;
331 input [15:0] mcu2_fsr4_cfgtx0;
332 input [15:0] mcu2_fsr4_cfgtx1;
333 input [15:0] mcu2_fsr4_cfgtx2;
334 input [15:0] mcu2_fsr4_cfgtx3;
335 input [15:0] mcu2_fsr4_cfgtx4;
336 input [15:0] mcu2_fsr4_cfgtx5;
337 input [15:0] mcu2_fsr4_cfgtx6;
338 input [15:0] mcu2_fsr4_cfgtx7;
339 input [15:0] mcu2_fsr4_cfgtx8;
340 input [15:0] mcu2_fsr4_cfgtx9;
341 input [17:0] mcu2_fsr4_testcfg0;
342 input [17:0] mcu2_fsr4_testcfg1;
343 input [17:0] mcu2_fsr4_testcfg2;
344 input [11:0] mcu2_fsr4_td0;
345 input [11:0] mcu2_fsr4_td1;
346 input [11:0] mcu2_fsr4_td2;
347 input [11:0] mcu2_fsr4_td3;
348 input [11:0] mcu2_fsr4_td4;
349 input [11:0] mcu2_fsr4_td5;
350 input [11:0] mcu2_fsr4_td6;
351 input [11:0] mcu2_fsr4_td7;
352 input [11:0] mcu2_fsr4_td8;
353 input [11:0] mcu2_fsr4_td9;
354 input [5:0] fsr4_stcicfg;
355 input [2:0] fsr4_txbclkin;
356 input [13:0] fsr4_rxbclkin;
357 input [2:0] fsr4_bsinitclk;
358 input [2:0] fsr4_fclk;
359 input [2:0] fsr4_fclrz;
360 input [2:0] fsr4_fdi;
361 input [13:0] FBDIMM2A_RX_N;
362 input [13:0] FBDIMM2A_RX_P;
363 input [2:0] fsr4_stciclk;
364 input [2:0] fsr4_stcid;
365 input [2:0] fsr4_testclkr;
366 input [2:0] fsr4_testclkt;
367
368 output [11:0] fsr5_mcu2_rd0;
369 output [11:0] fsr5_mcu2_rd1;
370 output [11:0] fsr5_mcu2_rd2;
371 output [11:0] fsr5_mcu2_rd3;
372 output [11:0] fsr5_mcu2_rd4;
373 output [11:0] fsr5_mcu2_rd5;
374 output [11:0] fsr5_mcu2_rd6;
375 output [11:0] fsr5_mcu2_rd7;
376 output [11:0] fsr5_mcu2_rd8;
377 output [11:0] fsr5_mcu2_rd9;
378 output [11:0] fsr5_mcu2_rd10;
379 output [11:0] fsr5_mcu2_rd11;
380 output [11:0] fsr5_mcu2_rd12;
381 output [11:0] fsr5_mcu2_rd13;
382 output [2:0] fsr5_mcu2_stspll_lock;
383 output [13:0] fsr5_mcu2_stsrx_testfail;
384 output [13:0] fsr5_mcu2_stsrx_sync;
385 output [13:0] fsr5_mcu2_stsrx_losdtct;
386 output [13:0] fsr5_mcu2_stsrx_bsrxp;
387 output [13:0] fsr5_mcu2_stsrx_bsrxn;
388 output [9:0] fsr5_mcu2_ststx_testfail;
389 output [13:0] fsr5_mcu2_rxbclk;
390 output [9:0] FBDIMM2B_TX_N;
391 output [9:0] FBDIMM2B_TX_P;
392 output [2:0] FBDIMM2B_AMUX;
393 output [2:0] fsr5_fdo;
394 output [2:0] fsr5_stciq;
395
396 input [6:0] mcu2_fsr5_cfgpll0;
397 input [6:0] mcu2_fsr5_cfgpll1;
398 input [6:0] mcu2_fsr5_cfgpll2;
399 input [19:0] mcu2_fsr5_cfgrx0;
400 input [19:0] mcu2_fsr5_cfgrx1;
401 input [19:0] mcu2_fsr5_cfgrx2;
402 input [19:0] mcu2_fsr5_cfgrx3;
403 input [19:0] mcu2_fsr5_cfgrx4;
404 input [19:0] mcu2_fsr5_cfgrx5;
405 input [19:0] mcu2_fsr5_cfgrx6;
406 input [19:0] mcu2_fsr5_cfgrx7;
407 input [19:0] mcu2_fsr5_cfgrx8;
408 input [19:0] mcu2_fsr5_cfgrx9;
409 input [19:0] mcu2_fsr5_cfgrx10;
410 input [19:0] mcu2_fsr5_cfgrx11;
411 input [19:0] mcu2_fsr5_cfgrx12;
412 input [19:0] mcu2_fsr5_cfgrx13;
413 input [15:0] mcu2_fsr5_cfgtx0;
414 input [15:0] mcu2_fsr5_cfgtx1;
415 input [15:0] mcu2_fsr5_cfgtx2;
416 input [15:0] mcu2_fsr5_cfgtx3;
417 input [15:0] mcu2_fsr5_cfgtx4;
418 input [15:0] mcu2_fsr5_cfgtx5;
419 input [15:0] mcu2_fsr5_cfgtx6;
420 input [15:0] mcu2_fsr5_cfgtx7;
421 input [15:0] mcu2_fsr5_cfgtx8;
422 input [15:0] mcu2_fsr5_cfgtx9;
423 input [17:0] mcu2_fsr5_testcfg0;
424 input [17:0] mcu2_fsr5_testcfg1;
425 input [17:0] mcu2_fsr5_testcfg2;
426 input [11:0] mcu2_fsr5_td0;
427 input [11:0] mcu2_fsr5_td1;
428 input [11:0] mcu2_fsr5_td2;
429 input [11:0] mcu2_fsr5_td3;
430 input [11:0] mcu2_fsr5_td4;
431 input [11:0] mcu2_fsr5_td5;
432 input [11:0] mcu2_fsr5_td6;
433 input [11:0] mcu2_fsr5_td7;
434 input [11:0] mcu2_fsr5_td8;
435 input [11:0] mcu2_fsr5_td9;
436 input [5:0] fsr5_stcicfg;
437 input [2:0] fsr5_txbclkin;
438 input [13:0] fsr5_rxbclkin;
439 input [2:0] fsr5_bsinitclk;
440 input [2:0] fsr5_fclk;
441 input [2:0] fsr5_fclrz;
442 input [2:0] fsr5_fdi;
443 input [13:0] FBDIMM2B_RX_N;
444 input [13:0] FBDIMM2B_RX_P;
445 input [2:0] fsr5_stciclk;
446 input [2:0] fsr5_stcid;
447 input [2:0] fsr5_testclkr;
448 input [2:0] fsr5_testclkt;
449
450 output [11:0] fsr6_mcu3_rd0;
451 output [11:0] fsr6_mcu3_rd1;
452 output [11:0] fsr6_mcu3_rd2;
453 output [11:0] fsr6_mcu3_rd3;
454 output [11:0] fsr6_mcu3_rd4;
455 output [11:0] fsr6_mcu3_rd5;
456 output [11:0] fsr6_mcu3_rd6;
457 output [11:0] fsr6_mcu3_rd7;
458 output [11:0] fsr6_mcu3_rd8;
459 output [11:0] fsr6_mcu3_rd9;
460 output [11:0] fsr6_mcu3_rd10;
461 output [11:0] fsr6_mcu3_rd11;
462 output [11:0] fsr6_mcu3_rd12;
463 output [11:0] fsr6_mcu3_rd13;
464 output [2:0] fsr6_mcu3_stspll_lock;
465 output [13:0] fsr6_mcu3_stsrx_testfail;
466 output [13:0] fsr6_mcu3_stsrx_sync;
467 output [13:0] fsr6_mcu3_stsrx_losdtct;
468 output [13:0] fsr6_mcu3_stsrx_bsrxp;
469 output [13:0] fsr6_mcu3_stsrx_bsrxn;
470 output [9:0] fsr6_mcu3_ststx_testfail;
471 output [13:0] fsr6_mcu3_rxbclk;
472 output [9:0] FBDIMM3A_TX_N;
473 output [9:0] FBDIMM3A_TX_P;
474 output [2:0] FBDIMM3A_AMUX;
475 output [2:0] fsr6_fdo;
476 output [2:0] fsr6_stciq;
477
478 input [6:0] mcu3_fsr6_cfgpll0;
479 input [6:0] mcu3_fsr6_cfgpll1;
480 input [6:0] mcu3_fsr6_cfgpll2;
481 input [19:0] mcu3_fsr6_cfgrx0;
482 input [19:0] mcu3_fsr6_cfgrx1;
483 input [19:0] mcu3_fsr6_cfgrx2;
484 input [19:0] mcu3_fsr6_cfgrx3;
485 input [19:0] mcu3_fsr6_cfgrx4;
486 input [19:0] mcu3_fsr6_cfgrx5;
487 input [19:0] mcu3_fsr6_cfgrx6;
488 input [19:0] mcu3_fsr6_cfgrx7;
489 input [19:0] mcu3_fsr6_cfgrx8;
490 input [19:0] mcu3_fsr6_cfgrx9;
491 input [19:0] mcu3_fsr6_cfgrx10;
492 input [19:0] mcu3_fsr6_cfgrx11;
493 input [19:0] mcu3_fsr6_cfgrx12;
494 input [19:0] mcu3_fsr6_cfgrx13;
495 input [15:0] mcu3_fsr6_cfgtx0;
496 input [15:0] mcu3_fsr6_cfgtx1;
497 input [15:0] mcu3_fsr6_cfgtx2;
498 input [15:0] mcu3_fsr6_cfgtx3;
499 input [15:0] mcu3_fsr6_cfgtx4;
500 input [15:0] mcu3_fsr6_cfgtx5;
501 input [15:0] mcu3_fsr6_cfgtx6;
502 input [15:0] mcu3_fsr6_cfgtx7;
503 input [15:0] mcu3_fsr6_cfgtx8;
504 input [15:0] mcu3_fsr6_cfgtx9;
505 input [17:0] mcu3_fsr6_testcfg0;
506 input [17:0] mcu3_fsr6_testcfg1;
507 input [17:0] mcu3_fsr6_testcfg2;
508 input [11:0] mcu3_fsr6_td0;
509 input [11:0] mcu3_fsr6_td1;
510 input [11:0] mcu3_fsr6_td2;
511 input [11:0] mcu3_fsr6_td3;
512 input [11:0] mcu3_fsr6_td4;
513 input [11:0] mcu3_fsr6_td5;
514 input [11:0] mcu3_fsr6_td6;
515 input [11:0] mcu3_fsr6_td7;
516 input [11:0] mcu3_fsr6_td8;
517 input [11:0] mcu3_fsr6_td9;
518 input [5:0] fsr6_stcicfg;
519 input [2:0] fsr6_txbclkin;
520 input [13:0] fsr6_rxbclkin;
521 input [2:0] fsr6_bsinitclk;
522 input [2:0] fsr6_fclk;
523 input [2:0] fsr6_fclrz;
524 input [2:0] fsr6_fdi;
525 input [13:0] FBDIMM3A_RX_N;
526 input [13:0] FBDIMM3A_RX_P;
527 input [2:0] fsr6_stciclk;
528 input [2:0] fsr6_stcid;
529 input [2:0] fsr6_testclkr;
530 input [2:0] fsr6_testclkt;
531
532 input fsr_right_atpgd;
533 output fsr_right_atpgq;
534
535 input FBDIMM2_REFCLK_N;
536 input FBDIMM2_REFCLK_P;
537
538 input VDDA;
539 input VDDD;
540 input VDDR;
541 input VDDT;
542 input VSSA;
543
544 assign clk622r_r_23 = FBDIMM2_REFCLK_P;
545 assign clk622r_r_23x = FBDIMM2_REFCLK_N;
546 assign clk622r_r_22 = FBDIMM2_REFCLK_P;
547 assign clk622r_r_22x = FBDIMM2_REFCLK_N;
548 assign clk622r_r_21 = FBDIMM2_REFCLK_P;
549 assign clk622r_r_21x = FBDIMM2_REFCLK_N;
550 assign clk622r_r_19 = FBDIMM2_REFCLK_P;
551 assign clk622r_r_19x = FBDIMM2_REFCLK_N;
552 assign clk622r_r_18 = FBDIMM2_REFCLK_P;
553 assign clk622r_r_18x = FBDIMM2_REFCLK_N;
554 assign clk622r_r_17 = FBDIMM2_REFCLK_P;
555 assign clk622r_r_17x = FBDIMM2_REFCLK_N;
556 assign clk622r_r_16 = FBDIMM2_REFCLK_P;
557 assign clk622r_r_16x = FBDIMM2_REFCLK_N;
558 assign clk622r_r_15 = FBDIMM2_REFCLK_P;
559 assign clk622r_r_15x = FBDIMM2_REFCLK_N;
560 assign clk622r_r_14 = FBDIMM2_REFCLK_P;
561 assign clk622r_r_14x = FBDIMM2_REFCLK_N;
562
563 wire [9:0] fsr4_txbclk_unused;
564 wire [13:0] fsr4_rxbclklln_unused;
565 wire [13:0] fsr4_rxbclkllp_unused;
566 wire [3:0] fsr4_mcu2_stspll_b80;
567 wire [3:0] fsr4_mcu2_stspll_b81;
568 wire [3:0] fsr4_mcu2_stspll_b62;
569 wire [7:0] fsr4_mcu2_stsrx0_unused;
570 wire [7:0] fsr4_mcu2_stsrx1_unused;
571 wire [7:0] fsr4_mcu2_stsrx2_unused;
572 wire [7:0] fsr4_mcu2_stsrx3_unused;
573 wire [7:0] fsr4_mcu2_stsrx4_unused;
574 wire [7:0] fsr4_mcu2_stsrx5_unused;
575 wire [7:0] fsr4_mcu2_stsrx6_unused;
576 wire [7:0] fsr4_mcu2_stsrx7_unused;
577 wire [7:0] fsr4_mcu2_stsrx8_unused;
578 wire [7:0] fsr4_mcu2_stsrx9_unused;
579 wire [7:0] fsr4_mcu2_stsrx10_unused;
580 wire [7:0] fsr4_mcu2_stsrx11_unused;
581 wire [7:0] fsr4_mcu2_stsrx12_unused;
582 wire [7:0] fsr4_mcu2_stsrx13_unused;
583 wire [3:0] fsr4_mcu2_ststx0_unused;
584 wire [3:0] fsr4_mcu2_ststx1_unused;
585 wire [3:0] fsr4_mcu2_ststx2_unused;
586 wire [3:0] fsr4_mcu2_ststx3_unused;
587 wire [3:0] fsr4_mcu2_ststx4_unused;
588 wire [3:0] fsr4_mcu2_ststx5_unused;
589 wire [3:0] fsr4_mcu2_ststx6_unused;
590 wire [3:0] fsr4_mcu2_ststx7_unused;
591 wire [3:0] fsr4_mcu2_ststx8_unused;
592 wire [3:0] fsr4_mcu2_ststx9_unused;
593 wire [1:0] fsr4_rdll0_b80;
594 wire [1:0] fsr4_rdll1_b80;
595 wire [1:0] fsr4_rdll2_b80;
596 wire [1:0] fsr4_rdll3_b80;
597 wire [1:0] fsr4_rdll0_b81;
598 wire [1:0] fsr4_rdll1_b81;
599 wire [1:0] fsr4_rdll2_b81;
600 wire [1:0] fsr4_rdll3_b81;
601 wire [1:0] fsr4_rdll0_b62;
602 wire [1:0] fsr4_rdll1_b62;
603 wire [1:0] fsr4_rdll2_b62;
604 wire [1:0] fsr4_rdll3_b62;
605
606 wire [9:0] fsr5_txbclk_unused;
607 wire [13:0] fsr5_rxbclklln_unused;
608 wire [13:0] fsr5_rxbclkllp_unused;
609 wire [3:0] fsr5_mcu2_stspll_b80;
610 wire [3:0] fsr5_mcu2_stspll_b81;
611 wire [3:0] fsr5_mcu2_stspll_b62;
612 wire [7:0] fsr5_mcu2_stsrx0_unused;
613 wire [7:0] fsr5_mcu2_stsrx1_unused;
614 wire [7:0] fsr5_mcu2_stsrx2_unused;
615 wire [7:0] fsr5_mcu2_stsrx3_unused;
616 wire [7:0] fsr5_mcu2_stsrx4_unused;
617 wire [7:0] fsr5_mcu2_stsrx5_unused;
618 wire [7:0] fsr5_mcu2_stsrx6_unused;
619 wire [7:0] fsr5_mcu2_stsrx7_unused;
620 wire [7:0] fsr5_mcu2_stsrx8_unused;
621 wire [7:0] fsr5_mcu2_stsrx9_unused;
622 wire [7:0] fsr5_mcu2_stsrx10_unused;
623 wire [7:0] fsr5_mcu2_stsrx11_unused;
624 wire [7:0] fsr5_mcu2_stsrx12_unused;
625 wire [7:0] fsr5_mcu2_stsrx13_unused;
626 wire [3:0] fsr5_mcu2_ststx0_unused;
627 wire [3:0] fsr5_mcu2_ststx1_unused;
628 wire [3:0] fsr5_mcu2_ststx2_unused;
629 wire [3:0] fsr5_mcu2_ststx3_unused;
630 wire [3:0] fsr5_mcu2_ststx4_unused;
631 wire [3:0] fsr5_mcu2_ststx5_unused;
632 wire [3:0] fsr5_mcu2_ststx6_unused;
633 wire [3:0] fsr5_mcu2_ststx7_unused;
634 wire [3:0] fsr5_mcu2_ststx8_unused;
635 wire [3:0] fsr5_mcu2_ststx9_unused;
636 wire [1:0] fsr5_rdll0_b80;
637 wire [1:0] fsr5_rdll1_b80;
638 wire [1:0] fsr5_rdll2_b80;
639 wire [1:0] fsr5_rdll3_b80;
640 wire [1:0] fsr5_rdll0_b81;
641 wire [1:0] fsr5_rdll1_b81;
642 wire [1:0] fsr5_rdll2_b81;
643 wire [1:0] fsr5_rdll3_b81;
644 wire [1:0] fsr5_rdll0_b62;
645 wire [1:0] fsr5_rdll1_b62;
646 wire [1:0] fsr5_rdll2_b62;
647 wire [1:0] fsr5_rdll3_b62;
648
649 wire [9:0] fsr6_txbclk_unused;
650 wire [13:0] fsr6_rxbclklln_unused;
651 wire [13:0] fsr6_rxbclkllp_unused;
652 wire [3:0] fsr6_mcu3_stspll_b80;
653 wire [3:0] fsr6_mcu3_stspll_b81;
654 wire [3:0] fsr6_mcu3_stspll_b62;
655 wire [7:0] fsr6_mcu3_stsrx0_unused;
656 wire [7:0] fsr6_mcu3_stsrx1_unused;
657 wire [7:0] fsr6_mcu3_stsrx2_unused;
658 wire [7:0] fsr6_mcu3_stsrx3_unused;
659 wire [7:0] fsr6_mcu3_stsrx4_unused;
660 wire [7:0] fsr6_mcu3_stsrx5_unused;
661 wire [7:0] fsr6_mcu3_stsrx6_unused;
662 wire [7:0] fsr6_mcu3_stsrx7_unused;
663 wire [7:0] fsr6_mcu3_stsrx8_unused;
664 wire [7:0] fsr6_mcu3_stsrx9_unused;
665 wire [7:0] fsr6_mcu3_stsrx10_unused;
666 wire [7:0] fsr6_mcu3_stsrx11_unused;
667 wire [7:0] fsr6_mcu3_stsrx12_unused;
668 wire [7:0] fsr6_mcu3_stsrx13_unused;
669 wire [3:0] fsr6_mcu3_ststx0_unused;
670 wire [3:0] fsr6_mcu3_ststx1_unused;
671 wire [3:0] fsr6_mcu3_ststx2_unused;
672 wire [3:0] fsr6_mcu3_ststx3_unused;
673 wire [3:0] fsr6_mcu3_ststx4_unused;
674 wire [3:0] fsr6_mcu3_ststx5_unused;
675 wire [3:0] fsr6_mcu3_ststx6_unused;
676 wire [3:0] fsr6_mcu3_ststx7_unused;
677 wire [3:0] fsr6_mcu3_ststx8_unused;
678 wire [3:0] fsr6_mcu3_ststx9_unused;
679 wire [1:0] fsr6_rdll0_b80;
680 wire [1:0] fsr6_rdll1_b80;
681 wire [1:0] fsr6_rdll2_b80;
682 wire [1:0] fsr6_rdll3_b80;
683 wire [1:0] fsr6_rdll0_b81;
684 wire [1:0] fsr6_rdll1_b81;
685 wire [1:0] fsr6_rdll2_b81;
686 wire [1:0] fsr6_rdll3_b81;
687 wire [1:0] fsr6_rdll0_b62;
688 wire [1:0] fsr6_rdll1_b62;
689 wire [1:0] fsr6_rdll2_b62;
690 wire [1:0] fsr6_rdll3_b62;
691
692 wire fsr4_atpgmq_b80;
693 wire fsr4_atpgmq_a8;
694 wire fsr4_atpgmq_b81;
695 wire [3:0] fsr4_atpgrq_b80;
696 wire [5:0] fsr4_atpgrq_a8;
697 wire [3:0] fsr4_atpgrq_b81;
698 wire [3:0] fsr4_atpgtq_b80;
699 wire [1:0] fsr4_atpgtq_a8;
700 wire [3:0] fsr4_atpgtq_b81;
701
702 wire fsr5_atpgmq_b80;
703 wire fsr5_atpgmq_a8;
704 wire fsr5_atpgmq_b81;
705 wire [3:0] fsr5_atpgrq_b80;
706 wire [5:0] fsr5_atpgrq_a8;
707 wire [3:0] fsr5_atpgrq_b81;
708 wire [3:0] fsr5_atpgtq_b80;
709 wire [1:0] fsr5_atpgtq_a8;
710 wire [3:0] fsr5_atpgtq_b81;
711
712 wire fsr6_atpgmq_b80;
713 wire fsr6_atpgmq_a8;
714 wire fsr6_atpgmq_b81;
715 wire [3:0] fsr6_atpgrq_b80;
716 wire [5:0] fsr6_atpgrq_a8;
717 wire [3:0] fsr6_atpgrq_b81;
718 wire [3:0] fsr6_atpgtq_b80;
719 wire [1:0] fsr6_atpgtq_a8;
720 wire [3:0] fsr6_atpgtq_b81;
721
722
723// first serdes macro: rx ports 0-3, tx ports 0-3
724
725wiz6c2b8n6d2t fsr4_b8_0 (
726 .bsinitclk ( fsr4_bsinitclk[0]),
727 .cfgpll ({2'b0, mcu2_fsr4_cfgpll0[6:5], 3'b0, mcu2_fsr4_cfgpll0[4:0]}),
728 .cfgrx0 ({2'b0, mcu2_fsr4_cfgrx0[19:18], 1'b0, mcu2_fsr4_cfgrx0[17:9], 1'b0, mcu2_fsr4_cfgrx0[8],
729 1'b0, mcu2_fsr4_cfgrx0[7:2], 3'b0, mcu2_fsr4_cfgrx0[1:0]}),
730 .cfgrx1 ({2'b0, mcu2_fsr4_cfgrx1[19:18], 1'b0, mcu2_fsr4_cfgrx1[17:9], 1'b0, mcu2_fsr4_cfgrx1[8],
731 1'b0, mcu2_fsr4_cfgrx1[7:2], 3'b0, mcu2_fsr4_cfgrx1[1:0]}),
732 .cfgrx2 ({2'b0, mcu2_fsr4_cfgrx2[19:18], 1'b0, mcu2_fsr4_cfgrx2[17:9], 1'b0, mcu2_fsr4_cfgrx2[8],
733 1'b0, mcu2_fsr4_cfgrx2[7:2], 3'b0, mcu2_fsr4_cfgrx2[1:0]}),
734 .cfgrx3 ({2'b0, mcu2_fsr4_cfgrx3[19:18], 1'b0, mcu2_fsr4_cfgrx3[17:9], 1'b0, mcu2_fsr4_cfgrx3[8],
735 1'b0, mcu2_fsr4_cfgrx3[7:2], 3'b0, mcu2_fsr4_cfgrx3[1:0]}),
736 .cfgtx0 ({1'b0, mcu2_fsr4_cfgtx0[15:2], 3'b0, mcu2_fsr4_cfgtx0[1:0]}),
737 .cfgtx1 ({1'b0, mcu2_fsr4_cfgtx1[15:2], 3'b0, mcu2_fsr4_cfgtx1[1:0]}),
738 .cfgtx2 ({1'b0, mcu2_fsr4_cfgtx2[15:2], 3'b0, mcu2_fsr4_cfgtx2[1:0]}),
739 .cfgtx3 ({1'b0, mcu2_fsr4_cfgtx3[15:2], 3'b0, mcu2_fsr4_cfgtx3[1:0]}),
740 .fclk ( fsr4_fclk[0] ),
741 .fclrz ( fsr4_fclrz[0] ),
742 .fdi ( fsr4_fdi[0] ),
743 .refclkn ( clk622r_r_14x ),
744 .refclkp ( clk622r_r_14 ),
745 .rxbclkin ( fsr4_rxbclkin[3:0] ),
746 .rxn0 ( FBDIMM2A_RX_N[0] ),
747 .rxn1 ( FBDIMM2A_RX_N[1] ),
748 .rxn2 ( FBDIMM2A_RX_N[2] ),
749 .rxn3 ( FBDIMM2A_RX_N[3] ),
750 .rxp0 ( FBDIMM2A_RX_P[0] ),
751 .rxp1 ( FBDIMM2A_RX_P[1] ),
752 .rxp2 ( FBDIMM2A_RX_P[2] ),
753 .rxp3 ( FBDIMM2A_RX_P[3] ),
754 .stcicfg ( fsr4_stcicfg[1:0] ),
755 .stciclk ( fsr4_stciclk[0] ),
756 .stcid ( fsr4_stcid[0] ),
757 .td0 ( {mcu2_fsr4_td0[0], mcu2_fsr4_td0[1], mcu2_fsr4_td0[2], mcu2_fsr4_td0[3],
758 mcu2_fsr4_td0[4], mcu2_fsr4_td0[5], mcu2_fsr4_td0[6], mcu2_fsr4_td0[7],
759 mcu2_fsr4_td0[8], mcu2_fsr4_td0[9], mcu2_fsr4_td0[10], mcu2_fsr4_td0[11]} ),
760 .td1 ( {mcu2_fsr4_td1[0], mcu2_fsr4_td1[1], mcu2_fsr4_td1[2], mcu2_fsr4_td1[3],
761 mcu2_fsr4_td1[4], mcu2_fsr4_td1[5], mcu2_fsr4_td1[6], mcu2_fsr4_td1[7],
762 mcu2_fsr4_td1[8], mcu2_fsr4_td1[9], mcu2_fsr4_td1[10], mcu2_fsr4_td1[11]} ),
763 .td2 ( {mcu2_fsr4_td2[0], mcu2_fsr4_td2[1], mcu2_fsr4_td2[2], mcu2_fsr4_td2[3],
764 mcu2_fsr4_td2[4], mcu2_fsr4_td2[5], mcu2_fsr4_td2[6], mcu2_fsr4_td2[7],
765 mcu2_fsr4_td2[8], mcu2_fsr4_td2[9], mcu2_fsr4_td2[10], mcu2_fsr4_td2[11]} ),
766 .td3 ( {mcu2_fsr4_td3[0], mcu2_fsr4_td3[1], mcu2_fsr4_td3[2], mcu2_fsr4_td3[3],
767 mcu2_fsr4_td3[4], mcu2_fsr4_td3[5], mcu2_fsr4_td3[6], mcu2_fsr4_td3[7],
768 mcu2_fsr4_td3[8], mcu2_fsr4_td3[9], mcu2_fsr4_td3[10], mcu2_fsr4_td3[11]} ),
769 .testcfg ( {mcu2_fsr4_testcfg0[17:14], 1'b0, mcu2_fsr4_testcfg0[13:11], 1'b0, mcu2_fsr4_testcfg0[10:0]} ),
770 .testclkr ( fsr4_testclkr[0] ),
771 .testclkt ( fsr4_testclkt[0] ),
772 .txbclkin ( {4{fsr4_txbclkin[0]}} ),
773 .amux ( FBDIMM2A_AMUX[0] ),
774 .fdo ( fsr4_fdo[0] ),
775 .rd0 ( {fsr4_mcu2_rd0[0], fsr4_mcu2_rd0[1], fsr4_mcu2_rd0[2], fsr4_mcu2_rd0[3],
776 fsr4_mcu2_rd0[4], fsr4_mcu2_rd0[5], fsr4_mcu2_rd0[6], fsr4_mcu2_rd0[7],
777 fsr4_mcu2_rd0[8], fsr4_mcu2_rd0[9], fsr4_mcu2_rd0[10], fsr4_mcu2_rd0[11]} ),
778 .rd1 ( {fsr4_mcu2_rd1[0], fsr4_mcu2_rd1[1], fsr4_mcu2_rd1[2], fsr4_mcu2_rd1[3],
779 fsr4_mcu2_rd1[4], fsr4_mcu2_rd1[5], fsr4_mcu2_rd1[6], fsr4_mcu2_rd1[7],
780 fsr4_mcu2_rd1[8], fsr4_mcu2_rd1[9], fsr4_mcu2_rd1[10], fsr4_mcu2_rd1[11]} ),
781 .rd2 ( {fsr4_mcu2_rd2[0], fsr4_mcu2_rd2[1], fsr4_mcu2_rd2[2], fsr4_mcu2_rd2[3],
782 fsr4_mcu2_rd2[4], fsr4_mcu2_rd2[5], fsr4_mcu2_rd2[6], fsr4_mcu2_rd2[7],
783 fsr4_mcu2_rd2[8], fsr4_mcu2_rd2[9], fsr4_mcu2_rd2[10], fsr4_mcu2_rd2[11]} ),
784 .rd3 ( {fsr4_mcu2_rd3[0], fsr4_mcu2_rd3[1], fsr4_mcu2_rd3[2], fsr4_mcu2_rd3[3],
785 fsr4_mcu2_rd3[4], fsr4_mcu2_rd3[5], fsr4_mcu2_rd3[6], fsr4_mcu2_rd3[7],
786 fsr4_mcu2_rd3[8], fsr4_mcu2_rd3[9], fsr4_mcu2_rd3[10], fsr4_mcu2_rd3[11]} ),
787 .rdll0 ( fsr4_rdll0_b80[1:0] ),
788 .rdll1 ( fsr4_rdll1_b80[1:0] ),
789 .rdll2 ( fsr4_rdll2_b80[1:0] ),
790 .rdll3 ( fsr4_rdll3_b80[1:0] ),
791 .rxbclk ( fsr4_mcu2_rxbclk[3:0] ),
792 .rxbclklln ( fsr4_rxbclklln_unused[3:0] ),
793 .rxbclkllp ( fsr4_rxbclkllp_unused[3:0] ),
794 .stciq ( fsr4_stciq[0] ),
795 .stspll ( {fsr4_mcu2_stspll_b80[2:0], fsr4_mcu2_stspll_lock[0]} ),
796 .stsrx0 ( {fsr4_mcu2_stsrx0_unused[2:1], fsr4_mcu2_stsrx_bsrxn[0], fsr4_mcu2_stsrx_bsrxp[0],
797 fsr4_mcu2_stsrx_losdtct[0], fsr4_mcu2_stsrx0_unused[0], fsr4_mcu2_stsrx_sync[0],
798 fsr4_mcu2_stsrx_testfail[0]} ),
799 .stsrx1 ( {fsr4_mcu2_stsrx1_unused[2:1], fsr4_mcu2_stsrx_bsrxn[1], fsr4_mcu2_stsrx_bsrxp[1],
800 fsr4_mcu2_stsrx_losdtct[1], fsr4_mcu2_stsrx1_unused[0], fsr4_mcu2_stsrx_sync[1],
801 fsr4_mcu2_stsrx_testfail[1]} ),
802 .stsrx2 ( {fsr4_mcu2_stsrx2_unused[2:1], fsr4_mcu2_stsrx_bsrxn[2], fsr4_mcu2_stsrx_bsrxp[2],
803 fsr4_mcu2_stsrx_losdtct[2], fsr4_mcu2_stsrx2_unused[0], fsr4_mcu2_stsrx_sync[2],
804 fsr4_mcu2_stsrx_testfail[2]} ),
805 .stsrx3 ( {fsr4_mcu2_stsrx3_unused[2:1], fsr4_mcu2_stsrx_bsrxn[3], fsr4_mcu2_stsrx_bsrxp[3],
806 fsr4_mcu2_stsrx_losdtct[3], fsr4_mcu2_stsrx3_unused[0], fsr4_mcu2_stsrx_sync[3],
807 fsr4_mcu2_stsrx_testfail[3]} ),
808 .ststx0 ( {fsr4_mcu2_ststx0_unused[2:0], fsr4_mcu2_ststx_testfail[0]} ),
809 .ststx1 ( {fsr4_mcu2_ststx1_unused[2:0], fsr4_mcu2_ststx_testfail[1]} ),
810 .ststx2 ( {fsr4_mcu2_ststx2_unused[2:0], fsr4_mcu2_ststx_testfail[2]} ),
811 .ststx3 ( {fsr4_mcu2_ststx3_unused[2:0], fsr4_mcu2_ststx_testfail[3]} ),
812 .txbclk ( fsr4_txbclk_unused[3:0] ),
813 .txn0 ( FBDIMM2A_TX_N[0] ),
814 .txn1 ( FBDIMM2A_TX_N[1] ),
815 .txn2 ( FBDIMM2A_TX_N[2] ),
816 .txn3 ( FBDIMM2A_TX_N[3] ),
817 .txp0 ( FBDIMM2A_TX_P[0] ),
818 .txp1 ( FBDIMM2A_TX_P[1] ),
819 .txp2 ( FBDIMM2A_TX_P[2] ),
820 .txp3 ( FBDIMM2A_TX_P[3] ),
821 .atpgmd ( fsr4_atpgtq_b80[2] ),
822 .atpgmq ( fsr4_atpgmq_b80 ),
823 .atpgrd ( {fsr4_atpgtq_b80[3],fsr4_atpgrq_b80[3],fsr4_atpgtq_b80[1],fsr4_atpgrq_b80[1]} ),
824 .atpgrq ( fsr4_atpgrq_b80[3:0] ),
825 .atpgtd ( {fsr4_atpgtq_a8[0],fsr4_atpgrq_b80[2],fsr4_atpgmq_b80,fsr4_atpgrq_b80[0]} ),
826 .atpgtq ( {fsr4_atpgtq_b80[3:1],fsr_right_atpgq} ),
827 .vdda ( VDDA ),
828 .vddd ( VDDD ),
829 .vddr ( VDDR ),
830 .vddt ( VDDT ),
831 .vssa ( VSSA )
832 );
833
834
835// second serdes macro: RX ports 4-9, TX ports 4-5
836
837wiz6c2a8n6d2t fsr4_a8 (
838 .bsinitclk ( fsr4_bsinitclk[1]),
839 .cfgpll ({2'b0, mcu2_fsr4_cfgpll1[6:5], 3'b0, mcu2_fsr4_cfgpll1[4:0]}),
840 .cfgrx0 ({2'b0, mcu2_fsr4_cfgrx4[19:18], 1'b0, mcu2_fsr4_cfgrx4[17:9], 1'b0, mcu2_fsr4_cfgrx4[8],
841 1'b0, mcu2_fsr4_cfgrx4[7:2], 3'b0, mcu2_fsr4_cfgrx4[1:0]}),
842 .cfgrx1 ({2'b0, mcu2_fsr4_cfgrx5[19:18], 1'b0, mcu2_fsr4_cfgrx5[17:9], 1'b0, mcu2_fsr4_cfgrx5[8],
843 1'b0, mcu2_fsr4_cfgrx5[7:2], 3'b0, mcu2_fsr4_cfgrx5[1:0]}),
844 .cfgrx2 ({2'b0, mcu2_fsr4_cfgrx6[19:18], 1'b0, mcu2_fsr4_cfgrx6[17:9], 1'b0, mcu2_fsr4_cfgrx6[8],
845 1'b0, mcu2_fsr4_cfgrx6[7:2], 3'b0, mcu2_fsr4_cfgrx6[1:0]}),
846 .cfgrx3 ({2'b0, mcu2_fsr4_cfgrx7[19:18], 1'b0, mcu2_fsr4_cfgrx7[17:9], 1'b0, mcu2_fsr4_cfgrx7[8],
847 1'b0, mcu2_fsr4_cfgrx7[7:2], 3'b0, mcu2_fsr4_cfgrx7[1:0]}),
848 .cfgrx4 ({2'b0, mcu2_fsr4_cfgrx8[19:18], 1'b0, mcu2_fsr4_cfgrx8[17:9], 1'b0, mcu2_fsr4_cfgrx8[8],
849 1'b0, mcu2_fsr4_cfgrx8[7:2], 3'b0, mcu2_fsr4_cfgrx8[1:0]}),
850 .cfgrx5 ({2'b0, mcu2_fsr4_cfgrx9[19:18], 1'b0, mcu2_fsr4_cfgrx9[17:9], 1'b0, mcu2_fsr4_cfgrx9[8],
851 1'b0, mcu2_fsr4_cfgrx9[7:2], 3'b0, mcu2_fsr4_cfgrx9[1:0]}),
852 .cfgtx0 ({1'b0, mcu2_fsr4_cfgtx4[15:2], 3'b0, mcu2_fsr4_cfgtx4[1:0]}),
853 .cfgtx1 ({1'b0, mcu2_fsr4_cfgtx5[15:2], 3'b0, mcu2_fsr4_cfgtx5[1:0]}),
854 .fclk ( fsr4_fclk[1] ),
855 .fclrz ( fsr4_fclrz[1] ),
856 .fdi ( fsr4_fdi[1] ),
857 .refclkn ( clk622r_r_15x ),
858 .refclkp ( clk622r_r_15 ),
859 .rxbclkin ( fsr4_rxbclkin[9:4] ),
860 .rxn0 ( FBDIMM2A_RX_N[4] ),
861 .rxn1 ( FBDIMM2A_RX_N[5] ),
862 .rxn2 ( FBDIMM2A_RX_N[6] ),
863 .rxn3 ( FBDIMM2A_RX_N[7] ),
864 .rxn4 ( FBDIMM2A_RX_N[8] ),
865 .rxn5 ( FBDIMM2A_RX_N[9] ),
866 .rxp0 ( FBDIMM2A_RX_P[4] ),
867 .rxp1 ( FBDIMM2A_RX_P[5] ),
868 .rxp2 ( FBDIMM2A_RX_P[6] ),
869 .rxp3 ( FBDIMM2A_RX_P[7] ),
870 .rxp4 ( FBDIMM2A_RX_P[8] ),
871 .rxp5 ( FBDIMM2A_RX_P[9] ),
872 .stcicfg ( fsr4_stcicfg[3:2] ),
873 .stciclk ( fsr4_stciclk[1] ),
874 .stcid ( fsr4_stcid[1] ),
875 .td0 ( {mcu2_fsr4_td4[0], mcu2_fsr4_td4[1], mcu2_fsr4_td4[2], mcu2_fsr4_td4[3],
876 mcu2_fsr4_td4[4], mcu2_fsr4_td4[5], mcu2_fsr4_td4[6], mcu2_fsr4_td4[7],
877 mcu2_fsr4_td4[8], mcu2_fsr4_td4[9], mcu2_fsr4_td4[10], mcu2_fsr4_td4[11]} ),
878 .td1 ( {mcu2_fsr4_td5[0], mcu2_fsr4_td5[1], mcu2_fsr4_td5[2], mcu2_fsr4_td5[3],
879 mcu2_fsr4_td5[4], mcu2_fsr4_td5[5], mcu2_fsr4_td5[6], mcu2_fsr4_td5[7],
880 mcu2_fsr4_td5[8], mcu2_fsr4_td5[9], mcu2_fsr4_td5[10], mcu2_fsr4_td5[11]} ),
881 .testcfg ( {mcu2_fsr4_testcfg1[17:14], 1'b0, mcu2_fsr4_testcfg1[13:11], 1'b0, mcu2_fsr4_testcfg1[10:0]} ),
882 .testclkr ( fsr4_testclkr[1] ),
883 .testclkt ( fsr4_testclkt[1] ),
884 .txbclkin ( {2{fsr4_txbclkin[1]}} ),
885 .amux ( FBDIMM2A_AMUX[1] ),
886 .fdo ( fsr4_fdo[1] ),
887 .rd0 ( {fsr4_mcu2_rd4[0], fsr4_mcu2_rd4[1], fsr4_mcu2_rd4[2], fsr4_mcu2_rd4[3],
888 fsr4_mcu2_rd4[4], fsr4_mcu2_rd4[5], fsr4_mcu2_rd4[6], fsr4_mcu2_rd4[7],
889 fsr4_mcu2_rd4[8], fsr4_mcu2_rd4[9], fsr4_mcu2_rd4[10], fsr4_mcu2_rd4[11]} ),
890 .rd1 ( {fsr4_mcu2_rd5[0], fsr4_mcu2_rd5[1], fsr4_mcu2_rd5[2], fsr4_mcu2_rd5[3],
891 fsr4_mcu2_rd5[4], fsr4_mcu2_rd5[5], fsr4_mcu2_rd5[6], fsr4_mcu2_rd5[7],
892 fsr4_mcu2_rd5[8], fsr4_mcu2_rd5[9], fsr4_mcu2_rd5[10], fsr4_mcu2_rd5[11]} ),
893 .rd2 ( {fsr4_mcu2_rd6[0], fsr4_mcu2_rd6[1], fsr4_mcu2_rd6[2], fsr4_mcu2_rd6[3],
894 fsr4_mcu2_rd6[4], fsr4_mcu2_rd6[5], fsr4_mcu2_rd6[6], fsr4_mcu2_rd6[7],
895 fsr4_mcu2_rd6[8], fsr4_mcu2_rd6[9], fsr4_mcu2_rd6[10], fsr4_mcu2_rd6[11]} ),
896 .rd3 ( {fsr4_mcu2_rd7[0], fsr4_mcu2_rd7[1], fsr4_mcu2_rd7[2], fsr4_mcu2_rd7[3],
897 fsr4_mcu2_rd7[4], fsr4_mcu2_rd7[5], fsr4_mcu2_rd7[6], fsr4_mcu2_rd7[7],
898 fsr4_mcu2_rd7[8], fsr4_mcu2_rd7[9], fsr4_mcu2_rd7[10], fsr4_mcu2_rd7[11]} ),
899 .rd4 ( {fsr4_mcu2_rd8[0], fsr4_mcu2_rd8[1], fsr4_mcu2_rd8[2], fsr4_mcu2_rd8[3],
900 fsr4_mcu2_rd8[4], fsr4_mcu2_rd8[5], fsr4_mcu2_rd8[6], fsr4_mcu2_rd8[7],
901 fsr4_mcu2_rd8[8], fsr4_mcu2_rd8[9], fsr4_mcu2_rd8[10], fsr4_mcu2_rd8[11]} ),
902 .rd5 ( {fsr4_mcu2_rd9[0], fsr4_mcu2_rd9[1], fsr4_mcu2_rd9[2], fsr4_mcu2_rd9[3],
903 fsr4_mcu2_rd9[4], fsr4_mcu2_rd9[5], fsr4_mcu2_rd9[6], fsr4_mcu2_rd9[7],
904 fsr4_mcu2_rd9[8], fsr4_mcu2_rd9[9], fsr4_mcu2_rd9[10], fsr4_mcu2_rd9[11]} ),
905 .rdll0 ( fsr4_rdll0_b62[1:0] ),
906 .rdll1 ( fsr4_rdll1_b62[1:0] ),
907 .rdll2 ( fsr4_rdll2_b62[1:0] ),
908 .rdll3 ( fsr4_rdll3_b62[1:0] ),
909 .rxbclk ( fsr4_mcu2_rxbclk[9:4] ),
910 .rxbclklln ( fsr4_rxbclklln_unused[9:4] ),
911 .rxbclkllp ( fsr4_rxbclkllp_unused[9:4] ),
912 .stciq ( fsr4_stciq[1] ),
913 .stspll ( {fsr4_mcu2_stspll_b62[2:0], fsr4_mcu2_stspll_lock[1]} ),
914 .stsrx0 ( {fsr4_mcu2_stsrx4_unused[2:1], fsr4_mcu2_stsrx_bsrxn[4], fsr4_mcu2_stsrx_bsrxp[4],
915 fsr4_mcu2_stsrx_losdtct[4], fsr4_mcu2_stsrx4_unused[0], fsr4_mcu2_stsrx_sync[4],
916 fsr4_mcu2_stsrx_testfail[4]} ),
917 .stsrx1 ( {fsr4_mcu2_stsrx5_unused[2:1], fsr4_mcu2_stsrx_bsrxn[5], fsr4_mcu2_stsrx_bsrxp[5],
918 fsr4_mcu2_stsrx_losdtct[5], fsr4_mcu2_stsrx5_unused[0], fsr4_mcu2_stsrx_sync[5],
919 fsr4_mcu2_stsrx_testfail[5]} ),
920 .stsrx2 ( {fsr4_mcu2_stsrx6_unused[2:1], fsr4_mcu2_stsrx_bsrxn[6], fsr4_mcu2_stsrx_bsrxp[6],
921 fsr4_mcu2_stsrx_losdtct[6], fsr4_mcu2_stsrx6_unused[0], fsr4_mcu2_stsrx_sync[6],
922 fsr4_mcu2_stsrx_testfail[6]} ),
923 .stsrx3 ( {fsr4_mcu2_stsrx7_unused[2:1], fsr4_mcu2_stsrx_bsrxn[7], fsr4_mcu2_stsrx_bsrxp[7],
924 fsr4_mcu2_stsrx_losdtct[7], fsr4_mcu2_stsrx7_unused[0], fsr4_mcu2_stsrx_sync[7],
925 fsr4_mcu2_stsrx_testfail[7]} ),
926 .stsrx4 ( {fsr4_mcu2_stsrx8_unused[2:1], fsr4_mcu2_stsrx_bsrxn[8], fsr4_mcu2_stsrx_bsrxp[8],
927 fsr4_mcu2_stsrx_losdtct[8], fsr4_mcu2_stsrx8_unused[0], fsr4_mcu2_stsrx_sync[8],
928 fsr4_mcu2_stsrx_testfail[8]} ),
929 .stsrx5 ( {fsr4_mcu2_stsrx9_unused[2:1], fsr4_mcu2_stsrx_bsrxn[9], fsr4_mcu2_stsrx_bsrxp[9],
930 fsr4_mcu2_stsrx_losdtct[9], fsr4_mcu2_stsrx9_unused[0], fsr4_mcu2_stsrx_sync[9],
931 fsr4_mcu2_stsrx_testfail[9]} ),
932 .ststx0 ( {fsr4_mcu2_ststx4_unused[2:0], fsr4_mcu2_ststx_testfail[4]} ),
933 .ststx1 ( {fsr4_mcu2_ststx5_unused[2:0], fsr4_mcu2_ststx_testfail[5]} ),
934 .txbclk ( fsr4_txbclk_unused[5:4] ),
935 .txn0 ( FBDIMM2A_TX_N[4] ),
936 .txn1 ( FBDIMM2A_TX_N[5] ),
937 .txp0 ( FBDIMM2A_TX_P[4] ),
938 .txp1 ( FBDIMM2A_TX_P[5] ),
939 .atpgmd ( fsr4_atpgrq_a8[5] ),
940 .atpgmq ( fsr4_atpgmq_a8 ),
941 .atpgrd ( {fsr4_atpgrq_a8[2],fsr4_atpgmq_a8,fsr4_atpgtq_a8[1],fsr4_atpgrq_a8[3],fsr4_atpgrq_a8[4],
942 fsr4_atpgrq_a8[1]} ),
943 .atpgrq ( fsr4_atpgrq_a8[5:0] ),
944 .atpgtd ( {fsr4_atpgtq_b81[0],fsr4_atpgrq_a8[0]} ),
945 .atpgtq ( fsr4_atpgtq_a8[1:0] ),
946 .vdda ( VDDA ),
947 .vddd ( VDDD ),
948 .vddr ( VDDR ),
949 .vddt ( VDDT ),
950 .vssa ( VSSA )
951 );
952
953// third serdes macro: RX ports 10-13, TX ports 6-9
954
955wiz6c2b8n6d2t fsr4_b8_1 (
956 .bsinitclk ( fsr4_bsinitclk[2]),
957 .cfgpll ({2'b0, mcu2_fsr4_cfgpll2[6:5], 3'b0, mcu2_fsr4_cfgpll2[4:0]}),
958 .cfgrx0 ({2'b0, mcu2_fsr4_cfgrx10[19:18], 1'b0, mcu2_fsr4_cfgrx10[17:9], 1'b0, mcu2_fsr4_cfgrx10[8],
959 1'b0, mcu2_fsr4_cfgrx10[7:2], 3'b0, mcu2_fsr4_cfgrx10[1:0]}),
960 .cfgrx1 ({2'b0, mcu2_fsr4_cfgrx11[19:18], 1'b0, mcu2_fsr4_cfgrx11[17:9], 1'b0, mcu2_fsr4_cfgrx11[8],
961 1'b0, mcu2_fsr4_cfgrx11[7:2], 3'b0, mcu2_fsr4_cfgrx11[1:0]}),
962 .cfgrx2 ({2'b0, mcu2_fsr4_cfgrx12[19:18], 1'b0, mcu2_fsr4_cfgrx12[17:9], 1'b0, mcu2_fsr4_cfgrx12[8],
963 1'b0, mcu2_fsr4_cfgrx12[7:2], 3'b0, mcu2_fsr4_cfgrx12[1:0]}),
964 .cfgrx3 ({2'b0, mcu2_fsr4_cfgrx13[19:18], 1'b0, mcu2_fsr4_cfgrx13[17:9], 1'b0, mcu2_fsr4_cfgrx13[8],
965 1'b0, mcu2_fsr4_cfgrx13[7:2], 3'b0, mcu2_fsr4_cfgrx13[1:0]}),
966 .cfgtx0 ({1'b0, mcu2_fsr4_cfgtx6[15:2], 3'b0, mcu2_fsr4_cfgtx6[1:0]}),
967 .cfgtx1 ({1'b0, mcu2_fsr4_cfgtx7[15:2], 3'b0, mcu2_fsr4_cfgtx7[1:0]}),
968 .cfgtx2 ({1'b0, mcu2_fsr4_cfgtx8[15:2], 3'b0, mcu2_fsr4_cfgtx8[1:0]}),
969 .cfgtx3 ({1'b0, mcu2_fsr4_cfgtx9[15:2], 3'b0, mcu2_fsr4_cfgtx9[1:0]}),
970 .fclk ( fsr4_fclk[2] ),
971 .fclrz ( fsr4_fclrz[2] ),
972 .fdi ( fsr4_fdi[2] ),
973 .refclkn ( clk622r_r_16x ),
974 .refclkp ( clk622r_r_16 ),
975 .rxbclkin ( fsr4_rxbclkin[13:10] ),
976 .rxn0 ( FBDIMM2A_RX_N[10] ),
977 .rxn1 ( FBDIMM2A_RX_N[11] ),
978 .rxn2 ( FBDIMM2A_RX_N[12] ),
979 .rxn3 ( FBDIMM2A_RX_N[13] ),
980 .rxp0 ( FBDIMM2A_RX_P[10] ),
981 .rxp1 ( FBDIMM2A_RX_P[11] ),
982 .rxp2 ( FBDIMM2A_RX_P[12] ),
983 .rxp3 ( FBDIMM2A_RX_P[13] ),
984 .stcicfg ( fsr4_stcicfg[5:4] ),
985 .stciclk ( fsr4_stciclk[2] ),
986 .stcid ( fsr4_stcid[2] ),
987 .td0 ( {mcu2_fsr4_td6[0], mcu2_fsr4_td6[1], mcu2_fsr4_td6[2], mcu2_fsr4_td6[3],
988 mcu2_fsr4_td6[4], mcu2_fsr4_td6[5], mcu2_fsr4_td6[6], mcu2_fsr4_td6[7],
989 mcu2_fsr4_td6[8], mcu2_fsr4_td6[9], mcu2_fsr4_td6[10], mcu2_fsr4_td6[11]} ),
990 .td1 ( {mcu2_fsr4_td7[0], mcu2_fsr4_td7[1], mcu2_fsr4_td7[2], mcu2_fsr4_td7[3],
991 mcu2_fsr4_td7[4], mcu2_fsr4_td7[5], mcu2_fsr4_td7[6], mcu2_fsr4_td7[7],
992 mcu2_fsr4_td7[8], mcu2_fsr4_td7[9], mcu2_fsr4_td7[10], mcu2_fsr4_td7[11]} ),
993 .td2 ( {mcu2_fsr4_td8[0], mcu2_fsr4_td8[1], mcu2_fsr4_td8[2], mcu2_fsr4_td8[3],
994 mcu2_fsr4_td8[4], mcu2_fsr4_td8[5], mcu2_fsr4_td8[6], mcu2_fsr4_td8[7],
995 mcu2_fsr4_td8[8], mcu2_fsr4_td8[9], mcu2_fsr4_td8[10], mcu2_fsr4_td8[11]} ),
996 .td3 ( {mcu2_fsr4_td9[0], mcu2_fsr4_td9[1], mcu2_fsr4_td9[2], mcu2_fsr4_td9[3],
997 mcu2_fsr4_td9[4], mcu2_fsr4_td9[5], mcu2_fsr4_td9[6], mcu2_fsr4_td9[7],
998 mcu2_fsr4_td9[8], mcu2_fsr4_td9[9], mcu2_fsr4_td9[10], mcu2_fsr4_td9[11]} ),
999 .testcfg ( {mcu2_fsr4_testcfg2[17:14], 1'b0, mcu2_fsr4_testcfg2[13:11], 1'b0, mcu2_fsr4_testcfg2[10:0]} ),
1000 .testclkr ( fsr4_testclkr[2] ),
1001 .testclkt ( fsr4_testclkt[2] ),
1002 .txbclkin ( {4{fsr4_txbclkin[2]}} ),
1003 .amux ( FBDIMM2A_AMUX[2] ),
1004 .fdo ( fsr4_fdo[2] ),
1005 .rd0 ( {fsr4_mcu2_rd10[0], fsr4_mcu2_rd10[1], fsr4_mcu2_rd10[2], fsr4_mcu2_rd10[3],
1006 fsr4_mcu2_rd10[4], fsr4_mcu2_rd10[5], fsr4_mcu2_rd10[6], fsr4_mcu2_rd10[7],
1007 fsr4_mcu2_rd10[8], fsr4_mcu2_rd10[9], fsr4_mcu2_rd10[10], fsr4_mcu2_rd10[11]} ),
1008 .rd1 ( {fsr4_mcu2_rd11[0], fsr4_mcu2_rd11[1], fsr4_mcu2_rd11[2], fsr4_mcu2_rd11[3],
1009 fsr4_mcu2_rd11[4], fsr4_mcu2_rd11[5], fsr4_mcu2_rd11[6], fsr4_mcu2_rd11[7],
1010 fsr4_mcu2_rd11[8], fsr4_mcu2_rd11[9], fsr4_mcu2_rd11[10], fsr4_mcu2_rd11[11]} ),
1011 .rd2 ( {fsr4_mcu2_rd12[0], fsr4_mcu2_rd12[1], fsr4_mcu2_rd12[2], fsr4_mcu2_rd12[3],
1012 fsr4_mcu2_rd12[4], fsr4_mcu2_rd12[5], fsr4_mcu2_rd12[6], fsr4_mcu2_rd12[7],
1013 fsr4_mcu2_rd12[8], fsr4_mcu2_rd12[9], fsr4_mcu2_rd12[10], fsr4_mcu2_rd12[11]} ),
1014 .rd3 ( {fsr4_mcu2_rd13[0], fsr4_mcu2_rd13[1], fsr4_mcu2_rd13[2], fsr4_mcu2_rd13[3],
1015 fsr4_mcu2_rd13[4], fsr4_mcu2_rd13[5], fsr4_mcu2_rd13[6], fsr4_mcu2_rd13[7],
1016 fsr4_mcu2_rd13[8], fsr4_mcu2_rd13[9], fsr4_mcu2_rd13[10], fsr4_mcu2_rd13[11]} ),
1017 .rdll0 ( fsr4_rdll0_b81[1:0] ),
1018 .rdll1 ( fsr4_rdll1_b81[1:0] ),
1019 .rdll2 ( fsr4_rdll2_b81[1:0] ),
1020 .rdll3 ( fsr4_rdll3_b81[1:0] ),
1021 .rxbclk ( fsr4_mcu2_rxbclk[13:10] ),
1022 .rxbclklln ( fsr4_rxbclklln_unused[13:10] ),
1023 .rxbclkllp ( fsr4_rxbclkllp_unused[13:10] ),
1024 .stciq ( fsr4_stciq[2] ),
1025 .stspll ( {fsr4_mcu2_stspll_b81[2:0], fsr4_mcu2_stspll_lock[2]} ),
1026 .stsrx0 ( {fsr4_mcu2_stsrx10_unused[2:1], fsr4_mcu2_stsrx_bsrxn[10], fsr4_mcu2_stsrx_bsrxp[10],
1027 fsr4_mcu2_stsrx_losdtct[10], fsr4_mcu2_stsrx10_unused[0], fsr4_mcu2_stsrx_sync[10],
1028 fsr4_mcu2_stsrx_testfail[10]} ),
1029 .stsrx1 ( {fsr4_mcu2_stsrx11_unused[2:1], fsr4_mcu2_stsrx_bsrxn[11], fsr4_mcu2_stsrx_bsrxp[11],
1030 fsr4_mcu2_stsrx_losdtct[11], fsr4_mcu2_stsrx11_unused[0], fsr4_mcu2_stsrx_sync[11],
1031 fsr4_mcu2_stsrx_testfail[11]} ),
1032 .stsrx2 ( {fsr4_mcu2_stsrx12_unused[2:1], fsr4_mcu2_stsrx_bsrxn[12], fsr4_mcu2_stsrx_bsrxp[12],
1033 fsr4_mcu2_stsrx_losdtct[12], fsr4_mcu2_stsrx12_unused[0], fsr4_mcu2_stsrx_sync[12],
1034 fsr4_mcu2_stsrx_testfail[12]} ),
1035 .stsrx3 ( {fsr4_mcu2_stsrx13_unused[2:1], fsr4_mcu2_stsrx_bsrxn[13], fsr4_mcu2_stsrx_bsrxp[13],
1036 fsr4_mcu2_stsrx_losdtct[13], fsr4_mcu2_stsrx13_unused[0], fsr4_mcu2_stsrx_sync[13],
1037 fsr4_mcu2_stsrx_testfail[13]} ),
1038 .ststx0 ( {fsr4_mcu2_ststx6_unused[2:0], fsr4_mcu2_ststx_testfail[6]} ),
1039 .ststx1 ( {fsr4_mcu2_ststx7_unused[2:0], fsr4_mcu2_ststx_testfail[7]} ),
1040 .ststx2 ( {fsr4_mcu2_ststx8_unused[2:0], fsr4_mcu2_ststx_testfail[8]} ),
1041 .ststx3 ( {fsr4_mcu2_ststx9_unused[2:0], fsr4_mcu2_ststx_testfail[9]} ),
1042 .txbclk ( fsr4_txbclk_unused[9:6] ),
1043 .txn0 ( FBDIMM2A_TX_N[6] ),
1044 .txn1 ( FBDIMM2A_TX_N[7] ),
1045 .txn2 ( FBDIMM2A_TX_N[8] ),
1046 .txn3 ( FBDIMM2A_TX_N[9] ),
1047 .txp0 ( FBDIMM2A_TX_P[6] ),
1048 .txp1 ( FBDIMM2A_TX_P[7] ),
1049 .txp2 ( FBDIMM2A_TX_P[8] ),
1050 .txp3 ( FBDIMM2A_TX_P[9] ),
1051 .atpgmd ( fsr4_atpgtq_b81[2] ),
1052 .atpgmq ( fsr4_atpgmq_b81 ),
1053 .atpgrd ( {fsr4_atpgtq_b81[3],fsr4_atpgrq_b81[3],fsr4_atpgtq_b81[1],fsr4_atpgrq_b81[1]} ),
1054 .atpgrq ( fsr4_atpgrq_b81[3:0] ),
1055 .atpgtd ( {fsr5_atpgtq_b80[0],fsr4_atpgrq_b81[2],fsr4_atpgmq_b81,fsr4_atpgrq_b81[0]} ),
1056 .atpgtq ( fsr4_atpgtq_b81[3:0] ),
1057 .vdda ( VDDA ),
1058 .vddd ( VDDD ),
1059 .vddr ( VDDR ),
1060 .vddt ( VDDT ),
1061 .vssa ( VSSA )
1062 );
1063
1064// first serdes macro: rx ports 0-3, tx ports 0-3
1065
1066wiz6c2b8n6d2t fsr5_b8_0 (
1067 .bsinitclk ( fsr5_bsinitclk[0]),
1068 .cfgpll ({2'b0, mcu2_fsr5_cfgpll0[6:5], 3'b0, mcu2_fsr5_cfgpll0[4:0]}),
1069 .cfgrx0 ({2'b0, mcu2_fsr5_cfgrx0[19:18], 1'b0, mcu2_fsr5_cfgrx0[17:9], 1'b0, mcu2_fsr5_cfgrx0[8],
1070 1'b0, mcu2_fsr5_cfgrx0[7:2], 3'b0, mcu2_fsr5_cfgrx0[1:0]}),
1071 .cfgrx1 ({2'b0, mcu2_fsr5_cfgrx1[19:18], 1'b0, mcu2_fsr5_cfgrx1[17:9], 1'b0, mcu2_fsr5_cfgrx1[8],
1072 1'b0, mcu2_fsr5_cfgrx1[7:2], 3'b0, mcu2_fsr5_cfgrx1[1:0]}),
1073 .cfgrx2 ({2'b0, mcu2_fsr5_cfgrx2[19:18], 1'b0, mcu2_fsr5_cfgrx2[17:9], 1'b0, mcu2_fsr5_cfgrx2[8],
1074 1'b0, mcu2_fsr5_cfgrx2[7:2], 3'b0, mcu2_fsr5_cfgrx2[1:0]}),
1075 .cfgrx3 ({2'b0, mcu2_fsr5_cfgrx3[19:18], 1'b0, mcu2_fsr5_cfgrx3[17:9], 1'b0, mcu2_fsr5_cfgrx3[8],
1076 1'b0, mcu2_fsr5_cfgrx3[7:2], 3'b0, mcu2_fsr5_cfgrx3[1:0]}),
1077 .cfgtx0 ({1'b0, mcu2_fsr5_cfgtx0[15:2], 3'b0, mcu2_fsr5_cfgtx0[1:0]}),
1078 .cfgtx1 ({1'b0, mcu2_fsr5_cfgtx1[15:2], 3'b0, mcu2_fsr5_cfgtx1[1:0]}),
1079 .cfgtx2 ({1'b0, mcu2_fsr5_cfgtx2[15:2], 3'b0, mcu2_fsr5_cfgtx2[1:0]}),
1080 .cfgtx3 ({1'b0, mcu2_fsr5_cfgtx3[15:2], 3'b0, mcu2_fsr5_cfgtx3[1:0]}),
1081 .fclk ( fsr5_fclk[0] ),
1082 .fclrz ( fsr5_fclrz[0] ),
1083 .fdi ( fsr5_fdi[0] ),
1084 .refclkn ( clk622r_r_17x ),
1085 .refclkp ( clk622r_r_17 ),
1086 .rxbclkin ( fsr5_rxbclkin[3:0] ),
1087 .rxn0 ( FBDIMM2B_RX_N[0] ),
1088 .rxn1 ( FBDIMM2B_RX_N[1] ),
1089 .rxn2 ( FBDIMM2B_RX_N[2] ),
1090 .rxn3 ( FBDIMM2B_RX_N[3] ),
1091 .rxp0 ( FBDIMM2B_RX_P[0] ),
1092 .rxp1 ( FBDIMM2B_RX_P[1] ),
1093 .rxp2 ( FBDIMM2B_RX_P[2] ),
1094 .rxp3 ( FBDIMM2B_RX_P[3] ),
1095 .stcicfg ( fsr5_stcicfg[1:0] ),
1096 .stciclk ( fsr5_stciclk[0] ),
1097 .stcid ( fsr5_stcid[0] ),
1098 .td0 ( {mcu2_fsr5_td0[0], mcu2_fsr5_td0[1], mcu2_fsr5_td0[2], mcu2_fsr5_td0[3],
1099 mcu2_fsr5_td0[4], mcu2_fsr5_td0[5], mcu2_fsr5_td0[6], mcu2_fsr5_td0[7],
1100 mcu2_fsr5_td0[8], mcu2_fsr5_td0[9], mcu2_fsr5_td0[10], mcu2_fsr5_td0[11]} ),
1101 .td1 ( {mcu2_fsr5_td1[0], mcu2_fsr5_td1[1], mcu2_fsr5_td1[2], mcu2_fsr5_td1[3],
1102 mcu2_fsr5_td1[4], mcu2_fsr5_td1[5], mcu2_fsr5_td1[6], mcu2_fsr5_td1[7],
1103 mcu2_fsr5_td1[8], mcu2_fsr5_td1[9], mcu2_fsr5_td1[10], mcu2_fsr5_td1[11]} ),
1104 .td2 ( {mcu2_fsr5_td2[0], mcu2_fsr5_td2[1], mcu2_fsr5_td2[2], mcu2_fsr5_td2[3],
1105 mcu2_fsr5_td2[4], mcu2_fsr5_td2[5], mcu2_fsr5_td2[6], mcu2_fsr5_td2[7],
1106 mcu2_fsr5_td2[8], mcu2_fsr5_td2[9], mcu2_fsr5_td2[10], mcu2_fsr5_td2[11]} ),
1107 .td3 ( {mcu2_fsr5_td3[0], mcu2_fsr5_td3[1], mcu2_fsr5_td3[2], mcu2_fsr5_td3[3],
1108 mcu2_fsr5_td3[4], mcu2_fsr5_td3[5], mcu2_fsr5_td3[6], mcu2_fsr5_td3[7],
1109 mcu2_fsr5_td3[8], mcu2_fsr5_td3[9], mcu2_fsr5_td3[10], mcu2_fsr5_td3[11]} ),
1110 .testcfg ( {mcu2_fsr5_testcfg0[17:14], 1'b0, mcu2_fsr5_testcfg0[13:11], 1'b0, mcu2_fsr5_testcfg0[10:0]} ),
1111 .testclkr ( fsr5_testclkr[0] ),
1112 .testclkt ( fsr5_testclkt[0] ),
1113 .txbclkin ( {4{fsr5_txbclkin[0]}} ),
1114 .amux ( FBDIMM2B_AMUX[0] ),
1115 .fdo ( fsr5_fdo[0] ),
1116 .rd0 ( {fsr5_mcu2_rd0[0], fsr5_mcu2_rd0[1], fsr5_mcu2_rd0[2], fsr5_mcu2_rd0[3],
1117 fsr5_mcu2_rd0[4], fsr5_mcu2_rd0[5], fsr5_mcu2_rd0[6], fsr5_mcu2_rd0[7],
1118 fsr5_mcu2_rd0[8], fsr5_mcu2_rd0[9], fsr5_mcu2_rd0[10], fsr5_mcu2_rd0[11]} ),
1119 .rd1 ( {fsr5_mcu2_rd1[0], fsr5_mcu2_rd1[1], fsr5_mcu2_rd1[2], fsr5_mcu2_rd1[3],
1120 fsr5_mcu2_rd1[4], fsr5_mcu2_rd1[5], fsr5_mcu2_rd1[6], fsr5_mcu2_rd1[7],
1121 fsr5_mcu2_rd1[8], fsr5_mcu2_rd1[9], fsr5_mcu2_rd1[10], fsr5_mcu2_rd1[11]} ),
1122 .rd2 ( {fsr5_mcu2_rd2[0], fsr5_mcu2_rd2[1], fsr5_mcu2_rd2[2], fsr5_mcu2_rd2[3],
1123 fsr5_mcu2_rd2[4], fsr5_mcu2_rd2[5], fsr5_mcu2_rd2[6], fsr5_mcu2_rd2[7],
1124 fsr5_mcu2_rd2[8], fsr5_mcu2_rd2[9], fsr5_mcu2_rd2[10], fsr5_mcu2_rd2[11]} ),
1125 .rd3 ( {fsr5_mcu2_rd3[0], fsr5_mcu2_rd3[1], fsr5_mcu2_rd3[2], fsr5_mcu2_rd3[3],
1126 fsr5_mcu2_rd3[4], fsr5_mcu2_rd3[5], fsr5_mcu2_rd3[6], fsr5_mcu2_rd3[7],
1127 fsr5_mcu2_rd3[8], fsr5_mcu2_rd3[9], fsr5_mcu2_rd3[10], fsr5_mcu2_rd3[11]} ),
1128 .rdll0 ( fsr5_rdll0_b80[1:0] ),
1129 .rdll1 ( fsr5_rdll1_b80[1:0] ),
1130 .rdll2 ( fsr5_rdll2_b80[1:0] ),
1131 .rdll3 ( fsr5_rdll3_b80[1:0] ),
1132 .rxbclk ( fsr5_mcu2_rxbclk[3:0] ),
1133 .rxbclklln ( fsr5_rxbclklln_unused[3:0] ),
1134 .rxbclkllp ( fsr5_rxbclkllp_unused[3:0] ),
1135 .stciq ( fsr5_stciq[0] ),
1136 .stspll ( {fsr5_mcu2_stspll_b80[2:0], fsr5_mcu2_stspll_lock[0]} ),
1137 .stsrx0 ( {fsr5_mcu2_stsrx0_unused[2:1], fsr5_mcu2_stsrx_bsrxn[0], fsr5_mcu2_stsrx_bsrxp[0],
1138 fsr5_mcu2_stsrx_losdtct[0], fsr5_mcu2_stsrx0_unused[0], fsr5_mcu2_stsrx_sync[0],
1139 fsr5_mcu2_stsrx_testfail[0]} ),
1140 .stsrx1 ( {fsr5_mcu2_stsrx1_unused[2:1], fsr5_mcu2_stsrx_bsrxn[1], fsr5_mcu2_stsrx_bsrxp[1],
1141 fsr5_mcu2_stsrx_losdtct[1], fsr5_mcu2_stsrx1_unused[0], fsr5_mcu2_stsrx_sync[1],
1142 fsr5_mcu2_stsrx_testfail[1]} ),
1143 .stsrx2 ( {fsr5_mcu2_stsrx2_unused[2:1], fsr5_mcu2_stsrx_bsrxn[2], fsr5_mcu2_stsrx_bsrxp[2],
1144 fsr5_mcu2_stsrx_losdtct[2], fsr5_mcu2_stsrx2_unused[0], fsr5_mcu2_stsrx_sync[2],
1145 fsr5_mcu2_stsrx_testfail[2]} ),
1146 .stsrx3 ( {fsr5_mcu2_stsrx3_unused[2:1], fsr5_mcu2_stsrx_bsrxn[3], fsr5_mcu2_stsrx_bsrxp[3],
1147 fsr5_mcu2_stsrx_losdtct[3], fsr5_mcu2_stsrx3_unused[0], fsr5_mcu2_stsrx_sync[3],
1148 fsr5_mcu2_stsrx_testfail[3]} ),
1149 .ststx0 ( {fsr5_mcu2_ststx0_unused[2:0], fsr5_mcu2_ststx_testfail[0]} ),
1150 .ststx1 ( {fsr5_mcu2_ststx1_unused[2:0], fsr5_mcu2_ststx_testfail[1]} ),
1151 .ststx2 ( {fsr5_mcu2_ststx2_unused[2:0], fsr5_mcu2_ststx_testfail[2]} ),
1152 .ststx3 ( {fsr5_mcu2_ststx3_unused[2:0], fsr5_mcu2_ststx_testfail[3]} ),
1153 .txbclk ( fsr5_txbclk_unused[3:0] ),
1154 .txn0 ( FBDIMM2B_TX_N[0] ),
1155 .txn1 ( FBDIMM2B_TX_N[1] ),
1156 .txn2 ( FBDIMM2B_TX_N[2] ),
1157 .txn3 ( FBDIMM2B_TX_N[3] ),
1158 .txp0 ( FBDIMM2B_TX_P[0] ),
1159 .txp1 ( FBDIMM2B_TX_P[1] ),
1160 .txp2 ( FBDIMM2B_TX_P[2] ),
1161 .txp3 ( FBDIMM2B_TX_P[3] ),
1162 .atpgmd ( fsr5_atpgtq_b80[2] ),
1163 .atpgmq ( fsr5_atpgmq_b80 ),
1164 .atpgrd ( {fsr5_atpgtq_b80[3],fsr5_atpgrq_b80[3],fsr5_atpgtq_b80[1],fsr5_atpgrq_b80[1]} ),
1165 .atpgrq ( fsr5_atpgrq_b80[3:0] ),
1166 .atpgtd ( {fsr5_atpgtq_a8[0],fsr5_atpgrq_b80[2],fsr5_atpgmq_b80,fsr5_atpgrq_b80[0]} ),
1167 .atpgtq ( fsr5_atpgtq_b80[3:0] ),
1168 .vdda ( VDDA ),
1169 .vddd ( VDDD ),
1170 .vddr ( VDDR ),
1171 .vddt ( VDDT ),
1172 .vssa ( VSSA )
1173 );
1174
1175
1176// second serdes macro: RX ports 4-9, TX ports 4-5
1177
1178wiz6c2a8n6d2t fsr5_a8 (
1179 .bsinitclk ( fsr5_bsinitclk[1] ),
1180 .cfgpll ({2'b0, mcu2_fsr5_cfgpll1[6:5], 3'b0, mcu2_fsr5_cfgpll1[4:0]}),
1181 .cfgrx0 ({2'b0, mcu2_fsr5_cfgrx4[19:18], 1'b0, mcu2_fsr5_cfgrx4[17:9], 1'b0, mcu2_fsr5_cfgrx4[8],
1182 1'b0, mcu2_fsr5_cfgrx4[7:2], 3'b0, mcu2_fsr5_cfgrx4[1:0]}),
1183 .cfgrx1 ({2'b0, mcu2_fsr5_cfgrx5[19:18], 1'b0, mcu2_fsr5_cfgrx5[17:9], 1'b0, mcu2_fsr5_cfgrx5[8],
1184 1'b0, mcu2_fsr5_cfgrx5[7:2], 3'b0, mcu2_fsr5_cfgrx5[1:0]}),
1185 .cfgrx2 ({2'b0, mcu2_fsr5_cfgrx6[19:18], 1'b0, mcu2_fsr5_cfgrx6[17:9], 1'b0, mcu2_fsr5_cfgrx6[8],
1186 1'b0, mcu2_fsr5_cfgrx6[7:2], 3'b0, mcu2_fsr5_cfgrx6[1:0]}),
1187 .cfgrx3 ({2'b0, mcu2_fsr5_cfgrx7[19:18], 1'b0, mcu2_fsr5_cfgrx7[17:9], 1'b0, mcu2_fsr5_cfgrx7[8],
1188 1'b0, mcu2_fsr5_cfgrx7[7:2], 3'b0, mcu2_fsr5_cfgrx7[1:0]}),
1189 .cfgrx4 ({2'b0, mcu2_fsr5_cfgrx8[19:18], 1'b0, mcu2_fsr5_cfgrx8[17:9], 1'b0, mcu2_fsr5_cfgrx8[8],
1190 1'b0, mcu2_fsr5_cfgrx8[7:2], 3'b0, mcu2_fsr5_cfgrx8[1:0]}),
1191 .cfgrx5 ({2'b0, mcu2_fsr5_cfgrx9[19:18], 1'b0, mcu2_fsr5_cfgrx9[17:9], 1'b0, mcu2_fsr5_cfgrx9[8],
1192 1'b0, mcu2_fsr5_cfgrx9[7:2], 3'b0, mcu2_fsr5_cfgrx9[1:0]}),
1193 .cfgtx0 ({1'b0, mcu2_fsr5_cfgtx4[15:2], 3'b0, mcu2_fsr5_cfgtx4[1:0]}),
1194 .cfgtx1 ({1'b0, mcu2_fsr5_cfgtx5[15:2], 3'b0, mcu2_fsr5_cfgtx5[1:0]}),
1195 .fclk ( fsr5_fclk[1] ),
1196 .fclrz ( fsr5_fclrz[1] ),
1197 .fdi ( fsr5_fdi[1] ),
1198 .refclkn ( clk622r_r_18x ),
1199 .refclkp ( clk622r_r_18 ),
1200 .rxbclkin ( fsr5_rxbclkin[9:4] ),
1201 .rxn0 ( FBDIMM2B_RX_N[4] ),
1202 .rxn1 ( FBDIMM2B_RX_N[5] ),
1203 .rxn2 ( FBDIMM2B_RX_N[6] ),
1204 .rxn3 ( FBDIMM2B_RX_N[7] ),
1205 .rxn4 ( FBDIMM2B_RX_N[8] ),
1206 .rxn5 ( FBDIMM2B_RX_N[9] ),
1207 .rxp0 ( FBDIMM2B_RX_P[4] ),
1208 .rxp1 ( FBDIMM2B_RX_P[5] ),
1209 .rxp2 ( FBDIMM2B_RX_P[6] ),
1210 .rxp3 ( FBDIMM2B_RX_P[7] ),
1211 .rxp4 ( FBDIMM2B_RX_P[8] ),
1212 .rxp5 ( FBDIMM2B_RX_P[9] ),
1213 .stcicfg ( fsr5_stcicfg[3:2] ),
1214 .stciclk ( fsr5_stciclk[1] ),
1215 .stcid ( fsr5_stcid[1] ),
1216 .td0 ( {mcu2_fsr5_td4[0], mcu2_fsr5_td4[1], mcu2_fsr5_td4[2], mcu2_fsr5_td4[3],
1217 mcu2_fsr5_td4[4], mcu2_fsr5_td4[5], mcu2_fsr5_td4[6], mcu2_fsr5_td4[7],
1218 mcu2_fsr5_td4[8], mcu2_fsr5_td4[9], mcu2_fsr5_td4[10], mcu2_fsr5_td4[11]} ),
1219 .td1 ( {mcu2_fsr5_td5[0], mcu2_fsr5_td5[1], mcu2_fsr5_td5[2], mcu2_fsr5_td5[3],
1220 mcu2_fsr5_td5[4], mcu2_fsr5_td5[5], mcu2_fsr5_td5[6], mcu2_fsr5_td5[7],
1221 mcu2_fsr5_td5[8], mcu2_fsr5_td5[9], mcu2_fsr5_td5[10], mcu2_fsr5_td5[11]} ),
1222 .testcfg ( {mcu2_fsr5_testcfg1[17:14], 1'b0, mcu2_fsr5_testcfg1[13:11], 1'b0, mcu2_fsr5_testcfg1[10:0]} ),
1223 .testclkr ( fsr5_testclkr[1] ),
1224 .testclkt ( fsr5_testclkt[1] ),
1225 .txbclkin ( {2{fsr5_txbclkin[1]}} ),
1226 .amux ( FBDIMM2B_AMUX[1] ),
1227 .fdo ( fsr5_fdo[1] ),
1228 .rd0 ( {fsr5_mcu2_rd4[0], fsr5_mcu2_rd4[1], fsr5_mcu2_rd4[2], fsr5_mcu2_rd4[3],
1229 fsr5_mcu2_rd4[4], fsr5_mcu2_rd4[5], fsr5_mcu2_rd4[6], fsr5_mcu2_rd4[7],
1230 fsr5_mcu2_rd4[8], fsr5_mcu2_rd4[9], fsr5_mcu2_rd4[10], fsr5_mcu2_rd4[11]} ),
1231 .rd1 ( {fsr5_mcu2_rd5[0], fsr5_mcu2_rd5[1], fsr5_mcu2_rd5[2], fsr5_mcu2_rd5[3],
1232 fsr5_mcu2_rd5[4], fsr5_mcu2_rd5[5], fsr5_mcu2_rd5[6], fsr5_mcu2_rd5[7],
1233 fsr5_mcu2_rd5[8], fsr5_mcu2_rd5[9], fsr5_mcu2_rd5[10], fsr5_mcu2_rd5[11]} ),
1234 .rd2 ( {fsr5_mcu2_rd6[0], fsr5_mcu2_rd6[1], fsr5_mcu2_rd6[2], fsr5_mcu2_rd6[3],
1235 fsr5_mcu2_rd6[4], fsr5_mcu2_rd6[5], fsr5_mcu2_rd6[6], fsr5_mcu2_rd6[7],
1236 fsr5_mcu2_rd6[8], fsr5_mcu2_rd6[9], fsr5_mcu2_rd6[10], fsr5_mcu2_rd6[11]} ),
1237 .rd3 ( {fsr5_mcu2_rd7[0], fsr5_mcu2_rd7[1], fsr5_mcu2_rd7[2], fsr5_mcu2_rd7[3],
1238 fsr5_mcu2_rd7[4], fsr5_mcu2_rd7[5], fsr5_mcu2_rd7[6], fsr5_mcu2_rd7[7],
1239 fsr5_mcu2_rd7[8], fsr5_mcu2_rd7[9], fsr5_mcu2_rd7[10], fsr5_mcu2_rd7[11]} ),
1240 .rd4 ( {fsr5_mcu2_rd8[0], fsr5_mcu2_rd8[1], fsr5_mcu2_rd8[2], fsr5_mcu2_rd8[3],
1241 fsr5_mcu2_rd8[4], fsr5_mcu2_rd8[5], fsr5_mcu2_rd8[6], fsr5_mcu2_rd8[7],
1242 fsr5_mcu2_rd8[8], fsr5_mcu2_rd8[9], fsr5_mcu2_rd8[10], fsr5_mcu2_rd8[11]} ),
1243 .rd5 ( {fsr5_mcu2_rd9[0], fsr5_mcu2_rd9[1], fsr5_mcu2_rd9[2], fsr5_mcu2_rd9[3],
1244 fsr5_mcu2_rd9[4], fsr5_mcu2_rd9[5], fsr5_mcu2_rd9[6], fsr5_mcu2_rd9[7],
1245 fsr5_mcu2_rd9[8], fsr5_mcu2_rd9[9], fsr5_mcu2_rd9[10], fsr5_mcu2_rd9[11]} ),
1246 .rdll0 ( fsr5_rdll0_b62[1:0] ),
1247 .rdll1 ( fsr5_rdll1_b62[1:0] ),
1248 .rdll2 ( fsr5_rdll2_b62[1:0] ),
1249 .rdll3 ( fsr5_rdll3_b62[1:0] ),
1250 .rxbclk ( fsr5_mcu2_rxbclk[9:4] ),
1251 .rxbclklln ( fsr5_rxbclklln_unused[9:4] ),
1252 .rxbclkllp ( fsr5_rxbclkllp_unused[9:4] ),
1253 .stciq ( fsr5_stciq[1] ),
1254 .stspll ( {fsr5_mcu2_stspll_b62[2:0], fsr5_mcu2_stspll_lock[1]} ),
1255 .stsrx0 ( {fsr5_mcu2_stsrx4_unused[2:1], fsr5_mcu2_stsrx_bsrxn[4], fsr5_mcu2_stsrx_bsrxp[4],
1256 fsr5_mcu2_stsrx_losdtct[4], fsr5_mcu2_stsrx4_unused[0], fsr5_mcu2_stsrx_sync[4],
1257 fsr5_mcu2_stsrx_testfail[4]} ),
1258 .stsrx1 ( {fsr5_mcu2_stsrx5_unused[2:1], fsr5_mcu2_stsrx_bsrxn[5], fsr5_mcu2_stsrx_bsrxp[5],
1259 fsr5_mcu2_stsrx_losdtct[5], fsr5_mcu2_stsrx5_unused[0], fsr5_mcu2_stsrx_sync[5],
1260 fsr5_mcu2_stsrx_testfail[5]} ),
1261 .stsrx2 ( {fsr5_mcu2_stsrx6_unused[2:1], fsr5_mcu2_stsrx_bsrxn[6], fsr5_mcu2_stsrx_bsrxp[6],
1262 fsr5_mcu2_stsrx_losdtct[6], fsr5_mcu2_stsrx6_unused[0], fsr5_mcu2_stsrx_sync[6],
1263 fsr5_mcu2_stsrx_testfail[6]} ),
1264 .stsrx3 ( {fsr5_mcu2_stsrx7_unused[2:1], fsr5_mcu2_stsrx_bsrxn[7], fsr5_mcu2_stsrx_bsrxp[7],
1265 fsr5_mcu2_stsrx_losdtct[7], fsr5_mcu2_stsrx7_unused[0], fsr5_mcu2_stsrx_sync[7],
1266 fsr5_mcu2_stsrx_testfail[7]} ),
1267 .stsrx4 ( {fsr5_mcu2_stsrx8_unused[2:1], fsr5_mcu2_stsrx_bsrxn[8], fsr5_mcu2_stsrx_bsrxp[8],
1268 fsr5_mcu2_stsrx_losdtct[8], fsr5_mcu2_stsrx8_unused[0], fsr5_mcu2_stsrx_sync[8],
1269 fsr5_mcu2_stsrx_testfail[8]} ),
1270 .stsrx5 ( {fsr5_mcu2_stsrx9_unused[2:1], fsr5_mcu2_stsrx_bsrxn[9], fsr5_mcu2_stsrx_bsrxp[9],
1271 fsr5_mcu2_stsrx_losdtct[9], fsr5_mcu2_stsrx9_unused[0], fsr5_mcu2_stsrx_sync[9],
1272 fsr5_mcu2_stsrx_testfail[9]} ),
1273 .ststx0 ( {fsr5_mcu2_ststx4_unused[2:0], fsr5_mcu2_ststx_testfail[4]} ),
1274 .ststx1 ( {fsr5_mcu2_ststx5_unused[2:0], fsr5_mcu2_ststx_testfail[5]} ),
1275 .txbclk ( fsr5_txbclk_unused[5:4] ),
1276 .txn0 ( FBDIMM2B_TX_N[4] ),
1277 .txn1 ( FBDIMM2B_TX_N[5] ),
1278 .txp0 ( FBDIMM2B_TX_P[4] ),
1279 .txp1 ( FBDIMM2B_TX_P[5] ),
1280 .atpgmd ( fsr5_atpgrq_a8[5] ),
1281 .atpgmq ( fsr5_atpgmq_a8 ),
1282 .atpgrd ( {fsr5_atpgrq_a8[2],fsr5_atpgmq_a8,fsr5_atpgtq_a8[1],fsr5_atpgrq_a8[3],fsr5_atpgrq_a8[4],
1283 fsr5_atpgrq_a8[1]} ),
1284 .atpgrq ( fsr5_atpgrq_a8[5:0] ),
1285 .atpgtd ( {fsr5_atpgtq_b81[0],fsr5_atpgrq_a8[0]} ),
1286 .atpgtq ( fsr5_atpgtq_a8[1:0] ),
1287 .vdda ( VDDA ),
1288 .vddd ( VDDD ),
1289 .vddr ( VDDR ),
1290 .vddt ( VDDT ),
1291 .vssa ( VSSA )
1292 );
1293
1294// third serdes macro: RX ports 10-13, TX ports 6-9
1295
1296wiz6c2b8n6d2t fsr5_b8_1 (
1297 .bsinitclk ( fsr5_bsinitclk[2]),
1298 .cfgpll ({2'b0, mcu2_fsr5_cfgpll2[6:5], 3'b0, mcu2_fsr5_cfgpll2[4:0]}),
1299 .cfgrx0 ({2'b0, mcu2_fsr5_cfgrx10[19:18], 1'b0, mcu2_fsr5_cfgrx10[17:9], 1'b0, mcu2_fsr5_cfgrx10[8],
1300 1'b0, mcu2_fsr5_cfgrx10[7:2], 3'b0, mcu2_fsr5_cfgrx10[1:0]}),
1301 .cfgrx1 ({2'b0, mcu2_fsr5_cfgrx11[19:18], 1'b0, mcu2_fsr5_cfgrx11[17:9], 1'b0, mcu2_fsr5_cfgrx11[8],
1302 1'b0, mcu2_fsr5_cfgrx11[7:2], 3'b0, mcu2_fsr5_cfgrx11[1:0]}),
1303 .cfgrx2 ({2'b0, mcu2_fsr5_cfgrx12[19:18], 1'b0, mcu2_fsr5_cfgrx12[17:9], 1'b0, mcu2_fsr5_cfgrx12[8],
1304 1'b0, mcu2_fsr5_cfgrx12[7:2], 3'b0, mcu2_fsr5_cfgrx12[1:0]}),
1305 .cfgrx3 ({2'b0, mcu2_fsr5_cfgrx13[19:18], 1'b0, mcu2_fsr5_cfgrx13[17:9], 1'b0, mcu2_fsr5_cfgrx13[8],
1306 1'b0, mcu2_fsr5_cfgrx13[7:2], 3'b0, mcu2_fsr5_cfgrx13[1:0]}),
1307 .cfgtx0 ({1'b0, mcu2_fsr5_cfgtx6[15:2], 3'b0, mcu2_fsr5_cfgtx6[1:0]}),
1308 .cfgtx1 ({1'b0, mcu2_fsr5_cfgtx7[15:2], 3'b0, mcu2_fsr5_cfgtx7[1:0]}),
1309 .cfgtx2 ({1'b0, mcu2_fsr5_cfgtx8[15:2], 3'b0, mcu2_fsr5_cfgtx8[1:0]}),
1310 .cfgtx3 ({1'b0, mcu2_fsr5_cfgtx9[15:2], 3'b0, mcu2_fsr5_cfgtx9[1:0]}),
1311 .fclk ( fsr5_fclk[2] ),
1312 .fclrz ( fsr5_fclrz[2] ),
1313 .fdi ( fsr5_fdi[2] ),
1314 .refclkn ( clk622r_r_19x ),
1315 .refclkp ( clk622r_r_19 ),
1316 .rxbclkin ( fsr5_rxbclkin[13:10] ),
1317 .rxn0 ( FBDIMM2B_RX_N[10] ),
1318 .rxn1 ( FBDIMM2B_RX_N[11] ),
1319 .rxn2 ( FBDIMM2B_RX_N[12] ),
1320 .rxn3 ( FBDIMM2B_RX_N[13] ),
1321 .rxp0 ( FBDIMM2B_RX_P[10] ),
1322 .rxp1 ( FBDIMM2B_RX_P[11] ),
1323 .rxp2 ( FBDIMM2B_RX_P[12] ),
1324 .rxp3 ( FBDIMM2B_RX_P[13] ),
1325 .stcicfg ( fsr5_stcicfg[5:4] ),
1326 .stciclk ( fsr5_stciclk[2] ),
1327 .stcid ( fsr5_stcid[2] ),
1328 .td0 ( {mcu2_fsr5_td6[0], mcu2_fsr5_td6[1], mcu2_fsr5_td6[2], mcu2_fsr5_td6[3],
1329 mcu2_fsr5_td6[4], mcu2_fsr5_td6[5], mcu2_fsr5_td6[6], mcu2_fsr5_td6[7],
1330 mcu2_fsr5_td6[8], mcu2_fsr5_td6[9], mcu2_fsr5_td6[10], mcu2_fsr5_td6[11]} ),
1331 .td1 ( {mcu2_fsr5_td7[0], mcu2_fsr5_td7[1], mcu2_fsr5_td7[2], mcu2_fsr5_td7[3],
1332 mcu2_fsr5_td7[4], mcu2_fsr5_td7[5], mcu2_fsr5_td7[6], mcu2_fsr5_td7[7],
1333 mcu2_fsr5_td7[8], mcu2_fsr5_td7[9], mcu2_fsr5_td7[10], mcu2_fsr5_td7[11]} ),
1334 .td2 ( {mcu2_fsr5_td8[0], mcu2_fsr5_td8[1], mcu2_fsr5_td8[2], mcu2_fsr5_td8[3],
1335 mcu2_fsr5_td8[4], mcu2_fsr5_td8[5], mcu2_fsr5_td8[6], mcu2_fsr5_td8[7],
1336 mcu2_fsr5_td8[8], mcu2_fsr5_td8[9], mcu2_fsr5_td8[10], mcu2_fsr5_td8[11]} ),
1337 .td3 ( {mcu2_fsr5_td9[0], mcu2_fsr5_td9[1], mcu2_fsr5_td9[2], mcu2_fsr5_td9[3],
1338 mcu2_fsr5_td9[4], mcu2_fsr5_td9[5], mcu2_fsr5_td9[6], mcu2_fsr5_td9[7],
1339 mcu2_fsr5_td9[8], mcu2_fsr5_td9[9], mcu2_fsr5_td9[10], mcu2_fsr5_td9[11]} ),
1340 .testcfg ( {mcu2_fsr5_testcfg2[17:14], 1'b0, mcu2_fsr5_testcfg2[13:11], 1'b0, mcu2_fsr5_testcfg2[10:0]} ),
1341 .testclkr ( fsr5_testclkr[2] ),
1342 .testclkt ( fsr5_testclkt[2] ),
1343 .txbclkin ( {4{fsr5_txbclkin[2]}} ),
1344 .amux ( FBDIMM2B_AMUX[2] ),
1345 .fdo ( fsr5_fdo[2] ),
1346 .rd0 ( {fsr5_mcu2_rd10[0], fsr5_mcu2_rd10[1], fsr5_mcu2_rd10[2], fsr5_mcu2_rd10[3],
1347 fsr5_mcu2_rd10[4], fsr5_mcu2_rd10[5], fsr5_mcu2_rd10[6], fsr5_mcu2_rd10[7],
1348 fsr5_mcu2_rd10[8], fsr5_mcu2_rd10[9], fsr5_mcu2_rd10[10], fsr5_mcu2_rd10[11]} ),
1349 .rd1 ( {fsr5_mcu2_rd11[0], fsr5_mcu2_rd11[1], fsr5_mcu2_rd11[2], fsr5_mcu2_rd11[3],
1350 fsr5_mcu2_rd11[4], fsr5_mcu2_rd11[5], fsr5_mcu2_rd11[6], fsr5_mcu2_rd11[7],
1351 fsr5_mcu2_rd11[8], fsr5_mcu2_rd11[9], fsr5_mcu2_rd11[10], fsr5_mcu2_rd11[11]} ),
1352 .rd2 ( {fsr5_mcu2_rd12[0], fsr5_mcu2_rd12[1], fsr5_mcu2_rd12[2], fsr5_mcu2_rd12[3],
1353 fsr5_mcu2_rd12[4], fsr5_mcu2_rd12[5], fsr5_mcu2_rd12[6], fsr5_mcu2_rd12[7],
1354 fsr5_mcu2_rd12[8], fsr5_mcu2_rd12[9], fsr5_mcu2_rd12[10], fsr5_mcu2_rd12[11]} ),
1355 .rd3 ( {fsr5_mcu2_rd13[0], fsr5_mcu2_rd13[1], fsr5_mcu2_rd13[2], fsr5_mcu2_rd13[3],
1356 fsr5_mcu2_rd13[4], fsr5_mcu2_rd13[5], fsr5_mcu2_rd13[6], fsr5_mcu2_rd13[7],
1357 fsr5_mcu2_rd13[8], fsr5_mcu2_rd13[9], fsr5_mcu2_rd13[10], fsr5_mcu2_rd13[11]} ),
1358 .rdll0 ( fsr5_rdll0_b81[1:0] ),
1359 .rdll1 ( fsr5_rdll1_b81[1:0] ),
1360 .rdll2 ( fsr5_rdll2_b81[1:0] ),
1361 .rdll3 ( fsr5_rdll3_b81[1:0] ),
1362 .rxbclk ( fsr5_mcu2_rxbclk[13:10] ),
1363 .rxbclklln ( fsr5_rxbclklln_unused[13:10] ),
1364 .rxbclkllp ( fsr5_rxbclkllp_unused[13:10] ),
1365 .stciq ( fsr5_stciq[2] ),
1366 .stspll ( {fsr5_mcu2_stspll_b81[2:0], fsr5_mcu2_stspll_lock[2]} ),
1367 .stsrx0 ( {fsr5_mcu2_stsrx10_unused[2:1], fsr5_mcu2_stsrx_bsrxn[10], fsr5_mcu2_stsrx_bsrxp[10],
1368 fsr5_mcu2_stsrx_losdtct[10], fsr5_mcu2_stsrx10_unused[0], fsr5_mcu2_stsrx_sync[10],
1369 fsr5_mcu2_stsrx_testfail[10]} ),
1370 .stsrx1 ( {fsr5_mcu2_stsrx11_unused[2:1], fsr5_mcu2_stsrx_bsrxn[11], fsr5_mcu2_stsrx_bsrxp[11],
1371 fsr5_mcu2_stsrx_losdtct[11], fsr5_mcu2_stsrx11_unused[0], fsr5_mcu2_stsrx_sync[11],
1372 fsr5_mcu2_stsrx_testfail[11]} ),
1373 .stsrx2 ( {fsr5_mcu2_stsrx12_unused[2:1], fsr5_mcu2_stsrx_bsrxn[12], fsr5_mcu2_stsrx_bsrxp[12],
1374 fsr5_mcu2_stsrx_losdtct[12], fsr5_mcu2_stsrx12_unused[0], fsr5_mcu2_stsrx_sync[12],
1375 fsr5_mcu2_stsrx_testfail[12]} ),
1376 .stsrx3 ( {fsr5_mcu2_stsrx13_unused[2:1], fsr5_mcu2_stsrx_bsrxn[13], fsr5_mcu2_stsrx_bsrxp[13],
1377 fsr5_mcu2_stsrx_losdtct[13], fsr5_mcu2_stsrx13_unused[0], fsr5_mcu2_stsrx_sync[13],
1378 fsr5_mcu2_stsrx_testfail[13]} ),
1379 .ststx0 ( {fsr5_mcu2_ststx6_unused[2:0], fsr5_mcu2_ststx_testfail[6]} ),
1380 .ststx1 ( {fsr5_mcu2_ststx7_unused[2:0], fsr5_mcu2_ststx_testfail[7]} ),
1381 .ststx2 ( {fsr5_mcu2_ststx8_unused[2:0], fsr5_mcu2_ststx_testfail[8]} ),
1382 .ststx3 ( {fsr5_mcu2_ststx9_unused[2:0], fsr5_mcu2_ststx_testfail[9]} ),
1383 .txbclk ( fsr5_txbclk_unused[9:6] ),
1384 .txn0 ( FBDIMM2B_TX_N[6] ),
1385 .txn1 ( FBDIMM2B_TX_N[7] ),
1386 .txn2 ( FBDIMM2B_TX_N[8] ),
1387 .txn3 ( FBDIMM2B_TX_N[9] ),
1388 .txp0 ( FBDIMM2B_TX_P[6] ),
1389 .txp1 ( FBDIMM2B_TX_P[7] ),
1390 .txp2 ( FBDIMM2B_TX_P[8] ),
1391 .txp3 ( FBDIMM2B_TX_P[9] ),
1392 .atpgmd ( fsr5_atpgtq_b81[2] ),
1393 .atpgmq ( fsr5_atpgmq_b81 ),
1394 .atpgrd ( {fsr5_atpgtq_b81[3],fsr5_atpgrq_b81[3],fsr5_atpgtq_b81[1],fsr5_atpgrq_b81[1]} ),
1395 .atpgrq ( fsr5_atpgrq_b81[3:0] ),
1396 .atpgtd ( {fsr6_atpgtq_b80[0],fsr5_atpgrq_b81[2],fsr5_atpgmq_b81,fsr5_atpgrq_b81[0]} ),
1397 .atpgtq ( fsr5_atpgtq_b81[3:0] ),
1398 .vdda ( VDDA ),
1399 .vddd ( VDDD ),
1400 .vddr ( VDDR ),
1401 .vddt ( VDDT ),
1402 .vssa ( VSSA )
1403 );
1404
1405// first serdes macro: rx ports 0-3, tx ports 0-3
1406
1407wiz6c2b8n6d2t fsr6_b8_0 (
1408 .bsinitclk ( fsr6_bsinitclk[0]),
1409 .cfgpll ({2'b0, mcu3_fsr6_cfgpll0[6:5], 3'b0, mcu3_fsr6_cfgpll0[4:0]}),
1410 .cfgrx0 ({2'b0, mcu3_fsr6_cfgrx0[19:18], 1'b0, mcu3_fsr6_cfgrx0[17:9], 1'b0, mcu3_fsr6_cfgrx0[8],
1411 1'b0, mcu3_fsr6_cfgrx0[7:2], 3'b0, mcu3_fsr6_cfgrx0[1:0]}),
1412 .cfgrx1 ({2'b0, mcu3_fsr6_cfgrx1[19:18], 1'b0, mcu3_fsr6_cfgrx1[17:9], 1'b0, mcu3_fsr6_cfgrx1[8],
1413 1'b0, mcu3_fsr6_cfgrx1[7:2], 3'b0, mcu3_fsr6_cfgrx1[1:0]}),
1414 .cfgrx2 ({2'b0, mcu3_fsr6_cfgrx2[19:18], 1'b0, mcu3_fsr6_cfgrx2[17:9], 1'b0, mcu3_fsr6_cfgrx2[8],
1415 1'b0, mcu3_fsr6_cfgrx2[7:2], 3'b0, mcu3_fsr6_cfgrx2[1:0]}),
1416 .cfgrx3 ({2'b0, mcu3_fsr6_cfgrx3[19:18], 1'b0, mcu3_fsr6_cfgrx3[17:9], 1'b0, mcu3_fsr6_cfgrx3[8],
1417 1'b0, mcu3_fsr6_cfgrx3[7:2], 3'b0, mcu3_fsr6_cfgrx3[1:0]}),
1418 .cfgtx0 ({1'b0, mcu3_fsr6_cfgtx0[15:2], 3'b0, mcu3_fsr6_cfgtx0[1:0]}),
1419 .cfgtx1 ({1'b0, mcu3_fsr6_cfgtx1[15:2], 3'b0, mcu3_fsr6_cfgtx1[1:0]}),
1420 .cfgtx2 ({1'b0, mcu3_fsr6_cfgtx2[15:2], 3'b0, mcu3_fsr6_cfgtx2[1:0]}),
1421 .cfgtx3 ({1'b0, mcu3_fsr6_cfgtx3[15:2], 3'b0, mcu3_fsr6_cfgtx3[1:0]}),
1422 .fclk ( fsr6_fclk[0] ),
1423 .fclrz ( fsr6_fclrz[0] ),
1424 .fdi ( fsr6_fdi[0] ),
1425 .refclkn ( clk622r_r_21x ),
1426 .refclkp ( clk622r_r_21 ),
1427 .rxbclkin ( fsr6_rxbclkin[3:0] ),
1428 .rxn0 ( FBDIMM3A_RX_N[0] ),
1429 .rxn1 ( FBDIMM3A_RX_N[1] ),
1430 .rxn2 ( FBDIMM3A_RX_N[2] ),
1431 .rxn3 ( FBDIMM3A_RX_N[3] ),
1432 .rxp0 ( FBDIMM3A_RX_P[0] ),
1433 .rxp1 ( FBDIMM3A_RX_P[1] ),
1434 .rxp2 ( FBDIMM3A_RX_P[2] ),
1435 .rxp3 ( FBDIMM3A_RX_P[3] ),
1436 .stcicfg ( fsr6_stcicfg[1:0] ),
1437 .stciclk ( fsr6_stciclk[0] ),
1438 .stcid ( fsr6_stcid[0] ),
1439 .td0 ( {mcu3_fsr6_td0[0], mcu3_fsr6_td0[1], mcu3_fsr6_td0[2], mcu3_fsr6_td0[3],
1440 mcu3_fsr6_td0[4], mcu3_fsr6_td0[5], mcu3_fsr6_td0[6], mcu3_fsr6_td0[7],
1441 mcu3_fsr6_td0[8], mcu3_fsr6_td0[9], mcu3_fsr6_td0[10], mcu3_fsr6_td0[11]} ),
1442 .td1 ( {mcu3_fsr6_td1[0], mcu3_fsr6_td1[1], mcu3_fsr6_td1[2], mcu3_fsr6_td1[3],
1443 mcu3_fsr6_td1[4], mcu3_fsr6_td1[5], mcu3_fsr6_td1[6], mcu3_fsr6_td1[7],
1444 mcu3_fsr6_td1[8], mcu3_fsr6_td1[9], mcu3_fsr6_td1[10], mcu3_fsr6_td1[11]} ),
1445 .td2 ( {mcu3_fsr6_td2[0], mcu3_fsr6_td2[1], mcu3_fsr6_td2[2], mcu3_fsr6_td2[3],
1446 mcu3_fsr6_td2[4], mcu3_fsr6_td2[5], mcu3_fsr6_td2[6], mcu3_fsr6_td2[7],
1447 mcu3_fsr6_td2[8], mcu3_fsr6_td2[9], mcu3_fsr6_td2[10], mcu3_fsr6_td2[11]} ),
1448 .td3 ( {mcu3_fsr6_td3[0], mcu3_fsr6_td3[1], mcu3_fsr6_td3[2], mcu3_fsr6_td3[3],
1449 mcu3_fsr6_td3[4], mcu3_fsr6_td3[5], mcu3_fsr6_td3[6], mcu3_fsr6_td3[7],
1450 mcu3_fsr6_td3[8], mcu3_fsr6_td3[9], mcu3_fsr6_td3[10], mcu3_fsr6_td3[11]} ),
1451 .testcfg ( {mcu3_fsr6_testcfg0[17:14], 1'b0, mcu3_fsr6_testcfg0[13:11], 1'b0, mcu3_fsr6_testcfg0[10:0]} ),
1452 .testclkr ( fsr6_testclkr[0] ),
1453 .testclkt ( fsr6_testclkt[0] ),
1454 .txbclkin ( {4{fsr6_txbclkin[0]}} ),
1455 .amux ( FBDIMM3A_AMUX[0] ),
1456 .fdo ( fsr6_fdo[0] ),
1457 .rd0 ( {fsr6_mcu3_rd0[0], fsr6_mcu3_rd0[1], fsr6_mcu3_rd0[2], fsr6_mcu3_rd0[3],
1458 fsr6_mcu3_rd0[4], fsr6_mcu3_rd0[5], fsr6_mcu3_rd0[6], fsr6_mcu3_rd0[7],
1459 fsr6_mcu3_rd0[8], fsr6_mcu3_rd0[9], fsr6_mcu3_rd0[10], fsr6_mcu3_rd0[11]} ),
1460 .rd1 ( {fsr6_mcu3_rd1[0], fsr6_mcu3_rd1[1], fsr6_mcu3_rd1[2], fsr6_mcu3_rd1[3],
1461 fsr6_mcu3_rd1[4], fsr6_mcu3_rd1[5], fsr6_mcu3_rd1[6], fsr6_mcu3_rd1[7],
1462 fsr6_mcu3_rd1[8], fsr6_mcu3_rd1[9], fsr6_mcu3_rd1[10], fsr6_mcu3_rd1[11]} ),
1463 .rd2 ( {fsr6_mcu3_rd2[0], fsr6_mcu3_rd2[1], fsr6_mcu3_rd2[2], fsr6_mcu3_rd2[3],
1464 fsr6_mcu3_rd2[4], fsr6_mcu3_rd2[5], fsr6_mcu3_rd2[6], fsr6_mcu3_rd2[7],
1465 fsr6_mcu3_rd2[8], fsr6_mcu3_rd2[9], fsr6_mcu3_rd2[10], fsr6_mcu3_rd2[11]} ),
1466 .rd3 ( {fsr6_mcu3_rd3[0], fsr6_mcu3_rd3[1], fsr6_mcu3_rd3[2], fsr6_mcu3_rd3[3],
1467 fsr6_mcu3_rd3[4], fsr6_mcu3_rd3[5], fsr6_mcu3_rd3[6], fsr6_mcu3_rd3[7],
1468 fsr6_mcu3_rd3[8], fsr6_mcu3_rd3[9], fsr6_mcu3_rd3[10], fsr6_mcu3_rd3[11]} ),
1469 .rdll0 ( fsr6_rdll0_b80[1:0] ),
1470 .rdll1 ( fsr6_rdll1_b80[1:0] ),
1471 .rdll2 ( fsr6_rdll2_b80[1:0] ),
1472 .rdll3 ( fsr6_rdll3_b80[1:0] ),
1473 .rxbclk ( fsr6_mcu3_rxbclk[3:0] ),
1474 .rxbclklln ( fsr6_rxbclklln_unused[3:0] ),
1475 .rxbclkllp ( fsr6_rxbclkllp_unused[3:0] ),
1476 .stciq ( fsr6_stciq[0] ),
1477 .stspll ( {fsr6_mcu3_stspll_b80[2:0], fsr6_mcu3_stspll_lock[0]} ),
1478 .stsrx0 ( {fsr6_mcu3_stsrx0_unused[2:1], fsr6_mcu3_stsrx_bsrxn[0], fsr6_mcu3_stsrx_bsrxp[0],
1479 fsr6_mcu3_stsrx_losdtct[0], fsr6_mcu3_stsrx0_unused[0], fsr6_mcu3_stsrx_sync[0],
1480 fsr6_mcu3_stsrx_testfail[0]} ),
1481 .stsrx1 ( {fsr6_mcu3_stsrx1_unused[2:1], fsr6_mcu3_stsrx_bsrxn[1], fsr6_mcu3_stsrx_bsrxp[1],
1482 fsr6_mcu3_stsrx_losdtct[1], fsr6_mcu3_stsrx1_unused[0], fsr6_mcu3_stsrx_sync[1],
1483 fsr6_mcu3_stsrx_testfail[1]} ),
1484 .stsrx2 ( {fsr6_mcu3_stsrx2_unused[2:1], fsr6_mcu3_stsrx_bsrxn[2], fsr6_mcu3_stsrx_bsrxp[2],
1485 fsr6_mcu3_stsrx_losdtct[2], fsr6_mcu3_stsrx2_unused[0], fsr6_mcu3_stsrx_sync[2],
1486 fsr6_mcu3_stsrx_testfail[2]} ),
1487 .stsrx3 ( {fsr6_mcu3_stsrx3_unused[2:1], fsr6_mcu3_stsrx_bsrxn[3], fsr6_mcu3_stsrx_bsrxp[3],
1488 fsr6_mcu3_stsrx_losdtct[3], fsr6_mcu3_stsrx3_unused[0], fsr6_mcu3_stsrx_sync[3],
1489 fsr6_mcu3_stsrx_testfail[3]} ),
1490 .ststx0 ( {fsr6_mcu3_ststx0_unused[2:0], fsr6_mcu3_ststx_testfail[0]} ),
1491 .ststx1 ( {fsr6_mcu3_ststx1_unused[2:0], fsr6_mcu3_ststx_testfail[1]} ),
1492 .ststx2 ( {fsr6_mcu3_ststx2_unused[2:0], fsr6_mcu3_ststx_testfail[2]} ),
1493 .ststx3 ( {fsr6_mcu3_ststx3_unused[2:0], fsr6_mcu3_ststx_testfail[3]} ),
1494 .txbclk ( fsr6_txbclk_unused[3:0] ),
1495 .txn0 ( FBDIMM3A_TX_N[0] ),
1496 .txn1 ( FBDIMM3A_TX_N[1] ),
1497 .txn2 ( FBDIMM3A_TX_N[2] ),
1498 .txn3 ( FBDIMM3A_TX_N[3] ),
1499 .txp0 ( FBDIMM3A_TX_P[0] ),
1500 .txp1 ( FBDIMM3A_TX_P[1] ),
1501 .txp2 ( FBDIMM3A_TX_P[2] ),
1502 .txp3 ( FBDIMM3A_TX_P[3] ),
1503 .atpgmd ( fsr6_atpgtq_b80[2] ),
1504 .atpgmq ( fsr6_atpgmq_b80 ),
1505 .atpgrd ( {fsr6_atpgtq_b80[3],fsr6_atpgrq_b80[3],fsr6_atpgtq_b80[1],fsr6_atpgrq_b80[1]} ),
1506 .atpgrq ( fsr6_atpgrq_b80[3:0] ),
1507 .atpgtd ( {fsr6_atpgtq_a8[0],fsr6_atpgrq_b80[2],fsr6_atpgmq_b80,fsr6_atpgrq_b80[0]} ),
1508 .atpgtq ( fsr6_atpgtq_b80[3:0] ),
1509 .vdda ( VDDA ),
1510 .vddd ( VDDD ),
1511 .vddr ( VDDR ),
1512 .vddt ( VDDT ),
1513 .vssa ( VSSA )
1514 );
1515
1516
1517// second serdes macro: RX ports 4-9, TX ports 4-5
1518
1519wiz6c2a8n6d2t fsr6_a8 (
1520 .bsinitclk ( fsr6_bsinitclk[1]),
1521 .cfgpll ({2'b0, mcu3_fsr6_cfgpll1[6:5], 3'b0, mcu3_fsr6_cfgpll1[4:0]}),
1522 .cfgrx0 ({2'b0, mcu3_fsr6_cfgrx4[19:18], 1'b0, mcu3_fsr6_cfgrx4[17:9], 1'b0, mcu3_fsr6_cfgrx4[8],
1523 1'b0, mcu3_fsr6_cfgrx4[7:2], 3'b0, mcu3_fsr6_cfgrx4[1:0]}),
1524 .cfgrx1 ({2'b0, mcu3_fsr6_cfgrx5[19:18], 1'b0, mcu3_fsr6_cfgrx5[17:9], 1'b0, mcu3_fsr6_cfgrx5[8],
1525 1'b0, mcu3_fsr6_cfgrx5[7:2], 3'b0, mcu3_fsr6_cfgrx5[1:0]}),
1526 .cfgrx2 ({2'b0, mcu3_fsr6_cfgrx6[19:18], 1'b0, mcu3_fsr6_cfgrx6[17:9], 1'b0, mcu3_fsr6_cfgrx6[8],
1527 1'b0, mcu3_fsr6_cfgrx6[7:2], 3'b0, mcu3_fsr6_cfgrx6[1:0]}),
1528 .cfgrx3 ({2'b0, mcu3_fsr6_cfgrx7[19:18], 1'b0, mcu3_fsr6_cfgrx7[17:9], 1'b0, mcu3_fsr6_cfgrx7[8],
1529 1'b0, mcu3_fsr6_cfgrx7[7:2], 3'b0, mcu3_fsr6_cfgrx7[1:0]}),
1530 .cfgrx4 ({2'b0, mcu3_fsr6_cfgrx8[19:18], 1'b0, mcu3_fsr6_cfgrx8[17:9], 1'b0, mcu3_fsr6_cfgrx8[8],
1531 1'b0, mcu3_fsr6_cfgrx8[7:2], 3'b0, mcu3_fsr6_cfgrx8[1:0]}),
1532 .cfgrx5 ({2'b0, mcu3_fsr6_cfgrx9[19:18], 1'b0, mcu3_fsr6_cfgrx9[17:9], 1'b0, mcu3_fsr6_cfgrx9[8],
1533 1'b0, mcu3_fsr6_cfgrx9[7:2], 3'b0, mcu3_fsr6_cfgrx9[1:0]}),
1534 .cfgtx0 ({1'b0, mcu3_fsr6_cfgtx4[15:2], 3'b0, mcu3_fsr6_cfgtx4[1:0]}),
1535 .cfgtx1 ({1'b0, mcu3_fsr6_cfgtx5[15:2], 3'b0, mcu3_fsr6_cfgtx5[1:0]}),
1536 .fclk ( fsr6_fclk[1] ),
1537 .fclrz ( fsr6_fclrz[1] ),
1538 .fdi ( fsr6_fdi[1] ),
1539 .refclkn ( clk622r_r_22x ),
1540 .refclkp ( clk622r_r_22 ),
1541 .rxbclkin ( fsr6_rxbclkin[9:4] ),
1542 .rxn0 ( FBDIMM3A_RX_N[4] ),
1543 .rxn1 ( FBDIMM3A_RX_N[5] ),
1544 .rxn2 ( FBDIMM3A_RX_N[6] ),
1545 .rxn3 ( FBDIMM3A_RX_N[7] ),
1546 .rxn4 ( FBDIMM3A_RX_N[8] ),
1547 .rxn5 ( FBDIMM3A_RX_N[9] ),
1548 .rxp0 ( FBDIMM3A_RX_P[4] ),
1549 .rxp1 ( FBDIMM3A_RX_P[5] ),
1550 .rxp2 ( FBDIMM3A_RX_P[6] ),
1551 .rxp3 ( FBDIMM3A_RX_P[7] ),
1552 .rxp4 ( FBDIMM3A_RX_P[8] ),
1553 .rxp5 ( FBDIMM3A_RX_P[9] ),
1554 .stcicfg ( fsr6_stcicfg[3:2] ),
1555 .stciclk ( fsr6_stciclk[1] ),
1556 .stcid ( fsr6_stcid[1] ),
1557 .td0 ( {mcu3_fsr6_td4[0], mcu3_fsr6_td4[1], mcu3_fsr6_td4[2], mcu3_fsr6_td4[3],
1558 mcu3_fsr6_td4[4], mcu3_fsr6_td4[5], mcu3_fsr6_td4[6], mcu3_fsr6_td4[7],
1559 mcu3_fsr6_td4[8], mcu3_fsr6_td4[9], mcu3_fsr6_td4[10], mcu3_fsr6_td4[11]} ),
1560 .td1 ( {mcu3_fsr6_td5[0], mcu3_fsr6_td5[1], mcu3_fsr6_td5[2], mcu3_fsr6_td5[3],
1561 mcu3_fsr6_td5[4], mcu3_fsr6_td5[5], mcu3_fsr6_td5[6], mcu3_fsr6_td5[7],
1562 mcu3_fsr6_td5[8], mcu3_fsr6_td5[9], mcu3_fsr6_td5[10], mcu3_fsr6_td5[11]} ),
1563 .testcfg ( {mcu3_fsr6_testcfg1[17:14], 1'b0, mcu3_fsr6_testcfg1[13:11], 1'b0, mcu3_fsr6_testcfg1[10:0]} ),
1564 .testclkr ( fsr6_testclkr[1] ),
1565 .testclkt ( fsr6_testclkt[1] ),
1566 .txbclkin ( {2{fsr6_txbclkin[1]}} ),
1567 .amux ( FBDIMM3A_AMUX[1] ),
1568 .fdo ( fsr6_fdo[1] ),
1569 .rd0 ( {fsr6_mcu3_rd4[0], fsr6_mcu3_rd4[1], fsr6_mcu3_rd4[2], fsr6_mcu3_rd4[3],
1570 fsr6_mcu3_rd4[4], fsr6_mcu3_rd4[5], fsr6_mcu3_rd4[6], fsr6_mcu3_rd4[7],
1571 fsr6_mcu3_rd4[8], fsr6_mcu3_rd4[9], fsr6_mcu3_rd4[10], fsr6_mcu3_rd4[11]} ),
1572 .rd1 ( {fsr6_mcu3_rd5[0], fsr6_mcu3_rd5[1], fsr6_mcu3_rd5[2], fsr6_mcu3_rd5[3],
1573 fsr6_mcu3_rd5[4], fsr6_mcu3_rd5[5], fsr6_mcu3_rd5[6], fsr6_mcu3_rd5[7],
1574 fsr6_mcu3_rd5[8], fsr6_mcu3_rd5[9], fsr6_mcu3_rd5[10], fsr6_mcu3_rd5[11]} ),
1575 .rd2 ( {fsr6_mcu3_rd6[0], fsr6_mcu3_rd6[1], fsr6_mcu3_rd6[2], fsr6_mcu3_rd6[3],
1576 fsr6_mcu3_rd6[4], fsr6_mcu3_rd6[5], fsr6_mcu3_rd6[6], fsr6_mcu3_rd6[7],
1577 fsr6_mcu3_rd6[8], fsr6_mcu3_rd6[9], fsr6_mcu3_rd6[10], fsr6_mcu3_rd6[11]} ),
1578 .rd3 ( {fsr6_mcu3_rd7[0], fsr6_mcu3_rd7[1], fsr6_mcu3_rd7[2], fsr6_mcu3_rd7[3],
1579 fsr6_mcu3_rd7[4], fsr6_mcu3_rd7[5], fsr6_mcu3_rd7[6], fsr6_mcu3_rd7[7],
1580 fsr6_mcu3_rd7[8], fsr6_mcu3_rd7[9], fsr6_mcu3_rd7[10], fsr6_mcu3_rd7[11]} ),
1581 .rd4 ( {fsr6_mcu3_rd8[0], fsr6_mcu3_rd8[1], fsr6_mcu3_rd8[2], fsr6_mcu3_rd8[3],
1582 fsr6_mcu3_rd8[4], fsr6_mcu3_rd8[5], fsr6_mcu3_rd8[6], fsr6_mcu3_rd8[7],
1583 fsr6_mcu3_rd8[8], fsr6_mcu3_rd8[9], fsr6_mcu3_rd8[10], fsr6_mcu3_rd8[11]} ),
1584 .rd5 ( {fsr6_mcu3_rd9[0], fsr6_mcu3_rd9[1], fsr6_mcu3_rd9[2], fsr6_mcu3_rd9[3],
1585 fsr6_mcu3_rd9[4], fsr6_mcu3_rd9[5], fsr6_mcu3_rd9[6], fsr6_mcu3_rd9[7],
1586 fsr6_mcu3_rd9[8], fsr6_mcu3_rd9[9], fsr6_mcu3_rd9[10], fsr6_mcu3_rd9[11]} ),
1587 .rdll0 ( fsr6_rdll0_b62[1:0] ),
1588 .rdll1 ( fsr6_rdll1_b62[1:0] ),
1589 .rdll2 ( fsr6_rdll2_b62[1:0] ),
1590 .rdll3 ( fsr6_rdll3_b62[1:0] ),
1591 .rxbclk ( fsr6_mcu3_rxbclk[9:4] ),
1592 .rxbclklln ( fsr6_rxbclklln_unused[9:4] ),
1593 .rxbclkllp ( fsr6_rxbclkllp_unused[9:4] ),
1594 .stciq ( fsr6_stciq[1] ),
1595 .stspll ( {fsr6_mcu3_stspll_b62[2:0], fsr6_mcu3_stspll_lock[1]} ),
1596 .stsrx0 ( {fsr6_mcu3_stsrx4_unused[2:1], fsr6_mcu3_stsrx_bsrxn[4], fsr6_mcu3_stsrx_bsrxp[4],
1597 fsr6_mcu3_stsrx_losdtct[4], fsr6_mcu3_stsrx4_unused[0], fsr6_mcu3_stsrx_sync[4],
1598 fsr6_mcu3_stsrx_testfail[4]} ),
1599 .stsrx1 ( {fsr6_mcu3_stsrx5_unused[2:1], fsr6_mcu3_stsrx_bsrxn[5], fsr6_mcu3_stsrx_bsrxp[5],
1600 fsr6_mcu3_stsrx_losdtct[5], fsr6_mcu3_stsrx5_unused[0], fsr6_mcu3_stsrx_sync[5],
1601 fsr6_mcu3_stsrx_testfail[5]} ),
1602 .stsrx2 ( {fsr6_mcu3_stsrx6_unused[2:1], fsr6_mcu3_stsrx_bsrxn[6], fsr6_mcu3_stsrx_bsrxp[6],
1603 fsr6_mcu3_stsrx_losdtct[6], fsr6_mcu3_stsrx6_unused[0], fsr6_mcu3_stsrx_sync[6],
1604 fsr6_mcu3_stsrx_testfail[6]} ),
1605 .stsrx3 ( {fsr6_mcu3_stsrx7_unused[2:1], fsr6_mcu3_stsrx_bsrxn[7], fsr6_mcu3_stsrx_bsrxp[7],
1606 fsr6_mcu3_stsrx_losdtct[7], fsr6_mcu3_stsrx7_unused[0], fsr6_mcu3_stsrx_sync[7],
1607 fsr6_mcu3_stsrx_testfail[7]} ),
1608 .stsrx4 ( {fsr6_mcu3_stsrx8_unused[2:1], fsr6_mcu3_stsrx_bsrxn[8], fsr6_mcu3_stsrx_bsrxp[8],
1609 fsr6_mcu3_stsrx_losdtct[8], fsr6_mcu3_stsrx8_unused[0], fsr6_mcu3_stsrx_sync[8],
1610 fsr6_mcu3_stsrx_testfail[8]} ),
1611 .stsrx5 ( {fsr6_mcu3_stsrx9_unused[2:1], fsr6_mcu3_stsrx_bsrxn[9], fsr6_mcu3_stsrx_bsrxp[9],
1612 fsr6_mcu3_stsrx_losdtct[9], fsr6_mcu3_stsrx9_unused[0], fsr6_mcu3_stsrx_sync[9],
1613 fsr6_mcu3_stsrx_testfail[9]} ),
1614 .ststx0 ( {fsr6_mcu3_ststx4_unused[2:0], fsr6_mcu3_ststx_testfail[4]} ),
1615 .ststx1 ( {fsr6_mcu3_ststx5_unused[2:0], fsr6_mcu3_ststx_testfail[5]} ),
1616 .txbclk ( fsr6_txbclk_unused[5:4] ),
1617 .txn0 ( FBDIMM3A_TX_N[4] ),
1618 .txn1 ( FBDIMM3A_TX_N[5] ),
1619 .txp0 ( FBDIMM3A_TX_P[4] ),
1620 .txp1 ( FBDIMM3A_TX_P[5] ),
1621 .atpgmd ( fsr6_atpgrq_a8[5] ),
1622 .atpgmq ( fsr6_atpgmq_a8 ),
1623 .atpgrd ( {fsr6_atpgrq_a8[2],fsr6_atpgmq_a8,fsr6_atpgtq_a8[1],fsr6_atpgrq_a8[3],fsr6_atpgrq_a8[4],
1624 fsr6_atpgrq_a8[1]} ),
1625 .atpgrq ( fsr6_atpgrq_a8[5:0] ),
1626 .atpgtd ( {fsr6_atpgtq_b81[0],fsr6_atpgrq_a8[0]} ),
1627 .atpgtq ( fsr6_atpgtq_a8[1:0] ),
1628 .vdda ( VDDA ),
1629 .vddd ( VDDD ),
1630 .vddr ( VDDR ),
1631 .vddt ( VDDT ),
1632 .vssa ( VSSA )
1633 );
1634
1635// third serdes macro: RX ports 10-13, TX ports 6-9
1636
1637wiz6c2b8n6d2t fsr6_b8_1 (
1638 .bsinitclk ( fsr6_bsinitclk[2]),
1639 .cfgpll ({2'b0, mcu3_fsr6_cfgpll2[6:5], 3'b0, mcu3_fsr6_cfgpll2[4:0]}),
1640 .cfgrx0 ({2'b0, mcu3_fsr6_cfgrx10[19:18], 1'b0, mcu3_fsr6_cfgrx10[17:9], 1'b0, mcu3_fsr6_cfgrx10[8],
1641 1'b0, mcu3_fsr6_cfgrx10[7:2], 3'b0, mcu3_fsr6_cfgrx10[1:0]}),
1642 .cfgrx1 ({2'b0, mcu3_fsr6_cfgrx11[19:18], 1'b0, mcu3_fsr6_cfgrx11[17:9], 1'b0, mcu3_fsr6_cfgrx11[8],
1643 1'b0, mcu3_fsr6_cfgrx11[7:2], 3'b0, mcu3_fsr6_cfgrx11[1:0]}),
1644 .cfgrx2 ({2'b0, mcu3_fsr6_cfgrx12[19:18], 1'b0, mcu3_fsr6_cfgrx12[17:9], 1'b0, mcu3_fsr6_cfgrx12[8],
1645 1'b0, mcu3_fsr6_cfgrx12[7:2], 3'b0, mcu3_fsr6_cfgrx12[1:0]}),
1646 .cfgrx3 ({2'b0, mcu3_fsr6_cfgrx13[19:18], 1'b0, mcu3_fsr6_cfgrx13[17:9], 1'b0, mcu3_fsr6_cfgrx13[8],
1647 1'b0, mcu3_fsr6_cfgrx13[7:2], 3'b0, mcu3_fsr6_cfgrx13[1:0]}),
1648 .cfgtx0 ({1'b0, mcu3_fsr6_cfgtx6[15:2], 3'b0, mcu3_fsr6_cfgtx6[1:0]}),
1649 .cfgtx1 ({1'b0, mcu3_fsr6_cfgtx7[15:2], 3'b0, mcu3_fsr6_cfgtx7[1:0]}),
1650 .cfgtx2 ({1'b0, mcu3_fsr6_cfgtx8[15:2], 3'b0, mcu3_fsr6_cfgtx8[1:0]}),
1651 .cfgtx3 ({1'b0, mcu3_fsr6_cfgtx9[15:2], 3'b0, mcu3_fsr6_cfgtx9[1:0]}),
1652 .fclk ( fsr6_fclk[2] ),
1653 .fclrz ( fsr6_fclrz[2] ),
1654 .fdi ( fsr6_fdi[2] ),
1655 .refclkn ( clk622r_r_23x ),
1656 .refclkp ( clk622r_r_23 ),
1657 .rxbclkin ( fsr6_rxbclkin[13:10] ),
1658 .rxn0 ( FBDIMM3A_RX_N[10] ),
1659 .rxn1 ( FBDIMM3A_RX_N[11] ),
1660 .rxn2 ( FBDIMM3A_RX_N[12] ),
1661 .rxn3 ( FBDIMM3A_RX_N[13] ),
1662 .rxp0 ( FBDIMM3A_RX_P[10] ),
1663 .rxp1 ( FBDIMM3A_RX_P[11] ),
1664 .rxp2 ( FBDIMM3A_RX_P[12] ),
1665 .rxp3 ( FBDIMM3A_RX_P[13] ),
1666 .stcicfg ( fsr6_stcicfg[5:4] ),
1667 .stciclk ( fsr6_stciclk[2] ),
1668 .stcid ( fsr6_stcid[2] ),
1669 .td0 ( {mcu3_fsr6_td6[0], mcu3_fsr6_td6[1], mcu3_fsr6_td6[2], mcu3_fsr6_td6[3],
1670 mcu3_fsr6_td6[4], mcu3_fsr6_td6[5], mcu3_fsr6_td6[6], mcu3_fsr6_td6[7],
1671 mcu3_fsr6_td6[8], mcu3_fsr6_td6[9], mcu3_fsr6_td6[10], mcu3_fsr6_td6[11]} ),
1672 .td1 ( {mcu3_fsr6_td7[0], mcu3_fsr6_td7[1], mcu3_fsr6_td7[2], mcu3_fsr6_td7[3],
1673 mcu3_fsr6_td7[4], mcu3_fsr6_td7[5], mcu3_fsr6_td7[6], mcu3_fsr6_td7[7],
1674 mcu3_fsr6_td7[8], mcu3_fsr6_td7[9], mcu3_fsr6_td7[10], mcu3_fsr6_td7[11]} ),
1675 .td2 ( {mcu3_fsr6_td8[0], mcu3_fsr6_td8[1], mcu3_fsr6_td8[2], mcu3_fsr6_td8[3],
1676 mcu3_fsr6_td8[4], mcu3_fsr6_td8[5], mcu3_fsr6_td8[6], mcu3_fsr6_td8[7],
1677 mcu3_fsr6_td8[8], mcu3_fsr6_td8[9], mcu3_fsr6_td8[10], mcu3_fsr6_td8[11]} ),
1678 .td3 ( {mcu3_fsr6_td9[0], mcu3_fsr6_td9[1], mcu3_fsr6_td9[2], mcu3_fsr6_td9[3],
1679 mcu3_fsr6_td9[4], mcu3_fsr6_td9[5], mcu3_fsr6_td9[6], mcu3_fsr6_td9[7],
1680 mcu3_fsr6_td9[8], mcu3_fsr6_td9[9], mcu3_fsr6_td9[10], mcu3_fsr6_td9[11]} ),
1681 .testcfg ( {mcu3_fsr6_testcfg2[17:14], 1'b0, mcu3_fsr6_testcfg2[13:11], 1'b0, mcu3_fsr6_testcfg2[10:0]} ),
1682 .testclkr ( fsr6_testclkr[2] ),
1683 .testclkt ( fsr6_testclkt[2] ),
1684 .txbclkin ( {4{fsr6_txbclkin[2]}} ),
1685 .amux ( FBDIMM3A_AMUX[2] ),
1686 .fdo ( fsr6_fdo[2] ),
1687 .rd0 ( {fsr6_mcu3_rd10[0], fsr6_mcu3_rd10[1], fsr6_mcu3_rd10[2], fsr6_mcu3_rd10[3],
1688 fsr6_mcu3_rd10[4], fsr6_mcu3_rd10[5], fsr6_mcu3_rd10[6], fsr6_mcu3_rd10[7],
1689 fsr6_mcu3_rd10[8], fsr6_mcu3_rd10[9], fsr6_mcu3_rd10[10], fsr6_mcu3_rd10[11]} ),
1690 .rd1 ( {fsr6_mcu3_rd11[0], fsr6_mcu3_rd11[1], fsr6_mcu3_rd11[2], fsr6_mcu3_rd11[3],
1691 fsr6_mcu3_rd11[4], fsr6_mcu3_rd11[5], fsr6_mcu3_rd11[6], fsr6_mcu3_rd11[7],
1692 fsr6_mcu3_rd11[8], fsr6_mcu3_rd11[9], fsr6_mcu3_rd11[10], fsr6_mcu3_rd11[11]} ),
1693 .rd2 ( {fsr6_mcu3_rd12[0], fsr6_mcu3_rd12[1], fsr6_mcu3_rd12[2], fsr6_mcu3_rd12[3],
1694 fsr6_mcu3_rd12[4], fsr6_mcu3_rd12[5], fsr6_mcu3_rd12[6], fsr6_mcu3_rd12[7],
1695 fsr6_mcu3_rd12[8], fsr6_mcu3_rd12[9], fsr6_mcu3_rd12[10], fsr6_mcu3_rd12[11]} ),
1696 .rd3 ( {fsr6_mcu3_rd13[0], fsr6_mcu3_rd13[1], fsr6_mcu3_rd13[2], fsr6_mcu3_rd13[3],
1697 fsr6_mcu3_rd13[4], fsr6_mcu3_rd13[5], fsr6_mcu3_rd13[6], fsr6_mcu3_rd13[7],
1698 fsr6_mcu3_rd13[8], fsr6_mcu3_rd13[9], fsr6_mcu3_rd13[10], fsr6_mcu3_rd13[11]} ),
1699 .rdll0 ( fsr6_rdll0_b81[1:0] ),
1700 .rdll1 ( fsr6_rdll1_b81[1:0] ),
1701 .rdll2 ( fsr6_rdll2_b81[1:0] ),
1702 .rdll3 ( fsr6_rdll3_b81[1:0] ),
1703 .rxbclk ( fsr6_mcu3_rxbclk[13:10] ),
1704 .rxbclklln ( fsr6_rxbclklln_unused[13:10] ),
1705 .rxbclkllp ( fsr6_rxbclkllp_unused[13:10] ),
1706 .stciq ( fsr6_stciq[2] ),
1707 .stspll ( {fsr6_mcu3_stspll_b81[2:0], fsr6_mcu3_stspll_lock[2]} ),
1708 .stsrx0 ( {fsr6_mcu3_stsrx10_unused[2:1], fsr6_mcu3_stsrx_bsrxn[10], fsr6_mcu3_stsrx_bsrxp[10],
1709 fsr6_mcu3_stsrx_losdtct[10], fsr6_mcu3_stsrx10_unused[0], fsr6_mcu3_stsrx_sync[10],
1710 fsr6_mcu3_stsrx_testfail[10]} ),
1711 .stsrx1 ( {fsr6_mcu3_stsrx11_unused[2:1], fsr6_mcu3_stsrx_bsrxn[11], fsr6_mcu3_stsrx_bsrxp[11],
1712 fsr6_mcu3_stsrx_losdtct[11], fsr6_mcu3_stsrx11_unused[0], fsr6_mcu3_stsrx_sync[11],
1713 fsr6_mcu3_stsrx_testfail[11]} ),
1714 .stsrx2 ( {fsr6_mcu3_stsrx12_unused[2:1], fsr6_mcu3_stsrx_bsrxn[12], fsr6_mcu3_stsrx_bsrxp[12],
1715 fsr6_mcu3_stsrx_losdtct[12], fsr6_mcu3_stsrx12_unused[0], fsr6_mcu3_stsrx_sync[12],
1716 fsr6_mcu3_stsrx_testfail[12]} ),
1717 .stsrx3 ( {fsr6_mcu3_stsrx13_unused[2:1], fsr6_mcu3_stsrx_bsrxn[13], fsr6_mcu3_stsrx_bsrxp[13],
1718 fsr6_mcu3_stsrx_losdtct[13], fsr6_mcu3_stsrx13_unused[0], fsr6_mcu3_stsrx_sync[13],
1719 fsr6_mcu3_stsrx_testfail[13]} ),
1720 .ststx0 ( {fsr6_mcu3_ststx6_unused[2:0], fsr6_mcu3_ststx_testfail[6]} ),
1721 .ststx1 ( {fsr6_mcu3_ststx7_unused[2:0], fsr6_mcu3_ststx_testfail[7]} ),
1722 .ststx2 ( {fsr6_mcu3_ststx8_unused[2:0], fsr6_mcu3_ststx_testfail[8]} ),
1723 .ststx3 ( {fsr6_mcu3_ststx9_unused[2:0], fsr6_mcu3_ststx_testfail[9]} ),
1724 .txbclk ( fsr6_txbclk_unused[9:6] ),
1725 .txn0 ( FBDIMM3A_TX_N[6] ),
1726 .txn1 ( FBDIMM3A_TX_N[7] ),
1727 .txn2 ( FBDIMM3A_TX_N[8] ),
1728 .txn3 ( FBDIMM3A_TX_N[9] ),
1729 .txp0 ( FBDIMM3A_TX_P[6] ),
1730 .txp1 ( FBDIMM3A_TX_P[7] ),
1731 .txp2 ( FBDIMM3A_TX_P[8] ),
1732 .txp3 ( FBDIMM3A_TX_P[9] ),
1733 .atpgmd ( fsr6_atpgtq_b81[2] ),
1734 .atpgmq ( fsr6_atpgmq_b81 ),
1735 .atpgrd ( {fsr6_atpgtq_b81[3],fsr6_atpgrq_b81[3],fsr6_atpgtq_b81[1],fsr6_atpgrq_b81[1]} ),
1736 .atpgrq ( fsr6_atpgrq_b81[3:0] ),
1737 .atpgtd ( {fsr_right_atpgd,fsr6_atpgrq_b81[2],fsr6_atpgmq_b81,fsr6_atpgrq_b81[0]} ),
1738 .atpgtq ( fsr6_atpgtq_b81[3:0] ),
1739 .vdda ( VDDA ),
1740 .vddd ( VDDD ),
1741 .vddr ( VDDR ),
1742 .vddt ( VDDT ),
1743 .vssa ( VSSA )
1744 );
1745
1746endmodule
1747
Full OpenSPARC design & verification tarball including full HDL.