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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2b_evict_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2b_evict_dp ( | |
36 | l2clk, | |
37 | wmr_l, | |
38 | l2t_l2b_wbrd_en_r0, | |
39 | wb_array_dout, | |
40 | l2t_l2b_evict_en_r0, | |
41 | l2t_l2b_ev_dword_r0, | |
42 | l2t_l2b_rdma_rden_r0, | |
43 | rdma_array_dout, | |
44 | l2t_l2b_wbrd_wl_r0, | |
45 | l2t_l2b_wbwr_wen_c6, | |
46 | l2t_l2b_wbwr_wl_c6, | |
47 | l2t_l2b_rdma_rdwl_r0, | |
48 | l2t_l2b_rdma_wren_s2, | |
49 | l2t_l2b_rdma_wrwl_s2, | |
50 | tcu_aclk, | |
51 | tcu_bclk, | |
52 | tcu_pce_ov, | |
53 | tcu_scan_en, | |
54 | tcu_clk_stop, | |
55 | tcu_muxtest, | |
56 | tcu_dectest, | |
57 | scan_in, | |
58 | scan_out, | |
59 | mbist_addr, | |
60 | wb_mbist_data_in, | |
61 | mbist_wb_array_wr_en, | |
62 | mbist_wb_array_rd_en, | |
63 | mbist_rdma_array_wr_en, | |
64 | mbist_rdma_array_rd_en, | |
65 | mbist_sel_wb_arrays, | |
66 | mbist_evict_muxsel, | |
67 | mbist_run, | |
68 | wb_or_rdma_rw_fail, | |
69 | evict_l2b_mcu_wr_data_r5, | |
70 | select_delay_mcu, | |
71 | evict_l2b_mcu_data_vld_r5, | |
72 | evict_l2b_mcu_data_mecc_r5, | |
73 | evict_l2b_l2t_ev_uerr_r5, | |
74 | evict_l2b_l2t_ev_cerr_r5, | |
75 | evict_l2t_l2b_wbrd_en_r1_v1, | |
76 | evict_l2t_l2b_wbrd_en_r1_v2, | |
77 | evict_l2t_l2b_wbrd_en_r1_v3, | |
78 | evict_l2t_l2b_wbrd_en_r1_v4, | |
79 | evict_l2t_l2b_wbrd_wl_r1_v1, | |
80 | evict_l2t_l2b_wbrd_wl_r1_v2, | |
81 | evict_l2t_l2b_wbrd_wl_r1_v3, | |
82 | evict_l2t_l2b_wbrd_wl_r1_v4, | |
83 | evict_l2t_l2b_wbwr_wen_c8_v1, | |
84 | evict_l2t_l2b_wbwr_wen_c8_v2, | |
85 | evict_l2t_l2b_wbwr_wen_c8_v3, | |
86 | evict_l2t_l2b_wbwr_wen_c8_v4, | |
87 | evict_l2t_l2b_wbwr_wl_c8_v1, | |
88 | evict_l2t_l2b_wbwr_wl_c8_v2, | |
89 | evict_l2t_l2b_wbwr_wl_c8_v3, | |
90 | evict_l2t_l2b_wbwr_wl_c8_v4, | |
91 | evict_l2t_l2b_rdma_rden_r1_v1, | |
92 | evict_l2t_l2b_rdma_rden_r1_v2, | |
93 | evict_l2t_l2b_rdma_rden_r1_v3, | |
94 | evict_l2t_l2b_rdma_rden_r1_v4, | |
95 | evict_l2t_l2b_rdma_rdwl_r1_v1, | |
96 | evict_l2t_l2b_rdma_rdwl_r1_v2, | |
97 | evict_l2t_l2b_rdma_rdwl_r1_v3, | |
98 | evict_l2t_l2b_rdma_rdwl_r1_v4, | |
99 | evict_l2t_l2b_rdma_wren_s3, | |
100 | evict_l2t_l2b_rdma_wren_s3_v4, | |
101 | evict_l2t_l2b_rdma_wren_s3_v3, | |
102 | evict_l2t_l2b_rdma_wren_s3_v2, | |
103 | evict_l2t_l2b_rdma_wren_s3_v1, | |
104 | evict_l2t_l2b_rdma_wrwl_s3_v1, | |
105 | evict_l2t_l2b_rdma_wrwl_s3_v2, | |
106 | evict_l2t_l2b_rdma_wrwl_s3_v3, | |
107 | evict_l2t_l2b_rdma_wrwl_s3_v4); | |
108 | wire pce_ov; | |
109 | wire siclk; | |
110 | wire soclk; | |
111 | wire se; | |
112 | wire stop; | |
113 | wire muxtst; | |
114 | wire test; | |
115 | wire [0:0] sel_evct_mux_r3_1a_unused; | |
116 | wire [3:0] sel_evct_mux_r3_1a; | |
117 | wire [0:0] sel_evct_mux_r3_1b_unused; | |
118 | wire [3:0] sel_evct_mux_r3_1b; | |
119 | wire [0:0] sel_evct_mux_r3_2a_unused; | |
120 | wire [3:0] sel_evct_mux_r3_2a; | |
121 | wire [0:0] sel_evct_mux_r3_2b_unused; | |
122 | wire [3:0] sel_evct_mux_r3_2b; | |
123 | wire [1:0] l2t_l2b_ev_dword_r2_unused; | |
124 | wire [1:0] l2t_l2b_ev_dword_r3_unused; | |
125 | wire ff_mbist_run_scanin; | |
126 | wire ff_mbist_run_scanout; | |
127 | wire mbist_run_reg; | |
128 | wire [7:0] wb_mbist_data_in_r2; | |
129 | wire [7:0] wb_mbist_data_in_r1; | |
130 | wire mbist_wb_array_rd_en_reg; | |
131 | wire mbist_rdma_array_rd_en_reg; | |
132 | wire mbist_sel_wb_arrays_reg; | |
133 | wire [4:0] mbist_evict_muxsel_reg; | |
134 | wire mbist_run_reg_n; | |
135 | wire mbist_run_reg_v1_n; | |
136 | wire mbist_run_reg_v1; | |
137 | wire mbist_run_reg_v2_n; | |
138 | wire mbist_run_reg_v2; | |
139 | wire mbist_run_reg_v3_n; | |
140 | wire mbist_run_reg_v3; | |
141 | wire mbist_run_reg_v4_n; | |
142 | wire mbist_run_reg_v4; | |
143 | wire ff_mbist_run_v1_scanin; | |
144 | wire ff_mbist_run_v1_scanout; | |
145 | wire mbist_wb_array_wr_en_reg_v1; | |
146 | wire [2:0] mbist_addr_reg_v1; | |
147 | wire mbist_wb_array_rd_en_reg_v1; | |
148 | wire mbist_rdma_array_wr_en_reg_v1; | |
149 | wire mbist_rdma_array_rd_en_reg_v1; | |
150 | wire ff_mbist_run_v2_scanin; | |
151 | wire ff_mbist_run_v2_scanout; | |
152 | wire mbist_wb_array_wr_en_reg_v2; | |
153 | wire [2:0] mbist_addr_reg_v2; | |
154 | wire mbist_wb_array_rd_en_reg_v2; | |
155 | wire mbist_rdma_array_wr_en_reg_v2; | |
156 | wire mbist_rdma_array_rd_en_reg_v2; | |
157 | wire ff_mbist_run_v3_scanin; | |
158 | wire ff_mbist_run_v3_scanout; | |
159 | wire mbist_wb_array_wr_en_reg_v3; | |
160 | wire [2:0] mbist_addr_reg_v3; | |
161 | wire mbist_wb_array_rd_en_reg_v3; | |
162 | wire mbist_rdma_array_wr_en_reg_v3; | |
163 | wire mbist_rdma_array_rd_en_reg_v3; | |
164 | wire ff_mbist_run_v4_scanin; | |
165 | wire ff_mbist_run_v4_scanout; | |
166 | wire mbist_wb_array_wr_en_reg_v4; | |
167 | wire [2:0] mbist_addr_reg_v4; | |
168 | wire mbist_wb_array_rd_en_reg_v4; | |
169 | wire mbist_rdma_array_wr_en_reg_v4; | |
170 | wire mbist_rdma_array_rd_en_reg_v4; | |
171 | wire mbist_wbarray_write_en_c8_v1; | |
172 | wire [2:0] writeback_array_wr_en_v1; | |
173 | wire [1:0] compute_evict_l2t_l2b_rdma_wrwl_s3_v1; | |
174 | wire l2t_l2b_wbwr_wen_c8_v1; | |
175 | wire [2:0] l2t_l2b_wbwr_wl_c8_v1; | |
176 | wire [2:0] l2t_l2b_wbrd_wl_r1_v1; | |
177 | wire [1:0] l2t_l2b_rdma_rdwl_r1_v1; | |
178 | wire [1:0] l2t_l2b_rdma_wrwl_s3_v1; | |
179 | wire l2t_l2b_wbrd_en_r1_v1; | |
180 | wire l2t_l2b_rdma_rden_r1_v1; | |
181 | wire fnl_evict_l2t_l2b_rdma_wren_s3_v1; | |
182 | wire mbist_wbarray_write_en_c8_v2; | |
183 | wire [2:0] writeback_array_wr_en_v2; | |
184 | wire [1:0] compute_evict_l2t_l2b_rdma_wrwl_s3_v2; | |
185 | wire l2t_l2b_wbwr_wen_c8_v2; | |
186 | wire [2:0] l2t_l2b_wbwr_wl_c8_v2; | |
187 | wire [2:0] l2t_l2b_wbrd_wl_r1_v2; | |
188 | wire [1:0] l2t_l2b_rdma_rdwl_r1_v2; | |
189 | wire [1:0] l2t_l2b_rdma_wrwl_s3_v2; | |
190 | wire l2t_l2b_wbrd_en_r1_v2; | |
191 | wire l2t_l2b_rdma_rden_r1_v2; | |
192 | wire fnl_evict_l2t_l2b_rdma_wren_s3_v2; | |
193 | wire mbist_wbarray_write_en_c8_v3; | |
194 | wire [2:0] writeback_array_wr_en_v3; | |
195 | wire [1:0] compute_evict_l2t_l2b_rdma_wrwl_s3_v3; | |
196 | wire l2t_l2b_wbwr_wen_c8_v3; | |
197 | wire [2:0] l2t_l2b_wbwr_wl_c8_v3; | |
198 | wire [2:0] l2t_l2b_wbrd_wl_r1_v3; | |
199 | wire [1:0] l2t_l2b_rdma_rdwl_r1_v3; | |
200 | wire [1:0] l2t_l2b_rdma_wrwl_s3_v3; | |
201 | wire l2t_l2b_wbrd_en_r1_v3; | |
202 | wire l2t_l2b_rdma_rden_r1_v3; | |
203 | wire fnl_evict_l2t_l2b_rdma_wren_s3_v3; | |
204 | wire mbist_wbarray_write_en_c8_v4; | |
205 | wire [2:0] writeback_array_wr_en_v4; | |
206 | wire [1:0] compute_evict_l2t_l2b_rdma_wrwl_s3_v4; | |
207 | wire l2t_l2b_wbwr_wen_c8_v4; | |
208 | wire [2:0] l2t_l2b_wbwr_wl_c8_v4; | |
209 | wire [2:0] l2t_l2b_wbrd_wl_r1_v4; | |
210 | wire [1:0] l2t_l2b_rdma_rdwl_r1_v4; | |
211 | wire [1:0] l2t_l2b_rdma_wrwl_s3_v4; | |
212 | wire l2t_l2b_wbrd_en_r1_v4; | |
213 | wire l2t_l2b_rdma_rden_r1_v4; | |
214 | wire fnl_evict_l2t_l2b_rdma_wren_s3_v4; | |
215 | wire evict_l2t_l2b_rdma_wren_s3_6_or_4; | |
216 | wire evict_l2t_l2b_rdma_wren_s3_0_or_2; | |
217 | wire evict_l2t_l2b_rdma_wren_s3_1_or_3; | |
218 | wire evict_l2t_l2b_rdma_wren_s3_5_or_7; | |
219 | wire evict_l2t_l2b_rdma_wren_s3_8_or_14; | |
220 | wire evict_l2t_l2b_rdma_wren_s3_10_or_12; | |
221 | wire evict_l2t_l2b_rdma_wren_s3_15_or_13; | |
222 | wire evict_l2t_l2b_rdma_wren_s3_11_or_9; | |
223 | wire l2t_l2b_wbrd_en_r1_in; | |
224 | wire l2t_l2b_wbrd_en_r1; | |
225 | wire error_qual_and_l2t_l2b_evict_en_r3; | |
226 | wire l2t_l2b_rdma_rden_r3; | |
227 | wire ff_array_rd_ptr_din; | |
228 | wire dbb_rst_l; | |
229 | wire wb_or_rdma_rden_r2_1; | |
230 | wire wb_or_rdma_rden_r2_sega; | |
231 | wire wb_or_rdma_rden_r2_segb; | |
232 | wire l2t_l2b_wbrd_en_r2_n; | |
233 | wire ff_wb_array_dout_r3_1a_scanin; | |
234 | wire ff_wb_array_dout_r3_1a_scanout; | |
235 | wire ff_wb_array_dout_r3_1b_scanin; | |
236 | wire ff_wb_array_dout_r3_1b_scanout; | |
237 | wire ff_wb_array_dout_r3_1c_scanin; | |
238 | wire ff_wb_array_dout_r3_1c_scanout; | |
239 | wire ff_wb_array_dout_r3_1d_scanin; | |
240 | wire ff_wb_array_dout_r3_1d_scanout; | |
241 | wire ff_wb_array_dout_r3_2a_scanin; | |
242 | wire ff_wb_array_dout_r3_2a_scanout; | |
243 | wire ff_wb_array_dout_r3_2b_scanin; | |
244 | wire ff_wb_array_dout_r3_2b_scanout; | |
245 | wire ff_wb_array_dout_r3_2c_scanin; | |
246 | wire ff_wb_array_dout_r3_2c_scanout; | |
247 | wire ff_wb_array_dout_r3_2d_scanin; | |
248 | wire ff_wb_array_dout_r3_2d_scanout; | |
249 | wire ff_wb_array_dout_r3_3a_scanin; | |
250 | wire ff_wb_array_dout_r3_3a_scanout; | |
251 | wire ff_wb_array_dout_r3_3b_scanin; | |
252 | wire ff_wb_array_dout_r3_3b_scanout; | |
253 | wire ff_wb_array_dout_r3_3c_scanin; | |
254 | wire ff_wb_array_dout_r3_3c_scanout; | |
255 | wire ff_wb_array_dout_r3_3d_scanin; | |
256 | wire ff_wb_array_dout_r3_3d_scanout; | |
257 | wire ff_wb_array_dout_r3_4a_scanin; | |
258 | wire ff_wb_array_dout_r3_4a_scanout; | |
259 | wire ff_wb_array_dout_r3_4b_scanin; | |
260 | wire ff_wb_array_dout_r3_4b_scanout; | |
261 | wire ff_wb_array_dout_r3_4c_scanin; | |
262 | wire ff_wb_array_dout_r3_4c_scanout; | |
263 | wire ff_wb_array_dout_r3_4d_scanin; | |
264 | wire ff_wb_array_dout_r3_4d_scanout; | |
265 | wire sel_in0_r1; | |
266 | wire sel_in1_r1; | |
267 | wire sel_in2_r1; | |
268 | wire sel_in3_r1; | |
269 | wire [3:0] sel_evct_mux_r1; | |
270 | wire l2t_l2b_ev_dword_r3_2; | |
271 | wire mbist_pick_top_bot; | |
272 | wire l2t_l2b_ev_dword_r3_2_n; | |
273 | wire ff_wb_array_dout_r4a_scanin; | |
274 | wire ff_wb_array_dout_r4a_scanout; | |
275 | wire ff_wb_array_dout_r4b_scanin; | |
276 | wire ff_wb_array_dout_r4b_scanout; | |
277 | wire [15:0] unused; | |
278 | wire [623:0] mbist_cmp_data; | |
279 | wire [155:0] mbist_cmp_data_4t1; | |
280 | wire [77:0] mbist_cmp_data_8t1; | |
281 | wire [77:0] mbist_compare_data; | |
282 | wire ff_mbist_cmp_r4a_scanin; | |
283 | wire ff_mbist_cmp_r4a_scanout; | |
284 | wire ff_mbist_cmp_r4b_scanin; | |
285 | wire ff_mbist_cmp_r4b_scanout; | |
286 | wire wb_or_rdma_rw_fail1; | |
287 | wire wb_or_rdma_rw_fail2; | |
288 | wire read_enable_piped; | |
289 | wire mbist_wb_array_rd_en_reg2; | |
290 | wire mbist_rdma_array_rd_en_reg2; | |
291 | wire wb_or_rdma_rw_fail_unreg; | |
292 | wire wb_or_rdma_rw_fail_unreg_out; | |
293 | wire read_enable_piped1; | |
294 | wire ff_fb_rw_fail_scanin; | |
295 | wire ff_fb_rw_fail_scanout; | |
296 | wire mbist_wb_array_rd_en_reg1; | |
297 | wire mbist_rdma_array_rd_en_reg1; | |
298 | wire parity0_r4; | |
299 | wire parity1_r4; | |
300 | wire check0_r4_3_0_nand; | |
301 | wire check0_r4_4_5_parity_0_nand; | |
302 | wire evict_notdata_err_lo_r4; | |
303 | wire check1_r4_3_0_nand; | |
304 | wire check1_r4_4_5_parity_1_nand; | |
305 | wire evict_notdata_err_hi_r4; | |
306 | wire error_qual_n; | |
307 | wire evict_en_and_error_qual_; | |
308 | wire l2t_l2b_evict_en_r4; | |
309 | wire l2t_l2b_evict_en_r4_n; | |
310 | wire check0or_n; | |
311 | wire check1or_n; | |
312 | wire parity0_nand_parity1; | |
313 | wire check0_nand_check1; | |
314 | wire parity0_nand_check1; | |
315 | wire parity1_nand_check0; | |
316 | wire evict_uncorr_err_r4_eqn2_; | |
317 | wire parity_0_or_1_r4_; | |
318 | wire parity_0_or_1_r4_err_qual_n; | |
319 | wire notdata_err_loorhi_r4_n; | |
320 | wire ff_wb_array_dout_r5_31_0_scanin; | |
321 | wire ff_wb_array_dout_r5_31_0_scanout; | |
322 | wire ff_wb_array_dout_r5_63_32_scanin; | |
323 | wire ff_wb_array_dout_r5_63_32_scanout; | |
324 | wire evict_uncorr_err_r5; | |
325 | wire evict_corr_err_r5; | |
326 | wire select_delay_mcu_n; | |
327 | wire ff_evict_l2b_mcu_wr_data_r5_d1_scanin; | |
328 | wire ff_evict_l2b_mcu_wr_data_r5_d1_scanout; | |
329 | wire [63:0] wb_array_dout_r5_d1; | |
330 | wire evict_mcu_uncorr_err_r5_d1; | |
331 | wire l2t_l2b_evict_en_r5_d1; | |
332 | wire evict_mcu_uncorr_err_r5; | |
333 | wire l2t_l2b_evict_en_r5; | |
334 | wire ff_evict_control_regs_slice_scanin; | |
335 | wire ff_evict_control_regs_slice_scanout; | |
336 | wire evict_uncorr_mcu_err_r5; | |
337 | wire evict_notdata_err_lo_r5; | |
338 | wire evict_notdata_err_hi_r5; | |
339 | wire l2t_l2b_evict_en_r1_fnl; | |
340 | wire l2t_l2b_evict_en_r2; | |
341 | wire [3:0] sel_evct_mux_r2; | |
342 | wire l2t_l2b_evict_en_r1; | |
343 | wire ff_mux_select0_2b_scanin; | |
344 | wire ff_mux_select0_2b_scanout; | |
345 | wire [3:0] sel_evct_fnl_mux_sel; | |
346 | wire ff_mux_select1_2a_scanin; | |
347 | wire ff_mux_select1_2a_scanout; | |
348 | wire ff_mux_select2_1b_scanin; | |
349 | wire ff_mux_select2_1b_scanout; | |
350 | wire ff_mux_select3_1a_scanin; | |
351 | wire ff_mux_select3_1a_scanout; | |
352 | wire ff_wb_control_regs_slice_scanin; | |
353 | wire ff_wb_control_regs_slice_scanout; | |
354 | wire ff_wb_control_regs_slice_v1_scanin; | |
355 | wire ff_wb_control_regs_slice_v1_scanout; | |
356 | wire ff_wb_control_regs_slice_v2_scanin; | |
357 | wire ff_wb_control_regs_slice_v2_scanout; | |
358 | wire ff_wb_control_regs_slice_v3_scanin; | |
359 | wire ff_wb_control_regs_slice_v3_scanout; | |
360 | wire ff_wb_control_regs_slice_v4_scanin; | |
361 | wire ff_wb_control_regs_slice_v4_scanout; | |
362 | wire [15:0] l2t_l2b_rdma_fnl_wren_s2; | |
363 | wire ff_rdma_control_regs_slice_scanin; | |
364 | wire ff_rdma_control_regs_slice_scanout; | |
365 | wire ff_rdma_control_regs_slice_v1_scanin; | |
366 | wire ff_rdma_control_regs_slice_v1_scanout; | |
367 | wire ff_rdma_control_regs_slice_v2_scanin; | |
368 | wire ff_rdma_control_regs_slice_v2_scanout; | |
369 | wire ff_rdma_control_regs_slice_v3_scanin; | |
370 | wire ff_rdma_control_regs_slice_v3_scanout; | |
371 | wire ff_rdma_control_regs_slice_v4_scanin; | |
372 | wire ff_rdma_control_regs_slice_v4_scanout; | |
373 | ||
374 | ||
375 | ||
376 | input l2clk; | |
377 | input wmr_l; | |
378 | input l2t_l2b_wbrd_en_r0; | |
379 | input [623:0] wb_array_dout; | |
380 | input l2t_l2b_evict_en_r0; | |
381 | input [2:0] l2t_l2b_ev_dword_r0; | |
382 | input l2t_l2b_rdma_rden_r0; | |
383 | input [623:0] rdma_array_dout; | |
384 | ||
385 | input [2:0] l2t_l2b_wbrd_wl_r0; | |
386 | input l2t_l2b_wbwr_wen_c6; | |
387 | input [2:0] l2t_l2b_wbwr_wl_c6; | |
388 | input [1:0] l2t_l2b_rdma_rdwl_r0; | |
389 | input [15:0] l2t_l2b_rdma_wren_s2; | |
390 | input [1:0] l2t_l2b_rdma_wrwl_s2; | |
391 | ||
392 | input tcu_aclk; | |
393 | input tcu_bclk; | |
394 | input tcu_pce_ov; | |
395 | input tcu_scan_en; | |
396 | input tcu_clk_stop; | |
397 | input tcu_muxtest; | |
398 | input tcu_dectest; | |
399 | ||
400 | input scan_in; | |
401 | output scan_out; | |
402 | ||
403 | // mbist ports | |
404 | ||
405 | input [2:0] mbist_addr; | |
406 | input [7:0] wb_mbist_data_in; | |
407 | input mbist_wb_array_wr_en; | |
408 | input mbist_wb_array_rd_en; | |
409 | input mbist_rdma_array_wr_en; | |
410 | input mbist_rdma_array_rd_en; | |
411 | input mbist_sel_wb_arrays; | |
412 | input [4:0] mbist_evict_muxsel; | |
413 | input mbist_run; | |
414 | //input [2:0] mbist_compare_read_sel; | |
415 | output wb_or_rdma_rw_fail; | |
416 | ||
417 | assign pce_ov = tcu_pce_ov; | |
418 | assign siclk = tcu_aclk; | |
419 | assign soclk = tcu_bclk; | |
420 | assign se = tcu_scan_en; | |
421 | assign stop = tcu_clk_stop; | |
422 | assign muxtst = tcu_muxtest; | |
423 | assign test = tcu_dectest; | |
424 | ||
425 | // Outputs | |
426 | output [63:0] evict_l2b_mcu_wr_data_r5; | |
427 | input select_delay_mcu; | |
428 | ||
429 | output evict_l2b_mcu_data_vld_r5; | |
430 | output evict_l2b_mcu_data_mecc_r5; | |
431 | output evict_l2b_l2t_ev_uerr_r5; | |
432 | output evict_l2b_l2t_ev_cerr_r5; | |
433 | ||
434 | output evict_l2t_l2b_wbrd_en_r1_v1; | |
435 | output evict_l2t_l2b_wbrd_en_r1_v2; | |
436 | output evict_l2t_l2b_wbrd_en_r1_v3; | |
437 | output evict_l2t_l2b_wbrd_en_r1_v4; | |
438 | ||
439 | output [2:0] evict_l2t_l2b_wbrd_wl_r1_v1; | |
440 | output [2:0] evict_l2t_l2b_wbrd_wl_r1_v2; | |
441 | output [2:0] evict_l2t_l2b_wbrd_wl_r1_v3; | |
442 | output [2:0] evict_l2t_l2b_wbrd_wl_r1_v4; | |
443 | ||
444 | output evict_l2t_l2b_wbwr_wen_c8_v1; | |
445 | output evict_l2t_l2b_wbwr_wen_c8_v2; | |
446 | output evict_l2t_l2b_wbwr_wen_c8_v3; | |
447 | output evict_l2t_l2b_wbwr_wen_c8_v4; | |
448 | ||
449 | output [2:0] evict_l2t_l2b_wbwr_wl_c8_v1; | |
450 | output [2:0] evict_l2t_l2b_wbwr_wl_c8_v2; | |
451 | output [2:0] evict_l2t_l2b_wbwr_wl_c8_v3; | |
452 | output [2:0] evict_l2t_l2b_wbwr_wl_c8_v4; | |
453 | ||
454 | output evict_l2t_l2b_rdma_rden_r1_v1; | |
455 | output evict_l2t_l2b_rdma_rden_r1_v2; | |
456 | output evict_l2t_l2b_rdma_rden_r1_v3; | |
457 | output evict_l2t_l2b_rdma_rden_r1_v4; | |
458 | ||
459 | output [1:0] evict_l2t_l2b_rdma_rdwl_r1_v1; | |
460 | output [1:0] evict_l2t_l2b_rdma_rdwl_r1_v2; | |
461 | output [1:0] evict_l2t_l2b_rdma_rdwl_r1_v3; | |
462 | output [1:0] evict_l2t_l2b_rdma_rdwl_r1_v4; | |
463 | ||
464 | output [15:0] evict_l2t_l2b_rdma_wren_s3; | |
465 | ||
466 | output evict_l2t_l2b_rdma_wren_s3_v4 ; | |
467 | output evict_l2t_l2b_rdma_wren_s3_v3 ; | |
468 | output evict_l2t_l2b_rdma_wren_s3_v2 ; | |
469 | output evict_l2t_l2b_rdma_wren_s3_v1 ; | |
470 | ||
471 | output [1:0] evict_l2t_l2b_rdma_wrwl_s3_v1; | |
472 | output [1:0] evict_l2t_l2b_rdma_wrwl_s3_v2; | |
473 | output [1:0] evict_l2t_l2b_rdma_wrwl_s3_v3; | |
474 | output [1:0] evict_l2t_l2b_rdma_wrwl_s3_v4; | |
475 | ||
476 | ||
477 | ||
478 | ////////////////////////////////////////////////////////////////////////////////// | |
479 | ||
480 | wire l2t_l2b_wbrd_en_r2; | |
481 | wire l2t_l2b_rdma_rden_r1; | |
482 | wire l2t_l2b_rdma_rden_r2; | |
483 | wire wb_or_rdma_rden_r2; | |
484 | wire [623:0] wb_rdma_mux_out; | |
485 | wire [623:0] wb_array_dout_r3; | |
486 | wire [ 77:0] wb_array_dout_r4; | |
487 | wire [ 63:0] wb_array_dout_r5; | |
488 | ||
489 | wire [ 2:0] l2t_l2b_ev_dword_r1; | |
490 | wire [ 2:0] l2t_l2b_ev_dword_r2; | |
491 | wire [ 2:0] l2t_l2b_ev_dword_r3; | |
492 | wire [155:0] wb_array_dout_r3_4t1; | |
493 | wire [ 77:0] wb_array_dout_r3_8t1; | |
494 | ||
495 | wire [ 63:0] wb_array_dout_ecc_r4; | |
496 | wire [ 5:0] check0_r4; | |
497 | wire [ 5:0] check1_r4; | |
498 | wire evict_uncorr_err_r4; | |
499 | wire evict_uncorr_mcu_err_r4; | |
500 | wire evict_corr_err_r4; | |
501 | ||
502 | wire l2t_l2b_wbwr_wen_c7; | |
503 | wire [ 2:0] l2t_l2b_wbwr_wl_c7; | |
504 | ||
505 | wire l2t_l2b_wbwr_wen_c8; | |
506 | //wire [1:0] l2t_l2b_rdma_rdwl_r1; | |
507 | //wire [1:0] l2t_l2b_rdma_wrwl_s3; | |
508 | ||
509 | wire l2t_l2b_evict_en_r3; | |
510 | wire error_qual_in; | |
511 | wire error_qual; | |
512 | ||
513 | // make vlint happy | |
514 | assign sel_evct_mux_r3_1a_unused[0] = sel_evct_mux_r3_1a[0]; | |
515 | assign sel_evct_mux_r3_1b_unused[0] = sel_evct_mux_r3_1b[0]; | |
516 | assign sel_evct_mux_r3_2a_unused[0] = sel_evct_mux_r3_2a[0]; | |
517 | assign sel_evct_mux_r3_2b_unused[0] = sel_evct_mux_r3_2b[0]; | |
518 | assign l2t_l2b_ev_dword_r2_unused[1:0] = 2'b0; | |
519 | assign l2t_l2b_ev_dword_r3_unused[1:0] = 2'b0; | |
520 | ||
521 | ||
522 | ////////////////////////////////////////////////////////////////////////////////// | |
523 | ||
524 | l2b_evict_dp_msff_macro__stack_26c__width_25 ff_mbist_run | |
525 | ( | |
526 | .scan_in(ff_mbist_run_scanin), | |
527 | .scan_out(ff_mbist_run_scanout), | |
528 | .dout ({mbist_run_reg, wb_mbist_data_in_r2[7:0],wb_mbist_data_in_r1[7:0], | |
529 | mbist_wb_array_rd_en_reg,mbist_rdma_array_rd_en_reg, | |
530 | mbist_sel_wb_arrays_reg,mbist_evict_muxsel_reg[4:0]}), | |
531 | .din ({mbist_run, wb_mbist_data_in_r1[7:0],wb_mbist_data_in[7:0], | |
532 | mbist_wb_array_rd_en,mbist_rdma_array_rd_en, | |
533 | mbist_sel_wb_arrays,mbist_evict_muxsel[4:0]}), | |
534 | .en (1'b1), | |
535 | .clk (l2clk), | |
536 | .se(se), | |
537 | .siclk(siclk), | |
538 | .soclk(soclk), | |
539 | .pce_ov(pce_ov), | |
540 | .stop(stop) | |
541 | ); | |
542 | ||
543 | ||
544 | l2b_evict_dp_inv_macro__width_1 inv_mbist_run_reg | |
545 | ( | |
546 | .dout (mbist_run_reg_n), | |
547 | .din (mbist_run_reg) | |
548 | ); | |
549 | ||
550 | l2b_evict_dp_inv_macro__width_1 inv_mbist_run_v1_reg | |
551 | ( | |
552 | .dout (mbist_run_reg_v1_n), | |
553 | .din (mbist_run_reg_v1) | |
554 | ); | |
555 | ||
556 | l2b_evict_dp_inv_macro__width_1 inv_mbist_run_v2_reg | |
557 | ( | |
558 | .dout (mbist_run_reg_v2_n), | |
559 | .din (mbist_run_reg_v2) | |
560 | ); | |
561 | ||
562 | l2b_evict_dp_inv_macro__width_1 inv_mbist_run_v3_reg | |
563 | ( | |
564 | .dout (mbist_run_reg_v3_n), | |
565 | .din (mbist_run_reg_v3) | |
566 | ); | |
567 | ||
568 | l2b_evict_dp_inv_macro__width_1 inv_mbist_run_v4_reg | |
569 | ( | |
570 | .dout (mbist_run_reg_v4_n), | |
571 | .din (mbist_run_reg_v4) | |
572 | ); | |
573 | ||
574 | l2b_evict_dp_msff_macro__stack_8c__width_8 ff_mbist_run_v1 | |
575 | ( | |
576 | .scan_in(ff_mbist_run_v1_scanin), | |
577 | .scan_out(ff_mbist_run_v1_scanout), | |
578 | .dout ({mbist_run_reg_v1,mbist_wb_array_wr_en_reg_v1,mbist_addr_reg_v1[2:0],mbist_wb_array_rd_en_reg_v1,mbist_rdma_array_wr_en_reg_v1, | |
579 | mbist_rdma_array_rd_en_reg_v1}), | |
580 | .din ({mbist_run ,mbist_wb_array_wr_en ,mbist_addr[2:0], mbist_wb_array_rd_en, mbist_rdma_array_wr_en, | |
581 | mbist_rdma_array_rd_en}), | |
582 | .clk (l2clk), | |
583 | .en (1'b1), | |
584 | .se(se), | |
585 | .siclk(siclk), | |
586 | .soclk(soclk), | |
587 | .pce_ov(pce_ov), | |
588 | .stop(stop) | |
589 | ); | |
590 | ||
591 | ||
592 | ||
593 | l2b_evict_dp_msff_macro__stack_8c__width_8 ff_mbist_run_v2 | |
594 | ( | |
595 | .scan_in(ff_mbist_run_v2_scanin), | |
596 | .scan_out(ff_mbist_run_v2_scanout), | |
597 | .dout ({mbist_run_reg_v2,mbist_wb_array_wr_en_reg_v2,mbist_addr_reg_v2[2:0],mbist_wb_array_rd_en_reg_v2,mbist_rdma_array_wr_en_reg_v2, | |
598 | mbist_rdma_array_rd_en_reg_v2}), | |
599 | .din ({mbist_run ,mbist_wb_array_wr_en ,mbist_addr[2:0], mbist_wb_array_rd_en, mbist_rdma_array_wr_en, | |
600 | mbist_rdma_array_rd_en}), | |
601 | .clk (l2clk), | |
602 | .en (1'b1), | |
603 | .se(se), | |
604 | .siclk(siclk), | |
605 | .soclk(soclk), | |
606 | .pce_ov(pce_ov), | |
607 | .stop(stop) | |
608 | ); | |
609 | ||
610 | ||
611 | l2b_evict_dp_msff_macro__stack_8c__width_8 ff_mbist_run_v3 | |
612 | ( | |
613 | .scan_in(ff_mbist_run_v3_scanin), | |
614 | .scan_out(ff_mbist_run_v3_scanout), | |
615 | .dout ({mbist_run_reg_v3,mbist_wb_array_wr_en_reg_v3,mbist_addr_reg_v3[2:0],mbist_wb_array_rd_en_reg_v3,mbist_rdma_array_wr_en_reg_v3, | |
616 | mbist_rdma_array_rd_en_reg_v3}), | |
617 | .din ({mbist_run ,mbist_wb_array_wr_en ,mbist_addr[2:0], mbist_wb_array_rd_en, mbist_rdma_array_wr_en, | |
618 | mbist_rdma_array_rd_en}), | |
619 | .clk (l2clk), | |
620 | .en (1'b1), | |
621 | .se(se), | |
622 | .siclk(siclk), | |
623 | .soclk(soclk), | |
624 | .pce_ov(pce_ov), | |
625 | .stop(stop) | |
626 | ); | |
627 | ||
628 | ||
629 | l2b_evict_dp_msff_macro__stack_8c__width_8 ff_mbist_run_v4 | |
630 | ( | |
631 | .scan_in(ff_mbist_run_v4_scanin), | |
632 | .scan_out(ff_mbist_run_v4_scanout), | |
633 | .dout ({mbist_run_reg_v4,mbist_wb_array_wr_en_reg_v4,mbist_addr_reg_v4[2:0],mbist_wb_array_rd_en_reg_v4,mbist_rdma_array_wr_en_reg_v4, | |
634 | mbist_rdma_array_rd_en_reg_v4}), | |
635 | .din ({mbist_run ,mbist_wb_array_wr_en ,mbist_addr[2:0], mbist_wb_array_rd_en, mbist_rdma_array_wr_en, | |
636 | mbist_rdma_array_rd_en}), | |
637 | .clk (l2clk), | |
638 | .en (1'b1), | |
639 | .se(se), | |
640 | .siclk(siclk), | |
641 | .soclk(soclk), | |
642 | .pce_ov(pce_ov), | |
643 | .stop(stop) | |
644 | ); | |
645 | ||
646 | ||
647 | ||
648 | // mux_macro mux_rdma_fnl_wren_v1 (width=1,mux=aonpe,ports=2,stack=2r,dmux=8x) | |
649 | // ( | |
650 | // .dout (mbist_wbarray_write_en_c8_v1), | |
651 | // .din0 (l2t_l2b_wbwr_wen_c8_v1), | |
652 | // .din1 (mbist_wb_array_wr_en_reg_v1), | |
653 | // .sel0 (mbist_run_reg_v1_n), | |
654 | // .sel1 (mbist_run_reg_v1) | |
655 | // ); | |
656 | // | |
657 | // | |
658 | //mux_macro mux_rdma_fnl_wren_v2 (width=1,mux=aonpe,ports=2,stack=2r,dmux=8x) | |
659 | // ( | |
660 | // .dout (mbist_wbarray_write_en_c8_v2), | |
661 | // .din0 (l2t_l2b_wbwr_wen_c8_v2), | |
662 | // .din1 (mbist_wb_array_wr_en_reg_v2), | |
663 | // .sel0 (mbist_run_reg_v2_n), | |
664 | // .sel1 (mbist_run_reg_v2) | |
665 | // ); | |
666 | // | |
667 | // | |
668 | //mux_macro mux_rdma_fnl_wren_v3 (width=1,mux=aonpe,ports=2,stack=2r,dmux=8x) | |
669 | // ( | |
670 | // .dout (mbist_wbarray_write_en_c8_v3), | |
671 | // .din0 (l2t_l2b_wbwr_wen_c8_v3), | |
672 | // .din1 (mbist_wb_array_wr_en_reg_v3), | |
673 | // .sel0 (mbist_run_reg_v3_n), | |
674 | // .sel1 (mbist_run_reg_v3) | |
675 | // ); | |
676 | // | |
677 | // mux_macro mux_rdma_fnl_wren_v4 (width=1,mux=aonpe,ports=2,stack=2r,dmux=8x) | |
678 | // ( | |
679 | // .dout (mbist_wbarray_write_en_c8_v4), | |
680 | // .din0 (l2t_l2b_wbwr_wen_c8_v4), | |
681 | // .din1 (mbist_wb_array_wr_en_reg_v4), | |
682 | // .sel0 (mbist_run_reg_v4_n), | |
683 | // .sel1 (mbist_run_reg_v4) | |
684 | // ); | |
685 | ||
686 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v1[2:0]), | |
687 | // .din0 (l2t_l2b_wbrd_wl_r1_v1[2:0]), | |
688 | // .din1 (mbist_addr_reg_v1[2:0]), | |
689 | ||
690 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v1[1:0]), | |
691 | // .din0 (l2t_l2b_rdma_rdwl_r1_v1[1:0]), | |
692 | // .din1 (mbist_addr_reg_v1[1:0]), | |
693 | ||
694 | // .dout (compute_evict_l2t_l2b_rdma_wrwl_s3_v1[1:0]), | |
695 | // .din0 (l2t_l2b_rdma_wrwl_s3_v1[1:0]), | |
696 | // .din1 (mbist_addr_reg_v1[1:0]), | |
697 | ||
698 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v1,evict_l2t_l2b_rdma_rden_r1_v1}), | |
699 | // .din0 ({l2t_l2b_wbrd_en_r1_v1,l2t_l2b_rdma_rden_r1_v1}), | |
700 | // .din1 ({mbist_wb_array_rd_en_reg_v1,mbist_rdma_array_rd_en_reg_v1}), | |
701 | ||
702 | ||
703 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14r__width_14 mux_mbist_v1 ( | |
704 | .dout ({mbist_wbarray_write_en_c8_v1, writeback_array_wr_en_v1[2:0],evict_l2t_l2b_wbrd_wl_r1_v1[2:0], | |
705 | evict_l2t_l2b_rdma_rdwl_r1_v1[1:0], compute_evict_l2t_l2b_rdma_wrwl_s3_v1[1:0] , | |
706 | evict_l2t_l2b_wbrd_en_r1_v1,evict_l2t_l2b_rdma_rden_r1_v1,evict_l2t_l2b_rdma_wren_s3_v1} ), | |
707 | .din0 ({l2t_l2b_wbwr_wen_c8_v1, l2t_l2b_wbwr_wl_c8_v1[2:0], l2t_l2b_wbrd_wl_r1_v1[2:0], | |
708 | l2t_l2b_rdma_rdwl_r1_v1[1:0], l2t_l2b_rdma_wrwl_s3_v1[1:0] , | |
709 | l2t_l2b_wbrd_en_r1_v1,l2t_l2b_rdma_rden_r1_v1,fnl_evict_l2t_l2b_rdma_wren_s3_v1} ), | |
710 | .din1 ({mbist_wb_array_wr_en_reg_v1, mbist_addr_reg_v1[2:0], mbist_addr_reg_v1[2:0], | |
711 | mbist_addr_reg_v1[1:0], mbist_addr_reg_v1[1:0], | |
712 | mbist_wb_array_rd_en_reg_v1,mbist_rdma_array_rd_en_reg_v1,mbist_rdma_array_wr_en_reg_v1} ), | |
713 | .sel0 (mbist_run_reg_v1_n), | |
714 | .sel1 (mbist_run_reg_v1) | |
715 | ); | |
716 | ||
717 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14r__width_14 mux_mbist_v2 ( | |
718 | .dout ({mbist_wbarray_write_en_c8_v2, writeback_array_wr_en_v2[2:0],evict_l2t_l2b_wbrd_wl_r1_v2[2:0], | |
719 | evict_l2t_l2b_rdma_rdwl_r1_v2[1:0], compute_evict_l2t_l2b_rdma_wrwl_s3_v2[1:0] , | |
720 | evict_l2t_l2b_wbrd_en_r1_v2,evict_l2t_l2b_rdma_rden_r1_v2,evict_l2t_l2b_rdma_wren_s3_v2} ), | |
721 | .din0 ({l2t_l2b_wbwr_wen_c8_v2, l2t_l2b_wbwr_wl_c8_v2[2:0], l2t_l2b_wbrd_wl_r1_v2[2:0], | |
722 | l2t_l2b_rdma_rdwl_r1_v2[1:0], l2t_l2b_rdma_wrwl_s3_v2[1:0] , | |
723 | l2t_l2b_wbrd_en_r1_v2,l2t_l2b_rdma_rden_r1_v2,fnl_evict_l2t_l2b_rdma_wren_s3_v2} ), | |
724 | .din1 ({mbist_wb_array_wr_en_reg_v2, mbist_addr_reg_v2[2:0], mbist_addr_reg_v2[2:0], | |
725 | mbist_addr_reg_v2[1:0], mbist_addr_reg_v2[1:0], | |
726 | mbist_wb_array_rd_en_reg_v2,mbist_rdma_array_rd_en_reg_v2,mbist_rdma_array_wr_en_reg_v2} ), | |
727 | .sel0 (mbist_run_reg_v2_n), | |
728 | .sel1 (mbist_run_reg_v2) | |
729 | ); | |
730 | ||
731 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14r__width_14 mux_mbist_v3 ( | |
732 | .dout ({mbist_wbarray_write_en_c8_v3, writeback_array_wr_en_v3[2:0],evict_l2t_l2b_wbrd_wl_r1_v3[2:0], | |
733 | evict_l2t_l2b_rdma_rdwl_r1_v3[1:0], compute_evict_l2t_l2b_rdma_wrwl_s3_v3[1:0] , | |
734 | evict_l2t_l2b_wbrd_en_r1_v3,evict_l2t_l2b_rdma_rden_r1_v3,evict_l2t_l2b_rdma_wren_s3_v3} ), | |
735 | .din0 ({l2t_l2b_wbwr_wen_c8_v3, l2t_l2b_wbwr_wl_c8_v3[2:0], l2t_l2b_wbrd_wl_r1_v3[2:0], | |
736 | l2t_l2b_rdma_rdwl_r1_v3[1:0], l2t_l2b_rdma_wrwl_s3_v3[1:0] , | |
737 | l2t_l2b_wbrd_en_r1_v3,l2t_l2b_rdma_rden_r1_v3,fnl_evict_l2t_l2b_rdma_wren_s3_v3} ), | |
738 | .din1 ({mbist_wb_array_wr_en_reg_v3, mbist_addr_reg_v3[2:0], mbist_addr_reg_v3[2:0], | |
739 | mbist_addr_reg_v3[1:0], mbist_addr_reg_v3[1:0], | |
740 | mbist_wb_array_rd_en_reg_v3,mbist_rdma_array_rd_en_reg_v3,mbist_rdma_array_wr_en_reg_v3} ), | |
741 | .sel0 (mbist_run_reg_v3_n), | |
742 | .sel1 (mbist_run_reg_v3) | |
743 | ); | |
744 | ||
745 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14r__width_14 mux_mbist_v4 ( | |
746 | .dout ({mbist_wbarray_write_en_c8_v4, writeback_array_wr_en_v4[2:0],evict_l2t_l2b_wbrd_wl_r1_v4[2:0], | |
747 | evict_l2t_l2b_rdma_rdwl_r1_v4[1:0], compute_evict_l2t_l2b_rdma_wrwl_s3_v4[1:0] , | |
748 | evict_l2t_l2b_wbrd_en_r1_v4,evict_l2t_l2b_rdma_rden_r1_v4,evict_l2t_l2b_rdma_wren_s3_v4} ), | |
749 | .din0 ({l2t_l2b_wbwr_wen_c8_v4, l2t_l2b_wbwr_wl_c8_v4[2:0], l2t_l2b_wbrd_wl_r1_v4[2:0], | |
750 | l2t_l2b_rdma_rdwl_r1_v4[1:0], l2t_l2b_rdma_wrwl_s3_v4[1:0] , | |
751 | l2t_l2b_wbrd_en_r1_v4,l2t_l2b_rdma_rden_r1_v4,fnl_evict_l2t_l2b_rdma_wren_s3_v4} ), | |
752 | .din1 ({mbist_wb_array_wr_en_reg_v4, mbist_addr_reg_v4[2:0], mbist_addr_reg_v4[2:0], | |
753 | mbist_addr_reg_v4[1:0], mbist_addr_reg_v4[1:0], | |
754 | mbist_wb_array_rd_en_reg_v4,mbist_rdma_array_rd_en_reg_v4,mbist_rdma_array_wr_en_reg_v4} ), | |
755 | .sel0 (mbist_run_reg_v4_n), | |
756 | .sel1 (mbist_run_reg_v4) | |
757 | ); | |
758 | ||
759 | l2b_evict_dp_buff_macro__width_1 l2t_l2b_wbwr_wen_c8_v1_slice | |
760 | ( | |
761 | .din ( mbist_wbarray_write_en_c8_v1 ), | |
762 | .dout( evict_l2t_l2b_wbwr_wen_c8_v1) | |
763 | ); | |
764 | ||
765 | l2b_evict_dp_buff_macro__width_1 l2t_l2b_wbwr_wen_c8_v2_slice | |
766 | ( | |
767 | .din ( mbist_wbarray_write_en_c8_v2 ), | |
768 | .dout( evict_l2t_l2b_wbwr_wen_c8_v2) | |
769 | ); | |
770 | ||
771 | l2b_evict_dp_buff_macro__width_1 l2t_l2b_wbwr_wen_c8_v3_slice | |
772 | ( | |
773 | .din ( mbist_wbarray_write_en_c8_v3 ), | |
774 | .dout( evict_l2t_l2b_wbwr_wen_c8_v3) | |
775 | ); | |
776 | ||
777 | l2b_evict_dp_buff_macro__width_1 l2t_l2b_wbwr_wen_c8_v4_slice | |
778 | ( | |
779 | .din ( mbist_wbarray_write_en_c8_v4 ), | |
780 | .dout( evict_l2t_l2b_wbwr_wen_c8_v4) | |
781 | ); | |
782 | ||
783 | // mux_macro mux_writeback_array_wr_en_v1 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
784 | // ( | |
785 | // .dout (writeback_array_wr_en_v1[2:0]), | |
786 | // .din0 (mbist_addr_reg_v1[2:0]), | |
787 | // .din1 (l2t_l2b_wbwr_wl_c8_v1[2:0]), | |
788 | // .sel0 (mbist_run_reg_v1), | |
789 | // .sel1 (mbist_run_reg_v1_n) | |
790 | // ); | |
791 | // | |
792 | // | |
793 | //mux_macro mux_writeback_array_wr_en_v2 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
794 | // ( | |
795 | // .dout (writeback_array_wr_en_v2[2:0]), | |
796 | // .din0 (mbist_addr_reg_v2[2:0]), | |
797 | // .din1 (l2t_l2b_wbwr_wl_c8_v2[2:0]), | |
798 | // .sel0 (mbist_run_reg_v2), | |
799 | // .sel1 (mbist_run_reg_v2_n) | |
800 | // ); | |
801 | // | |
802 | // | |
803 | //mux_macro mux_writeback_array_wr_en_v3 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
804 | // ( | |
805 | // .dout (writeback_array_wr_en_v3[2:0]), | |
806 | // .din0 (mbist_addr_reg_v3[2:0]), | |
807 | // .din1 (l2t_l2b_wbwr_wl_c8_v3[2:0]), | |
808 | // .sel0 (mbist_run_reg_v3), | |
809 | // .sel1 (mbist_run_reg_v3_n) | |
810 | // ); | |
811 | // | |
812 | // | |
813 | // mux_macro mux_writeback_array_wr_en_v4 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
814 | // ( | |
815 | // .dout (writeback_array_wr_en_v4[2:0]), | |
816 | // .din0 (mbist_addr_reg_v4[2:0]), | |
817 | // .din1 (l2t_l2b_wbwr_wl_c8_v4[2:0]), | |
818 | // .sel0 (mbist_run_reg_v4), | |
819 | // .sel1 (mbist_run_reg_v4_n) | |
820 | // ); | |
821 | ||
822 | ||
823 | l2b_evict_dp_buff_macro__width_3 evict_l2t_l2b_wbwr_wl_c8_v1_slice | |
824 | ( | |
825 | .din (writeback_array_wr_en_v1[2:0]), | |
826 | .dout (evict_l2t_l2b_wbwr_wl_c8_v1[2:0]) | |
827 | ); | |
828 | ||
829 | l2b_evict_dp_buff_macro__width_3 evict_l2t_l2b_wbwr_wl_c8_v2_slice | |
830 | ( | |
831 | .din (writeback_array_wr_en_v2[2:0]), | |
832 | .dout (evict_l2t_l2b_wbwr_wl_c8_v2[2:0]) | |
833 | ); | |
834 | ||
835 | ||
836 | l2b_evict_dp_buff_macro__width_3 evict_l2t_l2b_wbwr_wl_c8_v3_slice | |
837 | ( | |
838 | .din (writeback_array_wr_en_v3[2:0]), | |
839 | .dout (evict_l2t_l2b_wbwr_wl_c8_v3[2:0]) | |
840 | ); | |
841 | ||
842 | ||
843 | l2b_evict_dp_buff_macro__width_3 evict_l2t_l2b_wbwr_wl_c8_v4_slice | |
844 | ( | |
845 | .din (writeback_array_wr_en_v4[2:0]), | |
846 | .dout (evict_l2t_l2b_wbwr_wl_c8_v4[2:0]) | |
847 | ); | |
848 | ||
849 | //msff_macro ff_l2t_l2b_wbrd_wl_r1 (width=3) | |
850 | // (.dout (l2t_l2b_wbrd_wl_r1[2:0]), | |
851 | // .din (l2t_l2b_wbrd_wl_r0[2:0]), | |
852 | // .clk (l2clk), | |
853 | // .en (1'b1), .scan_in (), .scan_out () | |
854 | // ) ; | |
855 | ||
856 | ||
857 | //or_macro or_evict_l2t_l2b_wbrd_wl_r1_v1 (width=3) | |
858 | // ( | |
859 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v1[2:0]), | |
860 | // .din0 (l2t_l2b_wbrd_wl_r1[2:0]), | |
861 | // .din1 (mbist_addr_reg[2:0]) | |
862 | // ); | |
863 | // | |
864 | //or_macro or_evict_l2t_l2b_wbrd_wl_r1_v2 (width=3) | |
865 | // ( | |
866 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v2[2:0]), | |
867 | // .din0 (l2t_l2b_wbrd_wl_r1[2:0]), | |
868 | // .din1 (mbist_addr_reg[2:0]) | |
869 | // ); | |
870 | //or_macro or_evict_l2t_l2b_wbrd_wl_r1_v3 (width=3) | |
871 | // ( | |
872 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v3[2:0]), | |
873 | // .din0 (l2t_l2b_wbrd_wl_r1[2:0]), | |
874 | // .din1 (mbist_addr_reg[2:0]) | |
875 | // ); | |
876 | //or_macro or_evict_l2t_l2b_wbrd_wl_r1_v4 (width=3) | |
877 | // ( | |
878 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v4[2:0]), | |
879 | // .din0 (l2t_l2b_wbrd_wl_r1[2:0]), | |
880 | // .din1 (mbist_addr_reg[2:0]) | |
881 | // ); | |
882 | // | |
883 | //or_macro or_evict_l2t_l2b_rdma_rdwl_r1_v1 (width=2) | |
884 | // ( | |
885 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v1[1:0]), | |
886 | // .din0 (l2t_l2b_rdma_rdwl_r1[1:0]), | |
887 | // .din1 (mbist_addr_reg[1:0]) | |
888 | // ); | |
889 | // | |
890 | //or_macro or_evict_l2t_l2b_rdma_rdwl_r1_v2 (width=2) | |
891 | // ( | |
892 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v2[1:0]), | |
893 | // .din0 (l2t_l2b_rdma_rdwl_r1[1:0]), | |
894 | // .din1 (mbist_addr_reg[1:0]) | |
895 | // ); | |
896 | //or_macro or_evict_l2t_l2b_rdma_rdwl_r1_v3 (width=2) | |
897 | // ( | |
898 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v3[1:0]), | |
899 | // .din0 (l2t_l2b_rdma_rdwl_r1[1:0]), | |
900 | // .din1 (mbist_addr_reg[1:0]) | |
901 | // ); | |
902 | //or_macro or_evict_l2t_l2b_rdma_rdwl_r1_v4 (width=2) | |
903 | // ( | |
904 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v4[1:0]), | |
905 | // .din0 (l2t_l2b_rdma_rdwl_r1[1:0]), | |
906 | // .din1 (mbist_addr_reg[1:0]) | |
907 | // ); | |
908 | ||
909 | ||
910 | // mux_macro mux_evict_l2t_l2b_wbrd_wl_r1_v1 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
911 | // ( | |
912 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v1[2:0]), | |
913 | // .din0 (l2t_l2b_wbrd_wl_r1_v1[2:0]), | |
914 | // .din1 (mbist_addr_reg_v1[2:0]), | |
915 | // .sel0 (mbist_run_reg_v1_n), | |
916 | // .sel1 (mbist_run_reg_v1) | |
917 | // ); | |
918 | ||
919 | //mux_macro mux_evict_l2t_l2b_wbrd_wl_r1_v2 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
920 | // ( | |
921 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v2[2:0]), | |
922 | // .din0 (l2t_l2b_wbrd_wl_r1_v2[2:0]), | |
923 | // .din1 (mbist_addr_reg_v2[2:0]), | |
924 | // .sel0 (mbist_run_reg_v2_n), | |
925 | // .sel1 (mbist_run_reg_v2) | |
926 | // ); | |
927 | //mux_macro mux_evict_l2t_l2b_wbrd_wl_r1_v3 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
928 | // ( | |
929 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v3[2:0]), | |
930 | // .din0 (l2t_l2b_wbrd_wl_r1_v3[2:0]), | |
931 | // .din1 (mbist_addr_reg_v3[2:0]), | |
932 | // .sel0 (mbist_run_reg_v3_n), | |
933 | // .sel1 (mbist_run_reg_v3) | |
934 | // ); | |
935 | // mux_macro mux_evict_l2t_l2b_wbrd_wl_r1_v4 (width=3,mux=aonpe,ports=2,dmux=8x,stack=4c) | |
936 | // ( | |
937 | // .dout (evict_l2t_l2b_wbrd_wl_r1_v4[2:0]), | |
938 | // .din0 (l2t_l2b_wbrd_wl_r1_v4[2:0]), | |
939 | // .din1 (mbist_addr_reg_v4[2:0]), | |
940 | // .sel0 (mbist_run_reg_v4_n), | |
941 | // .sel1 (mbist_run_reg_v4) | |
942 | // ); | |
943 | // | |
944 | // mux_macro mux_evict_l2t_l2b_rdma_rdwl_r1_v1 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
945 | // ( | |
946 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v1[1:0]), | |
947 | // .din0 (l2t_l2b_rdma_rdwl_r1_v1[1:0]), | |
948 | // .din1 (mbist_addr_reg_v1[1:0]), | |
949 | // .sel0 (mbist_run_reg_v1_n), | |
950 | // .sel1 (mbist_run_reg_v1) | |
951 | // ); | |
952 | // | |
953 | //mux_macro mux_evict_l2t_l2b_rdma_rdwl_r1_v2 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
954 | // ( | |
955 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v2[1:0]), | |
956 | // .din0 (l2t_l2b_rdma_rdwl_r1_v2[1:0]), | |
957 | // .din1 (mbist_addr_reg_v2[1:0]), | |
958 | // .sel0 (mbist_run_reg_v2_n), | |
959 | // .sel1 (mbist_run_reg_v2) | |
960 | // ); | |
961 | //mux_macro mux_evict_l2t_l2b_rdma_rdwl_r1_v3 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
962 | // ( | |
963 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v3[1:0]), | |
964 | // .din0 (l2t_l2b_rdma_rdwl_r1_v3[1:0]), | |
965 | // .din1 (mbist_addr_reg_v3[1:0]), | |
966 | // .sel0 (mbist_run_reg_v3_n), | |
967 | // .sel1 (mbist_run_reg_v3) | |
968 | // ); | |
969 | //mux_macro mux_evict_l2t_l2b_rdma_rdwl_r1_v4 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
970 | // ( | |
971 | // .dout (evict_l2t_l2b_rdma_rdwl_r1_v4[1:0]), | |
972 | // .din0 (l2t_l2b_rdma_rdwl_r1_v4[1:0]), | |
973 | // .din1 (mbist_addr_reg_v4[1:0]), | |
974 | // .sel0 (mbist_run_reg_v4_n), | |
975 | // .sel1 (mbist_run_reg_v4) | |
976 | // ); | |
977 | // | |
978 | ||
979 | ||
980 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_6_or_4_slice | |
981 | ( | |
982 | .dout (evict_l2t_l2b_rdma_wren_s3_6_or_4), | |
983 | .din0 (evict_l2t_l2b_rdma_wren_s3[6]), | |
984 | .din1 (evict_l2t_l2b_rdma_wren_s3[4]) | |
985 | ); | |
986 | ||
987 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_0_or_2_slice | |
988 | ( | |
989 | .dout (evict_l2t_l2b_rdma_wren_s3_0_or_2), | |
990 | .din0 (evict_l2t_l2b_rdma_wren_s3[2]), | |
991 | .din1 (evict_l2t_l2b_rdma_wren_s3[0]) | |
992 | ); | |
993 | ||
994 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_v4_slice | |
995 | ( | |
996 | .dout (fnl_evict_l2t_l2b_rdma_wren_s3_v4), | |
997 | .din0 (evict_l2t_l2b_rdma_wren_s3_6_or_4), | |
998 | .din1 (evict_l2t_l2b_rdma_wren_s3_0_or_2) | |
999 | ); | |
1000 | ||
1001 | ||
1002 | //// Have not changed it yet. | |
1003 | // mux_macro mux_evict_l2t_l2b_rdma_wren_s3_v1_v2_v3_v4 (width=4,mux=aonpe,ports=2,dmux=8x, stack=4c) | |
1004 | // ( | |
1005 | // .dout ({evict_l2t_l2b_rdma_wren_s3_v4,evict_l2t_l2b_rdma_wren_s3_v3, | |
1006 | // evict_l2t_l2b_rdma_wren_s3_v2,evict_l2t_l2b_rdma_wren_s3_v1}), | |
1007 | // .din0 ({fnl_evict_l2t_l2b_rdma_wren_s3_v4,fnl_evict_l2t_l2b_rdma_wren_s3_v3, | |
1008 | // fnl_evict_l2t_l2b_rdma_wren_s3_v2,fnl_evict_l2t_l2b_rdma_wren_s3_v1}), | |
1009 | // .din1 ({4{mbist_rdma_array_wr_en_reg}}), | |
1010 | // .sel0 (mbist_run_reg_n), | |
1011 | // .sel1 (mbist_run_reg) | |
1012 | // ); | |
1013 | ||
1014 | ||
1015 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_1_or_3_slice | |
1016 | ( | |
1017 | .dout (evict_l2t_l2b_rdma_wren_s3_1_or_3), | |
1018 | .din0 (evict_l2t_l2b_rdma_wren_s3[1]), | |
1019 | .din1 (evict_l2t_l2b_rdma_wren_s3[3]) | |
1020 | ); | |
1021 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_5_or_7_slice | |
1022 | ( | |
1023 | .dout (evict_l2t_l2b_rdma_wren_s3_5_or_7), | |
1024 | .din0 (evict_l2t_l2b_rdma_wren_s3[5]), | |
1025 | .din1 (evict_l2t_l2b_rdma_wren_s3[7]) | |
1026 | ); | |
1027 | ||
1028 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_v3_slice | |
1029 | ( | |
1030 | .dout (fnl_evict_l2t_l2b_rdma_wren_s3_v3), | |
1031 | .din0 (evict_l2t_l2b_rdma_wren_s3_5_or_7), | |
1032 | .din1 (evict_l2t_l2b_rdma_wren_s3_1_or_3) | |
1033 | ); | |
1034 | ||
1035 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_8_or_14_slice | |
1036 | ( | |
1037 | .dout (evict_l2t_l2b_rdma_wren_s3_8_or_14), | |
1038 | .din0 (evict_l2t_l2b_rdma_wren_s3[8]), | |
1039 | .din1 (evict_l2t_l2b_rdma_wren_s3[14]) | |
1040 | ); | |
1041 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_10_or_12_slice | |
1042 | ( | |
1043 | .dout (evict_l2t_l2b_rdma_wren_s3_10_or_12), | |
1044 | .din0 (evict_l2t_l2b_rdma_wren_s3[12]), | |
1045 | .din1 (evict_l2t_l2b_rdma_wren_s3[10]) | |
1046 | ); | |
1047 | ||
1048 | l2b_evict_dp_or_macro__ports_2__width_1 evict_l2t_l2b_rdma_wren_s2_v4_slice | |
1049 | ( | |
1050 | .dout (fnl_evict_l2t_l2b_rdma_wren_s3_v2), | |
1051 | .din0 (evict_l2t_l2b_rdma_wren_s3_10_or_12), | |
1052 | .din1 (evict_l2t_l2b_rdma_wren_s3_8_or_14) | |
1053 | ); | |
1054 | ||
1055 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_15_or_13_slice | |
1056 | ( | |
1057 | .dout (evict_l2t_l2b_rdma_wren_s3_15_or_13), | |
1058 | .din0 (evict_l2t_l2b_rdma_wren_s3[15]), | |
1059 | .din1 (evict_l2t_l2b_rdma_wren_s3[13]) | |
1060 | ); | |
1061 | l2b_evict_dp_or_macro__width_1 evict_l2t_l2b_rdma_wren_s3_11_or_9_slice | |
1062 | ( | |
1063 | .dout (evict_l2t_l2b_rdma_wren_s3_11_or_9), | |
1064 | .din0 (evict_l2t_l2b_rdma_wren_s3[9]), | |
1065 | .din1 (evict_l2t_l2b_rdma_wren_s3[11]) | |
1066 | ); | |
1067 | ||
1068 | l2b_evict_dp_or_macro__ports_2__width_1 evict_l2t_l2b_rdma_wren_s3_v1_slice | |
1069 | ( | |
1070 | .dout (fnl_evict_l2t_l2b_rdma_wren_s3_v1), | |
1071 | .din0 (evict_l2t_l2b_rdma_wren_s3_11_or_9), | |
1072 | .din1 (evict_l2t_l2b_rdma_wren_s3_15_or_13) | |
1073 | ); | |
1074 | ||
1075 | //or_macro or_evict_l2t_l2b_rdma_wrwl_s3_v1 (width=2) | |
1076 | // ( | |
1077 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v1[1:0]), | |
1078 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1079 | // .din1 (mbist_addr_reg[1:0]) | |
1080 | // ); | |
1081 | //or_macro or_evict_l2t_l2b_rdma_wrwl_s3_v2 (width=2) | |
1082 | // ( | |
1083 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v2[1:0]), | |
1084 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1085 | // .din1 (mbist_addr_reg[1:0]) | |
1086 | // ); | |
1087 | //or_macro or_evict_l2t_l2b_rdma_wrwl_s3_v3 (width=2) | |
1088 | // ( | |
1089 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v3[1:0]), | |
1090 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1091 | // .din1 (mbist_addr_reg[1:0]) | |
1092 | // ); | |
1093 | ////or_macro or_evict_l2t_l2b_rdma_wrwl_s3_v4 (width=2) | |
1094 | // ( | |
1095 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v4[1:0]), | |
1096 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1097 | // .din1 (mbist_addr_reg[1:0]) | |
1098 | // ); | |
1099 | /// CHANGE | |
1100 | ||
1101 | //mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v1 (width=2,mux=aonpe,ports=2,dmux=8x) | |
1102 | // ( | |
1103 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v1[1:0]), | |
1104 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1105 | // .din1 (mbist_addr_reg[1:0]), | |
1106 | // .sel0 (mbist_run_reg_n), | |
1107 | // .sel1 (mbist_run_reg) | |
1108 | // ); | |
1109 | //mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v2 (width=2,mux=aonpe,ports=2,dmux=8x) | |
1110 | // ( | |
1111 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v2[1:0]), | |
1112 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1113 | // .din1 (mbist_addr_reg[1:0]), | |
1114 | // .sel0 (mbist_run_reg_n), | |
1115 | // .sel1 (mbist_run_reg) | |
1116 | // ); | |
1117 | //mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v3 (width=2,mux=aonpe,ports=2,dmux=8x) | |
1118 | // ( | |
1119 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v3[1:0]), | |
1120 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1121 | // .din1 (mbist_addr_reg[1:0]), | |
1122 | // .sel0 (mbist_run_reg_n), | |
1123 | // .sel1 (mbist_run_reg) | |
1124 | // ); | |
1125 | //mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v4 (width=2,mux=aonpe,ports=2,dmux=8x) | |
1126 | // ( | |
1127 | // .dout (evict_l2t_l2b_rdma_wrwl_s3_v4[1:0]), | |
1128 | // .din0 (l2t_l2b_rdma_wrwl_s3[1:0]), | |
1129 | // .din1 (mbist_addr_reg[1:0]), | |
1130 | // .sel0 (mbist_run_reg_n), | |
1131 | // .sel1 (mbist_run_reg) | |
1132 | // ); | |
1133 | ||
1134 | // mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v1 (width=2,mux=aonpe,ports=2,dmux=8x, stack=2c) | |
1135 | // ( | |
1136 | // .dout (compute_evict_l2t_l2b_rdma_wrwl_s3_v1[1:0]), | |
1137 | // .din0 (l2t_l2b_rdma_wrwl_s3_v1[1:0]), | |
1138 | // .din1 (mbist_addr_reg_v1[1:0]), | |
1139 | // .sel0 (mbist_run_reg_v1_n), | |
1140 | // .sel1 (mbist_run_reg_v1) | |
1141 | // ); | |
1142 | // | |
1143 | // | |
1144 | //mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v2 (width=2,mux=aonpe,ports=2,dmux=8x, stack=2c) | |
1145 | // ( | |
1146 | // .dout (compute_evict_l2t_l2b_rdma_wrwl_s3_v2[1:0]), | |
1147 | // .din0 (l2t_l2b_rdma_wrwl_s3_v2[1:0]), | |
1148 | // .din1 (mbist_addr_reg_v2[1:0]), | |
1149 | // .sel0 (mbist_run_reg_v2_n), | |
1150 | // .sel1 (mbist_run_reg_v2) | |
1151 | // ); | |
1152 | // | |
1153 | // | |
1154 | //mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v3 (width=2,mux=aonpe,ports=2,dmux=8x, stack=2c) | |
1155 | // ( | |
1156 | // .dout (compute_evict_l2t_l2b_rdma_wrwl_s3_v3[1:0]), | |
1157 | // .din0 (l2t_l2b_rdma_wrwl_s3_v3[1:0]), | |
1158 | // .din1 (mbist_addr_reg_v3[1:0]), | |
1159 | // .sel0 (mbist_run_reg_v3_n), | |
1160 | // .sel1 (mbist_run_reg_v3) | |
1161 | // ); | |
1162 | // | |
1163 | // | |
1164 | //mux_macro mux_evict_l2t_l2b_rdma_wrwl_s3_v4 (width=2,mux=aonpe,ports=2,dmux=8x, stack=2c) | |
1165 | // ( | |
1166 | // .dout (compute_evict_l2t_l2b_rdma_wrwl_s3_v4[1:0]), | |
1167 | // .din0 (l2t_l2b_rdma_wrwl_s3_v4[1:0]), | |
1168 | // .din1 (mbist_addr_reg_v4[1:0]), | |
1169 | // .sel0 (mbist_run_reg_v4_n), | |
1170 | // .sel1 (mbist_run_reg_v4) | |
1171 | // ); | |
1172 | // | |
1173 | // | |
1174 | assign evict_l2t_l2b_rdma_wrwl_s3_v1[1:0] = compute_evict_l2t_l2b_rdma_wrwl_s3_v1[1:0]; | |
1175 | assign evict_l2t_l2b_rdma_wrwl_s3_v2[1:0] = compute_evict_l2t_l2b_rdma_wrwl_s3_v2[1:0]; | |
1176 | assign evict_l2t_l2b_rdma_wrwl_s3_v3[1:0] = compute_evict_l2t_l2b_rdma_wrwl_s3_v3[1:0]; | |
1177 | assign evict_l2t_l2b_rdma_wrwl_s3_v4[1:0] = compute_evict_l2t_l2b_rdma_wrwl_s3_v4[1:0]; | |
1178 | ||
1179 | ||
1180 | ||
1181 | /// CHANGE | |
1182 | //////////////////////////////////////////////////////////////////////////////// | |
1183 | ||
1184 | ||
1185 | //or_macro or_evict_wb_and_rdma_rd_en_r1v1 (width=2) | |
1186 | // ( | |
1187 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v1,evict_l2t_l2b_rdma_rden_r1_v1}), | |
1188 | // .din0 ({l2t_l2b_wbrd_en_r1,l2t_l2b_rdma_rden_r1}), | |
1189 | // .din1 ({mbist_wb_array_rd_en_reg,mbist_rdma_array_rd_en_reg}) | |
1190 | // ); | |
1191 | // | |
1192 | //or_macro or_evict_wb_and_rdma_rd_en_r1v2 (width=2) | |
1193 | // ( | |
1194 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v2,evict_l2t_l2b_rdma_rden_r1_v2}), | |
1195 | // .din0 ({l2t_l2b_wbrd_en_r1,l2t_l2b_rdma_rden_r1}), | |
1196 | // .din1 ({mbist_wb_array_rd_en_reg,mbist_rdma_array_rd_en_reg}) | |
1197 | // ); | |
1198 | //or_macro or_evict_wb_and_rdma_rd_en_r1v3 (width=2) | |
1199 | // ( | |
1200 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v3,evict_l2t_l2b_rdma_rden_r1_v3}), | |
1201 | // .din0 ({l2t_l2b_wbrd_en_r1,l2t_l2b_rdma_rden_r1}), | |
1202 | // .din1 ({mbist_wb_array_rd_en_reg,mbist_rdma_array_rd_en_reg}) | |
1203 | // ); | |
1204 | //or_macro or_evict_wb_and_rdma_rd_en_r1v4 (width=2) | |
1205 | // ( | |
1206 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v4,evict_l2t_l2b_rdma_rden_r1_v4}), | |
1207 | // .din0 ({l2t_l2b_wbrd_en_r1,l2t_l2b_rdma_rden_r1}), | |
1208 | // .din1 ({mbist_wb_array_rd_en_reg,mbist_rdma_array_rd_en_reg}) | |
1209 | // ); | |
1210 | // | |
1211 | ||
1212 | // mux_macro mux_evict_wb_and_rdma_rd_en_r1v1 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
1213 | // ( | |
1214 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v1,evict_l2t_l2b_rdma_rden_r1_v1}), | |
1215 | // .din0 ({l2t_l2b_wbrd_en_r1_v1,l2t_l2b_rdma_rden_r1_v1}), | |
1216 | // .din1 ({mbist_wb_array_rd_en_reg_v1,mbist_rdma_array_rd_en_reg_v1}), | |
1217 | // .sel0 (mbist_run_reg_v1_n), | |
1218 | // .sel1 (mbist_run_reg_v1) | |
1219 | // ); | |
1220 | // | |
1221 | //mux_macro mux_evict_wb_and_rdma_rd_en_r1v2 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
1222 | // ( | |
1223 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v2,evict_l2t_l2b_rdma_rden_r1_v2}), | |
1224 | // .din0 ({l2t_l2b_wbrd_en_r1_v2,l2t_l2b_rdma_rden_r1_v2}), | |
1225 | // .din1 ({mbist_wb_array_rd_en_reg_v2,mbist_rdma_array_rd_en_reg_v2}), | |
1226 | // .sel0 (mbist_run_reg_v2_n), | |
1227 | // .sel1 (mbist_run_reg_v2) | |
1228 | // ); | |
1229 | //mux_macro mux_evict_wb_and_rdma_rd_en_r1v3 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
1230 | // ( | |
1231 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v3,evict_l2t_l2b_rdma_rden_r1_v3}), | |
1232 | // .din0 ({l2t_l2b_wbrd_en_r1_v3,l2t_l2b_rdma_rden_r1_v3}), | |
1233 | // .din1 ({mbist_wb_array_rd_en_reg_v3,mbist_rdma_array_rd_en_reg_v3}), | |
1234 | // .sel0 (mbist_run_reg_v3_n), | |
1235 | // .sel1 (mbist_run_reg_v3) | |
1236 | // ); | |
1237 | //mux_macro mux_evict_wb_and_rdma_rd_en_r1v4 (width=2,mux=aonpe,ports=2,dmux=8x,stack=2c) | |
1238 | // ( | |
1239 | // .dout ({evict_l2t_l2b_wbrd_en_r1_v4,evict_l2t_l2b_rdma_rden_r1_v4}), | |
1240 | // .din0 ({l2t_l2b_wbrd_en_r1_v4,l2t_l2b_rdma_rden_r1_v4}), | |
1241 | // .din1 ({mbist_wb_array_rd_en_reg_v4,mbist_rdma_array_rd_en_reg_v4}), | |
1242 | // .sel0 (mbist_run_reg_v4_n), | |
1243 | // .sel1 (mbist_run_reg_v4) | |
1244 | // ); | |
1245 | // | |
1246 | // | |
1247 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c__width_1 mux_wbrd_en_r1_in // int 5.0 changes | |
1248 | ( | |
1249 | .dout (l2t_l2b_wbrd_en_r1_in), | |
1250 | .din0 (l2t_l2b_wbrd_en_r1), | |
1251 | // .din1 (l2t_l2b_wbrd_en_r2), | |
1252 | .din1 (mbist_sel_wb_arrays_reg), | |
1253 | .sel0 (mbist_run_reg_n), | |
1254 | .sel1 (mbist_run_reg) | |
1255 | ); | |
1256 | ||
1257 | ||
1258 | l2b_evict_dp_and_macro__width_1 error_qual_and_l2t_l2b_evict_en_r3_slice | |
1259 | ( | |
1260 | .dout (error_qual_and_l2t_l2b_evict_en_r3), | |
1261 | .din0 (error_qual), | |
1262 | .din1 (l2t_l2b_evict_en_r3) | |
1263 | ); | |
1264 | ||
1265 | l2b_evict_dp_or_macro__width_1 error_qual_in_sloce | |
1266 | ( | |
1267 | .dout (error_qual_in), | |
1268 | .din0 (l2t_l2b_rdma_rden_r3), | |
1269 | .din1 (error_qual_and_l2t_l2b_evict_en_r3) | |
1270 | ); | |
1271 | ||
1272 | l2b_evict_dp_and_macro__width_1 ff_array_rd_ptr_and_slice | |
1273 | ( | |
1274 | .dout (ff_array_rd_ptr_din), | |
1275 | .din0 (dbb_rst_l), | |
1276 | .din1 (error_qual_in) | |
1277 | ); | |
1278 | ||
1279 | ||
1280 | /////////////////////////////////////////////////////////////////////////////// | |
1281 | // assign wb_or_rdma_rden_r2 = l2t_l2b_wbrd_en_r2 | l2t_l2b_rdma_rden_r2 ; | |
1282 | ||
1283 | l2b_evict_dp_or_macro__width_1 wb_or_rdma_rden_r2_slice1 // int 5.0 changes | |
1284 | ( | |
1285 | .dout (wb_or_rdma_rden_r2_1), | |
1286 | .din0 (l2t_l2b_rdma_rden_r2), | |
1287 | .din1 (l2t_l2b_wbrd_en_r2) | |
1288 | ); | |
1289 | ||
1290 | // | |
1291 | //and_macro wb_or_rdma_rden_r2_slice (width=1) // int 5.0 changes | |
1292 | // ( | |
1293 | // .din0 (wb_or_rdma_rden_r2_1), | |
1294 | // .din1 (sehold_n), | |
1295 | // .dout (wb_or_rdma_rden_r2) | |
1296 | // ); | |
1297 | // | |
1298 | ||
1299 | l2b_evict_dp_nand_macro__dnand_32x__ports_2__width_3 nand_mux_wb_or_rdma_rden_r2_slice | |
1300 | ( | |
1301 | .dout ({wb_or_rdma_rden_r2_sega,wb_or_rdma_rden_r2_segb,wb_or_rdma_rden_r2}), | |
1302 | .din0 ({wb_or_rdma_rden_r2_1,1'b1,wb_or_rdma_rden_r2_sega}), | |
1303 | .din1 ({mbist_run_reg_n,mbist_run_reg,wb_or_rdma_rden_r2_segb}) | |
1304 | ); | |
1305 | ||
1306 | ||
1307 | //mux_macro mux_wb_or_rdma_rden_r2_slice (width=1,ports=2,mux=pgnpe,stack=2c,dmux=32x) | |
1308 | // ( | |
1309 | // .dout (wb_or_rdma_rden_r2), | |
1310 | // .din0 (wb_or_rdma_rden_r2_1), | |
1311 | // .din1 (1'b1), | |
1312 | // .sel0 (mbist_run_reg_n), | |
1313 | // .sel1 (mbist_run_reg) | |
1314 | // ); | |
1315 | ||
1316 | l2b_evict_dp_inv_macro__width_1 l2t_l2b_wbrd_en_r2_inv_slice | |
1317 | ( | |
1318 | .dout (l2t_l2b_wbrd_en_r2_n ), | |
1319 | .din (l2t_l2b_wbrd_en_r2 ) | |
1320 | ); | |
1321 | ||
1322 | ||
1323 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out1a | |
1324 | ( | |
1325 | .dout (wb_rdma_mux_out[38:0]), | |
1326 | .din0 (wb_array_dout[38:0]), | |
1327 | .din1 (rdma_array_dout[38:0]), | |
1328 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1329 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1330 | ); | |
1331 | ||
1332 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out1b | |
1333 | ( | |
1334 | .dout (wb_rdma_mux_out[77:39]), | |
1335 | .din0 (wb_array_dout[77:39]), | |
1336 | .din1 (rdma_array_dout[77:39]), | |
1337 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1338 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1339 | ); | |
1340 | ||
1341 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out1c | |
1342 | ( | |
1343 | .dout (wb_rdma_mux_out[116:78]), | |
1344 | .din0 (wb_array_dout[116:78]), | |
1345 | .din1 (rdma_array_dout[116:78]), | |
1346 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1347 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1348 | ); | |
1349 | ||
1350 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out1d | |
1351 | ( | |
1352 | .dout (wb_rdma_mux_out[155:117]), | |
1353 | .din0 (wb_array_dout[155:117]), | |
1354 | .din1 (rdma_array_dout[155:117]), | |
1355 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1356 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1357 | ); | |
1358 | ||
1359 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out2a | |
1360 | ( | |
1361 | .dout (wb_rdma_mux_out[194:156]), | |
1362 | .din0 (wb_array_dout[194:156]), | |
1363 | .din1 (rdma_array_dout[194:156]), | |
1364 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1365 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1366 | ); | |
1367 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out2b | |
1368 | ( | |
1369 | .dout (wb_rdma_mux_out[233:195]), | |
1370 | .din0 (wb_array_dout[233:195]), | |
1371 | .din1 (rdma_array_dout[233:195]), | |
1372 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1373 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1374 | ); | |
1375 | ||
1376 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out2c | |
1377 | ( | |
1378 | .dout (wb_rdma_mux_out[272:234]), | |
1379 | .din0 (wb_array_dout[272:234]), | |
1380 | .din1 (rdma_array_dout[272:234]), | |
1381 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1382 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1383 | ); | |
1384 | ||
1385 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out2d | |
1386 | ( | |
1387 | .dout (wb_rdma_mux_out[311:273]), | |
1388 | .din0 (wb_array_dout[311:273]), | |
1389 | .din1 (rdma_array_dout[311:273]), | |
1390 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1391 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1392 | ); | |
1393 | ||
1394 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out3a | |
1395 | ( | |
1396 | .dout (wb_rdma_mux_out[350:312]), | |
1397 | .din0 (wb_array_dout[350:312]), | |
1398 | .din1 (rdma_array_dout[350:312]), | |
1399 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1400 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1401 | ); | |
1402 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out3b | |
1403 | ( | |
1404 | .dout (wb_rdma_mux_out[389:351]), | |
1405 | .din0 (wb_array_dout[389:351]), | |
1406 | .din1 (rdma_array_dout[389:351]), | |
1407 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1408 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1409 | ); | |
1410 | ||
1411 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out3c | |
1412 | ( | |
1413 | .dout (wb_rdma_mux_out[428:390]), | |
1414 | .din0 (wb_array_dout[428:390]), | |
1415 | .din1 (rdma_array_dout[428:390]), | |
1416 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1417 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1418 | ); | |
1419 | ||
1420 | ||
1421 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out3d | |
1422 | ( | |
1423 | .dout (wb_rdma_mux_out[467:429]), | |
1424 | .din0 (wb_array_dout[467:429]), | |
1425 | .din1 (rdma_array_dout[467:429]), | |
1426 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1427 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1428 | ); | |
1429 | ||
1430 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out4a | |
1431 | ( | |
1432 | .dout (wb_rdma_mux_out[506:468]), | |
1433 | .din0 (wb_array_dout[506:468]), | |
1434 | .din1 (rdma_array_dout[506:468]), | |
1435 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1436 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1437 | ); | |
1438 | ||
1439 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out4b | |
1440 | ( | |
1441 | .dout (wb_rdma_mux_out[545:507]), | |
1442 | .din0 (wb_array_dout[545:507]), | |
1443 | .din1 (rdma_array_dout[545:507]), | |
1444 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1445 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1446 | ); | |
1447 | ||
1448 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out4c | |
1449 | ( | |
1450 | .dout (wb_rdma_mux_out[584:546]), | |
1451 | .din0 (wb_array_dout[584:546]), | |
1452 | .din1 (rdma_array_dout[584:546]), | |
1453 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1454 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1455 | ); | |
1456 | ||
1457 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_rdma_mux_out4d | |
1458 | ( | |
1459 | .dout (wb_rdma_mux_out[623:585]), | |
1460 | .din0 (wb_array_dout[623:585]), | |
1461 | .din1 (rdma_array_dout[623:585]), | |
1462 | .sel0 (l2t_l2b_wbrd_en_r2), | |
1463 | .sel1 (l2t_l2b_wbrd_en_r2_n) | |
1464 | ); | |
1465 | ||
1466 | ||
1467 | /////////////////////////////////////////////// | |
1468 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_1a | |
1469 | (.dout (wb_array_dout_r3[38:0]), | |
1470 | .scan_in(ff_wb_array_dout_r3_1a_scanin), | |
1471 | .scan_out(ff_wb_array_dout_r3_1a_scanout), | |
1472 | .din (wb_rdma_mux_out[38:0]), | |
1473 | .clk (l2clk), | |
1474 | .en (wb_or_rdma_rden_r2), | |
1475 | .se(se), | |
1476 | .siclk(siclk), | |
1477 | .soclk(soclk), | |
1478 | .pce_ov(pce_ov), | |
1479 | .stop(stop) | |
1480 | ) ; | |
1481 | ||
1482 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_1b | |
1483 | (.dout (wb_array_dout_r3[77:39]), | |
1484 | .scan_in(ff_wb_array_dout_r3_1b_scanin), | |
1485 | .scan_out(ff_wb_array_dout_r3_1b_scanout), | |
1486 | .din (wb_rdma_mux_out[77:39]), | |
1487 | .clk (l2clk), | |
1488 | .en (wb_or_rdma_rden_r2), | |
1489 | .se(se), | |
1490 | .siclk(siclk), | |
1491 | .soclk(soclk), | |
1492 | .pce_ov(pce_ov), | |
1493 | .stop(stop) | |
1494 | ) ; | |
1495 | ||
1496 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_1c | |
1497 | (.dout (wb_array_dout_r3[116:78]), | |
1498 | .scan_in(ff_wb_array_dout_r3_1c_scanin), | |
1499 | .scan_out(ff_wb_array_dout_r3_1c_scanout), | |
1500 | .din (wb_rdma_mux_out[116:78]), | |
1501 | .en (wb_or_rdma_rden_r2), | |
1502 | .clk (l2clk), | |
1503 | .se(se), | |
1504 | .siclk(siclk), | |
1505 | .soclk(soclk), | |
1506 | .pce_ov(pce_ov), | |
1507 | .stop(stop) | |
1508 | ) ; | |
1509 | ||
1510 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_1d | |
1511 | (.dout (wb_array_dout_r3[155:117]), | |
1512 | .scan_in(ff_wb_array_dout_r3_1d_scanin), | |
1513 | .scan_out(ff_wb_array_dout_r3_1d_scanout), | |
1514 | .din (wb_rdma_mux_out[155:117]), | |
1515 | .en (wb_or_rdma_rden_r2), | |
1516 | .clk (l2clk), | |
1517 | .se(se), | |
1518 | .siclk(siclk), | |
1519 | .soclk(soclk), | |
1520 | .pce_ov(pce_ov), | |
1521 | .stop(stop) | |
1522 | ) ; | |
1523 | ||
1524 | /////////////////////////////////////////////// | |
1525 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_2a | |
1526 | (.dout (wb_array_dout_r3[194:156]), | |
1527 | .scan_in(ff_wb_array_dout_r3_2a_scanin), | |
1528 | .scan_out(ff_wb_array_dout_r3_2a_scanout), | |
1529 | .din (wb_rdma_mux_out[194:156]), | |
1530 | .en (wb_or_rdma_rden_r2), | |
1531 | .clk (l2clk), | |
1532 | .se(se), | |
1533 | .siclk(siclk), | |
1534 | .soclk(soclk), | |
1535 | .pce_ov(pce_ov), | |
1536 | .stop(stop) | |
1537 | ) ; | |
1538 | ||
1539 | ||
1540 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_2b | |
1541 | (.dout (wb_array_dout_r3[233:195]), | |
1542 | .scan_in(ff_wb_array_dout_r3_2b_scanin), | |
1543 | .scan_out(ff_wb_array_dout_r3_2b_scanout), | |
1544 | .din (wb_rdma_mux_out[233:195]), | |
1545 | .en (wb_or_rdma_rden_r2), | |
1546 | .clk (l2clk), | |
1547 | .se(se), | |
1548 | .siclk(siclk), | |
1549 | .soclk(soclk), | |
1550 | .pce_ov(pce_ov), | |
1551 | .stop(stop) | |
1552 | ) ; | |
1553 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_2c | |
1554 | (.dout (wb_array_dout_r3[272:234]), | |
1555 | .scan_in(ff_wb_array_dout_r3_2c_scanin), | |
1556 | .scan_out(ff_wb_array_dout_r3_2c_scanout), | |
1557 | .din (wb_rdma_mux_out[272:234]), | |
1558 | .en (wb_or_rdma_rden_r2), | |
1559 | .clk (l2clk), | |
1560 | .se(se), | |
1561 | .siclk(siclk), | |
1562 | .soclk(soclk), | |
1563 | .pce_ov(pce_ov), | |
1564 | .stop(stop) | |
1565 | ) ; | |
1566 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_2d | |
1567 | (.dout (wb_array_dout_r3[311:273]), | |
1568 | .scan_in(ff_wb_array_dout_r3_2d_scanin), | |
1569 | .scan_out(ff_wb_array_dout_r3_2d_scanout), | |
1570 | .din (wb_rdma_mux_out[311:273]), | |
1571 | .en (wb_or_rdma_rden_r2), | |
1572 | .clk (l2clk), | |
1573 | .se(se), | |
1574 | .siclk(siclk), | |
1575 | .soclk(soclk), | |
1576 | .pce_ov(pce_ov), | |
1577 | .stop(stop) | |
1578 | ) ; | |
1579 | ||
1580 | ||
1581 | /////////////////////////////////////////////// | |
1582 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_3a | |
1583 | (.dout (wb_array_dout_r3[350:312]), | |
1584 | .scan_in(ff_wb_array_dout_r3_3a_scanin), | |
1585 | .scan_out(ff_wb_array_dout_r3_3a_scanout), | |
1586 | .din (wb_rdma_mux_out[350:312]), | |
1587 | .en (wb_or_rdma_rden_r2), | |
1588 | .clk (l2clk), | |
1589 | .se(se), | |
1590 | .siclk(siclk), | |
1591 | .soclk(soclk), | |
1592 | .pce_ov(pce_ov), | |
1593 | .stop(stop) | |
1594 | ) ; | |
1595 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_3b | |
1596 | (.dout (wb_array_dout_r3[389:351]), | |
1597 | .scan_in(ff_wb_array_dout_r3_3b_scanin), | |
1598 | .scan_out(ff_wb_array_dout_r3_3b_scanout), | |
1599 | .din (wb_rdma_mux_out[389:351]), | |
1600 | .en (wb_or_rdma_rden_r2), | |
1601 | .clk (l2clk), | |
1602 | .se(se), | |
1603 | .siclk(siclk), | |
1604 | .soclk(soclk), | |
1605 | .pce_ov(pce_ov), | |
1606 | .stop(stop) | |
1607 | ) ; | |
1608 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_3c | |
1609 | (.dout (wb_array_dout_r3[428:390]), | |
1610 | .scan_in(ff_wb_array_dout_r3_3c_scanin), | |
1611 | .scan_out(ff_wb_array_dout_r3_3c_scanout), | |
1612 | .din (wb_rdma_mux_out[428:390]), | |
1613 | .en (wb_or_rdma_rden_r2), | |
1614 | .clk (l2clk), | |
1615 | .se(se), | |
1616 | .siclk(siclk), | |
1617 | .soclk(soclk), | |
1618 | .pce_ov(pce_ov), | |
1619 | .stop(stop) | |
1620 | ) ; | |
1621 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_3d | |
1622 | (.dout (wb_array_dout_r3[467:429]), | |
1623 | .scan_in(ff_wb_array_dout_r3_3d_scanin), | |
1624 | .scan_out(ff_wb_array_dout_r3_3d_scanout), | |
1625 | .din (wb_rdma_mux_out[467:429]), | |
1626 | .en (wb_or_rdma_rden_r2), | |
1627 | .clk (l2clk), | |
1628 | .se(se), | |
1629 | .siclk(siclk), | |
1630 | .soclk(soclk), | |
1631 | .pce_ov(pce_ov), | |
1632 | .stop(stop) | |
1633 | ) ; | |
1634 | ||
1635 | /////////////////////////////////////////////// | |
1636 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_4a | |
1637 | (.dout (wb_array_dout_r3[506:468]), | |
1638 | .scan_in(ff_wb_array_dout_r3_4a_scanin), | |
1639 | .scan_out(ff_wb_array_dout_r3_4a_scanout), | |
1640 | .din (wb_rdma_mux_out[506:468]), | |
1641 | .en (wb_or_rdma_rden_r2), | |
1642 | .clk (l2clk), | |
1643 | .se(se), | |
1644 | .siclk(siclk), | |
1645 | .soclk(soclk), | |
1646 | .pce_ov(pce_ov), | |
1647 | .stop(stop) | |
1648 | ) ; | |
1649 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_4b | |
1650 | (.dout (wb_array_dout_r3[545:507]), | |
1651 | .scan_in(ff_wb_array_dout_r3_4b_scanin), | |
1652 | .scan_out(ff_wb_array_dout_r3_4b_scanout), | |
1653 | .din (wb_rdma_mux_out[545:507]), | |
1654 | .en (wb_or_rdma_rden_r2), | |
1655 | .clk (l2clk), | |
1656 | .se(se), | |
1657 | .siclk(siclk), | |
1658 | .soclk(soclk), | |
1659 | .pce_ov(pce_ov), | |
1660 | .stop(stop) | |
1661 | ) ; | |
1662 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_4c | |
1663 | (.dout (wb_array_dout_r3[584:546]), | |
1664 | .scan_in(ff_wb_array_dout_r3_4c_scanin), | |
1665 | .scan_out(ff_wb_array_dout_r3_4c_scanout), | |
1666 | .din (wb_rdma_mux_out[584:546]), | |
1667 | .en (wb_or_rdma_rden_r2), | |
1668 | .clk (l2clk), | |
1669 | .se(se), | |
1670 | .siclk(siclk), | |
1671 | .soclk(soclk), | |
1672 | .pce_ov(pce_ov), | |
1673 | .stop(stop) | |
1674 | ) ; | |
1675 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r3_4d | |
1676 | (.dout (wb_array_dout_r3[623:585]), | |
1677 | .scan_in(ff_wb_array_dout_r3_4d_scanin), | |
1678 | .scan_out(ff_wb_array_dout_r3_4d_scanout), | |
1679 | .din (wb_rdma_mux_out[623:585]), | |
1680 | .en (wb_or_rdma_rden_r2), | |
1681 | .clk (l2clk), | |
1682 | .se(se), | |
1683 | .siclk(siclk), | |
1684 | .soclk(soclk), | |
1685 | .pce_ov(pce_ov), | |
1686 | .stop(stop) | |
1687 | ) ; | |
1688 | ||
1689 | ||
1690 | //////////////////////////////////////////////////////////////////////////////// | |
1691 | //assign sel_in0 = (l2t_l2b_ev_dword_r3[1:0] == 2'b00) ; | |
1692 | //assign sel_in1 = (l2t_l2b_ev_dword_r3[1:0] == 2'b01) ; | |
1693 | //assign sel_in2 = (l2t_l2b_ev_dword_r3[1:0] == 2'b10) ; | |
1694 | //assign sel_in3 = ~(sel_in0 | sel_in1 | sel_in2) ; | |
1695 | //////////////////////////////////////////////////////////////////////////////// | |
1696 | // | |
1697 | // | |
1698 | // MUX select generation | |
1699 | // | |
1700 | // | |
1701 | //////////////////////////////////////////////////////////////////////////////// | |
1702 | l2b_evict_dp_cmp_macro__width_4 sel_in0_slice | |
1703 | ( | |
1704 | .din0 ({2'b0,l2t_l2b_ev_dword_r1[1:0]}), | |
1705 | .din1 ({2'b0,2'b0}), | |
1706 | .dout (sel_in0_r1) | |
1707 | ); | |
1708 | l2b_evict_dp_cmp_macro__width_4 sel_in1_slice | |
1709 | ( | |
1710 | .din0 ({2'b0,l2t_l2b_ev_dword_r1[1:0]}), | |
1711 | .din1 ({2'b0,2'b01}), | |
1712 | .dout (sel_in1_r1) | |
1713 | ); | |
1714 | l2b_evict_dp_cmp_macro__width_4 sel_in2_slice | |
1715 | ( | |
1716 | .din0 ({2'b0,l2t_l2b_ev_dword_r1[1:0]}), | |
1717 | .din1 ({2'b0,2'b10}), | |
1718 | .dout (sel_in2_r1) | |
1719 | ); | |
1720 | ||
1721 | l2b_evict_dp_nor_macro__ports_3__width_1 or_sel3_slice | |
1722 | ( | |
1723 | .dout (sel_in3_r1), | |
1724 | .din0 (sel_in0_r1), | |
1725 | .din1 (sel_in1_r1), | |
1726 | .din2 (sel_in2_r1) | |
1727 | ); | |
1728 | ||
1729 | assign sel_evct_mux_r1[3:0] = {sel_in3_r1, sel_in2_r1, sel_in1_r1, sel_in0_r1}; | |
1730 | ||
1731 | ||
1732 | ///////////////////////////////////////////////////////////////////////// | |
1733 | ||
1734 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_wb_array_dout_1a | |
1735 | (.dout (wb_array_dout_r3_4t1[38:0]), | |
1736 | .din0 (wb_array_dout_r3[38:0]), | |
1737 | .din1 (wb_array_dout_r3[116:78]), | |
1738 | .din2 (wb_array_dout_r3[194:156]), | |
1739 | .din3 (wb_array_dout_r3[272:234]), | |
1740 | .sel0 (sel_evct_mux_r3_1a[3]), | |
1741 | .sel1 (sel_evct_mux_r3_1a[2]), | |
1742 | .sel2 (sel_evct_mux_r3_1a[1]), | |
1743 | .muxtst(muxtst), | |
1744 | .test(test) | |
1745 | // .sel3 (sel_evct_mux_r3_1a[0]) | |
1746 | ) ; | |
1747 | ||
1748 | ||
1749 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_wb_array_dout_1b | |
1750 | (.dout (wb_array_dout_r3_4t1[77:39]), | |
1751 | .din0 (wb_array_dout_r3[77:39]), | |
1752 | .din1 (wb_array_dout_r3[155:117]), | |
1753 | .din2 (wb_array_dout_r3[233:195]), | |
1754 | .din3 (wb_array_dout_r3[311:273]), | |
1755 | .sel0 (sel_evct_mux_r3_1b[3]), | |
1756 | .sel1 (sel_evct_mux_r3_1b[2]), | |
1757 | .sel2 (sel_evct_mux_r3_1b[1]), | |
1758 | .muxtst(muxtst), | |
1759 | .test(test) | |
1760 | // .sel3 (sel_evct_mux_r3_1b[0]) | |
1761 | ) ; | |
1762 | ||
1763 | ||
1764 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_wb_array_dout_2a | |
1765 | (.dout (wb_array_dout_r3_4t1[116:78]), | |
1766 | .din0 (wb_array_dout_r3[350:312]), | |
1767 | .din1 (wb_array_dout_r3[428:390]), | |
1768 | .din2 (wb_array_dout_r3[506:468]), | |
1769 | .din3 (wb_array_dout_r3[584:546]), | |
1770 | .sel0 (sel_evct_mux_r3_2a[3]), | |
1771 | .sel1 (sel_evct_mux_r3_2a[2]), | |
1772 | .sel2 (sel_evct_mux_r3_2a[1]), | |
1773 | .muxtst(muxtst), | |
1774 | .test(test) | |
1775 | // .sel3 (sel_evct_mux_r3_2a[0]) | |
1776 | ) ; | |
1777 | ||
1778 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_wb_array_dout_2b | |
1779 | (.dout (wb_array_dout_r3_4t1[155:117]), | |
1780 | .din0 (wb_array_dout_r3[389:351]), | |
1781 | .din1 (wb_array_dout_r3[467:429]), | |
1782 | .din2 (wb_array_dout_r3[545:507]), | |
1783 | .din3 (wb_array_dout_r3[623:585]), | |
1784 | .sel0 (sel_evct_mux_r3_2b[3]), | |
1785 | .sel1 (sel_evct_mux_r3_2b[2]), | |
1786 | .sel2 (sel_evct_mux_r3_2b[1]), | |
1787 | .muxtst(muxtst), | |
1788 | .test(test) | |
1789 | // .sel3 (sel_evct_mux_r3_2b[0]) | |
1790 | ) ; | |
1791 | ||
1792 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c mux_l2t_l2b_ev_dword_r3_bit2 | |
1793 | ( | |
1794 | .dout (l2t_l2b_ev_dword_r3_2), | |
1795 | .din0 (mbist_pick_top_bot), | |
1796 | .din1 (l2t_l2b_ev_dword_r3[2]), | |
1797 | .sel0 (mbist_run_reg), | |
1798 | .sel1 (mbist_run_reg_n) | |
1799 | ); | |
1800 | ||
1801 | l2b_evict_dp_inv_macro__width_1 l2t_l2b_ev_dword_r3_2_inv_slice | |
1802 | ( | |
1803 | .dout (l2t_l2b_ev_dword_r3_2_n ), | |
1804 | .din (l2t_l2b_ev_dword_r3_2 ) | |
1805 | ); | |
1806 | ||
1807 | ||
1808 | ||
1809 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_array_dout_8t1a | |
1810 | (.dout (wb_array_dout_r3_8t1[38:0]), | |
1811 | .din0 (wb_array_dout_r3_4t1[38:0]), | |
1812 | .din1 (wb_array_dout_r3_4t1[116:78]), | |
1813 | .sel0 (l2t_l2b_ev_dword_r3_2), | |
1814 | .sel1 (l2t_l2b_ev_dword_r3_2_n) | |
1815 | ) ; | |
1816 | ||
1817 | ||
1818 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_40r__width_39 mux_wb_array_dout_8t1b | |
1819 | (.dout (wb_array_dout_r3_8t1[77:39]), | |
1820 | .din0 (wb_array_dout_r3_4t1[77:39]), | |
1821 | .din1 (wb_array_dout_r3_4t1[155:117]), | |
1822 | // .sel0 (l2t_l2b_ev_dword_r3[2]), | |
1823 | .sel0 (l2t_l2b_ev_dword_r3_2), | |
1824 | .sel1 (l2t_l2b_ev_dword_r3_2_n) | |
1825 | ) ; | |
1826 | ||
1827 | ||
1828 | ||
1829 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r4a | |
1830 | (.dout (wb_array_dout_r4[38:0]), | |
1831 | .scan_in(ff_wb_array_dout_r4a_scanin), | |
1832 | .scan_out(ff_wb_array_dout_r4a_scanout), | |
1833 | .din (wb_array_dout_r3_8t1[38:0]), | |
1834 | .clk (l2clk), | |
1835 | .en (l2t_l2b_evict_en_r3), | |
1836 | .se(se), | |
1837 | .siclk(siclk), | |
1838 | .soclk(soclk), | |
1839 | .pce_ov(pce_ov), | |
1840 | .stop(stop) | |
1841 | ) ; | |
1842 | ||
1843 | ||
1844 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_wb_array_dout_r4b | |
1845 | (.dout (wb_array_dout_r4[77:39]), | |
1846 | .scan_in(ff_wb_array_dout_r4b_scanin), | |
1847 | .scan_out(ff_wb_array_dout_r4b_scanout), | |
1848 | .din (wb_array_dout_r3_8t1[77:39]), | |
1849 | .clk (l2clk), | |
1850 | .en (l2t_l2b_evict_en_r3), | |
1851 | .se(se), | |
1852 | .siclk(siclk), | |
1853 | .soclk(soclk), | |
1854 | .pce_ov(pce_ov), | |
1855 | .stop(stop) | |
1856 | ) ; | |
1857 | ||
1858 | ||
1859 | /////////////////////////////// MBIST ///////////////////////////////////// | |
1860 | ||
1861 | ||
1862 | assign {unused[3:0],mbist_cmp_data[0], mbist_cmp_data[78], mbist_cmp_data[156], mbist_cmp_data[234], | |
1863 | mbist_cmp_data[1], mbist_cmp_data[79], mbist_cmp_data[157], mbist_cmp_data[235], | |
1864 | mbist_cmp_data[2], mbist_cmp_data[80], mbist_cmp_data[158], mbist_cmp_data[236], | |
1865 | mbist_cmp_data[3], mbist_cmp_data[81], mbist_cmp_data[159], mbist_cmp_data[237], | |
1866 | mbist_cmp_data[4], mbist_cmp_data[82], mbist_cmp_data[160], mbist_cmp_data[238], | |
1867 | mbist_cmp_data[5], mbist_cmp_data[83], mbist_cmp_data[161], mbist_cmp_data[239], | |
1868 | mbist_cmp_data[6], mbist_cmp_data[84], mbist_cmp_data[162], mbist_cmp_data[240], | |
1869 | mbist_cmp_data[7], mbist_cmp_data[85], mbist_cmp_data[163], mbist_cmp_data[241], | |
1870 | mbist_cmp_data[8], mbist_cmp_data[86], mbist_cmp_data[164], mbist_cmp_data[242], | |
1871 | mbist_cmp_data[9], mbist_cmp_data[87], mbist_cmp_data[165], mbist_cmp_data[243], | |
1872 | mbist_cmp_data[10], mbist_cmp_data[88], mbist_cmp_data[166], mbist_cmp_data[244], | |
1873 | mbist_cmp_data[11], mbist_cmp_data[89], mbist_cmp_data[167], mbist_cmp_data[245], | |
1874 | mbist_cmp_data[12], mbist_cmp_data[90], mbist_cmp_data[168], mbist_cmp_data[246], | |
1875 | mbist_cmp_data[13], mbist_cmp_data[91], mbist_cmp_data[169], mbist_cmp_data[247], | |
1876 | mbist_cmp_data[14], mbist_cmp_data[92], mbist_cmp_data[170], mbist_cmp_data[248], | |
1877 | mbist_cmp_data[15], mbist_cmp_data[93], mbist_cmp_data[171], mbist_cmp_data[249], | |
1878 | mbist_cmp_data[16], mbist_cmp_data[94], mbist_cmp_data[172], mbist_cmp_data[250], | |
1879 | mbist_cmp_data[17], mbist_cmp_data[95], mbist_cmp_data[173], mbist_cmp_data[251], | |
1880 | mbist_cmp_data[18], mbist_cmp_data[96], mbist_cmp_data[174], mbist_cmp_data[252], | |
1881 | mbist_cmp_data[19], mbist_cmp_data[97], mbist_cmp_data[175], mbist_cmp_data[253], | |
1882 | mbist_cmp_data[20], mbist_cmp_data[98], mbist_cmp_data[176], mbist_cmp_data[254], | |
1883 | mbist_cmp_data[21], mbist_cmp_data[99], mbist_cmp_data[177], mbist_cmp_data[255], | |
1884 | mbist_cmp_data[22], mbist_cmp_data[100], mbist_cmp_data[178], mbist_cmp_data[256], | |
1885 | mbist_cmp_data[23], mbist_cmp_data[101], mbist_cmp_data[179], mbist_cmp_data[257], | |
1886 | mbist_cmp_data[24], mbist_cmp_data[102], mbist_cmp_data[180], mbist_cmp_data[258], | |
1887 | mbist_cmp_data[25], mbist_cmp_data[103], mbist_cmp_data[181], mbist_cmp_data[259], | |
1888 | mbist_cmp_data[26], mbist_cmp_data[104], mbist_cmp_data[182], mbist_cmp_data[260], | |
1889 | mbist_cmp_data[27], mbist_cmp_data[105], mbist_cmp_data[183], mbist_cmp_data[261], | |
1890 | mbist_cmp_data[28], mbist_cmp_data[106], mbist_cmp_data[184], mbist_cmp_data[262], | |
1891 | mbist_cmp_data[29], mbist_cmp_data[107], mbist_cmp_data[185], mbist_cmp_data[263], | |
1892 | mbist_cmp_data[30], mbist_cmp_data[108], mbist_cmp_data[186], mbist_cmp_data[264], | |
1893 | mbist_cmp_data[31], mbist_cmp_data[109], mbist_cmp_data[187], mbist_cmp_data[265], | |
1894 | mbist_cmp_data[32], mbist_cmp_data[110], mbist_cmp_data[188], mbist_cmp_data[266], | |
1895 | mbist_cmp_data[33], mbist_cmp_data[111], mbist_cmp_data[189], mbist_cmp_data[267], | |
1896 | mbist_cmp_data[34], mbist_cmp_data[112], mbist_cmp_data[190], mbist_cmp_data[268], | |
1897 | mbist_cmp_data[35], mbist_cmp_data[113], mbist_cmp_data[191], mbist_cmp_data[269], | |
1898 | mbist_cmp_data[36], mbist_cmp_data[114], mbist_cmp_data[192], mbist_cmp_data[270], | |
1899 | mbist_cmp_data[37], mbist_cmp_data[115], mbist_cmp_data[193], mbist_cmp_data[271], | |
1900 | mbist_cmp_data[38], mbist_cmp_data[116], mbist_cmp_data[194], mbist_cmp_data[272]} | |
1901 | = {20{wb_mbist_data_in_r2[7:0]}}; | |
1902 | ||
1903 | assign {unused[7:4],mbist_cmp_data[39], mbist_cmp_data[117], mbist_cmp_data[195], mbist_cmp_data[273], | |
1904 | mbist_cmp_data[40], mbist_cmp_data[118], mbist_cmp_data[196], mbist_cmp_data[274], | |
1905 | mbist_cmp_data[41], mbist_cmp_data[119], mbist_cmp_data[197], mbist_cmp_data[275], | |
1906 | mbist_cmp_data[42], mbist_cmp_data[120], mbist_cmp_data[198], mbist_cmp_data[276], | |
1907 | mbist_cmp_data[43], mbist_cmp_data[121], mbist_cmp_data[199], mbist_cmp_data[277], | |
1908 | mbist_cmp_data[44], mbist_cmp_data[122], mbist_cmp_data[200], mbist_cmp_data[278], | |
1909 | mbist_cmp_data[45], mbist_cmp_data[123], mbist_cmp_data[201], mbist_cmp_data[279], | |
1910 | mbist_cmp_data[46], mbist_cmp_data[124], mbist_cmp_data[202], mbist_cmp_data[280], | |
1911 | mbist_cmp_data[47], mbist_cmp_data[125], mbist_cmp_data[203], mbist_cmp_data[281], | |
1912 | mbist_cmp_data[48], mbist_cmp_data[126], mbist_cmp_data[204], mbist_cmp_data[282], | |
1913 | mbist_cmp_data[49], mbist_cmp_data[127], mbist_cmp_data[205], mbist_cmp_data[283], | |
1914 | mbist_cmp_data[50], mbist_cmp_data[128], mbist_cmp_data[206], mbist_cmp_data[284], | |
1915 | mbist_cmp_data[51], mbist_cmp_data[129], mbist_cmp_data[207], mbist_cmp_data[285], | |
1916 | mbist_cmp_data[52], mbist_cmp_data[130], mbist_cmp_data[208], mbist_cmp_data[286], | |
1917 | mbist_cmp_data[53], mbist_cmp_data[131], mbist_cmp_data[209], mbist_cmp_data[287], | |
1918 | mbist_cmp_data[54], mbist_cmp_data[132], mbist_cmp_data[210], mbist_cmp_data[288], | |
1919 | mbist_cmp_data[55], mbist_cmp_data[133], mbist_cmp_data[211], mbist_cmp_data[289], | |
1920 | mbist_cmp_data[56], mbist_cmp_data[134], mbist_cmp_data[212], mbist_cmp_data[290], | |
1921 | mbist_cmp_data[57], mbist_cmp_data[135], mbist_cmp_data[213], mbist_cmp_data[291], | |
1922 | mbist_cmp_data[58], mbist_cmp_data[136], mbist_cmp_data[214], mbist_cmp_data[292], | |
1923 | mbist_cmp_data[59], mbist_cmp_data[137], mbist_cmp_data[215], mbist_cmp_data[293], | |
1924 | mbist_cmp_data[60], mbist_cmp_data[138], mbist_cmp_data[216], mbist_cmp_data[294], | |
1925 | mbist_cmp_data[61], mbist_cmp_data[139], mbist_cmp_data[217], mbist_cmp_data[295], | |
1926 | mbist_cmp_data[62], mbist_cmp_data[140], mbist_cmp_data[218], mbist_cmp_data[296], | |
1927 | mbist_cmp_data[63], mbist_cmp_data[141], mbist_cmp_data[219], mbist_cmp_data[297], | |
1928 | mbist_cmp_data[64], mbist_cmp_data[142], mbist_cmp_data[220], mbist_cmp_data[298], | |
1929 | mbist_cmp_data[65], mbist_cmp_data[143], mbist_cmp_data[221], mbist_cmp_data[299], | |
1930 | mbist_cmp_data[66], mbist_cmp_data[144], mbist_cmp_data[222], mbist_cmp_data[300], | |
1931 | mbist_cmp_data[67], mbist_cmp_data[145], mbist_cmp_data[223], mbist_cmp_data[301], | |
1932 | mbist_cmp_data[68], mbist_cmp_data[146], mbist_cmp_data[224], mbist_cmp_data[302], | |
1933 | mbist_cmp_data[69], mbist_cmp_data[147], mbist_cmp_data[225], mbist_cmp_data[303], | |
1934 | mbist_cmp_data[70], mbist_cmp_data[148], mbist_cmp_data[226], mbist_cmp_data[304], | |
1935 | mbist_cmp_data[71], mbist_cmp_data[149], mbist_cmp_data[227], mbist_cmp_data[305], | |
1936 | mbist_cmp_data[72], mbist_cmp_data[150], mbist_cmp_data[228], mbist_cmp_data[306], | |
1937 | mbist_cmp_data[73], mbist_cmp_data[151], mbist_cmp_data[229], mbist_cmp_data[307], | |
1938 | mbist_cmp_data[74], mbist_cmp_data[152], mbist_cmp_data[230], mbist_cmp_data[308], | |
1939 | mbist_cmp_data[75], mbist_cmp_data[153], mbist_cmp_data[231], mbist_cmp_data[309], | |
1940 | mbist_cmp_data[76], mbist_cmp_data[154], mbist_cmp_data[232], mbist_cmp_data[310], | |
1941 | mbist_cmp_data[77], mbist_cmp_data[155], mbist_cmp_data[233], mbist_cmp_data[311]} | |
1942 | = {20{wb_mbist_data_in_r2[7:0]}}; | |
1943 | ||
1944 | assign {unused[11:8],mbist_cmp_data[312], mbist_cmp_data[390], mbist_cmp_data[468], mbist_cmp_data[546], | |
1945 | mbist_cmp_data[313], mbist_cmp_data[391], mbist_cmp_data[469], mbist_cmp_data[547], | |
1946 | mbist_cmp_data[314], mbist_cmp_data[392], mbist_cmp_data[470], mbist_cmp_data[548], | |
1947 | mbist_cmp_data[315], mbist_cmp_data[393], mbist_cmp_data[471], mbist_cmp_data[549], | |
1948 | mbist_cmp_data[316], mbist_cmp_data[394], mbist_cmp_data[472], mbist_cmp_data[550], | |
1949 | mbist_cmp_data[317], mbist_cmp_data[395], mbist_cmp_data[473], mbist_cmp_data[551], | |
1950 | mbist_cmp_data[318], mbist_cmp_data[396], mbist_cmp_data[474], mbist_cmp_data[552], | |
1951 | mbist_cmp_data[319], mbist_cmp_data[397], mbist_cmp_data[475], mbist_cmp_data[553], | |
1952 | mbist_cmp_data[320], mbist_cmp_data[398], mbist_cmp_data[476], mbist_cmp_data[554], | |
1953 | mbist_cmp_data[321], mbist_cmp_data[399], mbist_cmp_data[477], mbist_cmp_data[555], | |
1954 | mbist_cmp_data[322], mbist_cmp_data[400], mbist_cmp_data[478], mbist_cmp_data[556], | |
1955 | mbist_cmp_data[323], mbist_cmp_data[401], mbist_cmp_data[479], mbist_cmp_data[557], | |
1956 | mbist_cmp_data[324], mbist_cmp_data[402], mbist_cmp_data[480], mbist_cmp_data[558], | |
1957 | mbist_cmp_data[325], mbist_cmp_data[403], mbist_cmp_data[481], mbist_cmp_data[559], | |
1958 | mbist_cmp_data[326], mbist_cmp_data[404], mbist_cmp_data[482], mbist_cmp_data[560], | |
1959 | mbist_cmp_data[327], mbist_cmp_data[405], mbist_cmp_data[483], mbist_cmp_data[561], | |
1960 | mbist_cmp_data[328], mbist_cmp_data[406], mbist_cmp_data[484], mbist_cmp_data[562], | |
1961 | mbist_cmp_data[329], mbist_cmp_data[407], mbist_cmp_data[485], mbist_cmp_data[563], | |
1962 | mbist_cmp_data[330], mbist_cmp_data[408], mbist_cmp_data[486], mbist_cmp_data[564], | |
1963 | mbist_cmp_data[331], mbist_cmp_data[409], mbist_cmp_data[487], mbist_cmp_data[565], | |
1964 | mbist_cmp_data[332], mbist_cmp_data[410], mbist_cmp_data[488], mbist_cmp_data[566], | |
1965 | mbist_cmp_data[333], mbist_cmp_data[411], mbist_cmp_data[489], mbist_cmp_data[567], | |
1966 | mbist_cmp_data[334], mbist_cmp_data[412], mbist_cmp_data[490], mbist_cmp_data[568], | |
1967 | mbist_cmp_data[335], mbist_cmp_data[413], mbist_cmp_data[491], mbist_cmp_data[569], | |
1968 | mbist_cmp_data[336], mbist_cmp_data[414], mbist_cmp_data[492], mbist_cmp_data[570], | |
1969 | mbist_cmp_data[337], mbist_cmp_data[415], mbist_cmp_data[493], mbist_cmp_data[571], | |
1970 | mbist_cmp_data[338], mbist_cmp_data[416], mbist_cmp_data[494], mbist_cmp_data[572], | |
1971 | mbist_cmp_data[339], mbist_cmp_data[417], mbist_cmp_data[495], mbist_cmp_data[573], | |
1972 | mbist_cmp_data[340], mbist_cmp_data[418], mbist_cmp_data[496], mbist_cmp_data[574], | |
1973 | mbist_cmp_data[341], mbist_cmp_data[419], mbist_cmp_data[497], mbist_cmp_data[575], | |
1974 | mbist_cmp_data[342], mbist_cmp_data[420], mbist_cmp_data[498], mbist_cmp_data[576], | |
1975 | mbist_cmp_data[343], mbist_cmp_data[421], mbist_cmp_data[499], mbist_cmp_data[577], | |
1976 | mbist_cmp_data[344], mbist_cmp_data[422], mbist_cmp_data[500], mbist_cmp_data[578], | |
1977 | mbist_cmp_data[345], mbist_cmp_data[423], mbist_cmp_data[501], mbist_cmp_data[579], | |
1978 | mbist_cmp_data[346], mbist_cmp_data[424], mbist_cmp_data[502], mbist_cmp_data[580], | |
1979 | mbist_cmp_data[347], mbist_cmp_data[425], mbist_cmp_data[503], mbist_cmp_data[581], | |
1980 | mbist_cmp_data[348], mbist_cmp_data[426], mbist_cmp_data[504], mbist_cmp_data[582], | |
1981 | mbist_cmp_data[349], mbist_cmp_data[427], mbist_cmp_data[505], mbist_cmp_data[583], | |
1982 | mbist_cmp_data[350], mbist_cmp_data[428], mbist_cmp_data[506], mbist_cmp_data[584]} | |
1983 | = {20{wb_mbist_data_in_r2[7:0]}}; | |
1984 | ||
1985 | ||
1986 | ||
1987 | assign {unused[15:12],mbist_cmp_data[351], mbist_cmp_data[429], mbist_cmp_data[507], mbist_cmp_data[585], | |
1988 | mbist_cmp_data[352], mbist_cmp_data[430], mbist_cmp_data[508], mbist_cmp_data[586], | |
1989 | mbist_cmp_data[353], mbist_cmp_data[431], mbist_cmp_data[509], mbist_cmp_data[587], | |
1990 | mbist_cmp_data[354], mbist_cmp_data[432], mbist_cmp_data[510], mbist_cmp_data[588], | |
1991 | mbist_cmp_data[355], mbist_cmp_data[433], mbist_cmp_data[511], mbist_cmp_data[589], | |
1992 | mbist_cmp_data[356], mbist_cmp_data[434], mbist_cmp_data[512], mbist_cmp_data[590], | |
1993 | mbist_cmp_data[357], mbist_cmp_data[435], mbist_cmp_data[513], mbist_cmp_data[591], | |
1994 | mbist_cmp_data[358], mbist_cmp_data[436], mbist_cmp_data[514], mbist_cmp_data[592], | |
1995 | mbist_cmp_data[359], mbist_cmp_data[437], mbist_cmp_data[515], mbist_cmp_data[593], | |
1996 | mbist_cmp_data[360], mbist_cmp_data[438], mbist_cmp_data[516], mbist_cmp_data[594], | |
1997 | mbist_cmp_data[361], mbist_cmp_data[439], mbist_cmp_data[517], mbist_cmp_data[595], | |
1998 | mbist_cmp_data[362], mbist_cmp_data[440], mbist_cmp_data[518], mbist_cmp_data[596], | |
1999 | mbist_cmp_data[363], mbist_cmp_data[441], mbist_cmp_data[519], mbist_cmp_data[597], | |
2000 | mbist_cmp_data[364], mbist_cmp_data[442], mbist_cmp_data[520], mbist_cmp_data[598], | |
2001 | mbist_cmp_data[365], mbist_cmp_data[443], mbist_cmp_data[521], mbist_cmp_data[599], | |
2002 | mbist_cmp_data[366], mbist_cmp_data[444], mbist_cmp_data[522], mbist_cmp_data[600], | |
2003 | mbist_cmp_data[367], mbist_cmp_data[445], mbist_cmp_data[523], mbist_cmp_data[601], | |
2004 | mbist_cmp_data[368], mbist_cmp_data[446], mbist_cmp_data[524], mbist_cmp_data[602], | |
2005 | mbist_cmp_data[369], mbist_cmp_data[447], mbist_cmp_data[525], mbist_cmp_data[603], | |
2006 | mbist_cmp_data[370], mbist_cmp_data[448], mbist_cmp_data[526], mbist_cmp_data[604], | |
2007 | mbist_cmp_data[371], mbist_cmp_data[449], mbist_cmp_data[527], mbist_cmp_data[605], | |
2008 | mbist_cmp_data[372], mbist_cmp_data[450], mbist_cmp_data[528], mbist_cmp_data[606], | |
2009 | mbist_cmp_data[373], mbist_cmp_data[451], mbist_cmp_data[529], mbist_cmp_data[607], | |
2010 | mbist_cmp_data[374], mbist_cmp_data[452], mbist_cmp_data[530], mbist_cmp_data[608], | |
2011 | mbist_cmp_data[375], mbist_cmp_data[453], mbist_cmp_data[531], mbist_cmp_data[609], | |
2012 | mbist_cmp_data[376], mbist_cmp_data[454], mbist_cmp_data[532], mbist_cmp_data[610], | |
2013 | mbist_cmp_data[377], mbist_cmp_data[455], mbist_cmp_data[533], mbist_cmp_data[611], | |
2014 | mbist_cmp_data[378], mbist_cmp_data[456], mbist_cmp_data[534], mbist_cmp_data[612], | |
2015 | mbist_cmp_data[379], mbist_cmp_data[457], mbist_cmp_data[535], mbist_cmp_data[613], | |
2016 | mbist_cmp_data[380], mbist_cmp_data[458], mbist_cmp_data[536], mbist_cmp_data[614], | |
2017 | mbist_cmp_data[381], mbist_cmp_data[459], mbist_cmp_data[537], mbist_cmp_data[615], | |
2018 | mbist_cmp_data[382], mbist_cmp_data[460], mbist_cmp_data[538], mbist_cmp_data[616], | |
2019 | mbist_cmp_data[383], mbist_cmp_data[461], mbist_cmp_data[539], mbist_cmp_data[617], | |
2020 | mbist_cmp_data[384], mbist_cmp_data[462], mbist_cmp_data[540], mbist_cmp_data[618], | |
2021 | mbist_cmp_data[385], mbist_cmp_data[463], mbist_cmp_data[541], mbist_cmp_data[619], | |
2022 | mbist_cmp_data[386], mbist_cmp_data[464], mbist_cmp_data[542], mbist_cmp_data[620], | |
2023 | mbist_cmp_data[387], mbist_cmp_data[465], mbist_cmp_data[543], mbist_cmp_data[621], | |
2024 | mbist_cmp_data[388], mbist_cmp_data[466], mbist_cmp_data[544], mbist_cmp_data[622], | |
2025 | mbist_cmp_data[389], mbist_cmp_data[467], mbist_cmp_data[545], mbist_cmp_data[623]} | |
2026 | = {20{wb_mbist_data_in_r2[7:0]}}; | |
2027 | ||
2028 | //mux_macro mux_mbist_cmp_data1 (width=39,ports=8,mux=aodec) | |
2029 | // ( | |
2030 | // .dout (mbist_compare_data[38:0]), | |
2031 | // .din0 (mbist_cmp_data[38:0]), | |
2032 | // .din1 (mbist_cmp_data[116:78]), | |
2033 | // .din2 (mbist_cmp_data[194:156]), | |
2034 | // .din3 (mbist_cmp_data[272:234]), | |
2035 | // .din4 (mbist_cmp_data[350:312]), | |
2036 | // .din5 (mbist_cmp_data[428:390]), | |
2037 | // .din6 (mbist_cmp_data[506:468]), | |
2038 | // .din7 (mbist_cmp_data[584:546]), | |
2039 | // .sel (mbist_compare_read_sel[2:0]) | |
2040 | // ); | |
2041 | // | |
2042 | //mux_macro mux_mbist_cmp_data0 (width=39,ports=8,mux=aodec) | |
2043 | // ( | |
2044 | // .dout (mbist_compare_data[77:39]), | |
2045 | // .din0 (mbist_cmp_data[77:39]), | |
2046 | // .din1 (mbist_cmp_data[155:117]), | |
2047 | // .din2 (mbist_cmp_data[233:195]), | |
2048 | // .din3 (mbist_cmp_data[311:273]), | |
2049 | // .din4 (mbist_cmp_data[389:351]), | |
2050 | // .din5 (mbist_cmp_data[467:429]), | |
2051 | // .din6 (mbist_cmp_data[545:507]), | |
2052 | // .din7 (mbist_cmp_data[623:585]), | |
2053 | // .sel (mbist_compare_read_sel[2:0]) | |
2054 | // ); | |
2055 | // | |
2056 | // | |
2057 | //msff_macro ff_mbist_compare_data10 (width=39) | |
2058 | // ( | |
2059 | // .scan_in(ff_mbist_compare_data10_scanin), | |
2060 | // .scan_out(ff_mbist_compare_data10_scanout), | |
2061 | // .dout (mbist_compare_data_r1[38:0]), | |
2062 | // .din (mbist_compare_data[38:0]), | |
2063 | // .clk (l2clk), | |
2064 | // .en (1'b1), | |
2065 | // ); | |
2066 | //msff_macro ff_mbist_compare_data11 (width=39) | |
2067 | // ( | |
2068 | // .scan_in(ff_mbist_compare_data11_scanin), | |
2069 | // .scan_out(ff_mbist_compare_data11_scanout), | |
2070 | // .dout (mbist_compare_data_r2[38:0]), | |
2071 | // .din (mbist_compare_data_r1[38:0]), | |
2072 | // .clk (l2clk), | |
2073 | // .en (1'b1), | |
2074 | // ); | |
2075 | // | |
2076 | //msff_macro ff_mbist_compare_data12 (width=39) | |
2077 | // ( | |
2078 | // .scan_in(ff_mbist_compare_data12_scanin), | |
2079 | // .scan_out(ff_mbist_compare_data12_scanout), | |
2080 | // .dout (mbist_compare_data_r3[38:0]), | |
2081 | // .din (mbist_compare_data_r2[38:0]), | |
2082 | // .clk (l2clk), | |
2083 | // .en (1'b1), | |
2084 | // ); | |
2085 | // | |
2086 | // | |
2087 | //msff_macro ff_mbist_compare_data0 (width=39) | |
2088 | // ( | |
2089 | // .scan_in(ff_mbist_compare_data0_scanin), | |
2090 | // .scan_out(ff_mbist_compare_data0_scanout), | |
2091 | // .dout (mbist_compare_data_r1[77:39]), | |
2092 | // .din (mbist_compare_data[77:39]), | |
2093 | // .clk (l2clk), | |
2094 | // .en (1'b1), | |
2095 | // ); | |
2096 | // | |
2097 | //msff_macro ff_mbist_compare_data1 (width=39) | |
2098 | // ( | |
2099 | // .scan_in(ff_mbist_compare_data1_scanin), | |
2100 | // .scan_out(ff_mbist_compare_data1_scanout), | |
2101 | // .dout (mbist_compare_data_r2[77:39]), | |
2102 | // .din (mbist_compare_data_r1[77:39]), | |
2103 | // .clk (l2clk), | |
2104 | // .en (1'b1), | |
2105 | // ); | |
2106 | // | |
2107 | //msff_macro ff_mbist_compare_data2 (width=39) | |
2108 | // ( | |
2109 | // .scan_in(ff_mbist_compare_data2_scanin), | |
2110 | // .scan_out(ff_mbist_compare_data2_scanout), | |
2111 | // .dout (mbist_compare_data_r3[77:39]), | |
2112 | // .din (mbist_compare_data_r2[77:39]), | |
2113 | // .clk (l2clk), | |
2114 | // .en (1'b1), | |
2115 | // ); | |
2116 | // | |
2117 | // | |
2118 | ||
2119 | ||
2120 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_mbist_comp_mux1a | |
2121 | (.dout (mbist_cmp_data_4t1[38:0]), | |
2122 | .din0 (mbist_cmp_data[38:0]), | |
2123 | .din1 (mbist_cmp_data[116:78]), | |
2124 | .din2 (mbist_cmp_data[194:156]), | |
2125 | .din3 (mbist_cmp_data[272:234]), | |
2126 | .sel0 (sel_evct_mux_r3_1a[3]), | |
2127 | .sel1 (sel_evct_mux_r3_1a[2]), | |
2128 | .sel2 (sel_evct_mux_r3_1a[1]), | |
2129 | .muxtst(muxtst), | |
2130 | .test(test) | |
2131 | ) ; | |
2132 | ||
2133 | ||
2134 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_mbist_comp_mux1b | |
2135 | (.dout (mbist_cmp_data_4t1[77:39]), | |
2136 | .din0 (mbist_cmp_data[77:39]), | |
2137 | .din1 (mbist_cmp_data[155:117]), | |
2138 | .din2 (mbist_cmp_data[233:195]), | |
2139 | .din3 (mbist_cmp_data[311:273]), | |
2140 | .sel0 (sel_evct_mux_r3_1b[3]), | |
2141 | .sel1 (sel_evct_mux_r3_1b[2]), | |
2142 | .sel2 (sel_evct_mux_r3_1b[1]), | |
2143 | .muxtst(muxtst), | |
2144 | .test(test) | |
2145 | ) ; | |
2146 | ||
2147 | ||
2148 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_mbist_comp_mux2a | |
2149 | (.dout (mbist_cmp_data_4t1[116:78]), | |
2150 | .din0 (mbist_cmp_data[350:312]), | |
2151 | .din1 (mbist_cmp_data[428:390]), | |
2152 | .din2 (mbist_cmp_data[506:468]), | |
2153 | .din3 (mbist_cmp_data[584:546]), | |
2154 | .sel0 (sel_evct_mux_r3_2a[3]), | |
2155 | .sel1 (sel_evct_mux_r3_2a[2]), | |
2156 | .sel2 (sel_evct_mux_r3_2a[1]), | |
2157 | .muxtst(muxtst), | |
2158 | .test(test) | |
2159 | ) ; | |
2160 | ||
2161 | l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 mux_mbist_comp_mux2b | |
2162 | (.dout (mbist_cmp_data_4t1[155:117]), | |
2163 | .din0 (mbist_cmp_data[389:351]), | |
2164 | .din1 (mbist_cmp_data[467:429]), | |
2165 | .din2 (mbist_cmp_data[545:507]), | |
2166 | .din3 (mbist_cmp_data[623:585]), | |
2167 | .sel0 (sel_evct_mux_r3_2b[3]), | |
2168 | .sel1 (sel_evct_mux_r3_2b[2]), | |
2169 | .sel2 (sel_evct_mux_r3_2b[1]), | |
2170 | .muxtst(muxtst), | |
2171 | .test(test) | |
2172 | ) ; | |
2173 | ||
2174 | ||
2175 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_40r__width_39 mux_mbist_cmp_data_8t1a | |
2176 | (.dout (mbist_cmp_data_8t1[38:0]), | |
2177 | .din0 (mbist_cmp_data_4t1[38:0]), | |
2178 | .din1 (mbist_cmp_data_4t1[116:78]), | |
2179 | .sel0 (l2t_l2b_ev_dword_r3_2), | |
2180 | .sel1 (l2t_l2b_ev_dword_r3_2_n) | |
2181 | ) ; | |
2182 | ||
2183 | ||
2184 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_40r__width_39 mux_mbist_cmp_data_8t1b | |
2185 | (.dout (mbist_cmp_data_8t1[77:39]), | |
2186 | .din0 (mbist_cmp_data_4t1[77:39]), | |
2187 | .din1 (mbist_cmp_data_4t1[155:117]), | |
2188 | .sel0 (l2t_l2b_ev_dword_r3_2), | |
2189 | .sel1 (l2t_l2b_ev_dword_r3_2_n) | |
2190 | ) ; | |
2191 | ||
2192 | ||
2193 | ||
2194 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_mbist_cmp_r4a | |
2195 | (.dout (mbist_compare_data[38:0]), | |
2196 | .scan_in(ff_mbist_cmp_r4a_scanin), | |
2197 | .scan_out(ff_mbist_cmp_r4a_scanout), | |
2198 | .din (mbist_cmp_data_8t1[38:0]), | |
2199 | .clk (l2clk), | |
2200 | .en (1'b1), | |
2201 | .se(se), | |
2202 | .siclk(siclk), | |
2203 | .soclk(soclk), | |
2204 | .pce_ov(pce_ov), | |
2205 | .stop(stop) | |
2206 | ) ; | |
2207 | ||
2208 | ||
2209 | l2b_evict_dp_msff_macro__stack_40r__width_39 ff_mbist_cmp_r4b | |
2210 | (.dout (mbist_compare_data[77:39]), | |
2211 | .scan_in(ff_mbist_cmp_r4b_scanin), | |
2212 | .scan_out(ff_mbist_cmp_r4b_scanout), | |
2213 | .din (mbist_cmp_data_8t1[77:39]), | |
2214 | .clk (l2clk), | |
2215 | .en (1'b1), | |
2216 | .se(se), | |
2217 | .siclk(siclk), | |
2218 | .soclk(soclk), | |
2219 | .pce_ov(pce_ov), | |
2220 | .stop(stop) | |
2221 | ) ; | |
2222 | ||
2223 | l2b_evict_dp_cmp_macro__width_64 ff_mbist_compare0 | |
2224 | ( | |
2225 | .dout (wb_or_rdma_rw_fail1), | |
2226 | .din0 (wb_array_dout_r4[63:0]), | |
2227 | .din1 (mbist_compare_data[63:0]) | |
2228 | ); | |
2229 | ||
2230 | ||
2231 | l2b_evict_dp_cmp_macro__width_16 ff_mbist_compare1 | |
2232 | ( | |
2233 | .dout (wb_or_rdma_rw_fail2), | |
2234 | .din0 ({2'b0,wb_array_dout_r4[77:64]}), | |
2235 | .din1 ({2'b0,mbist_compare_data[77:64]}) | |
2236 | ); | |
2237 | ||
2238 | l2b_evict_dp_or_macro__width_1 or_wb_or_rdma_rw_fai_unregl | |
2239 | ( | |
2240 | .dout (read_enable_piped), | |
2241 | .din0 (mbist_wb_array_rd_en_reg2), | |
2242 | .din1 (mbist_rdma_array_rd_en_reg2) | |
2243 | ); | |
2244 | ||
2245 | l2b_evict_dp_nand_macro__width_1 and_wb_or_rdma_rw_fail_unreg | |
2246 | ( | |
2247 | .dout (wb_or_rdma_rw_fail_unreg), | |
2248 | .din0 (wb_or_rdma_rw_fail1), | |
2249 | .din1 (wb_or_rdma_rw_fail2) | |
2250 | ); | |
2251 | ||
2252 | l2b_evict_dp_nand_macro__width_1 nand_wb_or_rdma_rw_fail_qual | |
2253 | ( | |
2254 | .dout (wb_or_rdma_rw_fail_unreg_out), | |
2255 | .din0 (wb_or_rdma_rw_fail_unreg), | |
2256 | .din1 (read_enable_piped1) | |
2257 | ); | |
2258 | ||
2259 | l2b_evict_dp_msff_macro__stack_8c__width_6 ff_fb_rw_fail | |
2260 | ( | |
2261 | .scan_in(ff_fb_rw_fail_scanin), | |
2262 | .scan_out(ff_fb_rw_fail_scanout), | |
2263 | .dout ({read_enable_piped1, | |
2264 | mbist_wb_array_rd_en_reg2,mbist_wb_array_rd_en_reg1, | |
2265 | mbist_rdma_array_rd_en_reg2,mbist_rdma_array_rd_en_reg1, | |
2266 | wb_or_rdma_rw_fail}), | |
2267 | .din ({read_enable_piped, | |
2268 | mbist_wb_array_rd_en_reg1,mbist_wb_array_rd_en_reg, | |
2269 | mbist_rdma_array_rd_en_reg1,mbist_rdma_array_rd_en_reg, | |
2270 | wb_or_rdma_rw_fail_unreg_out}), | |
2271 | .clk (l2clk), | |
2272 | .en (1'b1), | |
2273 | .se(se), | |
2274 | .siclk(siclk), | |
2275 | .soclk(soclk), | |
2276 | .pce_ov(pce_ov), | |
2277 | .stop(stop) | |
2278 | ); | |
2279 | ||
2280 | // mux_macro mux_wb_or_rdma_rw_fail_unreg (width=1,mux=aonpe,ports=2,stack=2c) | |
2281 | // ( | |
2282 | // .dout (wb_or_rdma_rw_fail_unreg_out), | |
2283 | // .din0 (wb_or_rdma_rw_fail_unreg), | |
2284 | // .din1 (1'b1), | |
2285 | // .sel0 (read_enable_piped1), | |
2286 | // .sel1 (read_enable_piped1_n) | |
2287 | // ); | |
2288 | ||
2289 | // inv_macro inv_read_enable_piped1 (width=1) | |
2290 | // ( | |
2291 | // .dout (read_enable_piped1_n), | |
2292 | // .din (read_enable_piped1) | |
2293 | // ); | |
2294 | ||
2295 | //////////////////////////////////////////////////////////////////////////////// | |
2296 | ||
2297 | l2b_ecc39_dp u_ecctree_39b_1 | |
2298 | (.dout (wb_array_dout_ecc_r4[31:0]), | |
2299 | .cflag (check0_r4[5:0]), | |
2300 | .pflag (parity0_r4), | |
2301 | .parity (wb_array_dout_r4[6:0]), | |
2302 | .din (wb_array_dout_r4[38:7]) | |
2303 | ) ; | |
2304 | ||
2305 | l2b_ecc39_dp u_ecctree_39b_2 | |
2306 | (.dout (wb_array_dout_ecc_r4[63:32]), | |
2307 | .cflag (check1_r4[5:0]), | |
2308 | .pflag (parity1_r4), | |
2309 | .parity (wb_array_dout_r4[45:39]), | |
2310 | .din (wb_array_dout_r4[77:46]) | |
2311 | ) ; | |
2312 | ||
2313 | ||
2314 | //assign evict_uncorr_err_r4 = (l2t_l2b_evict_en_r4 & !error_qual) & | |
2315 | // (((|check0_r4[5:0]) & ~parity0_r4) | | |
2316 | // ((|check1_r4[5:0]) & ~parity1_r4)) ; | |
2317 | // | |
2318 | //assign evict_corr_err_r4 = (l2t_l2b_evict_en_r4 & !error_qual) & | |
2319 | // (parity0_r4 | parity1_r4) ; | |
2320 | ||
2321 | // BS 06/13/04 added Notdata logic | |
2322 | // in case notdata is detected on either 32 bit datum , we have to flag UE to | |
2323 | // MCU so that MCU stores the data in DRAM by polluting the ECC to indicate | |
2324 | // multi-bit data error | |
2325 | ||
2326 | // assign evict_notdata_err_lo_r4 = ({parity0_r4,check0_r4[5:0]} == 7'b1111111); | |
2327 | // assign evict_notdata_err_hi_r4 = ({parity1_r4,check1_r4[5:0]} == 7'b1111111); | |
2328 | ||
2329 | //Replace the comparator with and's because we always comparing | |
2330 | //against all 1's. | |
2331 | // cmp_macro cmp_evict_notdata_err_low (width=8) | |
2332 | // ( | |
2333 | // .din0 ({1'b0,7'b1111111}), | |
2334 | // .din1 ({1'b0,parity0_r4,check0_r4[5:0]}), | |
2335 | // .dout (evict_notdata_err_lo_r4) | |
2336 | // ); | |
2337 | ||
2338 | l2b_evict_dp_nand_macro__ports_4__width_1 cmp_nand_err_low_1 | |
2339 | ( | |
2340 | .dout (check0_r4_3_0_nand), | |
2341 | .din0 (check0_r4[0]), | |
2342 | .din1 (check0_r4[1]), | |
2343 | .din2 (check0_r4[2]), | |
2344 | .din3 (check0_r4[3]) | |
2345 | ); | |
2346 | ||
2347 | l2b_evict_dp_nand_macro__ports_3__width_1 cmp_nand_err_low_2 | |
2348 | ( | |
2349 | .dout (check0_r4_4_5_parity_0_nand), | |
2350 | .din0 (check0_r4[4]), | |
2351 | .din1 (check0_r4[5]), | |
2352 | .din2 (parity0_r4) | |
2353 | ); | |
2354 | ||
2355 | l2b_evict_dp_nor_macro__width_1 cmp_nor_low | |
2356 | ( | |
2357 | .dout (evict_notdata_err_lo_r4), | |
2358 | .din0 (check0_r4_3_0_nand), | |
2359 | .din1 (check0_r4_4_5_parity_0_nand) | |
2360 | ); | |
2361 | ||
2362 | //Replace the comparator with and's because we always comparing | |
2363 | //against all 1's. | |
2364 | // cmp_macro cmp_evict_notdata_err_hi (width=8) | |
2365 | // ( | |
2366 | // .din0 ({1'b0,7'b1111111}), | |
2367 | // .din1 ({1'b0,parity1_r4,check1_r4[5:0]}), | |
2368 | // .dout (evict_notdata_err_hi_r4) | |
2369 | // ); | |
2370 | ||
2371 | ||
2372 | l2b_evict_dp_nand_macro__ports_4__width_1 cmp_nand_err_hi_1 | |
2373 | ( | |
2374 | .dout (check1_r4_3_0_nand), | |
2375 | .din0 (check1_r4[0]), | |
2376 | .din1 (check1_r4[1]), | |
2377 | .din2 (check1_r4[2]), | |
2378 | .din3 (check1_r4[3]) | |
2379 | ); | |
2380 | ||
2381 | l2b_evict_dp_nand_macro__ports_3__width_1 cmp_nand_err_hi_2 | |
2382 | ( | |
2383 | .dout (check1_r4_4_5_parity_1_nand), | |
2384 | .din0 (check1_r4[4]), | |
2385 | .din1 (check1_r4[5]), | |
2386 | .din2 (parity1_r4) | |
2387 | ); | |
2388 | ||
2389 | l2b_evict_dp_nor_macro__width_1 cmp_nor_hi | |
2390 | ( | |
2391 | .dout (evict_notdata_err_hi_r4), | |
2392 | .din0 (check1_r4_3_0_nand), | |
2393 | .din1 (check1_r4_4_5_parity_1_nand) | |
2394 | ); | |
2395 | ||
2396 | ||
2397 | l2b_evict_dp_inv_macro__width_1 error_qual_inv_slice | |
2398 | ( | |
2399 | .dout (error_qual_n ), | |
2400 | .din (error_qual ) | |
2401 | ); | |
2402 | ||
2403 | l2b_evict_dp_nand_macro__width_1 evict_en_and_error_qual_slice | |
2404 | ( | |
2405 | .dout (evict_en_and_error_qual_), | |
2406 | .din0 (l2t_l2b_evict_en_r4), | |
2407 | .din1 (error_qual_n) | |
2408 | ); | |
2409 | ||
2410 | l2b_evict_dp_inv_macro__dinv_16x__width_1 l2t_l2b_evict_en_r4_inv | |
2411 | ( | |
2412 | .dout (l2t_l2b_evict_en_r4_n), | |
2413 | .din (l2t_l2b_evict_en_r4) | |
2414 | ); | |
2415 | ||
2416 | ||
2417 | l2b_evict_dp_cmp_macro__width_8 cmp_check0_r4 | |
2418 | ( | |
2419 | .dout (check0or_n), | |
2420 | .din0 ({2'b0,check0_r4[5:0]}), | |
2421 | .din1 (8'b0) | |
2422 | ); | |
2423 | ||
2424 | //inv_macro inv_check0or_n (width=1) | |
2425 | // ( | |
2426 | // .dout (check0or), | |
2427 | // .din (check0or_n) | |
2428 | // ); | |
2429 | // | |
2430 | //inv_macro parity0_r4_inv_slice (width=1) | |
2431 | // ( | |
2432 | // .dout (parity0_r4_n ), | |
2433 | // .din (parity0_r4 ) | |
2434 | // ); | |
2435 | // | |
2436 | /// | |
2437 | ||
2438 | l2b_evict_dp_cmp_macro__width_8 cmp_check1_r4 | |
2439 | ( | |
2440 | .dout (check1or_n), | |
2441 | .din0 ({2'b0,check1_r4[5:0]}), | |
2442 | .din1 (8'b0) | |
2443 | ); | |
2444 | ||
2445 | //inv_macro inv_check1or_n (width=1) | |
2446 | // ( | |
2447 | // .dout (check1or), | |
2448 | // .din (check1or_n) | |
2449 | // ); | |
2450 | // | |
2451 | //inv_macro parity1_r4_inv_slice (width=1) | |
2452 | // ( | |
2453 | // .dout (parity1_r4_n ), | |
2454 | // .din (parity1_r4 ) | |
2455 | // ); | |
2456 | // | |
2457 | l2b_evict_dp_nand_macro__width_1 parity0_nand_parity1_slice | |
2458 | ( | |
2459 | .dout (parity0_nand_parity1), | |
2460 | .din0 (parity1_r4), | |
2461 | .din1 (parity0_r4) | |
2462 | ); | |
2463 | l2b_evict_dp_nand_macro__width_1 parity1_nand_check1_slice | |
2464 | ( | |
2465 | .dout (check0_nand_check1), | |
2466 | .din0 (check0or_n), | |
2467 | .din1 (check1or_n) | |
2468 | ); | |
2469 | ||
2470 | l2b_evict_dp_nand_macro__width_1 parity0_nand_check1_slice | |
2471 | ( | |
2472 | .dout (parity0_nand_check1), | |
2473 | .din0 (check1or_n), | |
2474 | .din1 (parity0_r4) | |
2475 | ); | |
2476 | l2b_evict_dp_nand_macro__width_1 parity1_nand_check0_slice | |
2477 | ( | |
2478 | .dout (parity1_nand_check0), | |
2479 | .din0 (check0or_n), | |
2480 | .din1 (parity1_r4) | |
2481 | ); | |
2482 | ||
2483 | // or_macro evict_uncorr_err_r4_eqn2_slice (width=1) | |
2484 | // ( | |
2485 | // .dout (evict_uncorr_err_r4_eqn2), | |
2486 | // .din0 (parity0_n_and_check0), | |
2487 | // .din1 (parity1_n_and_check1) | |
2488 | // ); | |
2489 | ||
2490 | l2b_evict_dp_nand_macro__ports_4__width_1 evict_uncorr_err_r4_eqn2_slice | |
2491 | ( | |
2492 | .dout (evict_uncorr_err_r4_eqn2_), | |
2493 | .din0 (parity0_nand_parity1), | |
2494 | .din1 (check0_nand_check1), | |
2495 | .din2 (parity0_nand_check1), | |
2496 | .din3 (parity1_nand_check0) | |
2497 | ); | |
2498 | ||
2499 | l2b_evict_dp_nor_macro__width_1 evict_uncorr_err_r4_slice | |
2500 | ( | |
2501 | .dout (evict_uncorr_err_r4), | |
2502 | .din0 (evict_en_and_error_qual_), | |
2503 | .din1 (evict_uncorr_err_r4_eqn2_) | |
2504 | ); | |
2505 | ||
2506 | l2b_evict_dp_nor_macro__dnor_16x__width_1 evict_uncorr_mcu_err_r4_slice | |
2507 | ( | |
2508 | .dout (evict_uncorr_mcu_err_r4), | |
2509 | .din0 (l2t_l2b_evict_en_r4_n), | |
2510 | .din1 (evict_uncorr_err_r4_eqn2_) | |
2511 | ); | |
2512 | ||
2513 | ||
2514 | l2b_evict_dp_nor_macro__width_1 parity_0_or_1_r4_slice | |
2515 | ( | |
2516 | .dout (parity_0_or_1_r4_), | |
2517 | .din0 (parity0_r4), | |
2518 | .din1 (parity1_r4) | |
2519 | ); | |
2520 | ||
2521 | ||
2522 | //assign not_data_error_n = ~( evict_notdata_err_lo_r4 | evict_notdata_err_hi_r4); | |
2523 | ||
2524 | l2b_evict_dp_nor_macro__dnor_16x__width_1 not_not_data_error_n | |
2525 | ( | |
2526 | .dout (parity_0_or_1_r4_err_qual_n), | |
2527 | .din0 (evict_en_and_error_qual_), | |
2528 | .din1 (parity_0_or_1_r4_) | |
2529 | ); | |
2530 | ||
2531 | ||
2532 | //nor_macro evict_corr_err_r4_and_slice (width=1,ports=3) | |
2533 | // ( | |
2534 | // .dout (evict_corr_err_r4), | |
2535 | // .din0 (evict_notdata_err_lo_r4), | |
2536 | // .din1 (evict_notdata_err_hi_r4), | |
2537 | // .din2 (parity_0_or_1_r4_err_qual) | |
2538 | // ); | |
2539 | ||
2540 | l2b_evict_dp_nor_macro__dnor_16x__ports_2__width_1 nor_notdata_err_loorhi_r4 | |
2541 | ( | |
2542 | .dout (notdata_err_loorhi_r4_n), | |
2543 | .din0 (evict_notdata_err_lo_r4), | |
2544 | .din1 (evict_notdata_err_hi_r4) | |
2545 | ); | |
2546 | ||
2547 | //assign evict_corr_err_r4 = (notdata_err_loorhi_r4_n & parity_0_or_1_r4_err_qual_n); | |
2548 | ||
2549 | l2b_evict_dp_and_macro__dinv_48x__dnand_16x__ports_2__width_1 and_evict_corr_err_r4 | |
2550 | ( | |
2551 | .dout (evict_corr_err_r4), | |
2552 | .din0 (notdata_err_loorhi_r4_n), | |
2553 | .din1 (parity_0_or_1_r4_err_qual_n) | |
2554 | ); | |
2555 | ||
2556 | l2b_evict_dp_msff_macro__stack_32r__width_32 ff_wb_array_dout_r5_31_0 | |
2557 | (.dout (wb_array_dout_r5[31:0]), | |
2558 | .scan_in(ff_wb_array_dout_r5_31_0_scanin), | |
2559 | .scan_out(ff_wb_array_dout_r5_31_0_scanout), | |
2560 | .din (wb_array_dout_ecc_r4[31:0]), | |
2561 | .clk (l2clk), | |
2562 | .en (1'b1), | |
2563 | .se(se), | |
2564 | .siclk(siclk), | |
2565 | .soclk(soclk), | |
2566 | .pce_ov(pce_ov), | |
2567 | .stop(stop) | |
2568 | ) ; | |
2569 | ||
2570 | l2b_evict_dp_msff_macro__stack_32r__width_32 ff_wb_array_dout_r5_63_32 | |
2571 | (.dout (wb_array_dout_r5[63:32]), | |
2572 | .scan_in(ff_wb_array_dout_r5_63_32_scanin), | |
2573 | .scan_out(ff_wb_array_dout_r5_63_32_scanout), | |
2574 | .din (wb_array_dout_ecc_r4[63:32]), | |
2575 | .clk (l2clk), | |
2576 | .en (1'b1), | |
2577 | .se(se), | |
2578 | .siclk(siclk), | |
2579 | .soclk(soclk), | |
2580 | .pce_ov(pce_ov), | |
2581 | .stop(stop) | |
2582 | ) ; | |
2583 | ||
2584 | ||
2585 | //////////////////////////////////////////////////////////////////////////////// | |
2586 | //assign evict_l2b_mcu_wr_data_r5 = wb_array_dout_r5[63:0] ; | |
2587 | //assign evict_l2b_mcu_data_vld_r5 = l2t_l2b_evict_en_r5 ; | |
2588 | //assign evict_l2b_mcu_data_mecc_r5 = evict_mcu_uncorr_err_r5 ; | |
2589 | assign evict_l2b_l2t_ev_uerr_r5 = evict_uncorr_err_r5 ; | |
2590 | assign evict_l2b_l2t_ev_cerr_r5 = evict_corr_err_r5 ; | |
2591 | ||
2592 | //////////////////////////////////////////////////////////////////////////////// | |
2593 | ||
2594 | l2b_evict_dp_inv_macro__width_1 inv_select_delay_mcu | |
2595 | ( | |
2596 | .dout (select_delay_mcu_n), | |
2597 | .din (select_delay_mcu) | |
2598 | ); | |
2599 | ||
2600 | ||
2601 | ||
2602 | l2b_evict_dp_msff_macro__dmsff_32x__stack_64c__width_64 ff_evict_l2b_mcu_wr_data_r5_d1 | |
2603 | ( | |
2604 | .scan_in(ff_evict_l2b_mcu_wr_data_r5_d1_scanin), | |
2605 | .scan_out(ff_evict_l2b_mcu_wr_data_r5_d1_scanout), | |
2606 | .dout (wb_array_dout_r5_d1[63:0]), | |
2607 | .din (wb_array_dout_r5[63:0]), | |
2608 | .clk (l2clk), | |
2609 | .en (1'b1), | |
2610 | .se(se), | |
2611 | .siclk(siclk), | |
2612 | .soclk(soclk), | |
2613 | .pce_ov(pce_ov), | |
2614 | .stop(stop) | |
2615 | ); | |
2616 | ||
2617 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__stack_66c__width_66 mux_mcu_data0 | |
2618 | ( | |
2619 | .dout ({evict_l2b_mcu_wr_data_r5[63:0],evict_l2b_mcu_data_mecc_r5,evict_l2b_mcu_data_vld_r5}), | |
2620 | .din0 ({wb_array_dout_r5_d1[63:0],evict_mcu_uncorr_err_r5_d1,l2t_l2b_evict_en_r5_d1}), | |
2621 | .din1 ({wb_array_dout_r5[63:0],evict_mcu_uncorr_err_r5,l2t_l2b_evict_en_r5}), | |
2622 | .sel0 (select_delay_mcu), | |
2623 | .sel1 (select_delay_mcu_n) | |
2624 | ); | |
2625 | ||
2626 | ||
2627 | l2b_evict_dp_msff_macro__stack_21r__width_21 ff_evict_control_regs_slice | |
2628 | ( | |
2629 | .scan_in(ff_evict_control_regs_slice_scanin), | |
2630 | .scan_out(ff_evict_control_regs_slice_scanout), | |
2631 | .dout ({evict_mcu_uncorr_err_r5_d1, l2t_l2b_evict_en_r5_d1, | |
2632 | evict_uncorr_mcu_err_r5,evict_uncorr_err_r5,evict_corr_err_r5,evict_notdata_err_lo_r5, | |
2633 | evict_notdata_err_hi_r5, | |
2634 | l2t_l2b_evict_en_r1_fnl, l2t_l2b_evict_en_r2, | |
2635 | l2t_l2b_evict_en_r3, l2t_l2b_evict_en_r4,l2t_l2b_evict_en_r5, | |
2636 | l2t_l2b_ev_dword_r1[2:0],l2t_l2b_ev_dword_r2[2],l2t_l2b_ev_dword_r3[2], | |
2637 | sel_evct_mux_r2[3:0]}), | |
2638 | .din ({evict_mcu_uncorr_err_r5,l2t_l2b_evict_en_r5,evict_uncorr_mcu_err_r4, | |
2639 | evict_uncorr_err_r4,evict_corr_err_r4,evict_notdata_err_lo_r4, | |
2640 | evict_notdata_err_hi_r4, | |
2641 | l2t_l2b_evict_en_r0,l2t_l2b_evict_en_r1, | |
2642 | l2t_l2b_evict_en_r2,l2t_l2b_evict_en_r3,l2t_l2b_evict_en_r4, | |
2643 | l2t_l2b_ev_dword_r0[2:0], l2t_l2b_ev_dword_r1[2],l2t_l2b_ev_dword_r2[2], | |
2644 | sel_evct_mux_r1[3:0]}),// sel_evct_fnl_mux_sel[3:0]}), | |
2645 | .clk (l2clk), | |
2646 | .en (1'b1), | |
2647 | .se(se), | |
2648 | .siclk(siclk), | |
2649 | .soclk(soclk), | |
2650 | .pce_ov(pce_ov), | |
2651 | .stop(stop) | |
2652 | ); | |
2653 | ||
2654 | ||
2655 | ||
2656 | ||
2657 | l2b_evict_dp_msff_macro__stack_4r__width_4 ff_mux_select0_2b | |
2658 | ( | |
2659 | .scan_in(ff_mux_select0_2b_scanin), | |
2660 | .scan_out(ff_mux_select0_2b_scanout), | |
2661 | .dout (sel_evct_mux_r3_2b[3:0]), | |
2662 | .din (sel_evct_fnl_mux_sel[3:0]), | |
2663 | .clk (l2clk), | |
2664 | .en (1'b1), | |
2665 | .se(se), | |
2666 | .siclk(siclk), | |
2667 | .soclk(soclk), | |
2668 | .pce_ov(pce_ov), | |
2669 | .stop(stop) | |
2670 | ); | |
2671 | ||
2672 | l2b_evict_dp_msff_macro__stack_4r__width_4 ff_mux_select1_2a | |
2673 | ( | |
2674 | .scan_in(ff_mux_select1_2a_scanin), | |
2675 | .scan_out(ff_mux_select1_2a_scanout), | |
2676 | .dout (sel_evct_mux_r3_2a[3:0]), | |
2677 | .din (sel_evct_fnl_mux_sel[3:0]), | |
2678 | .clk (l2clk), | |
2679 | .en (1'b1), | |
2680 | .se(se), | |
2681 | .siclk(siclk), | |
2682 | .soclk(soclk), | |
2683 | .pce_ov(pce_ov), | |
2684 | .stop(stop) | |
2685 | ); | |
2686 | ||
2687 | l2b_evict_dp_msff_macro__stack_4r__width_4 ff_mux_select2_1b | |
2688 | ( | |
2689 | .scan_in(ff_mux_select2_1b_scanin), | |
2690 | .scan_out(ff_mux_select2_1b_scanout), | |
2691 | .dout (sel_evct_mux_r3_1b[3:0]), | |
2692 | .din (sel_evct_fnl_mux_sel[3:0]), | |
2693 | .clk (l2clk), | |
2694 | .en (1'b1), | |
2695 | .se(se), | |
2696 | .siclk(siclk), | |
2697 | .soclk(soclk), | |
2698 | .pce_ov(pce_ov), | |
2699 | .stop(stop) | |
2700 | ); | |
2701 | ||
2702 | l2b_evict_dp_msff_macro__stack_4r__width_4 ff_mux_select3_1a | |
2703 | ( | |
2704 | .scan_in(ff_mux_select3_1a_scanin), | |
2705 | .scan_out(ff_mux_select3_1a_scanout), | |
2706 | .dout (sel_evct_mux_r3_1a[3:0]), | |
2707 | .din (sel_evct_fnl_mux_sel[3:0]), | |
2708 | .clk (l2clk), | |
2709 | .en (1'b1), | |
2710 | .se(se), | |
2711 | .siclk(siclk), | |
2712 | .soclk(soclk), | |
2713 | .pce_ov(pce_ov), | |
2714 | .stop(stop) | |
2715 | ); | |
2716 | ||
2717 | ||
2718 | l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_6r__width_6 mux_gen_dword | |
2719 | ( | |
2720 | .dout ({l2t_l2b_evict_en_r1,mbist_pick_top_bot,sel_evct_fnl_mux_sel[3:0]}), | |
2721 | .din0 ({l2t_l2b_evict_en_r1_fnl,1'b0,sel_evct_mux_r2[3:0]}), | |
2722 | // .din1 ({1'b1,mbist_evict_muxsel_reg[4:0]}), | |
2723 | .din1 ({1'b1,mbist_evict_muxsel_reg[4],mbist_evict_muxsel_reg[0],mbist_evict_muxsel_reg[1], | |
2724 | mbist_evict_muxsel_reg[2],mbist_evict_muxsel_reg[3]}), | |
2725 | .sel0 (mbist_run_reg_n), | |
2726 | .sel1 (mbist_run_reg) | |
2727 | ); | |
2728 | ||
2729 | // BS 06/13/04 added Notdata logic | |
2730 | // in case notdata is detected on either 32 bit datum , we have to flag UE to | |
2731 | // MCU so that MCU stores the data in DRAM by polluting the ECC to indicate | |
2732 | // multi-bit data error | |
2733 | ||
2734 | l2b_evict_dp_or_macro__dinv_16x__dnor_4x__ports_3__width_1 evict_mcu_uncorr_err_r5_slice | |
2735 | ( | |
2736 | .dout (evict_mcu_uncorr_err_r5), | |
2737 | .din0 (evict_notdata_err_lo_r5), | |
2738 | .din1 (evict_notdata_err_hi_r5), | |
2739 | .din2 (evict_uncorr_mcu_err_r5) | |
2740 | ); | |
2741 | ||
2742 | ||
2743 | l2b_evict_dp_msff_macro__stack_6r__width_6 ff_wb_control_regs_slice | |
2744 | ( | |
2745 | .scan_in(ff_wb_control_regs_slice_scanin), | |
2746 | .scan_out(ff_wb_control_regs_slice_scanout), | |
2747 | .dout ({l2t_l2b_wbwr_wen_c7,l2t_l2b_wbrd_en_r1,l2t_l2b_wbrd_en_r2, | |
2748 | l2t_l2b_wbwr_wl_c7[2:0]}), | |
2749 | .din ({l2t_l2b_wbwr_wen_c6,l2t_l2b_wbrd_en_r0,l2t_l2b_wbrd_en_r1_in, | |
2750 | l2t_l2b_wbwr_wl_c6[2:0]}), | |
2751 | .clk (l2clk), | |
2752 | //.en (mbist_run_reg_n), | |
2753 | .en (1'b1), | |
2754 | .se(se), | |
2755 | .siclk(siclk), | |
2756 | .soclk(soclk), | |
2757 | .pce_ov(pce_ov), | |
2758 | .stop(stop) | |
2759 | ); | |
2760 | ||
2761 | l2b_evict_dp_msff_macro__stack_8r__width_8 ff_wb_control_regs_slice_v1 | |
2762 | ( | |
2763 | .scan_in(ff_wb_control_regs_slice_v1_scanin), | |
2764 | .scan_out(ff_wb_control_regs_slice_v1_scanout), | |
2765 | .dout ({l2t_l2b_wbrd_en_r1_v1,l2t_l2b_wbrd_wl_r1_v1[2:0],l2t_l2b_wbwr_wl_c8_v1[2:0],l2t_l2b_wbwr_wen_c8_v1}), | |
2766 | .din ({l2t_l2b_wbrd_en_r0 ,l2t_l2b_wbrd_wl_r0[2:0] ,l2t_l2b_wbwr_wl_c7[2:0],l2t_l2b_wbwr_wen_c7}) , | |
2767 | .clk (l2clk), | |
2768 | .en (1'b1), | |
2769 | .se(se), | |
2770 | .siclk(siclk), | |
2771 | .soclk(soclk), | |
2772 | .pce_ov(pce_ov), | |
2773 | .stop(stop) | |
2774 | ); | |
2775 | ||
2776 | l2b_evict_dp_msff_macro__stack_8r__width_8 ff_wb_control_regs_slice_v2 | |
2777 | ( | |
2778 | .scan_in(ff_wb_control_regs_slice_v2_scanin), | |
2779 | .scan_out(ff_wb_control_regs_slice_v2_scanout), | |
2780 | .dout ({l2t_l2b_wbrd_en_r1_v2,l2t_l2b_wbrd_wl_r1_v2[2:0],l2t_l2b_wbwr_wl_c8_v2[2:0],l2t_l2b_wbwr_wen_c8_v2}), | |
2781 | .din ({l2t_l2b_wbrd_en_r0 ,l2t_l2b_wbrd_wl_r0[2:0] ,l2t_l2b_wbwr_wl_c7[2:0],l2t_l2b_wbwr_wen_c7}) , | |
2782 | .clk (l2clk), | |
2783 | .en (1'b1), | |
2784 | .se(se), | |
2785 | .siclk(siclk), | |
2786 | .soclk(soclk), | |
2787 | .pce_ov(pce_ov), | |
2788 | .stop(stop) | |
2789 | ); | |
2790 | ||
2791 | l2b_evict_dp_msff_macro__stack_8r__width_8 ff_wb_control_regs_slice_v3 | |
2792 | ( | |
2793 | .scan_in(ff_wb_control_regs_slice_v3_scanin), | |
2794 | .scan_out(ff_wb_control_regs_slice_v3_scanout), | |
2795 | .dout ({l2t_l2b_wbrd_en_r1_v3,l2t_l2b_wbrd_wl_r1_v3[2:0],l2t_l2b_wbwr_wl_c8_v3[2:0],l2t_l2b_wbwr_wen_c8_v3}), | |
2796 | .din ({l2t_l2b_wbrd_en_r0 ,l2t_l2b_wbrd_wl_r0[2:0] ,l2t_l2b_wbwr_wl_c7[2:0],l2t_l2b_wbwr_wen_c7}) , | |
2797 | .clk (l2clk), | |
2798 | .en (1'b1), | |
2799 | .se(se), | |
2800 | .siclk(siclk), | |
2801 | .soclk(soclk), | |
2802 | .pce_ov(pce_ov), | |
2803 | .stop(stop) | |
2804 | ); | |
2805 | ||
2806 | l2b_evict_dp_msff_macro__stack_8r__width_8 ff_wb_control_regs_slice_v4 | |
2807 | ( | |
2808 | .scan_in(ff_wb_control_regs_slice_v4_scanin), | |
2809 | .scan_out(ff_wb_control_regs_slice_v4_scanout), | |
2810 | .dout ({l2t_l2b_wbrd_en_r1_v4,l2t_l2b_wbrd_wl_r1_v4[2:0],l2t_l2b_wbwr_wl_c8_v4[2:0],l2t_l2b_wbwr_wen_c8_v4}), | |
2811 | .din ({l2t_l2b_wbrd_en_r0 ,l2t_l2b_wbrd_wl_r0[2:0] ,l2t_l2b_wbwr_wl_c7[2:0],l2t_l2b_wbwr_wen_c7}) , | |
2812 | .clk (l2clk), | |
2813 | .en (1'b1), | |
2814 | .se(se), | |
2815 | .siclk(siclk), | |
2816 | .soclk(soclk), | |
2817 | .pce_ov(pce_ov), | |
2818 | .stop(stop) | |
2819 | ); | |
2820 | ||
2821 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_4r__width_4 mux_rdma_word_wen_v1 | |
2822 | ( | |
2823 | .dout ({l2t_l2b_rdma_fnl_wren_s2[15],l2t_l2b_rdma_fnl_wren_s2[13],l2t_l2b_rdma_fnl_wren_s2[11],l2t_l2b_rdma_fnl_wren_s2[9]}), | |
2824 | .din0 ({l2t_l2b_rdma_wren_s2[15],l2t_l2b_rdma_wren_s2[13],l2t_l2b_rdma_wren_s2[11],l2t_l2b_rdma_wren_s2[9]}), | |
2825 | .din1 (4'hF), | |
2826 | .sel0 (mbist_run_reg_v1_n), | |
2827 | .sel1 (mbist_run_reg_v1) | |
2828 | ); | |
2829 | ||
2830 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_4r__width_4 mux_rdma_word_wen_v2 | |
2831 | ( | |
2832 | .dout ({l2t_l2b_rdma_fnl_wren_s2[14],l2t_l2b_rdma_fnl_wren_s2[12],l2t_l2b_rdma_fnl_wren_s2[10],l2t_l2b_rdma_fnl_wren_s2[8]}), | |
2833 | .din0 ({l2t_l2b_rdma_wren_s2[14],l2t_l2b_rdma_wren_s2[12],l2t_l2b_rdma_wren_s2[10],l2t_l2b_rdma_wren_s2[8]}), | |
2834 | .din1 (4'hF), | |
2835 | .sel0 (mbist_run_reg_v2_n), | |
2836 | .sel1 (mbist_run_reg_v2) | |
2837 | ); | |
2838 | ||
2839 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_4r__width_4 mux_rdma_word_wen_v3 | |
2840 | ( | |
2841 | .dout ({l2t_l2b_rdma_fnl_wren_s2[7],l2t_l2b_rdma_fnl_wren_s2[5],l2t_l2b_rdma_fnl_wren_s2[3],l2t_l2b_rdma_fnl_wren_s2[1]}), | |
2842 | .din0 ({l2t_l2b_rdma_wren_s2[7],l2t_l2b_rdma_wren_s2[5],l2t_l2b_rdma_wren_s2[3],l2t_l2b_rdma_wren_s2[1]}), | |
2843 | .din1 (4'hF), | |
2844 | .sel0 (mbist_run_reg_v3_n), | |
2845 | .sel1 (mbist_run_reg_v3) | |
2846 | ); | |
2847 | ||
2848 | l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_4r__width_4 mux_rdma_word_wen_v4 | |
2849 | ( | |
2850 | .dout ({l2t_l2b_rdma_fnl_wren_s2[6],l2t_l2b_rdma_fnl_wren_s2[4],l2t_l2b_rdma_fnl_wren_s2[2],l2t_l2b_rdma_fnl_wren_s2[0]}), | |
2851 | .din0 ({l2t_l2b_rdma_wren_s2[6],l2t_l2b_rdma_wren_s2[4],l2t_l2b_rdma_wren_s2[2],l2t_l2b_rdma_wren_s2[0]}), | |
2852 | .din1 (4'hF), | |
2853 | .sel0 (mbist_run_reg_v4_n), | |
2854 | .sel1 (mbist_run_reg_v4) | |
2855 | ); | |
2856 | ||
2857 | l2b_evict_dp_msff_macro__stack_6r__width_5 ff_rdma_control_regs_slice | |
2858 | ( | |
2859 | .scan_in(ff_rdma_control_regs_slice_scanin), | |
2860 | .scan_out(ff_rdma_control_regs_slice_scanout), | |
2861 | .dout ({error_qual,l2t_l2b_rdma_rden_r1, | |
2862 | l2t_l2b_rdma_rden_r2, l2t_l2b_rdma_rden_r3, | |
2863 | dbb_rst_l}), | |
2864 | .din ({ff_array_rd_ptr_din,l2t_l2b_rdma_rden_r0, | |
2865 | l2t_l2b_rdma_rden_r1, l2t_l2b_rdma_rden_r2, | |
2866 | wmr_l}), | |
2867 | .clk (l2clk), | |
2868 | // .en (mbist_run_reg_n), | |
2869 | .en (1'b1), | |
2870 | .se(se), | |
2871 | .siclk(siclk), | |
2872 | .soclk(soclk), | |
2873 | .pce_ov(pce_ov), | |
2874 | .stop(stop) | |
2875 | ); | |
2876 | ||
2877 | ||
2878 | l2b_evict_dp_msff_macro__stack_10r__width_9 ff_rdma_control_regs_slice_v1 | |
2879 | ( | |
2880 | .scan_in(ff_rdma_control_regs_slice_v1_scanin), | |
2881 | .scan_out(ff_rdma_control_regs_slice_v1_scanout), | |
2882 | .dout ({l2t_l2b_rdma_rden_r1_v1,l2t_l2b_rdma_rdwl_r1_v1[1:0], evict_l2t_l2b_rdma_wren_s3[15], evict_l2t_l2b_rdma_wren_s3[13], | |
2883 | evict_l2t_l2b_rdma_wren_s3[11], evict_l2t_l2b_rdma_wren_s3[9],l2t_l2b_rdma_wrwl_s3_v1[1:0]}), | |
2884 | .din ({l2t_l2b_rdma_rden_r0 ,l2t_l2b_rdma_rdwl_r0[1:0], l2t_l2b_rdma_fnl_wren_s2[15], l2t_l2b_rdma_fnl_wren_s2[13], | |
2885 | l2t_l2b_rdma_fnl_wren_s2[11], l2t_l2b_rdma_fnl_wren_s2[9],l2t_l2b_rdma_wrwl_s2[1:0]}), | |
2886 | .clk (l2clk), | |
2887 | .en (1'b1), | |
2888 | .se(se), | |
2889 | .siclk(siclk), | |
2890 | .soclk(soclk), | |
2891 | .pce_ov(pce_ov), | |
2892 | .stop(stop) | |
2893 | ); | |
2894 | ||
2895 | ||
2896 | l2b_evict_dp_msff_macro__stack_10r__width_9 ff_rdma_control_regs_slice_v2 | |
2897 | ( | |
2898 | .scan_in(ff_rdma_control_regs_slice_v2_scanin), | |
2899 | .scan_out(ff_rdma_control_regs_slice_v2_scanout), | |
2900 | .dout ({l2t_l2b_rdma_rden_r1_v2,l2t_l2b_rdma_rdwl_r1_v2[1:0], evict_l2t_l2b_rdma_wren_s3[14], evict_l2t_l2b_rdma_wren_s3[12], | |
2901 | evict_l2t_l2b_rdma_wren_s3[10], evict_l2t_l2b_rdma_wren_s3[8],l2t_l2b_rdma_wrwl_s3_v2[1:0]}), | |
2902 | .din ({l2t_l2b_rdma_rden_r0 ,l2t_l2b_rdma_rdwl_r0[1:0], l2t_l2b_rdma_fnl_wren_s2[14], l2t_l2b_rdma_fnl_wren_s2[12], | |
2903 | l2t_l2b_rdma_fnl_wren_s2[10], l2t_l2b_rdma_fnl_wren_s2[8],l2t_l2b_rdma_wrwl_s2[1:0]}), | |
2904 | .clk (l2clk), | |
2905 | .en (1'b1), | |
2906 | .se(se), | |
2907 | .siclk(siclk), | |
2908 | .soclk(soclk), | |
2909 | .pce_ov(pce_ov), | |
2910 | .stop(stop) | |
2911 | ); | |
2912 | ||
2913 | ||
2914 | ||
2915 | l2b_evict_dp_msff_macro__stack_10r__width_9 ff_rdma_control_regs_slice_v3 | |
2916 | ( | |
2917 | .scan_in(ff_rdma_control_regs_slice_v3_scanin), | |
2918 | .scan_out(ff_rdma_control_regs_slice_v3_scanout), | |
2919 | .dout ({l2t_l2b_rdma_rden_r1_v3,l2t_l2b_rdma_rdwl_r1_v3[1:0], evict_l2t_l2b_rdma_wren_s3[7], evict_l2t_l2b_rdma_wren_s3[5], | |
2920 | evict_l2t_l2b_rdma_wren_s3[3], evict_l2t_l2b_rdma_wren_s3[1],l2t_l2b_rdma_wrwl_s3_v3[1:0]}), | |
2921 | .din ({l2t_l2b_rdma_rden_r0 ,l2t_l2b_rdma_rdwl_r0[1:0], l2t_l2b_rdma_fnl_wren_s2[7], l2t_l2b_rdma_fnl_wren_s2[5], | |
2922 | l2t_l2b_rdma_fnl_wren_s2[3], l2t_l2b_rdma_fnl_wren_s2[1],l2t_l2b_rdma_wrwl_s2[1:0]}), | |
2923 | .clk (l2clk), | |
2924 | .en (1'b1), | |
2925 | .se(se), | |
2926 | .siclk(siclk), | |
2927 | .soclk(soclk), | |
2928 | .pce_ov(pce_ov), | |
2929 | .stop(stop) | |
2930 | ); | |
2931 | ||
2932 | ||
2933 | l2b_evict_dp_msff_macro__stack_10r__width_9 ff_rdma_control_regs_slice_v4 | |
2934 | ( | |
2935 | .scan_in(ff_rdma_control_regs_slice_v4_scanin), | |
2936 | .scan_out(ff_rdma_control_regs_slice_v4_scanout), | |
2937 | .dout ({l2t_l2b_rdma_rden_r1_v4,l2t_l2b_rdma_rdwl_r1_v4[1:0], evict_l2t_l2b_rdma_wren_s3[6], evict_l2t_l2b_rdma_wren_s3[4], | |
2938 | evict_l2t_l2b_rdma_wren_s3[2], evict_l2t_l2b_rdma_wren_s3[0],l2t_l2b_rdma_wrwl_s3_v4[1:0]}), | |
2939 | .din ({l2t_l2b_rdma_rden_r0 ,l2t_l2b_rdma_rdwl_r0[1:0], l2t_l2b_rdma_fnl_wren_s2[6], l2t_l2b_rdma_fnl_wren_s2[4], | |
2940 | l2t_l2b_rdma_fnl_wren_s2[2], l2t_l2b_rdma_fnl_wren_s2[0],l2t_l2b_rdma_wrwl_s2[1:0]}), | |
2941 | .clk (l2clk), | |
2942 | .en (1'b1), | |
2943 | .se(se), | |
2944 | .siclk(siclk), | |
2945 | .soclk(soclk), | |
2946 | .pce_ov(pce_ov), | |
2947 | .stop(stop) | |
2948 | ); | |
2949 | ||
2950 | ||
2951 | ||
2952 | ||
2953 | // fixscan start: | |
2954 | assign ff_mbist_run_scanin = scan_in ; | |
2955 | assign ff_mbist_run_v1_scanin = ff_mbist_run_scanout ; | |
2956 | assign ff_mbist_run_v2_scanin = ff_mbist_run_v1_scanout ; | |
2957 | assign ff_mbist_run_v3_scanin = ff_mbist_run_v2_scanout ; | |
2958 | assign ff_mbist_run_v4_scanin = ff_mbist_run_v3_scanout ; | |
2959 | assign ff_wb_array_dout_r3_1a_scanin = ff_mbist_run_v4_scanout ; | |
2960 | assign ff_wb_array_dout_r3_1b_scanin = ff_wb_array_dout_r3_1a_scanout; | |
2961 | assign ff_wb_array_dout_r3_1c_scanin = ff_wb_array_dout_r3_1b_scanout; | |
2962 | assign ff_wb_array_dout_r3_1d_scanin = ff_wb_array_dout_r3_1c_scanout; | |
2963 | assign ff_wb_array_dout_r3_2a_scanin = ff_wb_array_dout_r3_1d_scanout; | |
2964 | assign ff_wb_array_dout_r3_2b_scanin = ff_wb_array_dout_r3_2a_scanout; | |
2965 | assign ff_wb_array_dout_r3_2c_scanin = ff_wb_array_dout_r3_2b_scanout; | |
2966 | assign ff_wb_array_dout_r3_2d_scanin = ff_wb_array_dout_r3_2c_scanout; | |
2967 | assign ff_wb_array_dout_r3_3a_scanin = ff_wb_array_dout_r3_2d_scanout; | |
2968 | assign ff_wb_array_dout_r3_3b_scanin = ff_wb_array_dout_r3_3a_scanout; | |
2969 | assign ff_wb_array_dout_r3_3c_scanin = ff_wb_array_dout_r3_3b_scanout; | |
2970 | assign ff_wb_array_dout_r3_3d_scanin = ff_wb_array_dout_r3_3c_scanout; | |
2971 | assign ff_wb_array_dout_r3_4a_scanin = ff_wb_array_dout_r3_3d_scanout; | |
2972 | assign ff_wb_array_dout_r3_4b_scanin = ff_wb_array_dout_r3_4a_scanout; | |
2973 | assign ff_wb_array_dout_r3_4c_scanin = ff_wb_array_dout_r3_4b_scanout; | |
2974 | assign ff_wb_array_dout_r3_4d_scanin = ff_wb_array_dout_r3_4c_scanout; | |
2975 | assign ff_wb_array_dout_r4a_scanin = ff_wb_array_dout_r3_4d_scanout; | |
2976 | assign ff_wb_array_dout_r4b_scanin = ff_wb_array_dout_r4a_scanout; | |
2977 | assign ff_mbist_cmp_r4a_scanin = ff_wb_array_dout_r4b_scanout; | |
2978 | assign ff_mbist_cmp_r4b_scanin = ff_mbist_cmp_r4a_scanout ; | |
2979 | assign ff_fb_rw_fail_scanin = ff_mbist_cmp_r4b_scanout ; | |
2980 | assign ff_wb_array_dout_r5_31_0_scanin = ff_fb_rw_fail_scanout ; | |
2981 | assign ff_wb_array_dout_r5_63_32_scanin = ff_wb_array_dout_r5_31_0_scanout; | |
2982 | assign ff_evict_l2b_mcu_wr_data_r5_d1_scanin = ff_wb_array_dout_r5_63_32_scanout; | |
2983 | assign ff_evict_control_regs_slice_scanin = ff_evict_l2b_mcu_wr_data_r5_d1_scanout; | |
2984 | assign ff_mux_select0_2b_scanin = ff_evict_control_regs_slice_scanout; | |
2985 | assign ff_mux_select1_2a_scanin = ff_mux_select0_2b_scanout; | |
2986 | assign ff_mux_select2_1b_scanin = ff_mux_select1_2a_scanout; | |
2987 | assign ff_mux_select3_1a_scanin = ff_mux_select2_1b_scanout; | |
2988 | assign ff_wb_control_regs_slice_scanin = ff_mux_select3_1a_scanout; | |
2989 | assign ff_wb_control_regs_slice_v1_scanin = ff_wb_control_regs_slice_scanout; | |
2990 | assign ff_wb_control_regs_slice_v2_scanin = ff_wb_control_regs_slice_v1_scanout; | |
2991 | assign ff_wb_control_regs_slice_v3_scanin = ff_wb_control_regs_slice_v2_scanout; | |
2992 | assign ff_wb_control_regs_slice_v4_scanin = ff_wb_control_regs_slice_v3_scanout; | |
2993 | assign ff_rdma_control_regs_slice_scanin = ff_wb_control_regs_slice_v4_scanout; | |
2994 | assign ff_rdma_control_regs_slice_v1_scanin = ff_rdma_control_regs_slice_scanout; | |
2995 | assign ff_rdma_control_regs_slice_v2_scanin = ff_rdma_control_regs_slice_v1_scanout; | |
2996 | assign ff_rdma_control_regs_slice_v3_scanin = ff_rdma_control_regs_slice_v2_scanout; | |
2997 | assign ff_rdma_control_regs_slice_v4_scanin = ff_rdma_control_regs_slice_v3_scanout; | |
2998 | assign scan_out = ff_rdma_control_regs_slice_v4_scanout; | |
2999 | // fixscan end: | |
3000 | endmodule | |
3001 | ||
3002 | ||
3003 | ||
3004 | ||
3005 | ||
3006 | ||
3007 | // any PARAMS parms go into naming of macro | |
3008 | ||
3009 | module l2b_evict_dp_msff_macro__stack_26c__width_25 ( | |
3010 | din, | |
3011 | clk, | |
3012 | en, | |
3013 | se, | |
3014 | scan_in, | |
3015 | siclk, | |
3016 | soclk, | |
3017 | pce_ov, | |
3018 | stop, | |
3019 | dout, | |
3020 | scan_out); | |
3021 | wire l1clk; | |
3022 | wire siclk_out; | |
3023 | wire soclk_out; | |
3024 | wire [23:0] so; | |
3025 | ||
3026 | input [24:0] din; | |
3027 | ||
3028 | ||
3029 | input clk; | |
3030 | input en; | |
3031 | input se; | |
3032 | input scan_in; | |
3033 | input siclk; | |
3034 | input soclk; | |
3035 | input pce_ov; | |
3036 | input stop; | |
3037 | ||
3038 | ||
3039 | ||
3040 | output [24:0] dout; | |
3041 | ||
3042 | ||
3043 | output scan_out; | |
3044 | ||
3045 | ||
3046 | ||
3047 | ||
3048 | cl_dp1_l1hdr_8x c0_0 ( | |
3049 | .l2clk(clk), | |
3050 | .pce(en), | |
3051 | .aclk(siclk), | |
3052 | .bclk(soclk), | |
3053 | .l1clk(l1clk), | |
3054 | .se(se), | |
3055 | .pce_ov(pce_ov), | |
3056 | .stop(stop), | |
3057 | .siclk_out(siclk_out), | |
3058 | .soclk_out(soclk_out) | |
3059 | ); | |
3060 | dff #(25) d0_0 ( | |
3061 | .l1clk(l1clk), | |
3062 | .siclk(siclk_out), | |
3063 | .soclk(soclk_out), | |
3064 | .d(din[24:0]), | |
3065 | .si({scan_in,so[23:0]}), | |
3066 | .so({so[23:0],scan_out}), | |
3067 | .q(dout[24:0]) | |
3068 | ); | |
3069 | ||
3070 | ||
3071 | ||
3072 | ||
3073 | ||
3074 | ||
3075 | ||
3076 | ||
3077 | ||
3078 | ||
3079 | ||
3080 | ||
3081 | ||
3082 | ||
3083 | ||
3084 | ||
3085 | ||
3086 | ||
3087 | ||
3088 | ||
3089 | endmodule | |
3090 | ||
3091 | ||
3092 | ||
3093 | ||
3094 | ||
3095 | ||
3096 | ||
3097 | ||
3098 | ||
3099 | // | |
3100 | // invert macro | |
3101 | // | |
3102 | // | |
3103 | ||
3104 | ||
3105 | ||
3106 | ||
3107 | ||
3108 | module l2b_evict_dp_inv_macro__width_1 ( | |
3109 | din, | |
3110 | dout); | |
3111 | input [0:0] din; | |
3112 | output [0:0] dout; | |
3113 | ||
3114 | ||
3115 | ||
3116 | ||
3117 | ||
3118 | ||
3119 | inv #(1) d0_0 ( | |
3120 | .in(din[0:0]), | |
3121 | .out(dout[0:0]) | |
3122 | ); | |
3123 | ||
3124 | ||
3125 | ||
3126 | ||
3127 | ||
3128 | ||
3129 | ||
3130 | ||
3131 | ||
3132 | endmodule | |
3133 | ||
3134 | ||
3135 | ||
3136 | ||
3137 | ||
3138 | ||
3139 | ||
3140 | ||
3141 | ||
3142 | // any PARAMS parms go into naming of macro | |
3143 | ||
3144 | module l2b_evict_dp_msff_macro__stack_8c__width_8 ( | |
3145 | din, | |
3146 | clk, | |
3147 | en, | |
3148 | se, | |
3149 | scan_in, | |
3150 | siclk, | |
3151 | soclk, | |
3152 | pce_ov, | |
3153 | stop, | |
3154 | dout, | |
3155 | scan_out); | |
3156 | wire l1clk; | |
3157 | wire siclk_out; | |
3158 | wire soclk_out; | |
3159 | wire [6:0] so; | |
3160 | ||
3161 | input [7:0] din; | |
3162 | ||
3163 | ||
3164 | input clk; | |
3165 | input en; | |
3166 | input se; | |
3167 | input scan_in; | |
3168 | input siclk; | |
3169 | input soclk; | |
3170 | input pce_ov; | |
3171 | input stop; | |
3172 | ||
3173 | ||
3174 | ||
3175 | output [7:0] dout; | |
3176 | ||
3177 | ||
3178 | output scan_out; | |
3179 | ||
3180 | ||
3181 | ||
3182 | ||
3183 | cl_dp1_l1hdr_8x c0_0 ( | |
3184 | .l2clk(clk), | |
3185 | .pce(en), | |
3186 | .aclk(siclk), | |
3187 | .bclk(soclk), | |
3188 | .l1clk(l1clk), | |
3189 | .se(se), | |
3190 | .pce_ov(pce_ov), | |
3191 | .stop(stop), | |
3192 | .siclk_out(siclk_out), | |
3193 | .soclk_out(soclk_out) | |
3194 | ); | |
3195 | dff #(8) d0_0 ( | |
3196 | .l1clk(l1clk), | |
3197 | .siclk(siclk_out), | |
3198 | .soclk(soclk_out), | |
3199 | .d(din[7:0]), | |
3200 | .si({scan_in,so[6:0]}), | |
3201 | .so({so[6:0],scan_out}), | |
3202 | .q(dout[7:0]) | |
3203 | ); | |
3204 | ||
3205 | ||
3206 | ||
3207 | ||
3208 | ||
3209 | ||
3210 | ||
3211 | ||
3212 | ||
3213 | ||
3214 | ||
3215 | ||
3216 | ||
3217 | ||
3218 | ||
3219 | ||
3220 | ||
3221 | ||
3222 | ||
3223 | ||
3224 | endmodule | |
3225 | ||
3226 | ||
3227 | ||
3228 | ||
3229 | ||
3230 | ||
3231 | ||
3232 | ||
3233 | ||
3234 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3235 | // also for pass-gate with decoder | |
3236 | ||
3237 | ||
3238 | ||
3239 | ||
3240 | ||
3241 | // any PARAMS parms go into naming of macro | |
3242 | ||
3243 | module l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_14r__width_14 ( | |
3244 | din0, | |
3245 | sel0, | |
3246 | din1, | |
3247 | sel1, | |
3248 | dout); | |
3249 | wire buffout0; | |
3250 | wire buffout1; | |
3251 | ||
3252 | input [13:0] din0; | |
3253 | input sel0; | |
3254 | input [13:0] din1; | |
3255 | input sel1; | |
3256 | output [13:0] dout; | |
3257 | ||
3258 | ||
3259 | ||
3260 | ||
3261 | ||
3262 | cl_dp1_muxbuff2_8x c0_0 ( | |
3263 | .in0(sel0), | |
3264 | .in1(sel1), | |
3265 | .out0(buffout0), | |
3266 | .out1(buffout1) | |
3267 | ); | |
3268 | mux2s #(14) d0_0 ( | |
3269 | .sel0(buffout0), | |
3270 | .sel1(buffout1), | |
3271 | .in0(din0[13:0]), | |
3272 | .in1(din1[13:0]), | |
3273 | .dout(dout[13:0]) | |
3274 | ); | |
3275 | ||
3276 | ||
3277 | ||
3278 | ||
3279 | ||
3280 | ||
3281 | ||
3282 | ||
3283 | ||
3284 | ||
3285 | ||
3286 | ||
3287 | ||
3288 | endmodule | |
3289 | ||
3290 | ||
3291 | // | |
3292 | // buff macro | |
3293 | // | |
3294 | // | |
3295 | ||
3296 | ||
3297 | ||
3298 | ||
3299 | ||
3300 | module l2b_evict_dp_buff_macro__width_1 ( | |
3301 | din, | |
3302 | dout); | |
3303 | input [0:0] din; | |
3304 | output [0:0] dout; | |
3305 | ||
3306 | ||
3307 | ||
3308 | ||
3309 | ||
3310 | ||
3311 | buff #(1) d0_0 ( | |
3312 | .in(din[0:0]), | |
3313 | .out(dout[0:0]) | |
3314 | ); | |
3315 | ||
3316 | ||
3317 | ||
3318 | ||
3319 | ||
3320 | ||
3321 | ||
3322 | ||
3323 | endmodule | |
3324 | ||
3325 | ||
3326 | ||
3327 | ||
3328 | ||
3329 | // | |
3330 | // buff macro | |
3331 | // | |
3332 | // | |
3333 | ||
3334 | ||
3335 | ||
3336 | ||
3337 | ||
3338 | module l2b_evict_dp_buff_macro__width_3 ( | |
3339 | din, | |
3340 | dout); | |
3341 | input [2:0] din; | |
3342 | output [2:0] dout; | |
3343 | ||
3344 | ||
3345 | ||
3346 | ||
3347 | ||
3348 | ||
3349 | buff #(3) d0_0 ( | |
3350 | .in(din[2:0]), | |
3351 | .out(dout[2:0]) | |
3352 | ); | |
3353 | ||
3354 | ||
3355 | ||
3356 | ||
3357 | ||
3358 | ||
3359 | ||
3360 | ||
3361 | endmodule | |
3362 | ||
3363 | ||
3364 | ||
3365 | ||
3366 | ||
3367 | // | |
3368 | // or macro for ports = 2,3 | |
3369 | // | |
3370 | // | |
3371 | ||
3372 | ||
3373 | ||
3374 | ||
3375 | ||
3376 | module l2b_evict_dp_or_macro__width_1 ( | |
3377 | din0, | |
3378 | din1, | |
3379 | dout); | |
3380 | input [0:0] din0; | |
3381 | input [0:0] din1; | |
3382 | output [0:0] dout; | |
3383 | ||
3384 | ||
3385 | ||
3386 | ||
3387 | ||
3388 | ||
3389 | or2 #(1) d0_0 ( | |
3390 | .in0(din0[0:0]), | |
3391 | .in1(din1[0:0]), | |
3392 | .out(dout[0:0]) | |
3393 | ); | |
3394 | ||
3395 | ||
3396 | ||
3397 | ||
3398 | ||
3399 | ||
3400 | ||
3401 | ||
3402 | ||
3403 | endmodule | |
3404 | ||
3405 | ||
3406 | ||
3407 | ||
3408 | ||
3409 | // | |
3410 | // or macro for ports = 2,3 | |
3411 | // | |
3412 | // | |
3413 | ||
3414 | ||
3415 | ||
3416 | ||
3417 | ||
3418 | module l2b_evict_dp_or_macro__ports_2__width_1 ( | |
3419 | din0, | |
3420 | din1, | |
3421 | dout); | |
3422 | input [0:0] din0; | |
3423 | input [0:0] din1; | |
3424 | output [0:0] dout; | |
3425 | ||
3426 | ||
3427 | ||
3428 | ||
3429 | ||
3430 | ||
3431 | or2 #(1) d0_0 ( | |
3432 | .in0(din0[0:0]), | |
3433 | .in1(din1[0:0]), | |
3434 | .out(dout[0:0]) | |
3435 | ); | |
3436 | ||
3437 | ||
3438 | ||
3439 | ||
3440 | ||
3441 | ||
3442 | ||
3443 | ||
3444 | ||
3445 | endmodule | |
3446 | ||
3447 | ||
3448 | ||
3449 | ||
3450 | ||
3451 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3452 | // also for pass-gate with decoder | |
3453 | ||
3454 | ||
3455 | ||
3456 | ||
3457 | ||
3458 | // any PARAMS parms go into naming of macro | |
3459 | ||
3460 | module l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c__width_1 ( | |
3461 | din0, | |
3462 | sel0, | |
3463 | din1, | |
3464 | sel1, | |
3465 | dout); | |
3466 | wire buffout0; | |
3467 | wire buffout1; | |
3468 | ||
3469 | input [0:0] din0; | |
3470 | input sel0; | |
3471 | input [0:0] din1; | |
3472 | input sel1; | |
3473 | output [0:0] dout; | |
3474 | ||
3475 | ||
3476 | ||
3477 | ||
3478 | ||
3479 | cl_dp1_muxbuff2_8x c0_0 ( | |
3480 | .in0(sel0), | |
3481 | .in1(sel1), | |
3482 | .out0(buffout0), | |
3483 | .out1(buffout1) | |
3484 | ); | |
3485 | mux2s #(1) d0_0 ( | |
3486 | .sel0(buffout0), | |
3487 | .sel1(buffout1), | |
3488 | .in0(din0[0:0]), | |
3489 | .in1(din1[0:0]), | |
3490 | .dout(dout[0:0]) | |
3491 | ); | |
3492 | ||
3493 | ||
3494 | ||
3495 | ||
3496 | ||
3497 | ||
3498 | ||
3499 | ||
3500 | ||
3501 | ||
3502 | ||
3503 | ||
3504 | ||
3505 | endmodule | |
3506 | ||
3507 | ||
3508 | // | |
3509 | // and macro for ports = 2,3,4 | |
3510 | // | |
3511 | // | |
3512 | ||
3513 | ||
3514 | ||
3515 | ||
3516 | ||
3517 | module l2b_evict_dp_and_macro__width_1 ( | |
3518 | din0, | |
3519 | din1, | |
3520 | dout); | |
3521 | input [0:0] din0; | |
3522 | input [0:0] din1; | |
3523 | output [0:0] dout; | |
3524 | ||
3525 | ||
3526 | ||
3527 | ||
3528 | ||
3529 | ||
3530 | and2 #(1) d0_0 ( | |
3531 | .in0(din0[0:0]), | |
3532 | .in1(din1[0:0]), | |
3533 | .out(dout[0:0]) | |
3534 | ); | |
3535 | ||
3536 | ||
3537 | ||
3538 | ||
3539 | ||
3540 | ||
3541 | ||
3542 | ||
3543 | ||
3544 | endmodule | |
3545 | ||
3546 | ||
3547 | ||
3548 | ||
3549 | ||
3550 | // | |
3551 | // nand macro for ports = 2,3,4 | |
3552 | // | |
3553 | // | |
3554 | ||
3555 | ||
3556 | ||
3557 | ||
3558 | ||
3559 | module l2b_evict_dp_nand_macro__dnand_32x__ports_2__width_3 ( | |
3560 | din0, | |
3561 | din1, | |
3562 | dout); | |
3563 | input [2:0] din0; | |
3564 | input [2:0] din1; | |
3565 | output [2:0] dout; | |
3566 | ||
3567 | ||
3568 | ||
3569 | ||
3570 | ||
3571 | ||
3572 | nand2 #(3) d0_0 ( | |
3573 | .in0(din0[2:0]), | |
3574 | .in1(din1[2:0]), | |
3575 | .out(dout[2:0]) | |
3576 | ); | |
3577 | ||
3578 | ||
3579 | ||
3580 | ||
3581 | ||
3582 | ||
3583 | ||
3584 | ||
3585 | ||
3586 | endmodule | |
3587 | ||
3588 | ||
3589 | ||
3590 | ||
3591 | ||
3592 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3593 | // also for pass-gate with decoder | |
3594 | ||
3595 | ||
3596 | ||
3597 | ||
3598 | ||
3599 | // any PARAMS parms go into naming of macro | |
3600 | ||
3601 | module l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_40r__width_39 ( | |
3602 | din0, | |
3603 | sel0, | |
3604 | din1, | |
3605 | sel1, | |
3606 | dout); | |
3607 | wire buffout0; | |
3608 | wire buffout1; | |
3609 | ||
3610 | input [38:0] din0; | |
3611 | input sel0; | |
3612 | input [38:0] din1; | |
3613 | input sel1; | |
3614 | output [38:0] dout; | |
3615 | ||
3616 | ||
3617 | ||
3618 | ||
3619 | ||
3620 | cl_dp1_muxbuff2_8x c0_0 ( | |
3621 | .in0(sel0), | |
3622 | .in1(sel1), | |
3623 | .out0(buffout0), | |
3624 | .out1(buffout1) | |
3625 | ); | |
3626 | mux2s #(39) d0_0 ( | |
3627 | .sel0(buffout0), | |
3628 | .sel1(buffout1), | |
3629 | .in0(din0[38:0]), | |
3630 | .in1(din1[38:0]), | |
3631 | .dout(dout[38:0]) | |
3632 | ); | |
3633 | ||
3634 | ||
3635 | ||
3636 | ||
3637 | ||
3638 | ||
3639 | ||
3640 | ||
3641 | ||
3642 | ||
3643 | ||
3644 | ||
3645 | ||
3646 | endmodule | |
3647 | ||
3648 | ||
3649 | ||
3650 | ||
3651 | ||
3652 | ||
3653 | // any PARAMS parms go into naming of macro | |
3654 | ||
3655 | module l2b_evict_dp_msff_macro__stack_40r__width_39 ( | |
3656 | din, | |
3657 | clk, | |
3658 | en, | |
3659 | se, | |
3660 | scan_in, | |
3661 | siclk, | |
3662 | soclk, | |
3663 | pce_ov, | |
3664 | stop, | |
3665 | dout, | |
3666 | scan_out); | |
3667 | wire l1clk; | |
3668 | wire siclk_out; | |
3669 | wire soclk_out; | |
3670 | wire [37:0] so; | |
3671 | ||
3672 | input [38:0] din; | |
3673 | ||
3674 | ||
3675 | input clk; | |
3676 | input en; | |
3677 | input se; | |
3678 | input scan_in; | |
3679 | input siclk; | |
3680 | input soclk; | |
3681 | input pce_ov; | |
3682 | input stop; | |
3683 | ||
3684 | ||
3685 | ||
3686 | output [38:0] dout; | |
3687 | ||
3688 | ||
3689 | output scan_out; | |
3690 | ||
3691 | ||
3692 | ||
3693 | ||
3694 | cl_dp1_l1hdr_8x c0_0 ( | |
3695 | .l2clk(clk), | |
3696 | .pce(en), | |
3697 | .aclk(siclk), | |
3698 | .bclk(soclk), | |
3699 | .l1clk(l1clk), | |
3700 | .se(se), | |
3701 | .pce_ov(pce_ov), | |
3702 | .stop(stop), | |
3703 | .siclk_out(siclk_out), | |
3704 | .soclk_out(soclk_out) | |
3705 | ); | |
3706 | dff #(39) d0_0 ( | |
3707 | .l1clk(l1clk), | |
3708 | .siclk(siclk_out), | |
3709 | .soclk(soclk_out), | |
3710 | .d(din[38:0]), | |
3711 | .si({scan_in,so[37:0]}), | |
3712 | .so({so[37:0],scan_out}), | |
3713 | .q(dout[38:0]) | |
3714 | ); | |
3715 | ||
3716 | ||
3717 | ||
3718 | ||
3719 | ||
3720 | ||
3721 | ||
3722 | ||
3723 | ||
3724 | ||
3725 | ||
3726 | ||
3727 | ||
3728 | ||
3729 | ||
3730 | ||
3731 | ||
3732 | ||
3733 | ||
3734 | ||
3735 | endmodule | |
3736 | ||
3737 | ||
3738 | ||
3739 | ||
3740 | ||
3741 | ||
3742 | ||
3743 | ||
3744 | ||
3745 | // | |
3746 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
3747 | // | |
3748 | // | |
3749 | ||
3750 | ||
3751 | ||
3752 | ||
3753 | ||
3754 | module l2b_evict_dp_cmp_macro__width_4 ( | |
3755 | din0, | |
3756 | din1, | |
3757 | dout); | |
3758 | input [3:0] din0; | |
3759 | input [3:0] din1; | |
3760 | output dout; | |
3761 | ||
3762 | ||
3763 | ||
3764 | ||
3765 | ||
3766 | ||
3767 | cmp #(4) m0_0 ( | |
3768 | .in0(din0[3:0]), | |
3769 | .in1(din1[3:0]), | |
3770 | .out(dout) | |
3771 | ); | |
3772 | ||
3773 | ||
3774 | ||
3775 | ||
3776 | ||
3777 | ||
3778 | ||
3779 | ||
3780 | ||
3781 | ||
3782 | endmodule | |
3783 | ||
3784 | ||
3785 | ||
3786 | ||
3787 | ||
3788 | // | |
3789 | // nor macro for ports = 2,3 | |
3790 | // | |
3791 | // | |
3792 | ||
3793 | ||
3794 | ||
3795 | ||
3796 | ||
3797 | module l2b_evict_dp_nor_macro__ports_3__width_1 ( | |
3798 | din0, | |
3799 | din1, | |
3800 | din2, | |
3801 | dout); | |
3802 | input [0:0] din0; | |
3803 | input [0:0] din1; | |
3804 | input [0:0] din2; | |
3805 | output [0:0] dout; | |
3806 | ||
3807 | ||
3808 | ||
3809 | ||
3810 | ||
3811 | ||
3812 | nor3 #(1) d0_0 ( | |
3813 | .in0(din0[0:0]), | |
3814 | .in1(din1[0:0]), | |
3815 | .in2(din2[0:0]), | |
3816 | .out(dout[0:0]) | |
3817 | ); | |
3818 | ||
3819 | ||
3820 | ||
3821 | ||
3822 | ||
3823 | ||
3824 | ||
3825 | endmodule | |
3826 | ||
3827 | ||
3828 | ||
3829 | ||
3830 | ||
3831 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3832 | // also for pass-gate with decoder | |
3833 | ||
3834 | ||
3835 | ||
3836 | ||
3837 | ||
3838 | // any PARAMS parms go into naming of macro | |
3839 | ||
3840 | module l2b_evict_dp_mux_macro__mux_pgpe__ports_4__stack_40r__width_39 ( | |
3841 | din0, | |
3842 | din1, | |
3843 | din2, | |
3844 | din3, | |
3845 | sel0, | |
3846 | sel1, | |
3847 | sel2, | |
3848 | muxtst, | |
3849 | test, | |
3850 | dout); | |
3851 | wire psel0; | |
3852 | wire psel1; | |
3853 | wire psel2; | |
3854 | wire psel3; | |
3855 | ||
3856 | input [38:0] din0; | |
3857 | input [38:0] din1; | |
3858 | input [38:0] din2; | |
3859 | input [38:0] din3; | |
3860 | input sel0; | |
3861 | input sel1; | |
3862 | input sel2; | |
3863 | input muxtst; | |
3864 | input test; | |
3865 | output [38:0] dout; | |
3866 | ||
3867 | ||
3868 | ||
3869 | ||
3870 | ||
3871 | cl_dp1_penc4_8x c0_0 ( | |
3872 | .sel0(sel0), | |
3873 | .sel1(sel1), | |
3874 | .sel2(sel2), | |
3875 | .psel0(psel0), | |
3876 | .psel1(psel1), | |
3877 | .psel2(psel2), | |
3878 | .psel3(psel3), | |
3879 | .test(test) | |
3880 | ); | |
3881 | ||
3882 | mux4 #(39) d0_0 ( | |
3883 | .sel0(psel0), | |
3884 | .sel1(psel1), | |
3885 | .sel2(psel2), | |
3886 | .sel3(psel3), | |
3887 | .in0(din0[38:0]), | |
3888 | .in1(din1[38:0]), | |
3889 | .in2(din2[38:0]), | |
3890 | .in3(din3[38:0]), | |
3891 | .dout(dout[38:0]), | |
3892 | .muxtst(muxtst) | |
3893 | ); | |
3894 | ||
3895 | ||
3896 | ||
3897 | ||
3898 | ||
3899 | ||
3900 | ||
3901 | ||
3902 | ||
3903 | ||
3904 | ||
3905 | ||
3906 | ||
3907 | endmodule | |
3908 | ||
3909 | ||
3910 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3911 | // also for pass-gate with decoder | |
3912 | ||
3913 | ||
3914 | ||
3915 | ||
3916 | ||
3917 | // any PARAMS parms go into naming of macro | |
3918 | ||
3919 | module l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_2c ( | |
3920 | din0, | |
3921 | sel0, | |
3922 | din1, | |
3923 | sel1, | |
3924 | dout); | |
3925 | wire buffout0; | |
3926 | wire buffout1; | |
3927 | ||
3928 | input [0:0] din0; | |
3929 | input sel0; | |
3930 | input [0:0] din1; | |
3931 | input sel1; | |
3932 | output [0:0] dout; | |
3933 | ||
3934 | ||
3935 | ||
3936 | ||
3937 | ||
3938 | cl_dp1_muxbuff2_8x c0_0 ( | |
3939 | .in0(sel0), | |
3940 | .in1(sel1), | |
3941 | .out0(buffout0), | |
3942 | .out1(buffout1) | |
3943 | ); | |
3944 | mux2s #(1) d0_0 ( | |
3945 | .sel0(buffout0), | |
3946 | .sel1(buffout1), | |
3947 | .in0(din0[0:0]), | |
3948 | .in1(din1[0:0]), | |
3949 | .dout(dout[0:0]) | |
3950 | ); | |
3951 | ||
3952 | ||
3953 | ||
3954 | ||
3955 | ||
3956 | ||
3957 | ||
3958 | ||
3959 | ||
3960 | ||
3961 | ||
3962 | ||
3963 | ||
3964 | endmodule | |
3965 | ||
3966 | ||
3967 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3968 | // also for pass-gate with decoder | |
3969 | ||
3970 | ||
3971 | ||
3972 | ||
3973 | ||
3974 | // any PARAMS parms go into naming of macro | |
3975 | ||
3976 | module l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_40r__width_39 ( | |
3977 | din0, | |
3978 | sel0, | |
3979 | din1, | |
3980 | sel1, | |
3981 | dout); | |
3982 | wire buffout0; | |
3983 | wire buffout1; | |
3984 | ||
3985 | input [38:0] din0; | |
3986 | input sel0; | |
3987 | input [38:0] din1; | |
3988 | input sel1; | |
3989 | output [38:0] dout; | |
3990 | ||
3991 | ||
3992 | ||
3993 | ||
3994 | ||
3995 | cl_dp1_muxbuff2_8x c0_0 ( | |
3996 | .in0(sel0), | |
3997 | .in1(sel1), | |
3998 | .out0(buffout0), | |
3999 | .out1(buffout1) | |
4000 | ); | |
4001 | mux2s #(39) d0_0 ( | |
4002 | .sel0(buffout0), | |
4003 | .sel1(buffout1), | |
4004 | .in0(din0[38:0]), | |
4005 | .in1(din1[38:0]), | |
4006 | .dout(dout[38:0]) | |
4007 | ); | |
4008 | ||
4009 | ||
4010 | ||
4011 | ||
4012 | ||
4013 | ||
4014 | ||
4015 | ||
4016 | ||
4017 | ||
4018 | ||
4019 | ||
4020 | ||
4021 | endmodule | |
4022 | ||
4023 | ||
4024 | // | |
4025 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
4026 | // | |
4027 | // | |
4028 | ||
4029 | ||
4030 | ||
4031 | ||
4032 | ||
4033 | module l2b_evict_dp_cmp_macro__width_64 ( | |
4034 | din0, | |
4035 | din1, | |
4036 | dout); | |
4037 | input [63:0] din0; | |
4038 | input [63:0] din1; | |
4039 | output dout; | |
4040 | ||
4041 | ||
4042 | ||
4043 | ||
4044 | ||
4045 | ||
4046 | cmp #(64) m0_0 ( | |
4047 | .in0(din0[63:0]), | |
4048 | .in1(din1[63:0]), | |
4049 | .out(dout) | |
4050 | ); | |
4051 | ||
4052 | ||
4053 | ||
4054 | ||
4055 | ||
4056 | ||
4057 | ||
4058 | ||
4059 | ||
4060 | ||
4061 | endmodule | |
4062 | ||
4063 | ||
4064 | ||
4065 | ||
4066 | ||
4067 | // | |
4068 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
4069 | // | |
4070 | // | |
4071 | ||
4072 | ||
4073 | ||
4074 | ||
4075 | ||
4076 | module l2b_evict_dp_cmp_macro__width_16 ( | |
4077 | din0, | |
4078 | din1, | |
4079 | dout); | |
4080 | input [15:0] din0; | |
4081 | input [15:0] din1; | |
4082 | output dout; | |
4083 | ||
4084 | ||
4085 | ||
4086 | ||
4087 | ||
4088 | ||
4089 | cmp #(16) m0_0 ( | |
4090 | .in0(din0[15:0]), | |
4091 | .in1(din1[15:0]), | |
4092 | .out(dout) | |
4093 | ); | |
4094 | ||
4095 | ||
4096 | ||
4097 | ||
4098 | ||
4099 | ||
4100 | ||
4101 | ||
4102 | ||
4103 | ||
4104 | endmodule | |
4105 | ||
4106 | ||
4107 | ||
4108 | ||
4109 | ||
4110 | // | |
4111 | // nand macro for ports = 2,3,4 | |
4112 | // | |
4113 | // | |
4114 | ||
4115 | ||
4116 | ||
4117 | ||
4118 | ||
4119 | module l2b_evict_dp_nand_macro__width_1 ( | |
4120 | din0, | |
4121 | din1, | |
4122 | dout); | |
4123 | input [0:0] din0; | |
4124 | input [0:0] din1; | |
4125 | output [0:0] dout; | |
4126 | ||
4127 | ||
4128 | ||
4129 | ||
4130 | ||
4131 | ||
4132 | nand2 #(1) d0_0 ( | |
4133 | .in0(din0[0:0]), | |
4134 | .in1(din1[0:0]), | |
4135 | .out(dout[0:0]) | |
4136 | ); | |
4137 | ||
4138 | ||
4139 | ||
4140 | ||
4141 | ||
4142 | ||
4143 | ||
4144 | ||
4145 | ||
4146 | endmodule | |
4147 | ||
4148 | ||
4149 | ||
4150 | ||
4151 | ||
4152 | ||
4153 | ||
4154 | ||
4155 | ||
4156 | // any PARAMS parms go into naming of macro | |
4157 | ||
4158 | module l2b_evict_dp_msff_macro__stack_8c__width_6 ( | |
4159 | din, | |
4160 | clk, | |
4161 | en, | |
4162 | se, | |
4163 | scan_in, | |
4164 | siclk, | |
4165 | soclk, | |
4166 | pce_ov, | |
4167 | stop, | |
4168 | dout, | |
4169 | scan_out); | |
4170 | wire l1clk; | |
4171 | wire siclk_out; | |
4172 | wire soclk_out; | |
4173 | wire [4:0] so; | |
4174 | ||
4175 | input [5:0] din; | |
4176 | ||
4177 | ||
4178 | input clk; | |
4179 | input en; | |
4180 | input se; | |
4181 | input scan_in; | |
4182 | input siclk; | |
4183 | input soclk; | |
4184 | input pce_ov; | |
4185 | input stop; | |
4186 | ||
4187 | ||
4188 | ||
4189 | output [5:0] dout; | |
4190 | ||
4191 | ||
4192 | output scan_out; | |
4193 | ||
4194 | ||
4195 | ||
4196 | ||
4197 | cl_dp1_l1hdr_8x c0_0 ( | |
4198 | .l2clk(clk), | |
4199 | .pce(en), | |
4200 | .aclk(siclk), | |
4201 | .bclk(soclk), | |
4202 | .l1clk(l1clk), | |
4203 | .se(se), | |
4204 | .pce_ov(pce_ov), | |
4205 | .stop(stop), | |
4206 | .siclk_out(siclk_out), | |
4207 | .soclk_out(soclk_out) | |
4208 | ); | |
4209 | dff #(6) d0_0 ( | |
4210 | .l1clk(l1clk), | |
4211 | .siclk(siclk_out), | |
4212 | .soclk(soclk_out), | |
4213 | .d(din[5:0]), | |
4214 | .si({scan_in,so[4:0]}), | |
4215 | .so({so[4:0],scan_out}), | |
4216 | .q(dout[5:0]) | |
4217 | ); | |
4218 | ||
4219 | ||
4220 | ||
4221 | ||
4222 | endmodule | |
4223 | ||
4224 | ||
4225 | ||
4226 | ||
4227 | // | |
4228 | // xor macro for ports = 2,3 | |
4229 | // | |
4230 | // | |
4231 | ||
4232 | ||
4233 | ||
4234 | ||
4235 | ||
4236 | module l2b_evict_dp_xor_macro__dxor_8x__ports_3__width_1 ( | |
4237 | din0, | |
4238 | din1, | |
4239 | din2, | |
4240 | dout); | |
4241 | input [0:0] din0; | |
4242 | input [0:0] din1; | |
4243 | input [0:0] din2; | |
4244 | output [0:0] dout; | |
4245 | ||
4246 | ||
4247 | ||
4248 | ||
4249 | ||
4250 | xor3 #(1) d0_0 ( | |
4251 | .in0(din0[0:0]), | |
4252 | .in1(din1[0:0]), | |
4253 | .in2(din2[0:0]), | |
4254 | .out(dout[0:0]) | |
4255 | ); | |
4256 | ||
4257 | ||
4258 | ||
4259 | ||
4260 | ||
4261 | ||
4262 | ||
4263 | ||
4264 | endmodule | |
4265 | ||
4266 | ||
4267 | ||
4268 | ||
4269 | ||
4270 | // | |
4271 | // xor macro for ports = 2,3 | |
4272 | // | |
4273 | // | |
4274 | ||
4275 | ||
4276 | ||
4277 | ||
4278 | ||
4279 | module l2b_evict_dp_xor_macro__dxor_16x__ports_3__width_1 ( | |
4280 | din0, | |
4281 | din1, | |
4282 | din2, | |
4283 | dout); | |
4284 | input [0:0] din0; | |
4285 | input [0:0] din1; | |
4286 | input [0:0] din2; | |
4287 | output [0:0] dout; | |
4288 | ||
4289 | ||
4290 | ||
4291 | ||
4292 | ||
4293 | xor3 #(1) d0_0 ( | |
4294 | .in0(din0[0:0]), | |
4295 | .in1(din1[0:0]), | |
4296 | .in2(din2[0:0]), | |
4297 | .out(dout[0:0]) | |
4298 | ); | |
4299 | ||
4300 | ||
4301 | ||
4302 | ||
4303 | ||
4304 | ||
4305 | ||
4306 | ||
4307 | endmodule | |
4308 | ||
4309 | ||
4310 | ||
4311 | ||
4312 | ||
4313 | // | |
4314 | // xor macro for ports = 2,3 | |
4315 | // | |
4316 | // | |
4317 | ||
4318 | ||
4319 | ||
4320 | ||
4321 | ||
4322 | module l2b_evict_dp_xor_macro__dxor_16x__ports_2__width_1 ( | |
4323 | din0, | |
4324 | din1, | |
4325 | dout); | |
4326 | input [0:0] din0; | |
4327 | input [0:0] din1; | |
4328 | output [0:0] dout; | |
4329 | ||
4330 | ||
4331 | ||
4332 | ||
4333 | ||
4334 | xor2 #(1) d0_0 ( | |
4335 | .in0(din0[0:0]), | |
4336 | .in1(din1[0:0]), | |
4337 | .out(dout[0:0]) | |
4338 | ); | |
4339 | ||
4340 | ||
4341 | ||
4342 | ||
4343 | ||
4344 | ||
4345 | ||
4346 | ||
4347 | endmodule | |
4348 | ||
4349 | ||
4350 | ||
4351 | ||
4352 | ||
4353 | // | |
4354 | // invert macro | |
4355 | // | |
4356 | // | |
4357 | ||
4358 | ||
4359 | ||
4360 | ||
4361 | ||
4362 | module l2b_evict_dp_inv_macro__dinv_32x__stack_1r__width_1 ( | |
4363 | din, | |
4364 | dout); | |
4365 | input [0:0] din; | |
4366 | output [0:0] dout; | |
4367 | ||
4368 | ||
4369 | ||
4370 | ||
4371 | ||
4372 | ||
4373 | inv #(1) d0_0 ( | |
4374 | .in(din[0:0]), | |
4375 | .out(dout[0:0]) | |
4376 | ); | |
4377 | ||
4378 | ||
4379 | ||
4380 | ||
4381 | ||
4382 | ||
4383 | ||
4384 | ||
4385 | ||
4386 | endmodule | |
4387 | ||
4388 | ||
4389 | ||
4390 | ||
4391 | ||
4392 | // | |
4393 | // nand macro for ports = 2,3,4 | |
4394 | // | |
4395 | // | |
4396 | ||
4397 | ||
4398 | ||
4399 | ||
4400 | ||
4401 | module l2b_evict_dp_nand_macro__ports_3__width_1 ( | |
4402 | din0, | |
4403 | din1, | |
4404 | din2, | |
4405 | dout); | |
4406 | input [0:0] din0; | |
4407 | input [0:0] din1; | |
4408 | input [0:0] din2; | |
4409 | output [0:0] dout; | |
4410 | ||
4411 | ||
4412 | ||
4413 | ||
4414 | ||
4415 | ||
4416 | nand3 #(1) d0_0 ( | |
4417 | .in0(din0[0:0]), | |
4418 | .in1(din1[0:0]), | |
4419 | .in2(din2[0:0]), | |
4420 | .out(dout[0:0]) | |
4421 | ); | |
4422 | ||
4423 | ||
4424 | ||
4425 | ||
4426 | ||
4427 | ||
4428 | ||
4429 | ||
4430 | ||
4431 | endmodule | |
4432 | ||
4433 | ||
4434 | ||
4435 | ||
4436 | ||
4437 | // | |
4438 | // nor macro for ports = 2,3 | |
4439 | // | |
4440 | // | |
4441 | ||
4442 | ||
4443 | ||
4444 | ||
4445 | ||
4446 | module l2b_evict_dp_nor_macro__ports_2__width_1 ( | |
4447 | din0, | |
4448 | din1, | |
4449 | dout); | |
4450 | input [0:0] din0; | |
4451 | input [0:0] din1; | |
4452 | output [0:0] dout; | |
4453 | ||
4454 | ||
4455 | ||
4456 | ||
4457 | ||
4458 | ||
4459 | nor2 #(1) d0_0 ( | |
4460 | .in0(din0[0:0]), | |
4461 | .in1(din1[0:0]), | |
4462 | .out(dout[0:0]) | |
4463 | ); | |
4464 | ||
4465 | ||
4466 | ||
4467 | ||
4468 | ||
4469 | ||
4470 | ||
4471 | endmodule | |
4472 | ||
4473 | ||
4474 | ||
4475 | ||
4476 | ||
4477 | // | |
4478 | // xor macro for ports = 2,3 | |
4479 | // | |
4480 | // | |
4481 | ||
4482 | ||
4483 | ||
4484 | ||
4485 | ||
4486 | module l2b_evict_dp_xor_macro__stack_32r__width_32 ( | |
4487 | din0, | |
4488 | din1, | |
4489 | dout); | |
4490 | input [31:0] din0; | |
4491 | input [31:0] din1; | |
4492 | output [31:0] dout; | |
4493 | ||
4494 | ||
4495 | ||
4496 | ||
4497 | ||
4498 | xor2 #(32) d0_0 ( | |
4499 | .in0(din0[31:0]), | |
4500 | .in1(din1[31:0]), | |
4501 | .out(dout[31:0]) | |
4502 | ); | |
4503 | ||
4504 | ||
4505 | ||
4506 | ||
4507 | ||
4508 | ||
4509 | ||
4510 | ||
4511 | endmodule | |
4512 | ||
4513 | ||
4514 | ||
4515 | ||
4516 | ||
4517 | // | |
4518 | // nand macro for ports = 2,3,4 | |
4519 | // | |
4520 | // | |
4521 | ||
4522 | ||
4523 | ||
4524 | ||
4525 | ||
4526 | module l2b_evict_dp_nand_macro__ports_4__width_1 ( | |
4527 | din0, | |
4528 | din1, | |
4529 | din2, | |
4530 | din3, | |
4531 | dout); | |
4532 | input [0:0] din0; | |
4533 | input [0:0] din1; | |
4534 | input [0:0] din2; | |
4535 | input [0:0] din3; | |
4536 | output [0:0] dout; | |
4537 | ||
4538 | ||
4539 | ||
4540 | ||
4541 | ||
4542 | ||
4543 | nand4 #(1) d0_0 ( | |
4544 | .in0(din0[0:0]), | |
4545 | .in1(din1[0:0]), | |
4546 | .in2(din2[0:0]), | |
4547 | .in3(din3[0:0]), | |
4548 | .out(dout[0:0]) | |
4549 | ); | |
4550 | ||
4551 | ||
4552 | ||
4553 | ||
4554 | ||
4555 | ||
4556 | ||
4557 | ||
4558 | ||
4559 | endmodule | |
4560 | ||
4561 | ||
4562 | ||
4563 | ||
4564 | ||
4565 | // | |
4566 | // nor macro for ports = 2,3 | |
4567 | // | |
4568 | // | |
4569 | ||
4570 | ||
4571 | ||
4572 | ||
4573 | ||
4574 | module l2b_evict_dp_nor_macro__width_1 ( | |
4575 | din0, | |
4576 | din1, | |
4577 | dout); | |
4578 | input [0:0] din0; | |
4579 | input [0:0] din1; | |
4580 | output [0:0] dout; | |
4581 | ||
4582 | ||
4583 | ||
4584 | ||
4585 | ||
4586 | ||
4587 | nor2 #(1) d0_0 ( | |
4588 | .in0(din0[0:0]), | |
4589 | .in1(din1[0:0]), | |
4590 | .out(dout[0:0]) | |
4591 | ); | |
4592 | ||
4593 | ||
4594 | ||
4595 | ||
4596 | ||
4597 | ||
4598 | ||
4599 | endmodule | |
4600 | ||
4601 | ||
4602 | ||
4603 | ||
4604 | ||
4605 | // | |
4606 | // invert macro | |
4607 | // | |
4608 | // | |
4609 | ||
4610 | ||
4611 | ||
4612 | ||
4613 | ||
4614 | module l2b_evict_dp_inv_macro__dinv_16x__width_1 ( | |
4615 | din, | |
4616 | dout); | |
4617 | input [0:0] din; | |
4618 | output [0:0] dout; | |
4619 | ||
4620 | ||
4621 | ||
4622 | ||
4623 | ||
4624 | ||
4625 | inv #(1) d0_0 ( | |
4626 | .in(din[0:0]), | |
4627 | .out(dout[0:0]) | |
4628 | ); | |
4629 | ||
4630 | ||
4631 | ||
4632 | ||
4633 | ||
4634 | ||
4635 | ||
4636 | ||
4637 | ||
4638 | endmodule | |
4639 | ||
4640 | ||
4641 | ||
4642 | ||
4643 | ||
4644 | // | |
4645 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
4646 | // | |
4647 | // | |
4648 | ||
4649 | ||
4650 | ||
4651 | ||
4652 | ||
4653 | module l2b_evict_dp_cmp_macro__width_8 ( | |
4654 | din0, | |
4655 | din1, | |
4656 | dout); | |
4657 | input [7:0] din0; | |
4658 | input [7:0] din1; | |
4659 | output dout; | |
4660 | ||
4661 | ||
4662 | ||
4663 | ||
4664 | ||
4665 | ||
4666 | cmp #(8) m0_0 ( | |
4667 | .in0(din0[7:0]), | |
4668 | .in1(din1[7:0]), | |
4669 | .out(dout) | |
4670 | ); | |
4671 | ||
4672 | ||
4673 | ||
4674 | ||
4675 | ||
4676 | ||
4677 | ||
4678 | ||
4679 | ||
4680 | ||
4681 | endmodule | |
4682 | ||
4683 | ||
4684 | ||
4685 | ||
4686 | ||
4687 | // | |
4688 | // nor macro for ports = 2,3 | |
4689 | // | |
4690 | // | |
4691 | ||
4692 | ||
4693 | ||
4694 | ||
4695 | ||
4696 | module l2b_evict_dp_nor_macro__dnor_16x__width_1 ( | |
4697 | din0, | |
4698 | din1, | |
4699 | dout); | |
4700 | input [0:0] din0; | |
4701 | input [0:0] din1; | |
4702 | output [0:0] dout; | |
4703 | ||
4704 | ||
4705 | ||
4706 | ||
4707 | ||
4708 | ||
4709 | nor2 #(1) d0_0 ( | |
4710 | .in0(din0[0:0]), | |
4711 | .in1(din1[0:0]), | |
4712 | .out(dout[0:0]) | |
4713 | ); | |
4714 | ||
4715 | ||
4716 | ||
4717 | ||
4718 | ||
4719 | ||
4720 | ||
4721 | endmodule | |
4722 | ||
4723 | ||
4724 | ||
4725 | ||
4726 | ||
4727 | // | |
4728 | // nor macro for ports = 2,3 | |
4729 | // | |
4730 | // | |
4731 | ||
4732 | ||
4733 | ||
4734 | ||
4735 | ||
4736 | module l2b_evict_dp_nor_macro__dnor_16x__ports_2__width_1 ( | |
4737 | din0, | |
4738 | din1, | |
4739 | dout); | |
4740 | input [0:0] din0; | |
4741 | input [0:0] din1; | |
4742 | output [0:0] dout; | |
4743 | ||
4744 | ||
4745 | ||
4746 | ||
4747 | ||
4748 | ||
4749 | nor2 #(1) d0_0 ( | |
4750 | .in0(din0[0:0]), | |
4751 | .in1(din1[0:0]), | |
4752 | .out(dout[0:0]) | |
4753 | ); | |
4754 | ||
4755 | ||
4756 | ||
4757 | ||
4758 | ||
4759 | ||
4760 | ||
4761 | endmodule | |
4762 | ||
4763 | ||
4764 | ||
4765 | ||
4766 | ||
4767 | // | |
4768 | // and macro for ports = 2,3,4 | |
4769 | // | |
4770 | // | |
4771 | ||
4772 | ||
4773 | ||
4774 | ||
4775 | ||
4776 | module l2b_evict_dp_and_macro__dinv_48x__dnand_16x__ports_2__width_1 ( | |
4777 | din0, | |
4778 | din1, | |
4779 | dout); | |
4780 | input [0:0] din0; | |
4781 | input [0:0] din1; | |
4782 | output [0:0] dout; | |
4783 | ||
4784 | ||
4785 | ||
4786 | ||
4787 | ||
4788 | ||
4789 | and2 #(1) d0_0 ( | |
4790 | .in0(din0[0:0]), | |
4791 | .in1(din1[0:0]), | |
4792 | .out(dout[0:0]) | |
4793 | ); | |
4794 | ||
4795 | ||
4796 | ||
4797 | ||
4798 | ||
4799 | ||
4800 | ||
4801 | ||
4802 | ||
4803 | endmodule | |
4804 | ||
4805 | ||
4806 | ||
4807 | ||
4808 | ||
4809 | ||
4810 | ||
4811 | ||
4812 | ||
4813 | // any PARAMS parms go into naming of macro | |
4814 | ||
4815 | module l2b_evict_dp_msff_macro__stack_32r__width_32 ( | |
4816 | din, | |
4817 | clk, | |
4818 | en, | |
4819 | se, | |
4820 | scan_in, | |
4821 | siclk, | |
4822 | soclk, | |
4823 | pce_ov, | |
4824 | stop, | |
4825 | dout, | |
4826 | scan_out); | |
4827 | wire l1clk; | |
4828 | wire siclk_out; | |
4829 | wire soclk_out; | |
4830 | wire [30:0] so; | |
4831 | ||
4832 | input [31:0] din; | |
4833 | ||
4834 | ||
4835 | input clk; | |
4836 | input en; | |
4837 | input se; | |
4838 | input scan_in; | |
4839 | input siclk; | |
4840 | input soclk; | |
4841 | input pce_ov; | |
4842 | input stop; | |
4843 | ||
4844 | ||
4845 | ||
4846 | output [31:0] dout; | |
4847 | ||
4848 | ||
4849 | output scan_out; | |
4850 | ||
4851 | ||
4852 | ||
4853 | ||
4854 | cl_dp1_l1hdr_8x c0_0 ( | |
4855 | .l2clk(clk), | |
4856 | .pce(en), | |
4857 | .aclk(siclk), | |
4858 | .bclk(soclk), | |
4859 | .l1clk(l1clk), | |
4860 | .se(se), | |
4861 | .pce_ov(pce_ov), | |
4862 | .stop(stop), | |
4863 | .siclk_out(siclk_out), | |
4864 | .soclk_out(soclk_out) | |
4865 | ); | |
4866 | dff #(32) d0_0 ( | |
4867 | .l1clk(l1clk), | |
4868 | .siclk(siclk_out), | |
4869 | .soclk(soclk_out), | |
4870 | .d(din[31:0]), | |
4871 | .si({scan_in,so[30:0]}), | |
4872 | .so({so[30:0],scan_out}), | |
4873 | .q(dout[31:0]) | |
4874 | ); | |
4875 | ||
4876 | ||
4877 | ||
4878 | ||
4879 | ||
4880 | ||
4881 | ||
4882 | ||
4883 | ||
4884 | ||
4885 | ||
4886 | ||
4887 | ||
4888 | ||
4889 | ||
4890 | ||
4891 | ||
4892 | ||
4893 | ||
4894 | ||
4895 | endmodule | |
4896 | ||
4897 | ||
4898 | ||
4899 | ||
4900 | ||
4901 | ||
4902 | ||
4903 | ||
4904 | ||
4905 | ||
4906 | ||
4907 | ||
4908 | ||
4909 | // any PARAMS parms go into naming of macro | |
4910 | ||
4911 | module l2b_evict_dp_msff_macro__dmsff_32x__stack_64c__width_64 ( | |
4912 | din, | |
4913 | clk, | |
4914 | en, | |
4915 | se, | |
4916 | scan_in, | |
4917 | siclk, | |
4918 | soclk, | |
4919 | pce_ov, | |
4920 | stop, | |
4921 | dout, | |
4922 | scan_out); | |
4923 | wire l1clk; | |
4924 | wire siclk_out; | |
4925 | wire soclk_out; | |
4926 | wire [62:0] so; | |
4927 | ||
4928 | input [63:0] din; | |
4929 | ||
4930 | ||
4931 | input clk; | |
4932 | input en; | |
4933 | input se; | |
4934 | input scan_in; | |
4935 | input siclk; | |
4936 | input soclk; | |
4937 | input pce_ov; | |
4938 | input stop; | |
4939 | ||
4940 | ||
4941 | ||
4942 | output [63:0] dout; | |
4943 | ||
4944 | ||
4945 | output scan_out; | |
4946 | ||
4947 | ||
4948 | ||
4949 | ||
4950 | cl_dp1_l1hdr_8x c0_0 ( | |
4951 | .l2clk(clk), | |
4952 | .pce(en), | |
4953 | .aclk(siclk), | |
4954 | .bclk(soclk), | |
4955 | .l1clk(l1clk), | |
4956 | .se(se), | |
4957 | .pce_ov(pce_ov), | |
4958 | .stop(stop), | |
4959 | .siclk_out(siclk_out), | |
4960 | .soclk_out(soclk_out) | |
4961 | ); | |
4962 | dff #(64) d0_0 ( | |
4963 | .l1clk(l1clk), | |
4964 | .siclk(siclk_out), | |
4965 | .soclk(soclk_out), | |
4966 | .d(din[63:0]), | |
4967 | .si({scan_in,so[62:0]}), | |
4968 | .so({so[62:0],scan_out}), | |
4969 | .q(dout[63:0]) | |
4970 | ); | |
4971 | ||
4972 | ||
4973 | ||
4974 | ||
4975 | ||
4976 | ||
4977 | ||
4978 | ||
4979 | ||
4980 | ||
4981 | ||
4982 | ||
4983 | ||
4984 | ||
4985 | ||
4986 | ||
4987 | ||
4988 | ||
4989 | ||
4990 | ||
4991 | endmodule | |
4992 | ||
4993 | ||
4994 | ||
4995 | ||
4996 | ||
4997 | ||
4998 | ||
4999 | ||
5000 | ||
5001 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
5002 | // also for pass-gate with decoder | |
5003 | ||
5004 | ||
5005 | ||
5006 | ||
5007 | ||
5008 | // any PARAMS parms go into naming of macro | |
5009 | ||
5010 | module l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__stack_66c__width_66 ( | |
5011 | din0, | |
5012 | sel0, | |
5013 | din1, | |
5014 | sel1, | |
5015 | dout); | |
5016 | wire buffout0; | |
5017 | wire buffout1; | |
5018 | ||
5019 | input [65:0] din0; | |
5020 | input sel0; | |
5021 | input [65:0] din1; | |
5022 | input sel1; | |
5023 | output [65:0] dout; | |
5024 | ||
5025 | ||
5026 | ||
5027 | ||
5028 | ||
5029 | cl_dp1_muxbuff2_8x c0_0 ( | |
5030 | .in0(sel0), | |
5031 | .in1(sel1), | |
5032 | .out0(buffout0), | |
5033 | .out1(buffout1) | |
5034 | ); | |
5035 | mux2s #(66) d0_0 ( | |
5036 | .sel0(buffout0), | |
5037 | .sel1(buffout1), | |
5038 | .in0(din0[65:0]), | |
5039 | .in1(din1[65:0]), | |
5040 | .dout(dout[65:0]) | |
5041 | ); | |
5042 | ||
5043 | ||
5044 | ||
5045 | ||
5046 | ||
5047 | ||
5048 | ||
5049 | ||
5050 | ||
5051 | ||
5052 | ||
5053 | ||
5054 | ||
5055 | endmodule | |
5056 | ||
5057 | ||
5058 | ||
5059 | ||
5060 | ||
5061 | ||
5062 | // any PARAMS parms go into naming of macro | |
5063 | ||
5064 | module l2b_evict_dp_msff_macro__stack_21r__width_21 ( | |
5065 | din, | |
5066 | clk, | |
5067 | en, | |
5068 | se, | |
5069 | scan_in, | |
5070 | siclk, | |
5071 | soclk, | |
5072 | pce_ov, | |
5073 | stop, | |
5074 | dout, | |
5075 | scan_out); | |
5076 | wire l1clk; | |
5077 | wire siclk_out; | |
5078 | wire soclk_out; | |
5079 | wire [19:0] so; | |
5080 | ||
5081 | input [20:0] din; | |
5082 | ||
5083 | ||
5084 | input clk; | |
5085 | input en; | |
5086 | input se; | |
5087 | input scan_in; | |
5088 | input siclk; | |
5089 | input soclk; | |
5090 | input pce_ov; | |
5091 | input stop; | |
5092 | ||
5093 | ||
5094 | ||
5095 | output [20:0] dout; | |
5096 | ||
5097 | ||
5098 | output scan_out; | |
5099 | ||
5100 | ||
5101 | ||
5102 | ||
5103 | cl_dp1_l1hdr_8x c0_0 ( | |
5104 | .l2clk(clk), | |
5105 | .pce(en), | |
5106 | .aclk(siclk), | |
5107 | .bclk(soclk), | |
5108 | .l1clk(l1clk), | |
5109 | .se(se), | |
5110 | .pce_ov(pce_ov), | |
5111 | .stop(stop), | |
5112 | .siclk_out(siclk_out), | |
5113 | .soclk_out(soclk_out) | |
5114 | ); | |
5115 | dff #(21) d0_0 ( | |
5116 | .l1clk(l1clk), | |
5117 | .siclk(siclk_out), | |
5118 | .soclk(soclk_out), | |
5119 | .d(din[20:0]), | |
5120 | .si({scan_in,so[19:0]}), | |
5121 | .so({so[19:0],scan_out}), | |
5122 | .q(dout[20:0]) | |
5123 | ); | |
5124 | ||
5125 | ||
5126 | ||
5127 | ||
5128 | ||
5129 | ||
5130 | ||
5131 | ||
5132 | ||
5133 | ||
5134 | ||
5135 | ||
5136 | ||
5137 | ||
5138 | ||
5139 | ||
5140 | ||
5141 | ||
5142 | ||
5143 | ||
5144 | endmodule | |
5145 | ||
5146 | ||
5147 | ||
5148 | ||
5149 | ||
5150 | ||
5151 | ||
5152 | ||
5153 | ||
5154 | ||
5155 | ||
5156 | ||
5157 | ||
5158 | // any PARAMS parms go into naming of macro | |
5159 | ||
5160 | module l2b_evict_dp_msff_macro__stack_4r__width_4 ( | |
5161 | din, | |
5162 | clk, | |
5163 | en, | |
5164 | se, | |
5165 | scan_in, | |
5166 | siclk, | |
5167 | soclk, | |
5168 | pce_ov, | |
5169 | stop, | |
5170 | dout, | |
5171 | scan_out); | |
5172 | wire l1clk; | |
5173 | wire siclk_out; | |
5174 | wire soclk_out; | |
5175 | wire [2:0] so; | |
5176 | ||
5177 | input [3:0] din; | |
5178 | ||
5179 | ||
5180 | input clk; | |
5181 | input en; | |
5182 | input se; | |
5183 | input scan_in; | |
5184 | input siclk; | |
5185 | input soclk; | |
5186 | input pce_ov; | |
5187 | input stop; | |
5188 | ||
5189 | ||
5190 | ||
5191 | output [3:0] dout; | |
5192 | ||
5193 | ||
5194 | output scan_out; | |
5195 | ||
5196 | ||
5197 | ||
5198 | ||
5199 | cl_dp1_l1hdr_8x c0_0 ( | |
5200 | .l2clk(clk), | |
5201 | .pce(en), | |
5202 | .aclk(siclk), | |
5203 | .bclk(soclk), | |
5204 | .l1clk(l1clk), | |
5205 | .se(se), | |
5206 | .pce_ov(pce_ov), | |
5207 | .stop(stop), | |
5208 | .siclk_out(siclk_out), | |
5209 | .soclk_out(soclk_out) | |
5210 | ); | |
5211 | dff #(4) d0_0 ( | |
5212 | .l1clk(l1clk), | |
5213 | .siclk(siclk_out), | |
5214 | .soclk(soclk_out), | |
5215 | .d(din[3:0]), | |
5216 | .si({scan_in,so[2:0]}), | |
5217 | .so({so[2:0],scan_out}), | |
5218 | .q(dout[3:0]) | |
5219 | ); | |
5220 | ||
5221 | ||
5222 | ||
5223 | ||
5224 | ||
5225 | ||
5226 | ||
5227 | ||
5228 | ||
5229 | ||
5230 | ||
5231 | ||
5232 | ||
5233 | ||
5234 | ||
5235 | ||
5236 | ||
5237 | ||
5238 | ||
5239 | ||
5240 | endmodule | |
5241 | ||
5242 | ||
5243 | ||
5244 | ||
5245 | ||
5246 | ||
5247 | ||
5248 | ||
5249 | ||
5250 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
5251 | // also for pass-gate with decoder | |
5252 | ||
5253 | ||
5254 | ||
5255 | ||
5256 | ||
5257 | // any PARAMS parms go into naming of macro | |
5258 | ||
5259 | module l2b_evict_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_6r__width_6 ( | |
5260 | din0, | |
5261 | sel0, | |
5262 | din1, | |
5263 | sel1, | |
5264 | dout); | |
5265 | wire buffout0; | |
5266 | wire buffout1; | |
5267 | ||
5268 | input [5:0] din0; | |
5269 | input sel0; | |
5270 | input [5:0] din1; | |
5271 | input sel1; | |
5272 | output [5:0] dout; | |
5273 | ||
5274 | ||
5275 | ||
5276 | ||
5277 | ||
5278 | cl_dp1_muxbuff2_8x c0_0 ( | |
5279 | .in0(sel0), | |
5280 | .in1(sel1), | |
5281 | .out0(buffout0), | |
5282 | .out1(buffout1) | |
5283 | ); | |
5284 | mux2s #(6) d0_0 ( | |
5285 | .sel0(buffout0), | |
5286 | .sel1(buffout1), | |
5287 | .in0(din0[5:0]), | |
5288 | .in1(din1[5:0]), | |
5289 | .dout(dout[5:0]) | |
5290 | ); | |
5291 | ||
5292 | ||
5293 | ||
5294 | ||
5295 | ||
5296 | ||
5297 | ||
5298 | ||
5299 | ||
5300 | ||
5301 | ||
5302 | ||
5303 | ||
5304 | endmodule | |
5305 | ||
5306 | ||
5307 | // | |
5308 | // or macro for ports = 2,3 | |
5309 | // | |
5310 | // | |
5311 | ||
5312 | ||
5313 | ||
5314 | ||
5315 | ||
5316 | module l2b_evict_dp_or_macro__dinv_16x__dnor_4x__ports_3__width_1 ( | |
5317 | din0, | |
5318 | din1, | |
5319 | din2, | |
5320 | dout); | |
5321 | input [0:0] din0; | |
5322 | input [0:0] din1; | |
5323 | input [0:0] din2; | |
5324 | output [0:0] dout; | |
5325 | ||
5326 | ||
5327 | ||
5328 | ||
5329 | ||
5330 | ||
5331 | or3 #(1) d0_0 ( | |
5332 | .in0(din0[0:0]), | |
5333 | .in1(din1[0:0]), | |
5334 | .in2(din2[0:0]), | |
5335 | .out(dout[0:0]) | |
5336 | ); | |
5337 | ||
5338 | ||
5339 | ||
5340 | ||
5341 | ||
5342 | ||
5343 | ||
5344 | ||
5345 | ||
5346 | endmodule | |
5347 | ||
5348 | ||
5349 | ||
5350 | ||
5351 | ||
5352 | ||
5353 | ||
5354 | ||
5355 | ||
5356 | // any PARAMS parms go into naming of macro | |
5357 | ||
5358 | module l2b_evict_dp_msff_macro__stack_6r__width_6 ( | |
5359 | din, | |
5360 | clk, | |
5361 | en, | |
5362 | se, | |
5363 | scan_in, | |
5364 | siclk, | |
5365 | soclk, | |
5366 | pce_ov, | |
5367 | stop, | |
5368 | dout, | |
5369 | scan_out); | |
5370 | wire l1clk; | |
5371 | wire siclk_out; | |
5372 | wire soclk_out; | |
5373 | wire [4:0] so; | |
5374 | ||
5375 | input [5:0] din; | |
5376 | ||
5377 | ||
5378 | input clk; | |
5379 | input en; | |
5380 | input se; | |
5381 | input scan_in; | |
5382 | input siclk; | |
5383 | input soclk; | |
5384 | input pce_ov; | |
5385 | input stop; | |
5386 | ||
5387 | ||
5388 | ||
5389 | output [5:0] dout; | |
5390 | ||
5391 | ||
5392 | output scan_out; | |
5393 | ||
5394 | ||
5395 | ||
5396 | ||
5397 | cl_dp1_l1hdr_8x c0_0 ( | |
5398 | .l2clk(clk), | |
5399 | .pce(en), | |
5400 | .aclk(siclk), | |
5401 | .bclk(soclk), | |
5402 | .l1clk(l1clk), | |
5403 | .se(se), | |
5404 | .pce_ov(pce_ov), | |
5405 | .stop(stop), | |
5406 | .siclk_out(siclk_out), | |
5407 | .soclk_out(soclk_out) | |
5408 | ); | |
5409 | dff #(6) d0_0 ( | |
5410 | .l1clk(l1clk), | |
5411 | .siclk(siclk_out), | |
5412 | .soclk(soclk_out), | |
5413 | .d(din[5:0]), | |
5414 | .si({scan_in,so[4:0]}), | |
5415 | .so({so[4:0],scan_out}), | |
5416 | .q(dout[5:0]) | |
5417 | ); | |
5418 | ||
5419 | ||
5420 | ||
5421 | ||
5422 | ||
5423 | ||
5424 | ||
5425 | ||
5426 | ||
5427 | ||
5428 | ||
5429 | ||
5430 | ||
5431 | ||
5432 | ||
5433 | ||
5434 | ||
5435 | ||
5436 | ||
5437 | ||
5438 | endmodule | |
5439 | ||
5440 | ||
5441 | ||
5442 | ||
5443 | ||
5444 | ||
5445 | ||
5446 | ||
5447 | ||
5448 | ||
5449 | ||
5450 | ||
5451 | ||
5452 | // any PARAMS parms go into naming of macro | |
5453 | ||
5454 | module l2b_evict_dp_msff_macro__stack_8r__width_8 ( | |
5455 | din, | |
5456 | clk, | |
5457 | en, | |
5458 | se, | |
5459 | scan_in, | |
5460 | siclk, | |
5461 | soclk, | |
5462 | pce_ov, | |
5463 | stop, | |
5464 | dout, | |
5465 | scan_out); | |
5466 | wire l1clk; | |
5467 | wire siclk_out; | |
5468 | wire soclk_out; | |
5469 | wire [6:0] so; | |
5470 | ||
5471 | input [7:0] din; | |
5472 | ||
5473 | ||
5474 | input clk; | |
5475 | input en; | |
5476 | input se; | |
5477 | input scan_in; | |
5478 | input siclk; | |
5479 | input soclk; | |
5480 | input pce_ov; | |
5481 | input stop; | |
5482 | ||
5483 | ||
5484 | ||
5485 | output [7:0] dout; | |
5486 | ||
5487 | ||
5488 | output scan_out; | |
5489 | ||
5490 | ||
5491 | ||
5492 | ||
5493 | cl_dp1_l1hdr_8x c0_0 ( | |
5494 | .l2clk(clk), | |
5495 | .pce(en), | |
5496 | .aclk(siclk), | |
5497 | .bclk(soclk), | |
5498 | .l1clk(l1clk), | |
5499 | .se(se), | |
5500 | .pce_ov(pce_ov), | |
5501 | .stop(stop), | |
5502 | .siclk_out(siclk_out), | |
5503 | .soclk_out(soclk_out) | |
5504 | ); | |
5505 | dff #(8) d0_0 ( | |
5506 | .l1clk(l1clk), | |
5507 | .siclk(siclk_out), | |
5508 | .soclk(soclk_out), | |
5509 | .d(din[7:0]), | |
5510 | .si({scan_in,so[6:0]}), | |
5511 | .so({so[6:0],scan_out}), | |
5512 | .q(dout[7:0]) | |
5513 | ); | |
5514 | ||
5515 | ||
5516 | ||
5517 | ||
5518 | ||
5519 | ||
5520 | ||
5521 | ||
5522 | ||
5523 | ||
5524 | ||
5525 | ||
5526 | ||
5527 | ||
5528 | ||
5529 | ||
5530 | ||
5531 | ||
5532 | ||
5533 | ||
5534 | endmodule | |
5535 | ||
5536 | ||
5537 | ||
5538 | ||
5539 | ||
5540 | ||
5541 | ||
5542 | ||
5543 | ||
5544 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
5545 | // also for pass-gate with decoder | |
5546 | ||
5547 | ||
5548 | ||
5549 | ||
5550 | ||
5551 | // any PARAMS parms go into naming of macro | |
5552 | ||
5553 | module l2b_evict_dp_mux_macro__mux_aonpe__ports_2__stack_4r__width_4 ( | |
5554 | din0, | |
5555 | sel0, | |
5556 | din1, | |
5557 | sel1, | |
5558 | dout); | |
5559 | wire buffout0; | |
5560 | wire buffout1; | |
5561 | ||
5562 | input [3:0] din0; | |
5563 | input sel0; | |
5564 | input [3:0] din1; | |
5565 | input sel1; | |
5566 | output [3:0] dout; | |
5567 | ||
5568 | ||
5569 | ||
5570 | ||
5571 | ||
5572 | cl_dp1_muxbuff2_8x c0_0 ( | |
5573 | .in0(sel0), | |
5574 | .in1(sel1), | |
5575 | .out0(buffout0), | |
5576 | .out1(buffout1) | |
5577 | ); | |
5578 | mux2s #(4) d0_0 ( | |
5579 | .sel0(buffout0), | |
5580 | .sel1(buffout1), | |
5581 | .in0(din0[3:0]), | |
5582 | .in1(din1[3:0]), | |
5583 | .dout(dout[3:0]) | |
5584 | ); | |
5585 | ||
5586 | ||
5587 | ||
5588 | ||
5589 | ||
5590 | ||
5591 | ||
5592 | ||
5593 | ||
5594 | ||
5595 | ||
5596 | ||
5597 | ||
5598 | endmodule | |
5599 | ||
5600 | ||
5601 | ||
5602 | ||
5603 | ||
5604 | ||
5605 | // any PARAMS parms go into naming of macro | |
5606 | ||
5607 | module l2b_evict_dp_msff_macro__stack_6r__width_5 ( | |
5608 | din, | |
5609 | clk, | |
5610 | en, | |
5611 | se, | |
5612 | scan_in, | |
5613 | siclk, | |
5614 | soclk, | |
5615 | pce_ov, | |
5616 | stop, | |
5617 | dout, | |
5618 | scan_out); | |
5619 | wire l1clk; | |
5620 | wire siclk_out; | |
5621 | wire soclk_out; | |
5622 | wire [3:0] so; | |
5623 | ||
5624 | input [4:0] din; | |
5625 | ||
5626 | ||
5627 | input clk; | |
5628 | input en; | |
5629 | input se; | |
5630 | input scan_in; | |
5631 | input siclk; | |
5632 | input soclk; | |
5633 | input pce_ov; | |
5634 | input stop; | |
5635 | ||
5636 | ||
5637 | ||
5638 | output [4:0] dout; | |
5639 | ||
5640 | ||
5641 | output scan_out; | |
5642 | ||
5643 | ||
5644 | ||
5645 | ||
5646 | cl_dp1_l1hdr_8x c0_0 ( | |
5647 | .l2clk(clk), | |
5648 | .pce(en), | |
5649 | .aclk(siclk), | |
5650 | .bclk(soclk), | |
5651 | .l1clk(l1clk), | |
5652 | .se(se), | |
5653 | .pce_ov(pce_ov), | |
5654 | .stop(stop), | |
5655 | .siclk_out(siclk_out), | |
5656 | .soclk_out(soclk_out) | |
5657 | ); | |
5658 | dff #(5) d0_0 ( | |
5659 | .l1clk(l1clk), | |
5660 | .siclk(siclk_out), | |
5661 | .soclk(soclk_out), | |
5662 | .d(din[4:0]), | |
5663 | .si({scan_in,so[3:0]}), | |
5664 | .so({so[3:0],scan_out}), | |
5665 | .q(dout[4:0]) | |
5666 | ); | |
5667 | ||
5668 | ||
5669 | ||
5670 | ||
5671 | ||
5672 | ||
5673 | ||
5674 | ||
5675 | ||
5676 | ||
5677 | ||
5678 | ||
5679 | ||
5680 | ||
5681 | ||
5682 | ||
5683 | ||
5684 | ||
5685 | ||
5686 | ||
5687 | endmodule | |
5688 | ||
5689 | ||
5690 | ||
5691 | ||
5692 | ||
5693 | ||
5694 | ||
5695 | ||
5696 | ||
5697 | ||
5698 | ||
5699 | ||
5700 | ||
5701 | // any PARAMS parms go into naming of macro | |
5702 | ||
5703 | module l2b_evict_dp_msff_macro__stack_10r__width_9 ( | |
5704 | din, | |
5705 | clk, | |
5706 | en, | |
5707 | se, | |
5708 | scan_in, | |
5709 | siclk, | |
5710 | soclk, | |
5711 | pce_ov, | |
5712 | stop, | |
5713 | dout, | |
5714 | scan_out); | |
5715 | wire l1clk; | |
5716 | wire siclk_out; | |
5717 | wire soclk_out; | |
5718 | wire [7:0] so; | |
5719 | ||
5720 | input [8:0] din; | |
5721 | ||
5722 | ||
5723 | input clk; | |
5724 | input en; | |
5725 | input se; | |
5726 | input scan_in; | |
5727 | input siclk; | |
5728 | input soclk; | |
5729 | input pce_ov; | |
5730 | input stop; | |
5731 | ||
5732 | ||
5733 | ||
5734 | output [8:0] dout; | |
5735 | ||
5736 | ||
5737 | output scan_out; | |
5738 | ||
5739 | ||
5740 | ||
5741 | ||
5742 | cl_dp1_l1hdr_8x c0_0 ( | |
5743 | .l2clk(clk), | |
5744 | .pce(en), | |
5745 | .aclk(siclk), | |
5746 | .bclk(soclk), | |
5747 | .l1clk(l1clk), | |
5748 | .se(se), | |
5749 | .pce_ov(pce_ov), | |
5750 | .stop(stop), | |
5751 | .siclk_out(siclk_out), | |
5752 | .soclk_out(soclk_out) | |
5753 | ); | |
5754 | dff #(9) d0_0 ( | |
5755 | .l1clk(l1clk), | |
5756 | .siclk(siclk_out), | |
5757 | .soclk(soclk_out), | |
5758 | .d(din[8:0]), | |
5759 | .si({scan_in,so[7:0]}), | |
5760 | .so({so[7:0],scan_out}), | |
5761 | .q(dout[8:0]) | |
5762 | ); | |
5763 | ||
5764 | ||
5765 | ||
5766 | ||
5767 | ||
5768 | ||
5769 | ||
5770 | ||
5771 | ||
5772 | ||
5773 | ||
5774 | ||
5775 | ||
5776 | ||
5777 | ||
5778 | ||
5779 | ||
5780 | ||
5781 | ||
5782 | ||
5783 | endmodule | |
5784 | ||
5785 | ||
5786 | ||
5787 | ||
5788 | ||
5789 | ||
5790 | ||
5791 |