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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: l2t_mb0_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module l2t_mb0_ctl ( | |
36 | mb0_l2t_run, | |
37 | mb0_l2t_cambist, | |
38 | mb0_l2t_addr, | |
39 | mb0_l2t_icrow_wr_en, | |
40 | mb0_l2t_icrow_rd_en, | |
41 | mb0_l2t_lookup_wdata, | |
42 | mb0_l2t_icrow_lookup_en, | |
43 | mb0_l2t_icrow_row_en, | |
44 | mb0_l2t_icrow_panel_en, | |
45 | mb0_l2t_mbist_write_data, | |
46 | mb0_l2t_dcrow_wr_en, | |
47 | mb0_l2t_dcrow_rd_en, | |
48 | mb0_l2t_dcrow_lookup_en, | |
49 | mb0_l2t_dcrow_row_en, | |
50 | mb0_l2t_dcrow_panel_en, | |
51 | mb0_l2t_mask, | |
52 | mb0_l2t_oqarray_wr_en, | |
53 | mb0_l2t_oqarray_rd_en, | |
54 | mb0_l2t_cmpsel, | |
55 | mb0_l2t_done, | |
56 | mb0_l2t_fail, | |
57 | scan_out, | |
58 | dc_cam_fail, | |
59 | ic_cam_fail, | |
60 | dir_dc_rw_fail, | |
61 | dir_ic_rw_fail, | |
62 | oqarray_rw_fail, | |
63 | l2clk, | |
64 | scan_in, | |
65 | tcu_pce_ov, | |
66 | tcu_aclk, | |
67 | tcu_bclk, | |
68 | tcu_scan_en, | |
69 | tcu_clk_stop, | |
70 | mbist_start, | |
71 | mbist_user_mode, | |
72 | mbist_bisi_mode); | |
73 | wire pce_ov; | |
74 | wire stop; | |
75 | wire siclk; | |
76 | wire soclk; | |
77 | wire se; | |
78 | wire l1clk; | |
79 | wire clock_enable; | |
80 | wire start_in; | |
81 | wire l1clk_pm1; | |
82 | wire mb_ic_rw_fail; | |
83 | wire mb_dc_rw_fail; | |
84 | wire array_usr_reg_scanin; | |
85 | wire array_usr_reg_scanout; | |
86 | wire [3:0] user_array_sel_in; | |
87 | wire [3:0] user_array_sel; | |
88 | wire user_addr_mode_reg_scanin; | |
89 | wire user_addr_mode_reg_scanout; | |
90 | wire user_addr_mode_in; | |
91 | wire user_addr_mode; | |
92 | wire user_start_addr_reg_scanin; | |
93 | wire user_start_addr_reg_scanout; | |
94 | wire [7:0] user_start_addr_in; | |
95 | wire [7:0] user_start_addr; | |
96 | wire user_stop_addr_reg_scanin; | |
97 | wire user_stop_addr_reg_scanout; | |
98 | wire [7:0] user_stop_addr_in; | |
99 | wire [7:0] user_stop_addr; | |
100 | wire user_incr_addr_reg_scanin; | |
101 | wire user_incr_addr_reg_scanout; | |
102 | wire [7:0] user_incr_addr_in; | |
103 | wire [7:0] user_incr_addr; | |
104 | wire user_data_mode_reg_scanin; | |
105 | wire user_data_mode_reg_scanout; | |
106 | wire user_data_mode_in; | |
107 | wire user_data_mode; | |
108 | wire user_data_reg_scanin; | |
109 | wire user_data_reg_scanout; | |
110 | wire [7:0] user_data_in; | |
111 | wire [7:0] user_data; | |
112 | wire user_cmpsel_hold_reg_scanin; | |
113 | wire user_cmpsel_hold_reg_scanout; | |
114 | wire user_cmpsel_hold_in; | |
115 | wire user_cmpsel_hold; | |
116 | wire user_cmpsel_reg_scanin; | |
117 | wire user_cmpsel_reg_scanout; | |
118 | wire [3:0] user_cmpsel_in; | |
119 | wire [3:0] user_cmpsel; | |
120 | wire user_loop_mode_reg_scanin; | |
121 | wire user_loop_mode_reg_scanout; | |
122 | wire user_loop_mode_in; | |
123 | wire user_loop_mode; | |
124 | wire ten_n_mode_reg_scanin; | |
125 | wire ten_n_mode_reg_scanout; | |
126 | wire ten_n_mode_in; | |
127 | wire ten_n_mode; | |
128 | wire user_cam_mode_reg_scanin; | |
129 | wire user_cam_mode_reg_scanout; | |
130 | wire user_cam_mode_in; | |
131 | wire user_cam_mode; | |
132 | wire user_cam_select_reg_scanin; | |
133 | wire user_cam_select_reg_scanout; | |
134 | wire [1:0] user_cam_sel_in; | |
135 | wire [1:0] user_cam_sel; | |
136 | wire user_cam_test_select_reg_scanin; | |
137 | wire user_cam_test_select_reg_scanout; | |
138 | wire [1:0] user_cam_test_sel_in; | |
139 | wire [1:0] user_cam_test_sel; | |
140 | wire user_bisi_wr_mode_reg_scanin; | |
141 | wire user_bisi_wr_mode_reg_scanout; | |
142 | wire user_bisi_wr_mode_in; | |
143 | wire user_bisi_wr_mode; | |
144 | wire user_bisi_rd_mode_reg_scanin; | |
145 | wire user_bisi_rd_mode_reg_scanout; | |
146 | wire user_bisi_rd_mode_in; | |
147 | wire user_bisi_rd_mode; | |
148 | wire mb_user_data_mode; | |
149 | wire user_mode; | |
150 | wire mb_user_addr_mode; | |
151 | wire mb_user_cmpsel_hold; | |
152 | wire mb_user_cam_mode; | |
153 | wire mb_user_ram_mode; | |
154 | wire mb_user_loop_mode; | |
155 | wire mb_user_bisi_wr_mode; | |
156 | wire bisi_mode; | |
157 | wire mb_user_bisi_rd_mode; | |
158 | wire mb_user_bisi_rw_mode; | |
159 | wire mb_default_bisi; | |
160 | wire input_signals_reg_scanin; | |
161 | wire input_signals_reg_scanout; | |
162 | wire mb_enable_reg_scanin; | |
163 | wire mb_enable_reg_scanout; | |
164 | wire mb_enable; | |
165 | wire mb_enable_out; | |
166 | wire start; | |
167 | wire config_reg_scanin; | |
168 | wire config_reg_scanout; | |
169 | wire [1:0] config_in; | |
170 | wire [1:0] config_out; | |
171 | wire start_transition; | |
172 | wire end_transition; | |
173 | wire reset_engine; | |
174 | wire loop_again; | |
175 | wire run; | |
176 | wire loop_again_reg_scanin; | |
177 | wire loop_again_reg_scanout; | |
178 | wire stop_engine_l; | |
179 | wire stop_engine_l_q; | |
180 | wire cam_cntl_reg_scanin; | |
181 | wire cam_cntl_reg_scanout; | |
182 | wire [18:0] cam_in; | |
183 | wire [18:0] cam_out; | |
184 | wire cam_shift_reg_scanin; | |
185 | wire cam_shift_reg_scanout; | |
186 | wire cam_shift_val; | |
187 | wire cam_shift; | |
188 | wire cam_msb; | |
189 | wire [1:0] cam_array_sel; | |
190 | wire [1:0] cam_panel_sel; | |
191 | wire [1:0] ctest; | |
192 | wire [1:0] cam_cseq; | |
193 | wire sel_cseq_pass; | |
194 | wire [7:0] cam_addr; | |
195 | wire ctest2; | |
196 | wire ctest3; | |
197 | wire cseq1; | |
198 | wire [1:0] cam_crw; | |
199 | wire sel_crw_pass; | |
200 | wire [1:0] crw; | |
201 | wire cseq2; | |
202 | wire cseq0; | |
203 | wire cambist; | |
204 | wire ctest0; | |
205 | wire [1:0] ctest_sel; | |
206 | wire ctest1; | |
207 | wire [1:0] cseq; | |
208 | wire cseq3; | |
209 | wire crw0; | |
210 | wire crw1; | |
211 | wire crw2; | |
212 | wire crw3; | |
213 | wire [15:0] lookup_wdata; | |
214 | wire cam_zero; | |
215 | wire [7:0] l2_mask; | |
216 | wire cam_wr_en; | |
217 | wire cam_en; | |
218 | wire cam_walk1; | |
219 | wire end_shift; | |
220 | wire [18:0] qual_cam; | |
221 | wire run3; | |
222 | wire mb_icrow0_cam_hit; | |
223 | wire [1:0] icrow_sel_d3; | |
224 | wire mb_icrow1_cam_hit; | |
225 | wire mb_dcrow0_cam_hit; | |
226 | wire [1:0] dcrow_sel_d3; | |
227 | wire mb_dcrow1_cam_hit; | |
228 | wire cam_hit_reg_scanin; | |
229 | wire cam_hit_reg_scanout; | |
230 | wire icrow0_cam_hit; | |
231 | wire icrow1_cam_hit; | |
232 | wire dcrow0_cam_hit; | |
233 | wire dcrow1_cam_hit; | |
234 | wire exp_cam_hit_delay_reg_scanin; | |
235 | wire exp_cam_hit_delay_reg_scanout; | |
236 | wire cam_hit_cmp; | |
237 | wire cam_hit_cmp_d1; | |
238 | wire cam_hit_cmp_d2; | |
239 | wire cam_hit_cmp_d3; | |
240 | wire cam_hit_cmp_d4; | |
241 | wire cam_hit_cmp_d5; | |
242 | wire exp_cam_exp_delay_reg_scanin; | |
243 | wire exp_cam_exp_delay_reg_scanout; | |
244 | wire cam_hit_exp; | |
245 | wire cam_hit_exp_d1; | |
246 | wire cam_hit_exp_d2; | |
247 | wire cam_hit_exp_d3; | |
248 | wire cam_hit_exp_d4; | |
249 | wire cam_hit_exp_d5; | |
250 | wire cam_sel_icrow_delay_reg_scanin; | |
251 | wire cam_sel_icrow_delay_reg_scanout; | |
252 | wire [1:0] icrow_sel_d1; | |
253 | wire [1:0] icrow_sel_d2; | |
254 | wire [1:0] icrow_sel_d4; | |
255 | wire [1:0] icrow_sel_d5; | |
256 | wire cam_sel_dcrow_delay_reg_scanin; | |
257 | wire cam_sel_dcrow_delay_reg_scanout; | |
258 | wire [1:0] dcrow_sel_d1; | |
259 | wire [1:0] dcrow_sel_d2; | |
260 | wire [1:0] dcrow_sel_d4; | |
261 | wire [1:0] dcrow_sel_d5; | |
262 | wire icrow0_cam_pass; | |
263 | wire icrow1_cam_pass; | |
264 | wire dcrow0_cam_pass; | |
265 | wire dcrow1_cam_pass; | |
266 | wire icrow0_cam_fail; | |
267 | wire icrow1_cam_fail; | |
268 | wire dcrow0_cam_fail; | |
269 | wire dcrow1_cam_fail; | |
270 | wire cntl_msb; | |
271 | wire valid_fail; | |
272 | wire cam_0; | |
273 | wire [1:0] cam_sel; | |
274 | wire cam_1; | |
275 | wire cam_2; | |
276 | wire cam_3; | |
277 | wire [3:0] icrow_lookup_en; | |
278 | wire cam_panel_en_0; | |
279 | wire cam_panel_en_1; | |
280 | wire cam_panel_en_2; | |
281 | wire cam_panel_en_3; | |
282 | wire [3:0] dcrow_lookup_en; | |
283 | wire [1:0] icrow_row_en; | |
284 | wire array_0; | |
285 | wire array_1; | |
286 | wire [1:0] dcrow_row_en; | |
287 | wire array_2; | |
288 | wire array_3; | |
289 | wire panel_en_0; | |
290 | wire cmp_0; | |
291 | wire panel_en_1; | |
292 | wire cmp_1; | |
293 | wire panel_en_2; | |
294 | wire cmp_2; | |
295 | wire panel_en_3; | |
296 | wire cmp_3; | |
297 | wire icrow_arrays; | |
298 | wire dcrow_arrays; | |
299 | wire [3:0] icrow_panel_en; | |
300 | wire [3:0] dcrow_panel_en; | |
301 | wire mbist_output_reg_scanin; | |
302 | wire mbist_output_reg_scanout; | |
303 | wire [15:0] mb_lookup_wdata; | |
304 | wire [7:0] mem_data; | |
305 | wire mbist_output_data_reg_scanin; | |
306 | wire mbist_output_data_reg_scanout; | |
307 | wire cntl_reg_scanin; | |
308 | wire cntl_reg_scanout; | |
309 | wire [35:0] cntl_in; | |
310 | wire [35:0] cntl_out; | |
311 | wire [16:0] cntl_algr; | |
312 | wire [16:0] next_algr; | |
313 | wire sel_nextaddr_reset; | |
314 | wire sel_nextaddr_restart; | |
315 | wire overflow; | |
316 | wire sel_nextaddr_incred; | |
317 | wire cout_rw; | |
318 | wire sel_nextaddr_same; | |
319 | wire [7:0] start_addr; | |
320 | wire [7:0] restart_addr; | |
321 | wire [7:0] incred_addr; | |
322 | wire [7:0] cntl_addr; | |
323 | wire [2:0] cntl_rw; | |
324 | wire [2:0] next_rw; | |
325 | wire cntl_bisi; | |
326 | wire [3:0] cntl_array_sel; | |
327 | wire last_array; | |
328 | wire [3:0] cntl_cmp_sel; | |
329 | wire sel_cmp_pass; | |
330 | wire [1:0] cntl_data_sel; | |
331 | wire cntl_addr_mix; | |
332 | wire [3:0] cntl_march_element; | |
333 | wire sel_march_1_pass; | |
334 | wire addr_mix; | |
335 | wire cout_addr; | |
336 | wire upaddr; | |
337 | wire march_0; | |
338 | wire march_1; | |
339 | wire march_2; | |
340 | wire march_6; | |
341 | wire march_7; | |
342 | wire [3:0] march_element_pre; | |
343 | wire march_pre_0; | |
344 | wire march_pre_1; | |
345 | wire march_pre_2; | |
346 | wire march_pre_6; | |
347 | wire march_pre_7; | |
348 | wire upaddr_pre; | |
349 | wire [7:0] incr_addr; | |
350 | wire [7:0] stop_addr; | |
351 | wire sel_rw_pass; | |
352 | wire one_cycle_march; | |
353 | wire march_5; | |
354 | wire five_cycle_march; | |
355 | wire march_8; | |
356 | wire two_cycle_march; | |
357 | wire mem_wr_pbi; | |
358 | wire march_3; | |
359 | wire march_4; | |
360 | wire rw_1; | |
361 | wire rw_0; | |
362 | wire rw_4; | |
363 | wire mem_wr; | |
364 | wire bisi_wr_mode; | |
365 | wire bisi_rd_mode; | |
366 | wire mem_rd_pbi; | |
367 | wire mem_rd; | |
368 | wire [7:0] adj_addr; | |
369 | wire rw_3; | |
370 | wire [7:0] mem_addr1; | |
371 | wire true_data_l; | |
372 | wire rw_2; | |
373 | wire true_data; | |
374 | wire [7:0] data_pat_sel; | |
375 | wire array_4; | |
376 | wire [7:0] mem_addr; | |
377 | wire [3:0] array_sel; | |
378 | wire [3:0] cmp_sel; | |
379 | wire [3:0] march_element; | |
380 | wire [2:0] rw; | |
381 | wire [1:0] cseq_cntl_out; | |
382 | wire cseq_reg_scanin; | |
383 | wire cseq_reg_scanout; | |
384 | wire [1:0] cseq_out; | |
385 | wire [1:0] cam_sel_cntl_out; | |
386 | wire [1:0] ctest_sel_cntl_out; | |
387 | wire ctest_sel_reg_scanin; | |
388 | wire ctest_sel_reg_scanout; | |
389 | wire [1:0] ctest_sel_out; | |
390 | wire [3:0] array_sel_cntl_out; | |
391 | wire array_sel_reg_scanin; | |
392 | wire array_sel_reg_scanout; | |
393 | wire [3:0] array_sel_out; | |
394 | wire [3:0] cmp_sel_cntl_out; | |
395 | wire cmp_sel_reg_scanin; | |
396 | wire cmp_sel_reg_scanout; | |
397 | wire [3:0] cmp_sel_out; | |
398 | wire [3:0] march_element_cntl_out; | |
399 | wire marche_element_reg_scanin; | |
400 | wire marche_element_reg_scanout; | |
401 | wire [3:0] march_element_out; | |
402 | wire sel_rw_1_pass; | |
403 | wire sel_rw_2_pass; | |
404 | wire sel_rw_5_pass; | |
405 | wire [3:0] mb_cmp_sel; | |
406 | wire [7:0] mb_addr; | |
407 | wire [7:0] mb_write_data; | |
408 | wire mb_array_0_rd; | |
409 | wire mb_array_1_rd; | |
410 | wire mb_array_2_rd; | |
411 | wire mb_array_3_rd; | |
412 | wire mb_array_4_rd; | |
413 | wire mb_array_0_wr; | |
414 | wire mb_array_1_wr; | |
415 | wire mb_array_2_wr; | |
416 | wire mb_array_3_wr; | |
417 | wire mb_array_4_wr; | |
418 | wire mb_run; | |
419 | wire [4:0] done_delay; | |
420 | wire msb_latch_scanin; | |
421 | wire msb_latch_scanout; | |
422 | wire msb_in; | |
423 | wire msb_out; | |
424 | wire mb_done; | |
425 | wire run3_transition_reg_scanin; | |
426 | wire run3_transition_reg_scanout; | |
427 | wire run3_out; | |
428 | wire run3_transition; | |
429 | wire done_delay_reg_scanin; | |
430 | wire done_delay_reg_scanout; | |
431 | wire [4:0] done_delay_in; | |
432 | wire mb_ic0_rw_fail; | |
433 | wire mb_ic1_rw_fail; | |
434 | wire mb_dc0_rw_fail; | |
435 | wire mb_dc1_rw_fail; | |
436 | wire mb_oqarray_rw_fail; | |
437 | wire ic0_fail_d; | |
438 | wire ic0_fail_sticky; | |
439 | wire ic1_fail_d; | |
440 | wire ic1_fail_sticky; | |
441 | wire dc0_fail_d; | |
442 | wire dc0_fail_sticky; | |
443 | wire dc1_fail_d; | |
444 | wire dc1_fail_sticky; | |
445 | wire oqarray_fail_d; | |
446 | wire oqarray_fail_sticky; | |
447 | wire icrow0_cam_fail_d; | |
448 | wire icrow0_cam_fail_sticky; | |
449 | wire icrow1_cam_fail_d; | |
450 | wire icrow1_cam_fail_sticky; | |
451 | wire dcrow0_cam_fail_d; | |
452 | wire dcrow0_cam_fail_sticky; | |
453 | wire dcrow1_cam_fail_d; | |
454 | wire dcrow1_cam_fail_sticky; | |
455 | wire mbist_fail_input_reg_scanin; | |
456 | wire mbist_fail_input_reg_scanout; | |
457 | wire mbist_fail_sticky; | |
458 | wire mbist_fail_array; | |
459 | wire mb_fail; | |
460 | wire out_mb_tcu_done_reg_scanin; | |
461 | wire out_mb_tcu_done_reg_scanout; | |
462 | wire mb_done_out; | |
463 | wire inv_mask_reg_scanin; | |
464 | wire inv_mask_reg_scanout; | |
465 | wire out_mb_tcu_fail_reg_scanin; | |
466 | wire out_mb_tcu_fail_reg_scanout; | |
467 | wire mb_fail_out; | |
468 | wire out_cmp_sel_reg_scanin; | |
469 | wire out_cmp_sel_reg_scanout; | |
470 | wire [3:0] mb_cmpsel_out; | |
471 | wire out_run_mb_arrays_reg_scanin; | |
472 | wire out_run_mb_arrays_reg_scanout; | |
473 | wire mb_run_out; | |
474 | wire out_data_mb_arrays_reg_scanin; | |
475 | wire out_data_mb_arrays_reg_scanout; | |
476 | wire [7:0] mb_write_data_out; | |
477 | wire out_addr_mb_arrays_reg_scanin; | |
478 | wire out_addr_mb_arrays_reg_scanout; | |
479 | wire [7:0] mb_addr_out; | |
480 | wire out_wr_mb_arrays_reg_scanin; | |
481 | wire out_wr_mb_arrays_reg_scanout; | |
482 | wire mb_array_0_wr_out; | |
483 | wire mb_array_1_wr_out; | |
484 | wire mb_array_2_wr_out; | |
485 | wire mb_array_3_wr_out; | |
486 | wire mb_array_4_wr_out; | |
487 | wire out_rd_mb_arrays_reg_scanin; | |
488 | wire out_rd_mb_arrays_reg_scanout; | |
489 | wire mb_array_0_rd_out; | |
490 | wire mb_array_1_rd_out; | |
491 | wire mb_array_2_rd_out; | |
492 | wire mb_array_3_rd_out; | |
493 | wire mb_array_4_rd_out; | |
494 | wire spares_scanin; | |
495 | wire spares_scanout; | |
496 | ||
497 | ||
498 | // Please note that this is going to be used as a place holder. | |
499 | // The inputs and outputs are defined based on the analysis of cluster memories. | |
500 | // For this version, the outputs of memories are taken into mbist controller. | |
501 | // | |
502 | ||
503 | ||
504 | ||
505 | // ///////////////////////////////////////////////////////////////////////////// | |
506 | // Outputs | |
507 | // ///////////////////////////////////////////////////////////////////////////// | |
508 | ||
509 | output mb0_l2t_run; | |
510 | output mb0_l2t_cambist; | |
511 | // IC row | |
512 | output [5:0] mb0_l2t_addr; // Writing to 1/64 entries | |
513 | output mb0_l2t_icrow_wr_en; | |
514 | output mb0_l2t_icrow_rd_en; | |
515 | output [15:0] mb0_l2t_lookup_wdata; // CAM compare data | |
516 | output [3:0] mb0_l2t_icrow_lookup_en; // CAM enable for 4 panels | |
517 | output [1:0] mb0_l2t_icrow_row_en; // pick 1/2 rows | |
518 | output [3:0] mb0_l2t_icrow_panel_en; // one of 4 panels select | |
519 | ||
520 | output [7:0] mb0_l2t_mbist_write_data; // only for oqarray | |
521 | ||
522 | // DC row | |
523 | output mb0_l2t_dcrow_wr_en; | |
524 | output mb0_l2t_dcrow_rd_en; | |
525 | output [3:0] mb0_l2t_dcrow_lookup_en; // CAM enable for 4 panels | |
526 | output [1:0] mb0_l2t_dcrow_row_en; // pick 1/2 rows | |
527 | output [3:0] mb0_l2t_dcrow_panel_en; // one of 4 panels select | |
528 | ||
529 | output [7:0] mb0_l2t_mask; // mask to mask off the cam hit resetting valid bit | |
530 | ||
531 | output mb0_l2t_oqarray_wr_en; | |
532 | output mb0_l2t_oqarray_rd_en; | |
533 | output [3:0] mb0_l2t_cmpsel; // 1/16 mux select | |
534 | output mb0_l2t_done; | |
535 | output mb0_l2t_fail; | |
536 | ||
537 | output scan_out; | |
538 | ||
539 | input [1:0] dc_cam_fail; // free flowing will be qualified in mb0 | |
540 | input [1:0] ic_cam_fail; // free flowing will be qualified in mb0 | |
541 | input [3:0] dir_dc_rw_fail; // free flowing will be qualified in mb0 | |
542 | input [3:0] dir_ic_rw_fail; // free flowing will be qualified in mb0 | |
543 | ||
544 | input oqarray_rw_fail; | |
545 | ||
546 | ||
547 | /////////////////////////////////////////////////////////////////////////////// | |
548 | // Inputs | |
549 | /////////////////////////////////////////////////////////////////////////////// | |
550 | ||
551 | input l2clk; | |
552 | input scan_in; | |
553 | input tcu_pce_ov; // scan signals | |
554 | input tcu_aclk; | |
555 | input tcu_bclk; | |
556 | input tcu_scan_en; | |
557 | input tcu_clk_stop; | |
558 | ||
559 | input mbist_start; | |
560 | input mbist_user_mode; | |
561 | input mbist_bisi_mode; | |
562 | ||
563 | ||
564 | // ///////////////////////////////////////////////////////////////////////////// | |
565 | // Scan Renames | |
566 | // ///////////////////////////////////////////////////////////////////////////// | |
567 | ||
568 | assign pce_ov = tcu_pce_ov; | |
569 | assign stop = tcu_clk_stop; | |
570 | assign siclk = tcu_aclk; | |
571 | assign soclk = tcu_bclk; | |
572 | assign se = tcu_scan_en; | |
573 | ||
574 | ||
575 | ||
576 | //////////////////////////////////////////////////////////////////////////////// | |
577 | // Clock header | |
578 | ||
579 | ||
580 | ||
581 | l2t_mb0_ctl_l1clkhdr_ctl_macro clkgen_freeclk ( | |
582 | .l2clk (l2clk ), | |
583 | .l1en (1'b1 ), | |
584 | .l1clk (l1clk ), | |
585 | .pce_ov(pce_ov), | |
586 | .stop(stop), | |
587 | .se(se)); | |
588 | ||
589 | ||
590 | ||
591 | assign clock_enable = start_in | mb0_l2t_done | mb0_l2t_run | mb0_l2t_fail ; | |
592 | ||
593 | l2t_mb0_ctl_l1clkhdr_ctl_macro clkgen ( | |
594 | .l2clk (l2clk ), | |
595 | .l1en (clock_enable ), | |
596 | .l1clk (l1clk_pm1 ), | |
597 | .pce_ov(pce_ov), | |
598 | .stop(stop), | |
599 | .se(se) | |
600 | ); | |
601 | ||
602 | ||
603 | ||
604 | // ///////////////////////////////////////////////////////////////////////////// | |
605 | // | |
606 | // user mode resgisters | |
607 | // MBIST PGM Control Register | |
608 | // | |
609 | // ///////////////////////////////////////////////////////////////////////////// | |
610 | // ///////////////////////////////////////////////////////////////////////////// | |
611 | ||
612 | // TEMP ASSIGN | |
613 | ||
614 | ||
615 | ||
616 | // there are 4 panels in the directory and 2 rows. | |
617 | // One of the rows depending on the read enable/row select | |
618 | // picks the row and muxes the top/bottom column | |
619 | // Hence there are 4 places where in the data gets compared | |
620 | // and 4 bit NOT fail. All the 4 bit fails should be OR-ed | |
621 | // after inverting it. | |
622 | ||
623 | ||
624 | assign mb_ic_rw_fail = |(~(dir_ic_rw_fail[3:0])); | |
625 | assign mb_dc_rw_fail = |(~(dir_dc_rw_fail[3:0])); | |
626 | ||
627 | //////////////////////////////////////////////////////////////////////////////// | |
628 | // user control registers | |
629 | // size | |
630 | // - user_array_sel 4 | |
631 | // - user_addr_mode 1 | |
632 | // - user_start_addr 15 | |
633 | // - user_stop_addr 15 | |
634 | // - user_inc_addr 15 | |
635 | // - user_data_mode 1 | |
636 | // - user_data 8 | |
637 | // - user_cmpsel_hold 1 | |
638 | // - user_cmpsel 3 | |
639 | // - user_loop_mode 1 | |
640 | ||
641 | l2t_mb0_ctl_msff_ctl_macro__width_4 array_usr_reg ( | |
642 | .scan_in(array_usr_reg_scanin), | |
643 | .scan_out(array_usr_reg_scanout), | |
644 | .l1clk ( l1clk_pm1 ), | |
645 | .din ( user_array_sel_in[3:0] ), | |
646 | .dout ( user_array_sel[3:0] ), | |
647 | .siclk(siclk), | |
648 | .soclk(soclk)); | |
649 | ||
650 | assign user_array_sel_in[3:0]=user_array_sel[3:0]; | |
651 | ||
652 | ||
653 | // user address mode | |
654 | ||
655 | l2t_mb0_ctl_msff_ctl_macro__width_1 user_addr_mode_reg ( | |
656 | .scan_in(user_addr_mode_reg_scanin), | |
657 | .scan_out(user_addr_mode_reg_scanout), | |
658 | .l1clk ( l1clk_pm1 ), | |
659 | .din ( user_addr_mode_in ), | |
660 | .dout ( user_addr_mode ), | |
661 | .siclk(siclk), | |
662 | .soclk(soclk)); | |
663 | ||
664 | assign user_addr_mode_in=user_addr_mode; | |
665 | ||
666 | ||
667 | // user start address | |
668 | ||
669 | l2t_mb0_ctl_msff_ctl_macro__width_8 user_start_addr_reg ( | |
670 | .scan_in(user_start_addr_reg_scanin), | |
671 | .scan_out(user_start_addr_reg_scanout), | |
672 | .l1clk ( l1clk_pm1 ), | |
673 | .din ( user_start_addr_in[7:0] ), | |
674 | .dout ( user_start_addr[7:0] ), | |
675 | .siclk(siclk), | |
676 | .soclk(soclk)); | |
677 | ||
678 | ||
679 | assign user_start_addr_in[7:0]=user_start_addr[7:0]; | |
680 | ||
681 | // user stop address | |
682 | ||
683 | l2t_mb0_ctl_msff_ctl_macro__width_8 user_stop_addr_reg ( | |
684 | .scan_in(user_stop_addr_reg_scanin), | |
685 | .scan_out(user_stop_addr_reg_scanout), | |
686 | .l1clk ( l1clk_pm1 ), | |
687 | .din ( user_stop_addr_in[7:0] ), | |
688 | .dout ( user_stop_addr[7:0] ), | |
689 | .siclk(siclk), | |
690 | .soclk(soclk)); | |
691 | ||
692 | ||
693 | assign user_stop_addr_in[7:0]=user_stop_addr[7:0]; | |
694 | ||
695 | ||
696 | // user increment address | |
697 | ||
698 | l2t_mb0_ctl_msff_ctl_macro__width_8 user_incr_addr_reg ( | |
699 | .scan_in(user_incr_addr_reg_scanin), | |
700 | .scan_out(user_incr_addr_reg_scanout), | |
701 | .l1clk ( l1clk_pm1 ), | |
702 | .din ( user_incr_addr_in[7:0] ), | |
703 | .dout ( user_incr_addr[7:0] ), | |
704 | .siclk(siclk), | |
705 | .soclk(soclk)); | |
706 | ||
707 | ||
708 | assign user_incr_addr_in[7:0]=user_incr_addr[7:0]; | |
709 | ||
710 | // user data mode | |
711 | ||
712 | l2t_mb0_ctl_msff_ctl_macro__width_1 user_data_mode_reg ( | |
713 | .scan_in(user_data_mode_reg_scanin), | |
714 | .scan_out(user_data_mode_reg_scanout), | |
715 | .l1clk ( l1clk_pm1 ), | |
716 | .din ( user_data_mode_in ), | |
717 | .dout ( user_data_mode ), | |
718 | .siclk(siclk), | |
719 | .soclk(soclk)); | |
720 | ||
721 | ||
722 | assign user_data_mode_in=user_data_mode; | |
723 | ||
724 | // user data select | |
725 | ||
726 | l2t_mb0_ctl_msff_ctl_macro__width_8 user_data_reg ( | |
727 | .scan_in(user_data_reg_scanin), | |
728 | .scan_out(user_data_reg_scanout), | |
729 | .l1clk ( l1clk_pm1 ), | |
730 | .din ( user_data_in[7:0] ), | |
731 | .dout ( user_data[7:0] ), | |
732 | .siclk(siclk), | |
733 | .soclk(soclk)); | |
734 | ||
735 | ||
736 | assign user_data_in[7:0] = user_data[7:0]; | |
737 | ||
738 | // user cmp sel inc | |
739 | // if its one, user need to program the cmpselinc register | |
740 | // otherwise it will loop all cmpsel | |
741 | ||
742 | l2t_mb0_ctl_msff_ctl_macro__width_1 user_cmpsel_hold_reg ( | |
743 | .scan_in(user_cmpsel_hold_reg_scanin), | |
744 | .scan_out(user_cmpsel_hold_reg_scanout), | |
745 | .l1clk ( l1clk_pm1 ), | |
746 | .din ( user_cmpsel_hold_in ), | |
747 | .dout ( user_cmpsel_hold ), | |
748 | .siclk(siclk), | |
749 | .soclk(soclk)); | |
750 | ||
751 | ||
752 | assign user_cmpsel_hold_in=user_cmpsel_hold; | |
753 | ||
754 | ||
755 | ||
756 | // user cmp sel reg | |
757 | ||
758 | l2t_mb0_ctl_msff_ctl_macro__width_4 user_cmpsel_reg ( | |
759 | .scan_in(user_cmpsel_reg_scanin), | |
760 | .scan_out(user_cmpsel_reg_scanout), | |
761 | .l1clk ( l1clk_pm1 ), | |
762 | .din ( user_cmpsel_in[3:0] ), | |
763 | .dout ( user_cmpsel[3:0] ), | |
764 | .siclk(siclk), | |
765 | .soclk(soclk)); | |
766 | ||
767 | assign user_cmpsel_in[3:0]=user_cmpsel[3:0]; | |
768 | ||
769 | ||
770 | // user loop mode | |
771 | ||
772 | l2t_mb0_ctl_msff_ctl_macro__width_1 user_loop_mode_reg ( | |
773 | .scan_in(user_loop_mode_reg_scanin), | |
774 | .scan_out(user_loop_mode_reg_scanout), | |
775 | .l1clk ( l1clk_pm1 ), | |
776 | .din ( user_loop_mode_in ), | |
777 | .dout ( user_loop_mode ), | |
778 | .siclk(siclk), | |
779 | .soclk(soclk)); | |
780 | ||
781 | ||
782 | assign user_loop_mode_in=user_loop_mode; | |
783 | ||
784 | ||
785 | ||
786 | // 10N Algorithm for bit mapping | |
787 | ||
788 | l2t_mb0_ctl_msff_ctl_macro__width_1 ten_n_mode_reg ( | |
789 | .scan_in(ten_n_mode_reg_scanin), | |
790 | .scan_out(ten_n_mode_reg_scanout), | |
791 | .l1clk ( l1clk_pm1 ), | |
792 | .din ( ten_n_mode_in ), | |
793 | .dout ( ten_n_mode ), | |
794 | .siclk(siclk), | |
795 | .soclk(soclk)); | |
796 | ||
797 | ||
798 | assign ten_n_mode_in=ten_n_mode; | |
799 | ||
800 | ||
801 | // cambist: user array select | |
802 | ||
803 | ||
804 | ||
805 | l2t_mb0_ctl_msff_ctl_macro__width_1 user_cam_mode_reg ( | |
806 | .scan_in(user_cam_mode_reg_scanin), | |
807 | .scan_out(user_cam_mode_reg_scanout), | |
808 | .l1clk ( l1clk_pm1 ), | |
809 | .din ( user_cam_mode_in ), | |
810 | .dout ( user_cam_mode ), | |
811 | .siclk(siclk), | |
812 | .soclk(soclk)); | |
813 | ||
814 | assign user_cam_mode_in=user_cam_mode; | |
815 | ||
816 | ||
817 | ||
818 | l2t_mb0_ctl_msff_ctl_macro__width_2 user_cam_select_reg ( | |
819 | .scan_in(user_cam_select_reg_scanin), | |
820 | .scan_out(user_cam_select_reg_scanout), | |
821 | .l1clk ( l1clk_pm1 ), | |
822 | .din ( user_cam_sel_in[1:0] ), | |
823 | .dout ( user_cam_sel[1:0] ), | |
824 | .siclk(siclk), | |
825 | .soclk(soclk)); | |
826 | ||
827 | assign user_cam_sel_in[1:0]=user_cam_sel[1:0]; | |
828 | ||
829 | ||
830 | l2t_mb0_ctl_msff_ctl_macro__width_2 user_cam_test_select_reg ( | |
831 | .scan_in(user_cam_test_select_reg_scanin), | |
832 | .scan_out(user_cam_test_select_reg_scanout), | |
833 | .l1clk ( l1clk_pm1 ), | |
834 | .din ( user_cam_test_sel_in[1:0] ), | |
835 | .dout ( user_cam_test_sel[1:0] ), | |
836 | .siclk(siclk), | |
837 | .soclk(soclk)); | |
838 | ||
839 | assign user_cam_test_sel_in[1:0]=user_cam_test_sel[1:0]; | |
840 | ||
841 | ||
842 | l2t_mb0_ctl_msff_ctl_macro__width_1 user_bisi_wr_mode_reg ( | |
843 | .scan_in(user_bisi_wr_mode_reg_scanin), | |
844 | .scan_out(user_bisi_wr_mode_reg_scanout), | |
845 | .l1clk ( l1clk_pm1 ), | |
846 | .din ( user_bisi_wr_mode_in ), | |
847 | .dout ( user_bisi_wr_mode ), | |
848 | .siclk(siclk), | |
849 | .soclk(soclk)); | |
850 | ||
851 | assign user_bisi_wr_mode_in=user_bisi_wr_mode; | |
852 | ||
853 | l2t_mb0_ctl_msff_ctl_macro__width_1 user_bisi_rd_mode_reg ( | |
854 | .scan_in(user_bisi_rd_mode_reg_scanin), | |
855 | .scan_out(user_bisi_rd_mode_reg_scanout), | |
856 | .l1clk ( l1clk_pm1 ), | |
857 | .din ( user_bisi_rd_mode_in ), | |
858 | .dout ( user_bisi_rd_mode ), | |
859 | .siclk(siclk), | |
860 | .soclk(soclk)); | |
861 | ||
862 | assign user_bisi_rd_mode_in=user_bisi_rd_mode; | |
863 | ||
864 | ||
865 | ||
866 | assign mb_user_data_mode = user_mode & user_data_mode; | |
867 | assign mb_user_addr_mode = user_mode & user_addr_mode; | |
868 | assign mb_user_cmpsel_hold = user_mode & user_cmpsel_hold; | |
869 | assign mb_user_cam_mode = user_mode & user_cam_mode; | |
870 | assign mb_user_ram_mode = user_mode & ~user_cam_mode; | |
871 | assign mb_user_loop_mode = user_mode & user_loop_mode; | |
872 | ||
873 | ||
874 | assign mb_user_bisi_wr_mode = user_mode & user_bisi_wr_mode & bisi_mode; | |
875 | assign mb_user_bisi_rd_mode = user_mode & user_bisi_rd_mode & bisi_mode; | |
876 | ||
877 | assign mb_user_bisi_rw_mode = ((~user_bisi_wr_mode & ~user_bisi_rd_mode) | (user_bisi_wr_mode & user_bisi_rd_mode)) & bisi_mode; | |
878 | ||
879 | assign mb_default_bisi = bisi_mode & ~user_mode; | |
880 | ||
881 | ||
882 | ||
883 | // ///////////////////////////////////////////////////////////////////////////// | |
884 | // | |
885 | // MBIST Config Register | |
886 | // | |
887 | // ///////////////////////////////////////////////////////////////////////////// | |
888 | // | |
889 | // A low to high transition on mbist_start will reset and start the engine. | |
890 | // mbist_start must remain active high for the duration of MBIST. | |
891 | // If mbist_start deasserts the engine will stop but not reset. | |
892 | // Once MBIST has completed mb0_done will assert and the fail status | |
893 | // signals will be valid. | |
894 | // To run MBIST again the mbist_start signal must transition low then high. | |
895 | // | |
896 | // Loop on Address will disable the address mix function. | |
897 | // | |
898 | // ///////////////////////////////////////////////////////////////////////////// | |
899 | ||
900 | ||
901 | // flop incoming signals: | |
902 | ||
903 | l2t_mb0_ctl_msff_ctl_macro__width_3 input_signals_reg ( | |
904 | .scan_in(input_signals_reg_scanin), | |
905 | .scan_out(input_signals_reg_scanout), | |
906 | .l1clk ( l1clk ), | |
907 | .din ( {mbist_start,mbist_bisi_mode,mbist_user_mode} ), | |
908 | .dout ( {start_in,bisi_mode,user_mode} ), | |
909 | .siclk(siclk), | |
910 | .soclk(soclk)); | |
911 | ||
912 | ||
913 | ||
914 | // default : mb_enable=0 | |
915 | // bisi : mb_enable=0 | |
916 | // user_mode : mb_enable=depend on programmed value | |
917 | ||
918 | l2t_mb0_ctl_msff_ctl_macro__width_1 mb_enable_reg ( | |
919 | .scan_in(mb_enable_reg_scanin), | |
920 | .scan_out(mb_enable_reg_scanout), | |
921 | .l1clk ( l1clk_pm1 ), | |
922 | .din ( mb_enable ), | |
923 | .dout ( mb_enable_out ), | |
924 | .siclk(siclk), | |
925 | .soclk(soclk)); | |
926 | ||
927 | ||
928 | assign mb_enable = user_mode ? mb_enable_out : 1'b0; | |
929 | ||
930 | ||
931 | assign start = user_mode ? (mb_enable_out & start_in) : | |
932 | (start_in); | |
933 | ||
934 | ||
935 | ||
936 | l2t_mb0_ctl_msff_ctl_macro__width_2 config_reg ( | |
937 | .scan_in(config_reg_scanin), | |
938 | .scan_out(config_reg_scanout), | |
939 | .l1clk ( l1clk_pm1 ), | |
940 | .din ( config_in[1:0] ), | |
941 | .dout ( config_out[1:0] ), | |
942 | .siclk(siclk), | |
943 | .soclk(soclk)); | |
944 | ||
945 | ||
946 | assign config_in[0] = start; | |
947 | assign config_in[1] = config_out[0]; | |
948 | assign start_transition = config_out[0] & ~config_out[1]; | |
949 | assign end_transition = ~config_out[0] & config_out[1]; | |
950 | assign reset_engine = start_transition | loop_again | end_transition; | |
951 | assign run = config_out[1]; | |
952 | ||
953 | ||
954 | l2t_mb0_ctl_msff_ctl_macro__width_1 loop_again_reg ( | |
955 | .scan_in(loop_again_reg_scanin), | |
956 | .scan_out(loop_again_reg_scanout), | |
957 | .l1clk ( l1clk_pm1 ), | |
958 | .din ( stop_engine_l ), | |
959 | .dout ( stop_engine_l_q ), | |
960 | .siclk(siclk), | |
961 | .soclk(soclk)); | |
962 | ||
963 | ||
964 | assign loop_again=mb_user_loop_mode ? stop_engine_l & ~stop_engine_l_q: 1'b0; | |
965 | ||
966 | ||
967 | ||
968 | ||
969 | // ///////////////////////////////////////////////////////////////////////////// | |
970 | // | |
971 | // MBIST Control Register | |
972 | // | |
973 | // ///////////////////////////////////////////////////////////////////////////// | |
974 | // standard membist | |
975 | // ///////////////////////////////////////////////////////////////////////////// | |
976 | // 0 1 2 3 4 5 6 7 8 | |
977 | // ^(W0);^(R0W1);^(R1W0);v(R0W1);v(R1W0);v(R0);^(W1W0*R1R0W0);^(W1);v(W0W1*R0R1W1); | |
978 | // | |
979 | ||
980 | // mbist address: | |
981 | ||
982 | ||
983 | ||
984 | ||
985 | // ///////////////////////////////////////////////////////////////////////////// | |
986 | // | |
987 | // CAM BIST: | |
988 | // | |
989 | // ///////////////////////////////////////////////////////////////////////////// | |
990 | ||
991 | // cambistwork | |
992 | ||
993 | ||
994 | // - ctest 0: match camdata 0 | |
995 | // - write data 0 ^(W0); | |
996 | // - cam data 0 ^(W0C0RxW1); | |
997 | // this requires (cseq0, cseq1, cseq2, cseq3) | |
998 | // - ctest 1: match camdata 1 | |
999 | // - write data 1 ^(W1); | |
1000 | // - camdata 1 ^(W1C1RxW0); | |
1001 | // this requires (cseq0, cseq1, cseq2, cseq3) | |
1002 | // - ctest 2: walking1 mismatch | |
1003 | // - write 0 | |
1004 | // - walking 1 | |
1005 | // | |
1006 | ||
1007 | // ctest0: | |
1008 | // cseq0: camdata | |
1009 | // crw0 write 0 | |
1010 | // cseq1: | |
1011 | // crw0 write 1 | |
1012 | // crw1 cam 1 | |
1013 | // crw2 write1 0 | |
1014 | // crw3 dead cycle 0 | |
1015 | ||
1016 | // cseq1: camdata (valid bit test) | |
1017 | // crw0 write 0 | |
1018 | // cseq2: | |
1019 | // crw0 write 1 | |
1020 | // crw1 cam 1 | |
1021 | // crw2 write1 0 | |
1022 | // crw3 dead cycle 0 | |
1023 | ||
1024 | // ctest1: | |
1025 | // cseq0: camdata | |
1026 | // crw0 write 1 | |
1027 | // cseq1: | |
1028 | // crw0 write 0 | |
1029 | // crw1 cam 0 | |
1030 | // crw2 write1 1 | |
1031 | // crw3 dead cycle 0 | |
1032 | // cseq2: camdata (valid bit test) | |
1033 | // crw0 write 1 | |
1034 | // cseq3: | |
1035 | // crw0 write 0 | |
1036 | // crw1 cam 0 | |
1037 | // crw2 write1 1 | |
1038 | // crw3 dead cycle 0 | |
1039 | ||
1040 | ||
1041 | // ctest2: camdata | |
1042 | // cseq0: write 0 | |
1043 | // cseq1-2: walkin1 N/A | |
1044 | // cam_zer0 | |
1045 | // cam_walk1 | |
1046 | ||
1047 | ||
1048 | l2t_mb0_ctl_msff_ctl_macro__width_19 cam_cntl_reg ( | |
1049 | .scan_in(cam_cntl_reg_scanin), | |
1050 | .scan_out(cam_cntl_reg_scanout), | |
1051 | .l1clk ( l1clk_pm1 ), | |
1052 | .din ( cam_in[18:0] ), | |
1053 | .dout ( cam_out[18:0] ), | |
1054 | .siclk(siclk), | |
1055 | .soclk(soclk)); | |
1056 | ||
1057 | ||
1058 | l2t_mb0_ctl_msff_ctl_macro__width_1 cam_shift_reg ( | |
1059 | .scan_in(cam_shift_reg_scanin), | |
1060 | .scan_out(cam_shift_reg_scanout), | |
1061 | .l1clk ( l1clk_pm1 ), | |
1062 | .din ( cam_shift_val ), | |
1063 | .dout ( cam_shift ), | |
1064 | .siclk(siclk), | |
1065 | .soclk(soclk)); | |
1066 | ||
1067 | ||
1068 | assign cam_msb = start_in & cam_out[18]; // | |
1069 | ||
1070 | assign cam_array_sel[1:0] = mb_user_cam_mode ? 2'b11: | |
1071 | cam_out[17:16]; // 2 bits | |
1072 | ||
1073 | assign cam_panel_sel[1:0] = cam_out[15:14]; | |
1074 | ||
1075 | // assign ctest[1:0] = mb_user_cam_mode ? user_cam_test_sel[1:0] : | |
1076 | assign ctest[1:0] = mb_user_cam_mode ? 2'b11 : | |
1077 | cam_out[13:12]; // | |
1078 | ||
1079 | assign cam_cseq[1:0] = sel_cseq_pass ? 2'b11 : cam_out[11:10]; | |
1080 | ||
1081 | // assign cam_addr[7:0] = (ctest2_out & cseq2_out) ? cam_out[9:2]: | |
1082 | // (ctest3_out & cseq2_out) ? cam_out[9:2]: | |
1083 | // (cam_walk1 & cseq3_out) ? {4'b1111,cam_out[5:2]}: | |
1084 | // cam_out[9:2]; | |
1085 | ||
1086 | assign cam_addr[7:0] = (ctest2 | ctest3) & cseq1 ? {1'b1, cam_out[8:2]}: | |
1087 | {2'b11, cam_out[7:2]}; | |
1088 | ||
1089 | ||
1090 | // assign cam_crw[1:0] = (cseq2_out) ? 2'b11: | |
1091 | // (ctest2_out) ? 2'b11: | |
1092 | // (ctest3_out) ? 2'b11: | |
1093 | // cam_out[1:0]; // read write control | |
1094 | ||
1095 | ||
1096 | assign cam_crw[1:0] = sel_crw_pass ? 2'b11: | |
1097 | cam_out[1:0]; // read write control | |
1098 | ||
1099 | ||
1100 | ||
1101 | assign crw[1:0] = cam_out[1:0]; | |
1102 | ||
1103 | assign sel_cseq_pass = (ctest2 & cseq1) | | |
1104 | (ctest3 & cseq2) ; | |
1105 | ||
1106 | assign sel_crw_pass = ((cseq0 | cseq2 | ((ctest2 | ctest3) & cseq1)) & cambist); | |
1107 | ||
1108 | // assign ctest2_out=cam_out[13:12]==2'b10; | |
1109 | // assign ctest3_out=cam_out[13:12]==2'b11; | |
1110 | ||
1111 | ||
1112 | assign ctest0 = ctest_sel[1:0]==2'b00 & cambist; | |
1113 | assign ctest1 = ctest_sel[1:0]==2'b01 & cambist; | |
1114 | assign ctest2 = ctest_sel[1:0]==2'b10 & cambist; | |
1115 | assign ctest3 = ctest_sel[1:0]==2'b11 & cambist; | |
1116 | ||
1117 | assign cseq0 = ~( cseq[1] | cseq[0]); | |
1118 | assign cseq1 = ~( cseq[1] | ~cseq[0]); | |
1119 | assign cseq2 = ~(~cseq[1] | cseq[0]); | |
1120 | assign cseq3 = ~(~cseq[1] | ~cseq[0]); | |
1121 | ||
1122 | assign crw0 = ~( crw[1] | crw[0]); | |
1123 | assign crw1 = ~( crw[1] | ~crw[0]); | |
1124 | assign crw2 = ~(~crw[1] | crw[0]); | |
1125 | assign crw3 = ~(~crw[1] | ~crw[0]); | |
1126 | ||
1127 | // use lookup_wdata for write data and cam data | |
1128 | // bit 15 valid, bit 14 parity | |
1129 | assign lookup_wdata[15:0] = (ctest0 & (cseq1 | cseq3) & (crw0 | crw1 | crw2)) | | |
1130 | (ctest1 & (cseq0 | cseq2) & crw0) | | |
1131 | (ctest1 & (cseq1 | cseq3) & crw3) | | |
1132 | (ctest2 & cseq0) ? 16'hBFFF: | |
1133 | (ctest3 & cseq0 ) ? 16'h8000: | |
1134 | (ctest3 & cseq2 ) ? 16'h0000: | |
1135 | (ctest3 & cam_zero) ? 16'h8001: | |
1136 | (ctest3 & cam_shift) ? {2'b10,mb0_l2t_lookup_wdata[12:0],1'b0}: | |
1137 | (ctest2 & cam_zero) ? 16'hBFFE: | |
1138 | (ctest2 & cam_shift) ? {2'b10,mb0_l2t_lookup_wdata[12:0],1'b1}: | |
1139 | 16'h8000; | |
1140 | ||
1141 | ||
1142 | assign l2_mask[7:0] = (ctest0 & cseq1 ) | | |
1143 | (ctest1 & cseq1 ) ? 8'hFF: | |
1144 | 8'h00; | |
1145 | ||
1146 | ||
1147 | // assign cam_wr_en = (ctest0 & cseq2) ? crw3 : | |
1148 | // (ctest0 & cseq3) ? (crw0 | crw2) : | |
1149 | // (ctest1 & cseq2) ? crw3 : | |
1150 | // (ctest1 & cseq3) ? (crw0 | crw2) : | |
1151 | // (ctest2 & cseq2) ? crw3 : | |
1152 | // (ctest3 & cseq2) ? crw3 : | |
1153 | // 1'b0; | |
1154 | ||
1155 | ||
1156 | assign cam_wr_en = ( ctest0 & (cseq0 | cseq2) & crw0) | | |
1157 | ( ctest0 & (cseq1 | cseq3) & (crw0 | crw3)) | | |
1158 | ( ctest1 & (cseq0 | cseq2) & crw0) | | |
1159 | ( ctest1 & (cseq1 | cseq3) & (crw0 | crw3)) | | |
1160 | ( ctest2 & cseq0 & crw0) | | |
1161 | ( ctest3 & cseq0 & crw0) | | |
1162 | ( ctest3 & cseq2 ) ; | |
1163 | ||
1164 | // assign cam_en = (ctest0 & cseq3) ? crw1 : | |
1165 | // (ctest1 & cseq3) ? crw1 : | |
1166 | // (ctest2 & cseq3) ? cam_shift : | |
1167 | // (ctest3 & cseq3) ? cam_shift : | |
1168 | // 1'b0; | |
1169 | ||
1170 | assign cam_en = (ctest0 & (cseq1 | cseq3) & (crw1 | crw2)) | | |
1171 | (ctest1 & (cseq1 | cseq3) & (crw1 | crw2)) | | |
1172 | (cam_shift | cam_zero); // valid bit test | |
1173 | ||
1174 | ||
1175 | assign cam_walk1 = (ctest2 | ctest3) & cseq1; | |
1176 | ||
1177 | // assign end_shift = cam_walk1 & (tlb_addr[6] & tlb_addr[5] & ~tlb_addr[4] & tlb_addr[3] & ~tlb_addr[2] & ~tlb_addr[1] & ~tlb_addr[0]); | |
1178 | ||
1179 | assign cam_zero = ~|cam_addr[6:0] & cam_walk1 & cseq1; | |
1180 | ||
1181 | assign end_shift = cambist ? (cam_walk1 & (cam_addr[7:0]==8'b10001101)): | |
1182 | 1'b0; | |
1183 | ||
1184 | ||
1185 | assign cam_shift_val = ~cambist | end_shift ? 1'b0 : | |
1186 | cam_zero & cseq1 ? 1'b1 : | |
1187 | cam_shift; | |
1188 | ||
1189 | ||
1190 | assign qual_cam[18:0]={cam_msb, | |
1191 | cam_array_sel[1:0], | |
1192 | cam_panel_sel[1:0], | |
1193 | ctest[1:0], | |
1194 | cam_cseq[1:0], | |
1195 | cam_addr[7:0], | |
1196 | cam_crw[1:0]}; | |
1197 | ||
1198 | assign cam_in[18:0]=reset_engine ? 19'b0: // set zero | |
1199 | ~run3 | ~cambist ? qual_cam[18:0]: // save value | |
1200 | qual_cam[18:0]+19'h1; // increment | |
1201 | ||
1202 | ||
1203 | assign mb_icrow0_cam_hit= ic_cam_fail[0] & icrow_sel_d3[0]; | |
1204 | assign mb_icrow1_cam_hit= ic_cam_fail[1] & icrow_sel_d3[1]; | |
1205 | assign mb_dcrow0_cam_hit= dc_cam_fail[0] & dcrow_sel_d3[0]; | |
1206 | assign mb_dcrow1_cam_hit= dc_cam_fail[1] & dcrow_sel_d3[1]; | |
1207 | ||
1208 | ||
1209 | ||
1210 | l2t_mb0_ctl_msff_ctl_macro__width_4 cam_hit_reg ( | |
1211 | .scan_in(cam_hit_reg_scanin), | |
1212 | .scan_out(cam_hit_reg_scanout), | |
1213 | .l1clk ( l1clk_pm1 ), | |
1214 | .din ( {mb_icrow0_cam_hit, mb_icrow1_cam_hit, mb_dcrow0_cam_hit, mb_dcrow1_cam_hit} ), | |
1215 | .dout ( {icrow0_cam_hit, icrow1_cam_hit, dcrow0_cam_hit, dcrow1_cam_hit} ), | |
1216 | .siclk(siclk), | |
1217 | .soclk(soclk)); | |
1218 | ||
1219 | ||
1220 | ||
1221 | l2t_mb0_ctl_msff_ctl_macro__width_5 exp_cam_hit_delay_reg ( | |
1222 | .scan_in(exp_cam_hit_delay_reg_scanin), | |
1223 | .scan_out(exp_cam_hit_delay_reg_scanout), | |
1224 | .l1clk ( l1clk_pm1 ), | |
1225 | .din ( {cam_hit_cmp, cam_hit_cmp_d1,cam_hit_cmp_d2,cam_hit_cmp_d3, cam_hit_cmp_d4}), | |
1226 | .dout ( {cam_hit_cmp_d1,cam_hit_cmp_d2,cam_hit_cmp_d3,cam_hit_cmp_d4, cam_hit_cmp_d5}), | |
1227 | .siclk(siclk), | |
1228 | .soclk(soclk)); | |
1229 | ||
1230 | ||
1231 | l2t_mb0_ctl_msff_ctl_macro__width_5 exp_cam_exp_delay_reg ( | |
1232 | .scan_in(exp_cam_exp_delay_reg_scanin), | |
1233 | .scan_out(exp_cam_exp_delay_reg_scanout), | |
1234 | .l1clk ( l1clk_pm1 ), | |
1235 | .din ( {cam_hit_exp, cam_hit_exp_d1,cam_hit_exp_d2,cam_hit_exp_d3, cam_hit_exp_d4}), | |
1236 | .dout ( {cam_hit_exp_d1,cam_hit_exp_d2,cam_hit_exp_d3,cam_hit_exp_d4, cam_hit_exp_d5}), | |
1237 | .siclk(siclk), | |
1238 | .soclk(soclk)); | |
1239 | ||
1240 | ||
1241 | ||
1242 | l2t_mb0_ctl_msff_ctl_macro__width_10 cam_sel_icrow_delay_reg ( | |
1243 | .scan_in(cam_sel_icrow_delay_reg_scanin), | |
1244 | .scan_out(cam_sel_icrow_delay_reg_scanout), | |
1245 | .l1clk ( l1clk_pm1 ), | |
1246 | .din ( {mb0_l2t_icrow_row_en[1:0],icrow_sel_d1[1:0],icrow_sel_d2[1:0],icrow_sel_d3[1:0],icrow_sel_d4[1:0]}), | |
1247 | .dout ( {icrow_sel_d1[1:0], icrow_sel_d2[1:0],icrow_sel_d3[1:0],icrow_sel_d4[1:0],icrow_sel_d5[1:0]}), | |
1248 | .siclk(siclk), | |
1249 | .soclk(soclk)); | |
1250 | ||
1251 | ||
1252 | l2t_mb0_ctl_msff_ctl_macro__width_10 cam_sel_dcrow_delay_reg ( | |
1253 | .scan_in(cam_sel_dcrow_delay_reg_scanin), | |
1254 | .scan_out(cam_sel_dcrow_delay_reg_scanout), | |
1255 | .l1clk ( l1clk_pm1 ), | |
1256 | .din ( {mb0_l2t_dcrow_row_en[1:0],dcrow_sel_d1[1:0],dcrow_sel_d2[1:0],dcrow_sel_d3[1:0],dcrow_sel_d4[1:0]}), | |
1257 | .dout ( {dcrow_sel_d1[1:0], dcrow_sel_d2[1:0],dcrow_sel_d3[1:0],dcrow_sel_d4[1:0],dcrow_sel_d5[1:0]}), | |
1258 | .siclk(siclk), | |
1259 | .soclk(soclk)); | |
1260 | ||
1261 | ||
1262 | assign cam_hit_cmp =cam_en; | |
1263 | ||
1264 | assign cam_hit_exp =(ctest0 & cseq1 & crw1) | | |
1265 | (ctest0 & cseq3 & (crw1 | crw2)) | | |
1266 | (ctest1 & cseq1 & crw1) | | |
1267 | (ctest1 & cseq3 & (crw1 | crw2)) ; | |
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | assign icrow0_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == icrow0_cam_hit)); | |
1273 | assign icrow1_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == icrow1_cam_hit)); | |
1274 | assign dcrow0_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == dcrow0_cam_hit)); | |
1275 | assign dcrow1_cam_pass = (~cam_hit_cmp_d5) | (cam_hit_cmp_d5 & (cam_hit_exp_d5 == dcrow1_cam_hit)); | |
1276 | ||
1277 | ||
1278 | assign icrow0_cam_fail = ~icrow0_cam_pass & icrow_sel_d5[0]; | |
1279 | assign icrow1_cam_fail = ~icrow1_cam_pass & icrow_sel_d5[1]; | |
1280 | assign dcrow0_cam_fail = ~dcrow0_cam_pass & dcrow_sel_d5[0]; | |
1281 | assign dcrow1_cam_fail = ~dcrow1_cam_pass & dcrow_sel_d5[1]; | |
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | ||
1288 | assign cambist = ((mb_user_cam_mode | (cntl_msb & ~bisi_mode)) & (valid_fail & ~mb_user_ram_mode)); | |
1289 | ||
1290 | ||
1291 | assign cam_0 = (cam_sel[1:0]==2'b00) & cambist; | |
1292 | assign cam_1 = (cam_sel[1:0]==2'b01) & cambist; | |
1293 | assign cam_2 = (cam_sel[1:0]==2'b10) & cambist; | |
1294 | assign cam_3 = (cam_sel[1:0]==2'b11) & cambist; | |
1295 | ||
1296 | ||
1297 | ||
1298 | ||
1299 | ||
1300 | ||
1301 | ||
1302 | ||
1303 | // assign icrow_rd = mb_array_0_rd | mb_array_1_rd; | |
1304 | // assign icrow_wr = mb_array_0_wr | mb_array_1_wr; | |
1305 | ||
1306 | // assign dcrow_rd = mb_array_2_rd | mb_array_3_rd; | |
1307 | // assign dcrow_wr = mb_array_2_wr | mb_array_3_wr; | |
1308 | ||
1309 | ||
1310 | // cam signals | |
1311 | ||
1312 | assign icrow_lookup_en[0]=cam_en & (cam_0 | cam_1) & cam_panel_en_0; | |
1313 | assign icrow_lookup_en[1]=cam_en & (cam_0 | cam_1) & cam_panel_en_1; | |
1314 | assign icrow_lookup_en[2]=cam_en & (cam_0 | cam_1) & cam_panel_en_2; | |
1315 | assign icrow_lookup_en[3]=cam_en & (cam_0 | cam_1) & cam_panel_en_3; | |
1316 | ||
1317 | assign dcrow_lookup_en[0]=cam_en & (cam_2 | cam_3) & cam_panel_en_0; | |
1318 | assign dcrow_lookup_en[1]=cam_en & (cam_2 | cam_3) & cam_panel_en_1; | |
1319 | assign dcrow_lookup_en[2]=cam_en & (cam_2 | cam_3) & cam_panel_en_2; | |
1320 | assign dcrow_lookup_en[3]=cam_en & (cam_2 | cam_3) & cam_panel_en_3; | |
1321 | ||
1322 | ||
1323 | assign icrow_row_en[0]=array_0 | cam_0; | |
1324 | assign icrow_row_en[1]=array_1 | cam_1; | |
1325 | ||
1326 | assign dcrow_row_en[0]=array_2 | cam_2; | |
1327 | assign dcrow_row_en[1]=array_3 | cam_3; | |
1328 | ||
1329 | ||
1330 | assign panel_en_0 = cmp_0 & ~cambist; | |
1331 | assign panel_en_1 = cmp_1 & ~cambist; | |
1332 | assign panel_en_2 = cmp_2 & ~cambist; | |
1333 | assign panel_en_3 = cmp_3 & ~cambist; | |
1334 | ||
1335 | ||
1336 | assign cam_panel_en_0 = ~( cam_panel_sel[1] | cam_panel_sel[0]) & cambist; | |
1337 | assign cam_panel_en_1 = ~( cam_panel_sel[1] | ~cam_panel_sel[0]) & cambist; | |
1338 | assign cam_panel_en_2 = ~(~cam_panel_sel[1] | cam_panel_sel[0]) & cambist; | |
1339 | assign cam_panel_en_3 = ~(~cam_panel_sel[1] | ~cam_panel_sel[0]) & cambist; | |
1340 | ||
1341 | ||
1342 | ||
1343 | assign icrow_arrays = array_0 | array_1 | cam_0 | cam_1; | |
1344 | assign dcrow_arrays = array_2 | array_3 | cam_2 | cam_3; | |
1345 | ||
1346 | assign icrow_panel_en[0] = icrow_arrays & (panel_en_0 | cam_panel_en_0); | |
1347 | assign icrow_panel_en[1] = icrow_arrays & (panel_en_1 | cam_panel_en_1); | |
1348 | assign icrow_panel_en[2] = icrow_arrays & (panel_en_2 | cam_panel_en_2); | |
1349 | assign icrow_panel_en[3] = icrow_arrays & (panel_en_3 | cam_panel_en_3); | |
1350 | ||
1351 | assign dcrow_panel_en[0] = dcrow_arrays & (panel_en_0 | cam_panel_en_0); | |
1352 | assign dcrow_panel_en[1] = dcrow_arrays & (panel_en_1 | cam_panel_en_1); | |
1353 | assign dcrow_panel_en[2] = dcrow_arrays & (panel_en_2 | cam_panel_en_2); | |
1354 | assign dcrow_panel_en[3] = dcrow_arrays & (panel_en_3 | cam_panel_en_3); | |
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | l2t_mb0_ctl_msff_ctl_macro__width_21 mbist_output_reg ( | |
1362 | .scan_in(mbist_output_reg_scanin), | |
1363 | .scan_out(mbist_output_reg_scanout), | |
1364 | .l1clk ( l1clk_pm1 ), | |
1365 | .din ({ | |
1366 | cambist, | |
1367 | icrow_lookup_en[3:0], | |
1368 | icrow_row_en[1:0], | |
1369 | icrow_panel_en[3:0], | |
1370 | dcrow_lookup_en[3:0], | |
1371 | dcrow_row_en[1:0], | |
1372 | dcrow_panel_en[3:0] | |
1373 | }), | |
1374 | .dout ({ | |
1375 | mb0_l2t_cambist, | |
1376 | mb0_l2t_icrow_lookup_en[3:0], | |
1377 | mb0_l2t_icrow_row_en[1:0], | |
1378 | mb0_l2t_icrow_panel_en[3:0], | |
1379 | mb0_l2t_dcrow_lookup_en[3:0], | |
1380 | mb0_l2t_dcrow_row_en[1:0], | |
1381 | mb0_l2t_dcrow_panel_en[3:0] | |
1382 | }), | |
1383 | .siclk(siclk), | |
1384 | .soclk(soclk)); | |
1385 | ||
1386 | assign mb_lookup_wdata[15:0] = cambist ? lookup_wdata[15:0] : | |
1387 | {mem_data[7:0],mem_data[7:0]}; | |
1388 | ||
1389 | l2t_mb0_ctl_msff_ctl_macro__width_16 mbist_output_data_reg ( | |
1390 | .scan_in(mbist_output_data_reg_scanin), | |
1391 | .scan_out(mbist_output_data_reg_scanout), | |
1392 | .l1clk( l1clk_pm1 ), | |
1393 | .din (mb_lookup_wdata[15:0]), | |
1394 | .dout (mb0_l2t_lookup_wdata[15:0]), | |
1395 | .siclk(siclk), | |
1396 | .soclk(soclk) | |
1397 | ); | |
1398 | ||
1399 | ||
1400 | ||
1401 | ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
1402 | //////////////////////////////////// //////////////////////////////////// | |
1403 | // CONTROL REG: | |
1404 | //////////////////////////////////// //////////////////////////////////// | |
1405 | ||
1406 | ||
1407 | l2t_mb0_ctl_msff_ctl_macro__width_36 cntl_reg ( | |
1408 | .scan_in(cntl_reg_scanin), | |
1409 | .scan_out(cntl_reg_scanout), | |
1410 | .l1clk( l1clk_pm1 ), | |
1411 | .din ( cntl_in[35:0] ), | |
1412 | .dout ( cntl_out[35:0] ), | |
1413 | .siclk(siclk), | |
1414 | .soclk(soclk)); | |
1415 | ||
1416 | ||
1417 | assign cntl_in[35:19] = reset_engine ? {17'b000000_0000000000}: | |
1418 | (~run3 | cambist) ? cntl_algr[16:0]: | |
1419 | next_algr[16:0]; | |
1420 | ||
1421 | ||
1422 | // assign cntl_in[12:3] = reset_engine ? start_addr[7:0]: | |
1423 | // ~run3 ? cntl_addr[7:0]: | |
1424 | // next_addr[7:0]; | |
1425 | ||
1426 | // reset_engine run3 overflow cout_rw output | |
1427 | // --------------------------------------------------------- | |
1428 | // 1 x x x start_addr | |
1429 | // 0 0 x x cntl_addr | |
1430 | // 0 1 1 x restart_addr | |
1431 | // 0 1 0 1 incred_addr | |
1432 | // 0 1 0 0 cntl_addr | |
1433 | ||
1434 | ||
1435 | assign sel_nextaddr_reset = reset_engine; | |
1436 | assign sel_nextaddr_restart = ~reset_engine & run3 & overflow; | |
1437 | assign sel_nextaddr_incred = ~reset_engine & run3 & ~overflow & cout_rw; | |
1438 | assign sel_nextaddr_same = ~(sel_nextaddr_reset | sel_nextaddr_restart | sel_nextaddr_incred) | cambist; | |
1439 | ||
1440 | assign cntl_in[10:3] = ({8{sel_nextaddr_reset}} & start_addr[7:0]) | | |
1441 | ({8{sel_nextaddr_restart}} & restart_addr[7:0]) | | |
1442 | ({8{sel_nextaddr_incred}} & incred_addr[7:0]) | | |
1443 | ({8{sel_nextaddr_same}} & cntl_addr[7:0]); | |
1444 | ||
1445 | ||
1446 | ||
1447 | assign cntl_in[18:11] = 8'b00000000; | |
1448 | ||
1449 | ||
1450 | assign cntl_in[2:0] = reset_engine ? 3'b000 : | |
1451 | (~run3 | cambist) ? cntl_rw[2:0]: | |
1452 | next_rw[2:0]; | |
1453 | ||
1454 | ||
1455 | ||
1456 | //////////////////////////////////// //////////////////////////////////// | |
1457 | // NEXT ALGR | |
1458 | //////////////////////////////////// //////////////////////////////////// | |
1459 | ||
1460 | // msb | |
1461 | assign cntl_msb = start_in & cntl_out[ 35]; // done selection | |
1462 | ||
1463 | ||
1464 | assign cntl_bisi = mb_default_bisi | mb_user_bisi_rw_mode ? cntl_out[34] : | |
1465 | 1'b1; | |
1466 | ||
1467 | ||
1468 | // array | |
1469 | assign cntl_array_sel[3:0] = (user_mode | last_array) ? 4'b1111: | |
1470 | cntl_out[33:30]; // array selection | |
1471 | // cmpel | |
1472 | assign cntl_cmp_sel[3:0] = sel_cmp_pass ? {4'b1111} : | |
1473 | cntl_out[29:26]; | |
1474 | ||
1475 | // data | |
1476 | assign cntl_data_sel[1:0] = (bisi_mode | mb_user_data_mode) ? 2'b11 : cntl_out[25:24]; // data selection | |
1477 | ||
1478 | // address mix | |
1479 | assign cntl_addr_mix = (mb_user_addr_mode | bisi_mode) ? 1'b1 : cntl_out[ 23]; // address mix | |
1480 | ||
1481 | ||
1482 | ||
1483 | assign cntl_march_element[3:0] = sel_march_1_pass ? 4'b1111: | |
1484 | cntl_out[22:19]; // march element | |
1485 | ||
1486 | assign addr_mix = (bisi_mode | mb_user_addr_mode) ? 1'b0 : | |
1487 | cntl_addr_mix; | |
1488 | ||
1489 | ||
1490 | assign cntl_algr[16:0] = {cntl_msb, | |
1491 | cntl_bisi, | |
1492 | cntl_array_sel[3:0], | |
1493 | cntl_cmp_sel[3:0], | |
1494 | cntl_data_sel[1:0], | |
1495 | cntl_addr_mix, | |
1496 | cntl_march_element[3:0]}; | |
1497 | ||
1498 | assign next_algr[16:0] = cout_addr ? cntl_algr[16:0] + 17'h1 : cntl_algr[16:0]; // mbist control | |
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | //////////////////////////////////// //////////////////////////////////// | |
1504 | // NEXT ADDR | |
1505 | //////////////////////////////////// //////////////////////////////////// | |
1506 | ||
1507 | ||
1508 | ///////////////////////// | |
1509 | // address engine | |
1510 | ///////////////////////// | |
1511 | ||
1512 | ||
1513 | assign upaddr = march_0 | march_1 | march_2 | march_6 | march_7 | bisi_mode ; | |
1514 | ||
1515 | ||
1516 | assign march_element_pre[3:0]=next_algr[3:0]; | |
1517 | ||
1518 | assign march_pre_0 = march_element_pre[3:0]==4'h0; | |
1519 | assign march_pre_1 = march_element_pre[3:0]==4'h1; | |
1520 | assign march_pre_2 = march_element_pre[3:0]==4'h2; | |
1521 | assign march_pre_6 = march_element_pre[3:0]==4'h6; | |
1522 | assign march_pre_7 = march_element_pre[3:0]==4'h7; | |
1523 | ||
1524 | assign upaddr_pre = march_pre_0 | march_pre_1 | march_pre_2 | march_pre_6 | march_pre_7; | |
1525 | ||
1526 | ||
1527 | assign incr_addr[7:0] = mb_user_addr_mode ? user_incr_addr[7:0] : 8'b00000001; | |
1528 | ||
1529 | assign start_addr[7:0] = mb_user_addr_mode ? user_start_addr[7:0] : 8'b00000000; | |
1530 | ||
1531 | ||
1532 | // assign next_addr_out[8:0] = cout_rw ? cntl_addr[8:0] + incr_addr[8:0] : cntl_addr[8:0]; // next address | |
1533 | ||
1534 | ||
1535 | assign incred_addr[7:0] = cntl_addr[7:0] + incr_addr[7:0]; | |
1536 | ||
1537 | ||
1538 | assign overflow = upaddr ? ( cntl_addr[7:0] == stop_addr[7:0]) & (cntl_rw[2:0]==3'b111): | |
1539 | (~cntl_addr[7:0] == start_addr[7:0]) & (cntl_rw[2:0]==3'b111); | |
1540 | ||
1541 | ||
1542 | // assign next_addr[7:0]= overflow ? restart_addr[7:0] : next_addr_out[7:0]; | |
1543 | ||
1544 | assign restart_addr[7:0] = upaddr_pre ? start_addr[7:0] : ~stop_addr[7:0]; | |
1545 | ||
1546 | assign cout_addr = overflow; | |
1547 | ||
1548 | ||
1549 | ||
1550 | ||
1551 | //////////////////////////////////// //////////////////////////////////// | |
1552 | // NEXT RW | |
1553 | //////////////////////////////////// //////////////////////////////////// | |
1554 | ||
1555 | ||
1556 | assign cntl_rw[2:0] = sel_rw_pass ? 3'b111: | |
1557 | cntl_out[ 2: 0]; // read write control | |
1558 | ||
1559 | assign next_rw[2:0] = cntl_rw[2:0]+3'b001 ; | |
1560 | ||
1561 | assign cout_rw = &cntl_rw[2:0]; // carry over for rw | |
1562 | ||
1563 | ||
1564 | ||
1565 | ||
1566 | ||
1567 | //////////////////////////////////// //////////////////////////////////// | |
1568 | // MBIST CONTROL SIGNAL | |
1569 | // - mem_wr | |
1570 | //////////////////////////////////// //////////////////////////////////// | |
1571 | ||
1572 | ||
1573 | assign one_cycle_march = march_0 | march_5 | march_7; | |
1574 | assign five_cycle_march = march_6 | march_8; | |
1575 | assign two_cycle_march = ~(one_cycle_march | five_cycle_march); | |
1576 | ||
1577 | ||
1578 | ///////////////////////// | |
1579 | // membist write enable | |
1580 | ///////////////////////// | |
1581 | ||
1582 | ||
1583 | assign mem_wr_pbi = run3 & ( | |
1584 | march_0 | | |
1585 | ((march_1 | march_2 | march_3 | march_4 ) & rw_1) | | |
1586 | (march_6 & (rw_0 | rw_1 | rw_4)) | | |
1587 | march_7 | | |
1588 | (march_8 & (rw_0 | rw_1 | rw_4)) | |
1589 | ); | |
1590 | ||
1591 | ||
1592 | assign mem_wr = bisi_wr_mode ? 1'b1 : | |
1593 | bisi_rd_mode ? 1'b0 : | |
1594 | mem_wr_pbi; | |
1595 | ||
1596 | ///////////////////////// | |
1597 | // membist read enable | |
1598 | ///////////////////////// | |
1599 | ||
1600 | ||
1601 | ||
1602 | assign mem_rd_pbi = run3 & ~mem_wr; | |
1603 | ||
1604 | assign mem_rd= bisi_rd_mode ? 1'b1 : mem_rd_pbi; | |
1605 | ||
1606 | ///////////////////// | |
1607 | // membist address: | |
1608 | //////////////////// | |
1609 | ||
1610 | assign cntl_addr[7:0] = cntl_out[10:3]; | |
1611 | ||
1612 | assign adj_addr = (five_cycle_march & (rw_1 | rw_3)) ? {cntl_addr[7:4],~cntl_addr[3],cntl_addr[2:0]}: | |
1613 | cntl_addr[7:0] ; | |
1614 | ||
1615 | assign mem_addr1[7:0] = upaddr ? adj_addr[7:0]: ~adj_addr[7:0]; | |
1616 | ||
1617 | ||
1618 | ||
1619 | ///////////////////// | |
1620 | // true data | |
1621 | //////////////////// | |
1622 | ||
1623 | assign true_data_l = bisi_mode | | |
1624 | march_0 | | |
1625 | (march_1 & rw_0) | | |
1626 | (march_2 & rw_1) | | |
1627 | (march_3 & rw_0) | | |
1628 | (march_4 & rw_1) | | |
1629 | (march_5) | | |
1630 | (march_6 & (rw_1 | rw_3 | rw_4)) | | |
1631 | (march_8 & (rw_0 | rw_2)); | |
1632 | ||
1633 | assign true_data=~true_data_l; | |
1634 | ||
1635 | ///////////////////// | |
1636 | // membist data: | |
1637 | //////////////////// | |
1638 | ||
1639 | assign data_pat_sel[7:0] = (mb_user_data_mode & bisi_mode) ? ~user_data[7:0]: | |
1640 | (mb_user_data_mode) ? user_data[7:0]: | |
1641 | bisi_mode ? 8'hFF: | |
1642 | (cntl_data_sel[1:0] == 2'h0) ? 8'hAA: | |
1643 | (cntl_data_sel[1:0] == 2'h1) ? 8'h99: | |
1644 | (cntl_data_sel[1:0] == 2'h2) ? 8'hCC: | |
1645 | 8'h00; | |
1646 | assign mem_data[7:0] = true_data ? data_pat_sel[7:0] : ~data_pat_sel[7:0]; | |
1647 | ||
1648 | ||
1649 | //////////////////////////////////// //////////////////////////////////// | |
1650 | // STOP ADDR | |
1651 | //////////////////////////////////// //////////////////////////////////// | |
1652 | ||
1653 | assign stop_addr[7:0] = mb_user_addr_mode ? user_stop_addr[7:0] : | |
1654 | array_0 ? 8'b00111111: // icrow0 | |
1655 | array_1 ? 8'b00111111: // icrow1 | |
1656 | array_2 ? 8'b00111111: // dcrow0 | |
1657 | array_3 ? 8'b00111111: // dcrow1 | |
1658 | array_4 ? 8'b00001111: // oqarray | |
1659 | 8'b00111111; | |
1660 | ||
1661 | ||
1662 | //////////////////////////////////// //////////////////////////////////// | |
1663 | // ADDR MIX | |
1664 | //////////////////////////////////// //////////////////////////////////// | |
1665 | ||
1666 | ||
1667 | assign mem_addr[7:0] = (addr_mix & (array_0 | array_1 | array_2 | array_3)) | |
1668 | ? {mem_addr1[7:6],mem_addr1[0],mem_addr1[5:1]} : // done | |
1669 | (addr_mix & array_4) ? {mem_addr1[7:4],mem_addr1[0],mem_addr1[3:1]} : // done | |
1670 | mem_addr1[7:0]; | |
1671 | ||
1672 | ||
1673 | ||
1674 | ||
1675 | //////////////////////////////////// //////////////////////////////////// | |
1676 | // SEQ selection | |
1677 | //////////////////////////////////// //////////////////////////////////// | |
1678 | ||
1679 | // array | |
1680 | ||
1681 | assign array_0 = array_sel[3:0]==4'h0 & ~cambist; | |
1682 | assign array_1 = array_sel[3:0]==4'h1 & ~cambist; | |
1683 | assign array_2 = array_sel[3:0]==4'h2 & ~cambist; | |
1684 | assign array_3 = array_sel[3:0]==4'h3 & ~cambist; | |
1685 | assign array_4 = array_sel[3:0]==4'h4 & ~cambist; | |
1686 | ||
1687 | assign last_array = array_4; | |
1688 | // cmp | |
1689 | assign cmp_0 = cmp_sel[3:0]==4'b0000; | |
1690 | assign cmp_1 = cmp_sel[3:0]==4'b0001; | |
1691 | assign cmp_2 = cmp_sel[3:0]==4'b0010; | |
1692 | assign cmp_3 = cmp_sel[3:0]==4'b0011; | |
1693 | // assign cmp_4 = cmp_sel[3:0]==4'b0100; | |
1694 | // assign cmp_5 = cmp_sel[3:0]==4'b0101; | |
1695 | // assign cmp_6 = cmp_sel[3:0]==4'b0110; | |
1696 | // assign cmp_7 = cmp_sel[3:0]==4'b0111; | |
1697 | // assign cmp_15 = cmp_sel[3:0]==4'b1111; | |
1698 | ||
1699 | // march | |
1700 | ||
1701 | assign march_0 = (march_element[3:0]==4'h0); | |
1702 | assign march_1 = (march_element[3:0]==4'h1); | |
1703 | assign march_2 = (march_element[3:0]==4'h2); | |
1704 | assign march_3 = (march_element[3:0]==4'h3); | |
1705 | assign march_4 = (march_element[3:0]==4'h4); | |
1706 | assign march_5 = (march_element[3:0]==4'h5); | |
1707 | assign march_6 = (march_element[3:0]==4'h6); | |
1708 | assign march_7 = (march_element[3:0]==4'h7); | |
1709 | assign march_8 = (march_element[3:0]==4'h8); | |
1710 | ||
1711 | // rw | |
1712 | ||
1713 | assign rw_0 = (rw[2:0]==3'b000); | |
1714 | assign rw_1 = (rw[2:0]==3'b001); | |
1715 | assign rw_2 = (rw[2:0]==3'b010); | |
1716 | assign rw_3 = (rw[2:0]==3'b011); | |
1717 | assign rw_4 = (rw[2:0]==3'b100); | |
1718 | // assign rw_5 = (rw[2:0]==3'b101); | |
1719 | // assign rw_6 = (rw[2:0]==3'b110); | |
1720 | // assign rw_7 = (rw[2:0]==3'b111); | |
1721 | ||
1722 | ||
1723 | ||
1724 | ||
1725 | ||
1726 | //////////////////////////////////// //////////////////////////////////// | |
1727 | // SEQ logic | |
1728 | //////////////////////////////////// //////////////////////////////////// | |
1729 | ||
1730 | // cseq | |
1731 | ||
1732 | ||
1733 | assign cseq_cntl_out[1:0]=cam_out[11:10]; | |
1734 | ||
1735 | ||
1736 | l2t_mb0_ctl_msff_ctl_macro__width_2 cseq_reg ( | |
1737 | .scan_in(cseq_reg_scanin), | |
1738 | .scan_out(cseq_reg_scanout), | |
1739 | .l1clk ( l1clk_pm1 ), | |
1740 | .din ( cseq[1:0] ), | |
1741 | .dout ( cseq_out[1:0] ), | |
1742 | .siclk(siclk), | |
1743 | .soclk(soclk)); | |
1744 | ||
1745 | assign cseq[1:0]=(&cseq_cntl_out[1:0] & ~(ctest0 | ctest1)) ? cseq_out[1:0] : | |
1746 | cseq_cntl_out[1:0]; | |
1747 | ||
1748 | ||
1749 | // cam select logic | |
1750 | ||
1751 | assign cam_sel_cntl_out[1:0]=cam_out[17:16]; | |
1752 | ||
1753 | ||
1754 | assign cam_sel[1:0]= user_mode ? user_cam_sel[1:0] : | |
1755 | cam_sel_cntl_out[1:0]; | |
1756 | ||
1757 | ||
1758 | // ctest select logic | |
1759 | ||
1760 | assign ctest_sel_cntl_out[1:0]=cam_out[13:12]; | |
1761 | ||
1762 | ||
1763 | l2t_mb0_ctl_msff_ctl_macro__width_2 ctest_sel_reg ( | |
1764 | .scan_in(ctest_sel_reg_scanin), | |
1765 | .scan_out(ctest_sel_reg_scanout), | |
1766 | .l1clk ( l1clk_pm1 ), | |
1767 | .din ( ctest_sel[1:0] ), | |
1768 | .dout ( ctest_sel_out[1:0] ), | |
1769 | .siclk(siclk), | |
1770 | .soclk(soclk)); | |
1771 | ||
1772 | assign ctest_sel[1:0]=(&ctest_sel_cntl_out[1:0] & ~(ctest[1:0]==2'b11)) ? ctest_sel_out[1:0] : | |
1773 | mb_user_cam_mode ? user_cam_test_sel[1:0] : | |
1774 | ctest_sel_cntl_out[1:0]; | |
1775 | ||
1776 | ||
1777 | // array logic | |
1778 | ||
1779 | assign array_sel_cntl_out[3:0]=cntl_out[33:30]; | |
1780 | ||
1781 | ||
1782 | l2t_mb0_ctl_msff_ctl_macro__width_4 array_sel_reg ( | |
1783 | .scan_in(array_sel_reg_scanin), | |
1784 | .scan_out(array_sel_reg_scanout), | |
1785 | .l1clk ( l1clk_pm1 ), | |
1786 | .din ( array_sel[3:0] ), | |
1787 | .dout ( array_sel_out[3:0] ), | |
1788 | .siclk(siclk), | |
1789 | .soclk(soclk)); | |
1790 | ||
1791 | assign array_sel[3:0]=(&array_sel_cntl_out[3:0]) ? array_sel_out[3:0] : | |
1792 | user_mode ? user_array_sel[3:0] : | |
1793 | array_sel_cntl_out[3:0]; | |
1794 | ||
1795 | ||
1796 | ||
1797 | // cmp logic | |
1798 | ||
1799 | assign cmp_sel_cntl_out[3:0] = cntl_out[29:26]; | |
1800 | ||
1801 | l2t_mb0_ctl_msff_ctl_macro__width_4 cmp_sel_reg ( | |
1802 | .scan_in(cmp_sel_reg_scanin), | |
1803 | .scan_out(cmp_sel_reg_scanout), | |
1804 | .l1clk ( l1clk_pm1 ), | |
1805 | .din ( cmp_sel[3:0] ), | |
1806 | .dout ( cmp_sel_out[3:0] ), | |
1807 | .siclk(siclk), | |
1808 | .soclk(soclk)); | |
1809 | ||
1810 | assign cmp_sel[3:0]= (&cmp_sel_cntl_out[3:0] & ~array_4) ? cmp_sel_out[3:0] : | |
1811 | mb_user_cmpsel_hold ? user_cmpsel[3:0] : | |
1812 | cmp_sel_cntl_out[3:0]; | |
1813 | ||
1814 | ||
1815 | // march logic | |
1816 | ||
1817 | assign march_element_cntl_out[3:0]=cntl_out[22:19]; | |
1818 | ||
1819 | ||
1820 | l2t_mb0_ctl_msff_ctl_macro__width_4 marche_element_reg ( | |
1821 | .scan_in(marche_element_reg_scanin), | |
1822 | .scan_out(marche_element_reg_scanout), | |
1823 | .l1clk ( l1clk_pm1 ), | |
1824 | .din ( march_element[3:0] ), | |
1825 | .dout ( march_element_out ), | |
1826 | .siclk(siclk), | |
1827 | .soclk(soclk)); | |
1828 | ||
1829 | assign march_element[3:0]=(&march_element_cntl_out[3:0]) ? march_element_out[3:0] : | |
1830 | march_element_cntl_out[3:0]; | |
1831 | ||
1832 | ||
1833 | // rw | |
1834 | assign rw[2:0]=cntl_out[2:0]; | |
1835 | ||
1836 | ||
1837 | ||
1838 | ||
1839 | ||
1840 | ////////////////////////////////////////////////////////////////// | |
1841 | // SEL_PASS LOGIC | |
1842 | ////////////////////////////////////////////////////////////////// | |
1843 | ||
1844 | ||
1845 | // pass logic: | |
1846 | ||
1847 | ||
1848 | ||
1849 | ||
1850 | ||
1851 | // march | |
1852 | assign sel_march_1_pass = bisi_mode | (ten_n_mode & march_5) | march_8 ; | |
1853 | ||
1854 | // cmp | |
1855 | ||
1856 | assign bisi_wr_mode = mb_default_bisi | mb_user_bisi_rw_mode ? ~cntl_bisi & run3 : | |
1857 | mb_user_bisi_wr_mode & run3; | |
1858 | ||
1859 | assign bisi_rd_mode =mb_default_bisi | mb_user_bisi_rw_mode ? cntl_bisi & run3 : | |
1860 | mb_user_bisi_rd_mode & run3; | |
1861 | ||
1862 | ||
1863 | ||
1864 | // cmp | |
1865 | ||
1866 | ||
1867 | assign sel_cmp_pass= (mb_user_cmpsel_hold ) | | |
1868 | (array_0 & cmp_3) | | |
1869 | (array_1 & cmp_3) | | |
1870 | (array_2 & cmp_3) | | |
1871 | (array_3 & cmp_3) | | |
1872 | (array_4 & cmp_3) ; | |
1873 | ||
1874 | ||
1875 | ||
1876 | // rw | |
1877 | assign sel_rw_1_pass = bisi_mode | one_cycle_march ; | |
1878 | ||
1879 | assign sel_rw_2_pass = two_cycle_march; | |
1880 | assign sel_rw_5_pass = five_cycle_march; | |
1881 | ||
1882 | assign sel_rw_pass = (run3 & sel_rw_1_pass & rw_0) | | |
1883 | (run3 & sel_rw_2_pass & rw_1) | | |
1884 | (run3 & sel_rw_5_pass & rw_4) ; | |
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | ||
1893 | ||
1894 | ||
1895 | ||
1896 | //////////////////////////////////// //////////////////////////////////// | |
1897 | // membist control assignment | |
1898 | //////////////////////////////////// //////////////////////////////////// | |
1899 | ||
1900 | ||
1901 | ||
1902 | assign mb_cmp_sel[0] = cmp_sel[1:0]==2'b00 & array_4; | |
1903 | assign mb_cmp_sel[1] = cmp_sel[1:0]==2'b01 & array_4; | |
1904 | assign mb_cmp_sel[2] = cmp_sel[1:0]==2'b10 & array_4; | |
1905 | assign mb_cmp_sel[3] = cmp_sel[1:0]==2'b11 & array_4; | |
1906 | ||
1907 | ||
1908 | assign mb_addr[7:0]= cambist ? cam_addr[7:0] : mem_addr[7:0]; | |
1909 | ||
1910 | ||
1911 | assign mb_write_data[7:0] = mem_data[7:0]; | |
1912 | ||
1913 | ||
1914 | ||
1915 | // only one array read signal should be active | |
1916 | ||
1917 | assign mb_array_0_rd = array_0 & mem_rd; | |
1918 | assign mb_array_1_rd = array_1 & mem_rd; | |
1919 | assign mb_array_2_rd = array_2 & mem_rd; | |
1920 | assign mb_array_3_rd = array_3 & mem_rd; | |
1921 | assign mb_array_4_rd = array_4 & mem_rd; | |
1922 | ||
1923 | ||
1924 | assign mb_array_0_wr = (array_0 & mem_wr & run) | (cam_0 & cam_wr_en & run); | |
1925 | assign mb_array_1_wr = (array_1 & mem_wr & run) | (cam_1 & cam_wr_en & run); | |
1926 | assign mb_array_2_wr = (array_2 & mem_wr & run) | (cam_2 & cam_wr_en & run); | |
1927 | assign mb_array_3_wr = (array_3 & mem_wr & run) | (cam_3 & cam_wr_en & run); | |
1928 | assign mb_array_4_wr = array_4 & mem_wr & run; | |
1929 | ||
1930 | ||
1931 | assign mb_run = run | ((cntl_msb | cam_msb) & ~&done_delay[2:1]); | |
1932 | ||
1933 | ||
1934 | ||
1935 | ||
1936 | //////////////////////////////////// //////////////////////////////////// | |
1937 | // DONE LOGIC | |
1938 | //////////////////////////////////// //////////////////////////////////// | |
1939 | ||
1940 | ||
1941 | ||
1942 | ||
1943 | ||
1944 | l2t_mb0_ctl_msff_ctl_macro__width_1 msb_latch ( | |
1945 | .scan_in(msb_latch_scanin), | |
1946 | .scan_out(msb_latch_scanout), | |
1947 | .l1clk ( l1clk_pm1 ), | |
1948 | .din ( msb_in ), | |
1949 | .dout ( msb_out ), | |
1950 | .siclk(siclk), | |
1951 | .soclk(soclk)); | |
1952 | ||
1953 | assign msb_in= (~start_in ) | (mb_user_loop_mode & mb_done) ? 1'b0 : | |
1954 | (cntl_msb | cam_msb) ? 1'b1 : | |
1955 | msb_out; | |
1956 | ||
1957 | assign stop_engine_l = ~start_in ? 1'b0 : | |
1958 | mb_user_cam_mode ? cam_msb : | |
1959 | mb_user_loop_mode ? cntl_msb : | |
1960 | (mb_user_ram_mode | bisi_mode) ? cntl_msb : | |
1961 | cam_msb; | |
1962 | ||
1963 | assign mb_done= ~start_in ? 1'b0 : | |
1964 | bisi_mode | mb_user_loop_mode | mb_user_ram_mode ? msb_out & (done_delay[4:0]==5'b11110): | |
1965 | cam_msb & (done_delay[4:0]==5'b11110) ; | |
1966 | ||
1967 | assign run3 = &done_delay[4:1] & ~stop_engine_l & start_in; | |
1968 | ||
1969 | ||
1970 | l2t_mb0_ctl_msff_ctl_macro__width_1 run3_transition_reg ( | |
1971 | .scan_in(run3_transition_reg_scanin), | |
1972 | .scan_out(run3_transition_reg_scanout), | |
1973 | .l1clk ( l1clk_pm1 ), | |
1974 | .din ( run3 ), | |
1975 | .dout ( run3_out ), | |
1976 | .siclk(siclk), | |
1977 | .soclk(soclk)); | |
1978 | ||
1979 | assign run3_transition = run3 & ~run3_out; | |
1980 | ||
1981 | l2t_mb0_ctl_msff_ctl_macro__width_5 done_delay_reg ( | |
1982 | .scan_in(done_delay_reg_scanin), | |
1983 | .scan_out(done_delay_reg_scanout), | |
1984 | .l1clk ( l1clk_pm1 ), | |
1985 | .din ( done_delay_in[4:0] ), | |
1986 | .dout ( done_delay[4:0] ), | |
1987 | .siclk(siclk), | |
1988 | .soclk(soclk)); | |
1989 | ||
1990 | ||
1991 | assign done_delay_in[4:0] = run3 ? 5'b11111 : | |
1992 | mb_done ? 5'b11110 : | |
1993 | (run & ~run3) ? done_delay[4:0] + 5'b00001 : | |
1994 | 5'b00000; | |
1995 | ||
1996 | ||
1997 | ||
1998 | ||
1999 | ||
2000 | //////////////////////////////////// //////////////////////////////////// | |
2001 | // FAIL LOGIC | |
2002 | //////////////////////////////////// //////////////////////////////////// | |
2003 | ||
2004 | ||
2005 | ||
2006 | assign mb_ic0_rw_fail = (array_0 & mb_ic_rw_fail); | |
2007 | assign mb_ic1_rw_fail = (array_1 & mb_ic_rw_fail); | |
2008 | assign mb_dc0_rw_fail = (array_2 & mb_dc_rw_fail); | |
2009 | assign mb_dc1_rw_fail = (array_3 & mb_dc_rw_fail); | |
2010 | ||
2011 | assign mb_oqarray_rw_fail = ~oqarray_rw_fail; | |
2012 | ||
2013 | assign ic0_fail_d = run3_transition ? 1'b0 : mb_ic0_rw_fail | ic0_fail_sticky; | |
2014 | assign ic1_fail_d = run3_transition ? 1'b0 : mb_ic1_rw_fail | ic1_fail_sticky; | |
2015 | assign dc0_fail_d = run3_transition ? 1'b0 : mb_dc0_rw_fail | dc0_fail_sticky; | |
2016 | assign dc1_fail_d = run3_transition ? 1'b0 : mb_dc1_rw_fail | dc1_fail_sticky; | |
2017 | assign oqarray_fail_d = run3_transition ? 1'b0 : mb_oqarray_rw_fail | oqarray_fail_sticky; | |
2018 | assign icrow0_cam_fail_d = run3_transition ? 1'b0 : icrow0_cam_fail | icrow0_cam_fail_sticky; | |
2019 | assign icrow1_cam_fail_d = run3_transition ? 1'b0 : icrow1_cam_fail | icrow1_cam_fail_sticky; | |
2020 | assign dcrow0_cam_fail_d = run3_transition ? 1'b0 : dcrow0_cam_fail | dcrow0_cam_fail_sticky; | |
2021 | assign dcrow1_cam_fail_d = run3_transition ? 1'b0 : dcrow1_cam_fail | dcrow1_cam_fail_sticky; | |
2022 | ||
2023 | ||
2024 | l2t_mb0_ctl_msff_ctl_macro__width_9 mbist_fail_input_reg ( | |
2025 | .scan_in(mbist_fail_input_reg_scanin), | |
2026 | .scan_out(mbist_fail_input_reg_scanout), | |
2027 | .l1clk ( l1clk_pm1 ), | |
2028 | .din ({ic0_fail_d, | |
2029 | ic1_fail_d, | |
2030 | dc0_fail_d, | |
2031 | dc1_fail_d, | |
2032 | oqarray_fail_d, | |
2033 | icrow0_cam_fail_d, | |
2034 | icrow1_cam_fail_d, | |
2035 | dcrow0_cam_fail_d, | |
2036 | dcrow1_cam_fail_d | |
2037 | }), | |
2038 | .dout ({ic0_fail_sticky, | |
2039 | ic1_fail_sticky, | |
2040 | dc0_fail_sticky, | |
2041 | dc1_fail_sticky, | |
2042 | oqarray_fail_sticky, | |
2043 | icrow0_cam_fail_sticky, | |
2044 | icrow1_cam_fail_sticky, | |
2045 | dcrow0_cam_fail_sticky, | |
2046 | dcrow1_cam_fail_sticky | |
2047 | }), | |
2048 | .siclk(siclk), | |
2049 | .soclk(soclk)); | |
2050 | ||
2051 | ||
2052 | ||
2053 | assign mbist_fail_sticky = ic0_fail_sticky | | |
2054 | ic1_fail_sticky | | |
2055 | dc0_fail_sticky | | |
2056 | dc1_fail_sticky | | |
2057 | oqarray_fail_sticky | | |
2058 | icrow0_cam_fail_sticky | | |
2059 | icrow1_cam_fail_sticky | | |
2060 | dcrow0_cam_fail_sticky | | |
2061 | dcrow1_cam_fail_sticky; | |
2062 | ||
2063 | ||
2064 | assign mbist_fail_array = mb_ic0_rw_fail | | |
2065 | mb_ic1_rw_fail | | |
2066 | mb_dc0_rw_fail | | |
2067 | mb_dc1_rw_fail | | |
2068 | mb_oqarray_rw_fail | | |
2069 | icrow0_cam_fail | | |
2070 | icrow1_cam_fail | | |
2071 | dcrow0_cam_fail | | |
2072 | dcrow1_cam_fail ; | |
2073 | ||
2074 | ||
2075 | ||
2076 | ||
2077 | assign valid_fail=run3 | (stop_engine_l & ~mb_done); | |
2078 | ||
2079 | ||
2080 | assign mb_fail = mb_done ? mbist_fail_sticky : mbist_fail_array & valid_fail; | |
2081 | ||
2082 | ||
2083 | ||
2084 | ||
2085 | ////////////////////////////////////////////////////////////////// | |
2086 | // OUTPUT FLOP: | |
2087 | ////////////////////////////////////////////////////////////////// | |
2088 | ||
2089 | // mb_done | |
2090 | ||
2091 | ||
2092 | l2t_mb0_ctl_msff_ctl_macro__width_1 out_mb_tcu_done_reg ( | |
2093 | .scan_in(out_mb_tcu_done_reg_scanin), | |
2094 | .scan_out(out_mb_tcu_done_reg_scanout), | |
2095 | .l1clk ( l1clk_pm1 ), | |
2096 | .din ( mb_done ), | |
2097 | .dout ( mb_done_out ), | |
2098 | .siclk(siclk), | |
2099 | .soclk(soclk)); | |
2100 | ||
2101 | ||
2102 | l2t_mb0_ctl_msff_ctl_macro__width_8 inv_mask_reg ( | |
2103 | .scan_in(inv_mask_reg_scanin), | |
2104 | .scan_out(inv_mask_reg_scanout), | |
2105 | .l1clk ( l1clk_pm1 ), | |
2106 | .din ( l2_mask[7:0] ), | |
2107 | .dout ( mb0_l2t_mask[7:0] ), | |
2108 | .siclk(siclk), | |
2109 | .soclk(soclk)); | |
2110 | ||
2111 | ||
2112 | // mb_fail | |
2113 | ||
2114 | ||
2115 | l2t_mb0_ctl_msff_ctl_macro__width_1 out_mb_tcu_fail_reg ( | |
2116 | .scan_in(out_mb_tcu_fail_reg_scanin), | |
2117 | .scan_out(out_mb_tcu_fail_reg_scanout), | |
2118 | .l1clk ( l1clk_pm1 ), | |
2119 | .din ( mb_fail ), | |
2120 | .dout ( mb_fail_out ), | |
2121 | .siclk(siclk), | |
2122 | .soclk(soclk)); | |
2123 | ||
2124 | ||
2125 | ||
2126 | ||
2127 | // out cmpsel | |
2128 | ||
2129 | l2t_mb0_ctl_msff_ctl_macro__width_4 out_cmp_sel_reg ( | |
2130 | .scan_in(out_cmp_sel_reg_scanin), | |
2131 | .scan_out(out_cmp_sel_reg_scanout), | |
2132 | .l1clk ( l1clk_pm1 ), | |
2133 | .din ({ | |
2134 | mb_cmp_sel[3:0] } ), | |
2135 | .dout ({ | |
2136 | mb_cmpsel_out[3:0]} ), | |
2137 | .siclk(siclk), | |
2138 | .soclk(soclk)); | |
2139 | ||
2140 | ||
2141 | ||
2142 | // thes are all the output flops to arrays | |
2143 | // for the following signals: | |
2144 | // | |
2145 | // - run | |
2146 | // - data | |
2147 | // - address | |
2148 | ||
2149 | ||
2150 | l2t_mb0_ctl_msff_ctl_macro__width_1 out_run_mb_arrays_reg ( | |
2151 | .scan_in(out_run_mb_arrays_reg_scanin), | |
2152 | .scan_out(out_run_mb_arrays_reg_scanout), | |
2153 | .l1clk ( l1clk_pm1 ), | |
2154 | .din ( mb_run), | |
2155 | .dout ( mb_run_out), | |
2156 | .siclk(siclk), | |
2157 | .soclk(soclk)); | |
2158 | ||
2159 | // data 8 bits | |
2160 | ||
2161 | l2t_mb0_ctl_msff_ctl_macro__width_8 out_data_mb_arrays_reg ( | |
2162 | .scan_in(out_data_mb_arrays_reg_scanin), | |
2163 | .scan_out(out_data_mb_arrays_reg_scanout), | |
2164 | .l1clk ( l1clk_pm1 ), | |
2165 | .din ( mb_write_data[7:0]), | |
2166 | .dout ( mb_write_data_out[7:0]), | |
2167 | .siclk(siclk), | |
2168 | .soclk(soclk)); | |
2169 | ||
2170 | ||
2171 | // address 16 bits | |
2172 | ||
2173 | ||
2174 | l2t_mb0_ctl_msff_ctl_macro__width_8 out_addr_mb_arrays_reg ( | |
2175 | .scan_in(out_addr_mb_arrays_reg_scanin), | |
2176 | .scan_out(out_addr_mb_arrays_reg_scanout), | |
2177 | .l1clk ( l1clk_pm1 ), | |
2178 | .din ( mb_addr[7:0]), | |
2179 | .dout ( mb_addr_out[7:0]), | |
2180 | .siclk(siclk), | |
2181 | .soclk(soclk)); | |
2182 | ||
2183 | ||
2184 | ||
2185 | ||
2186 | // write enable | |
2187 | ||
2188 | l2t_mb0_ctl_msff_ctl_macro__width_5 out_wr_mb_arrays_reg ( | |
2189 | .scan_in(out_wr_mb_arrays_reg_scanin), | |
2190 | .scan_out(out_wr_mb_arrays_reg_scanout), | |
2191 | .l1clk ( l1clk_pm1 ), | |
2192 | .din ( { | |
2193 | mb_array_0_wr, | |
2194 | mb_array_1_wr, | |
2195 | mb_array_2_wr, | |
2196 | mb_array_3_wr, | |
2197 | mb_array_4_wr | |
2198 | } ), | |
2199 | .dout ({ | |
2200 | mb_array_0_wr_out, | |
2201 | mb_array_1_wr_out, | |
2202 | mb_array_2_wr_out, | |
2203 | mb_array_3_wr_out, | |
2204 | mb_array_4_wr_out | |
2205 | } ), | |
2206 | .siclk(siclk), | |
2207 | .soclk(soclk)); | |
2208 | ||
2209 | ||
2210 | ||
2211 | ||
2212 | // read enable | |
2213 | ||
2214 | l2t_mb0_ctl_msff_ctl_macro__width_5 out_rd_mb_arrays_reg ( | |
2215 | .scan_in(out_rd_mb_arrays_reg_scanin), | |
2216 | .scan_out(out_rd_mb_arrays_reg_scanout), | |
2217 | .l1clk ( l1clk_pm1 ), | |
2218 | .din ( { | |
2219 | mb_array_0_rd, | |
2220 | mb_array_1_rd, | |
2221 | mb_array_2_rd, | |
2222 | mb_array_3_rd, | |
2223 | mb_array_4_rd | |
2224 | } ), | |
2225 | .dout ({ | |
2226 | mb_array_0_rd_out, | |
2227 | mb_array_1_rd_out, | |
2228 | mb_array_2_rd_out, | |
2229 | mb_array_3_rd_out, | |
2230 | mb_array_4_rd_out | |
2231 | } ), | |
2232 | .siclk(siclk), | |
2233 | .soclk(soclk)); | |
2234 | ||
2235 | ||
2236 | ||
2237 | ||
2238 | // port name re-assignment | |
2239 | ||
2240 | ||
2241 | assign mb0_l2t_run =mb_run_out; | |
2242 | assign mb0_l2t_mbist_write_data[7:0] =mb_write_data_out[7:0]; | |
2243 | assign mb0_l2t_addr[5:0] =mb_addr_out[5:0]; | |
2244 | assign mb0_l2t_cmpsel[3:0] =mb_cmpsel_out[3:0]; | |
2245 | assign mb0_l2t_fail =mb_fail_out; | |
2246 | assign mb0_l2t_done =mb_done_out; | |
2247 | ||
2248 | assign mb0_l2t_icrow_wr_en =mb_array_0_wr_out | mb_array_1_wr_out; | |
2249 | assign mb0_l2t_dcrow_wr_en =mb_array_2_wr_out | mb_array_3_wr_out; | |
2250 | assign mb0_l2t_oqarray_wr_en =mb_array_4_wr_out; | |
2251 | ||
2252 | assign mb0_l2t_icrow_rd_en =mb_array_0_rd_out | mb_array_1_rd_out; | |
2253 | assign mb0_l2t_dcrow_rd_en =mb_array_2_rd_out | mb_array_3_rd_out; | |
2254 | assign mb0_l2t_oqarray_rd_en =mb_array_4_rd_out; | |
2255 | ||
2256 | ||
2257 | ||
2258 | ||
2259 | ||
2260 | // spare gates: | |
2261 | ||
2262 | l2t_mb0_ctl_spare_ctl_macro__num_2 spares ( | |
2263 | .scan_in(spares_scanin), | |
2264 | .scan_out(spares_scanout), | |
2265 | .l1clk (l1clk_pm1), | |
2266 | .siclk(siclk), | |
2267 | .soclk(soclk) | |
2268 | ); | |
2269 | ||
2270 | ||
2271 | ||
2272 | supply0 vss; // <- port for ground | |
2273 | supply1 vdd; // <- port for power | |
2274 | // ///////////////////////////////////////////////////////////////////////////// | |
2275 | ||
2276 | ||
2277 | ||
2278 | // fixscan start: | |
2279 | assign array_usr_reg_scanin = scan_in ; | |
2280 | assign user_addr_mode_reg_scanin = array_usr_reg_scanout ; | |
2281 | assign user_start_addr_reg_scanin = user_addr_mode_reg_scanout; | |
2282 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
2283 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
2284 | assign user_data_mode_reg_scanin = user_incr_addr_reg_scanout; | |
2285 | assign user_data_reg_scanin = user_data_mode_reg_scanout; | |
2286 | assign user_cmpsel_hold_reg_scanin = user_data_reg_scanout ; | |
2287 | assign user_cmpsel_reg_scanin = user_cmpsel_hold_reg_scanout; | |
2288 | assign user_loop_mode_reg_scanin = user_cmpsel_reg_scanout ; | |
2289 | assign ten_n_mode_reg_scanin = user_loop_mode_reg_scanout; | |
2290 | assign user_cam_mode_reg_scanin = ten_n_mode_reg_scanout ; | |
2291 | assign user_cam_select_reg_scanin = user_cam_mode_reg_scanout; | |
2292 | assign user_cam_test_select_reg_scanin = user_cam_select_reg_scanout; | |
2293 | assign user_bisi_wr_mode_reg_scanin = user_cam_test_select_reg_scanout; | |
2294 | assign user_bisi_rd_mode_reg_scanin = user_bisi_wr_mode_reg_scanout; | |
2295 | assign input_signals_reg_scanin = user_bisi_rd_mode_reg_scanout; | |
2296 | assign mb_enable_reg_scanin = input_signals_reg_scanout; | |
2297 | assign config_reg_scanin = mb_enable_reg_scanout ; | |
2298 | assign loop_again_reg_scanin = config_reg_scanout ; | |
2299 | assign cam_cntl_reg_scanin = loop_again_reg_scanout ; | |
2300 | assign cam_shift_reg_scanin = cam_cntl_reg_scanout ; | |
2301 | assign cam_hit_reg_scanin = cam_shift_reg_scanout ; | |
2302 | assign exp_cam_hit_delay_reg_scanin = cam_hit_reg_scanout ; | |
2303 | assign exp_cam_exp_delay_reg_scanin = exp_cam_hit_delay_reg_scanout; | |
2304 | assign cam_sel_icrow_delay_reg_scanin = exp_cam_exp_delay_reg_scanout; | |
2305 | assign cam_sel_dcrow_delay_reg_scanin = cam_sel_icrow_delay_reg_scanout; | |
2306 | assign mbist_output_reg_scanin = cam_sel_dcrow_delay_reg_scanout; | |
2307 | assign mbist_output_data_reg_scanin = mbist_output_reg_scanout ; | |
2308 | assign cntl_reg_scanin = mbist_output_data_reg_scanout; | |
2309 | assign cseq_reg_scanin = cntl_reg_scanout ; | |
2310 | assign ctest_sel_reg_scanin = cseq_reg_scanout ; | |
2311 | assign array_sel_reg_scanin = ctest_sel_reg_scanout ; | |
2312 | assign cmp_sel_reg_scanin = array_sel_reg_scanout ; | |
2313 | assign marche_element_reg_scanin = cmp_sel_reg_scanout ; | |
2314 | assign msb_latch_scanin = marche_element_reg_scanout; | |
2315 | assign run3_transition_reg_scanin = msb_latch_scanout ; | |
2316 | assign done_delay_reg_scanin = run3_transition_reg_scanout; | |
2317 | assign mbist_fail_input_reg_scanin = done_delay_reg_scanout ; | |
2318 | assign out_mb_tcu_done_reg_scanin = mbist_fail_input_reg_scanout; | |
2319 | assign inv_mask_reg_scanin = out_mb_tcu_done_reg_scanout; | |
2320 | assign out_mb_tcu_fail_reg_scanin = inv_mask_reg_scanout ; | |
2321 | assign out_cmp_sel_reg_scanin = out_mb_tcu_fail_reg_scanout; | |
2322 | assign out_run_mb_arrays_reg_scanin = out_cmp_sel_reg_scanout ; | |
2323 | assign out_data_mb_arrays_reg_scanin = out_run_mb_arrays_reg_scanout; | |
2324 | assign out_addr_mb_arrays_reg_scanin = out_data_mb_arrays_reg_scanout; | |
2325 | assign out_wr_mb_arrays_reg_scanin = out_addr_mb_arrays_reg_scanout; | |
2326 | assign out_rd_mb_arrays_reg_scanin = out_wr_mb_arrays_reg_scanout; | |
2327 | assign spares_scanin = out_rd_mb_arrays_reg_scanout; | |
2328 | assign scan_out = spares_scanout ; | |
2329 | // fixscan end: | |
2330 | endmodule | |
2331 | // ///////////////////////////////////////////////////////////////////////////// | |
2332 | ||
2333 | ||
2334 | ||
2335 | ||
2336 | ||
2337 | ||
2338 | // any PARAMS parms go into naming of macro | |
2339 | ||
2340 | module l2t_mb0_ctl_l1clkhdr_ctl_macro ( | |
2341 | l2clk, | |
2342 | l1en, | |
2343 | pce_ov, | |
2344 | stop, | |
2345 | se, | |
2346 | l1clk); | |
2347 | ||
2348 | ||
2349 | input l2clk; | |
2350 | input l1en; | |
2351 | input pce_ov; | |
2352 | input stop; | |
2353 | input se; | |
2354 | output l1clk; | |
2355 | ||
2356 | ||
2357 | ||
2358 | ||
2359 | ||
2360 | cl_sc1_l1hdr_8x c_0 ( | |
2361 | ||
2362 | ||
2363 | .l2clk(l2clk), | |
2364 | .pce(l1en), | |
2365 | .l1clk(l1clk), | |
2366 | .se(se), | |
2367 | .pce_ov(pce_ov), | |
2368 | .stop(stop) | |
2369 | ); | |
2370 | ||
2371 | ||
2372 | ||
2373 | endmodule | |
2374 | ||
2375 | ||
2376 | ||
2377 | ||
2378 | ||
2379 | ||
2380 | ||
2381 | ||
2382 | ||
2383 | ||
2384 | ||
2385 | ||
2386 | ||
2387 | // any PARAMS parms go into naming of macro | |
2388 | ||
2389 | module l2t_mb0_ctl_msff_ctl_macro__width_4 ( | |
2390 | din, | |
2391 | l1clk, | |
2392 | scan_in, | |
2393 | siclk, | |
2394 | soclk, | |
2395 | dout, | |
2396 | scan_out); | |
2397 | wire [3:0] fdin; | |
2398 | wire [2:0] so; | |
2399 | ||
2400 | input [3:0] din; | |
2401 | input l1clk; | |
2402 | input scan_in; | |
2403 | ||
2404 | ||
2405 | input siclk; | |
2406 | input soclk; | |
2407 | ||
2408 | output [3:0] dout; | |
2409 | output scan_out; | |
2410 | assign fdin[3:0] = din[3:0]; | |
2411 | ||
2412 | ||
2413 | ||
2414 | ||
2415 | ||
2416 | ||
2417 | dff #(4) d0_0 ( | |
2418 | .l1clk(l1clk), | |
2419 | .siclk(siclk), | |
2420 | .soclk(soclk), | |
2421 | .d(fdin[3:0]), | |
2422 | .si({scan_in,so[2:0]}), | |
2423 | .so({so[2:0],scan_out}), | |
2424 | .q(dout[3:0]) | |
2425 | ); | |
2426 | ||
2427 | ||
2428 | ||
2429 | ||
2430 | ||
2431 | ||
2432 | ||
2433 | ||
2434 | ||
2435 | ||
2436 | ||
2437 | ||
2438 | endmodule | |
2439 | ||
2440 | ||
2441 | ||
2442 | ||
2443 | ||
2444 | ||
2445 | ||
2446 | ||
2447 | ||
2448 | ||
2449 | ||
2450 | ||
2451 | ||
2452 | // any PARAMS parms go into naming of macro | |
2453 | ||
2454 | module l2t_mb0_ctl_msff_ctl_macro__width_1 ( | |
2455 | din, | |
2456 | l1clk, | |
2457 | scan_in, | |
2458 | siclk, | |
2459 | soclk, | |
2460 | dout, | |
2461 | scan_out); | |
2462 | wire [0:0] fdin; | |
2463 | ||
2464 | input [0:0] din; | |
2465 | input l1clk; | |
2466 | input scan_in; | |
2467 | ||
2468 | ||
2469 | input siclk; | |
2470 | input soclk; | |
2471 | ||
2472 | output [0:0] dout; | |
2473 | output scan_out; | |
2474 | assign fdin[0:0] = din[0:0]; | |
2475 | ||
2476 | ||
2477 | ||
2478 | ||
2479 | ||
2480 | ||
2481 | dff #(1) d0_0 ( | |
2482 | .l1clk(l1clk), | |
2483 | .siclk(siclk), | |
2484 | .soclk(soclk), | |
2485 | .d(fdin[0:0]), | |
2486 | .si(scan_in), | |
2487 | .so(scan_out), | |
2488 | .q(dout[0:0]) | |
2489 | ); | |
2490 | ||
2491 | ||
2492 | ||
2493 | ||
2494 | ||
2495 | ||
2496 | ||
2497 | ||
2498 | ||
2499 | ||
2500 | ||
2501 | ||
2502 | endmodule | |
2503 | ||
2504 | ||
2505 | ||
2506 | ||
2507 | ||
2508 | ||
2509 | ||
2510 | ||
2511 | ||
2512 | ||
2513 | ||
2514 | ||
2515 | ||
2516 | // any PARAMS parms go into naming of macro | |
2517 | ||
2518 | module l2t_mb0_ctl_msff_ctl_macro__width_8 ( | |
2519 | din, | |
2520 | l1clk, | |
2521 | scan_in, | |
2522 | siclk, | |
2523 | soclk, | |
2524 | dout, | |
2525 | scan_out); | |
2526 | wire [7:0] fdin; | |
2527 | wire [6:0] so; | |
2528 | ||
2529 | input [7:0] din; | |
2530 | input l1clk; | |
2531 | input scan_in; | |
2532 | ||
2533 | ||
2534 | input siclk; | |
2535 | input soclk; | |
2536 | ||
2537 | output [7:0] dout; | |
2538 | output scan_out; | |
2539 | assign fdin[7:0] = din[7:0]; | |
2540 | ||
2541 | ||
2542 | ||
2543 | ||
2544 | ||
2545 | ||
2546 | dff #(8) d0_0 ( | |
2547 | .l1clk(l1clk), | |
2548 | .siclk(siclk), | |
2549 | .soclk(soclk), | |
2550 | .d(fdin[7:0]), | |
2551 | .si({scan_in,so[6:0]}), | |
2552 | .so({so[6:0],scan_out}), | |
2553 | .q(dout[7:0]) | |
2554 | ); | |
2555 | ||
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | ||
2562 | ||
2563 | ||
2564 | ||
2565 | ||
2566 | ||
2567 | endmodule | |
2568 | ||
2569 | ||
2570 | ||
2571 | ||
2572 | ||
2573 | ||
2574 | ||
2575 | ||
2576 | ||
2577 | ||
2578 | ||
2579 | ||
2580 | ||
2581 | // any PARAMS parms go into naming of macro | |
2582 | ||
2583 | module l2t_mb0_ctl_msff_ctl_macro__width_2 ( | |
2584 | din, | |
2585 | l1clk, | |
2586 | scan_in, | |
2587 | siclk, | |
2588 | soclk, | |
2589 | dout, | |
2590 | scan_out); | |
2591 | wire [1:0] fdin; | |
2592 | wire [0:0] so; | |
2593 | ||
2594 | input [1:0] din; | |
2595 | input l1clk; | |
2596 | input scan_in; | |
2597 | ||
2598 | ||
2599 | input siclk; | |
2600 | input soclk; | |
2601 | ||
2602 | output [1:0] dout; | |
2603 | output scan_out; | |
2604 | assign fdin[1:0] = din[1:0]; | |
2605 | ||
2606 | ||
2607 | ||
2608 | ||
2609 | ||
2610 | ||
2611 | dff #(2) d0_0 ( | |
2612 | .l1clk(l1clk), | |
2613 | .siclk(siclk), | |
2614 | .soclk(soclk), | |
2615 | .d(fdin[1:0]), | |
2616 | .si({scan_in,so[0:0]}), | |
2617 | .so({so[0:0],scan_out}), | |
2618 | .q(dout[1:0]) | |
2619 | ); | |
2620 | ||
2621 | ||
2622 | ||
2623 | ||
2624 | ||
2625 | ||
2626 | ||
2627 | ||
2628 | ||
2629 | ||
2630 | ||
2631 | ||
2632 | endmodule | |
2633 | ||
2634 | ||
2635 | ||
2636 | ||
2637 | ||
2638 | ||
2639 | ||
2640 | ||
2641 | ||
2642 | ||
2643 | ||
2644 | ||
2645 | ||
2646 | // any PARAMS parms go into naming of macro | |
2647 | ||
2648 | module l2t_mb0_ctl_msff_ctl_macro__width_3 ( | |
2649 | din, | |
2650 | l1clk, | |
2651 | scan_in, | |
2652 | siclk, | |
2653 | soclk, | |
2654 | dout, | |
2655 | scan_out); | |
2656 | wire [2:0] fdin; | |
2657 | wire [1:0] so; | |
2658 | ||
2659 | input [2:0] din; | |
2660 | input l1clk; | |
2661 | input scan_in; | |
2662 | ||
2663 | ||
2664 | input siclk; | |
2665 | input soclk; | |
2666 | ||
2667 | output [2:0] dout; | |
2668 | output scan_out; | |
2669 | assign fdin[2:0] = din[2:0]; | |
2670 | ||
2671 | ||
2672 | ||
2673 | ||
2674 | ||
2675 | ||
2676 | dff #(3) d0_0 ( | |
2677 | .l1clk(l1clk), | |
2678 | .siclk(siclk), | |
2679 | .soclk(soclk), | |
2680 | .d(fdin[2:0]), | |
2681 | .si({scan_in,so[1:0]}), | |
2682 | .so({so[1:0],scan_out}), | |
2683 | .q(dout[2:0]) | |
2684 | ); | |
2685 | ||
2686 | ||
2687 | ||
2688 | ||
2689 | ||
2690 | ||
2691 | ||
2692 | ||
2693 | ||
2694 | ||
2695 | ||
2696 | ||
2697 | endmodule | |
2698 | ||
2699 | ||
2700 | ||
2701 | ||
2702 | ||
2703 | ||
2704 | ||
2705 | ||
2706 | ||
2707 | ||
2708 | ||
2709 | ||
2710 | ||
2711 | // any PARAMS parms go into naming of macro | |
2712 | ||
2713 | module l2t_mb0_ctl_msff_ctl_macro__width_19 ( | |
2714 | din, | |
2715 | l1clk, | |
2716 | scan_in, | |
2717 | siclk, | |
2718 | soclk, | |
2719 | dout, | |
2720 | scan_out); | |
2721 | wire [18:0] fdin; | |
2722 | wire [17:0] so; | |
2723 | ||
2724 | input [18:0] din; | |
2725 | input l1clk; | |
2726 | input scan_in; | |
2727 | ||
2728 | ||
2729 | input siclk; | |
2730 | input soclk; | |
2731 | ||
2732 | output [18:0] dout; | |
2733 | output scan_out; | |
2734 | assign fdin[18:0] = din[18:0]; | |
2735 | ||
2736 | ||
2737 | ||
2738 | ||
2739 | ||
2740 | ||
2741 | dff #(19) d0_0 ( | |
2742 | .l1clk(l1clk), | |
2743 | .siclk(siclk), | |
2744 | .soclk(soclk), | |
2745 | .d(fdin[18:0]), | |
2746 | .si({scan_in,so[17:0]}), | |
2747 | .so({so[17:0],scan_out}), | |
2748 | .q(dout[18:0]) | |
2749 | ); | |
2750 | ||
2751 | ||
2752 | ||
2753 | ||
2754 | ||
2755 | ||
2756 | ||
2757 | ||
2758 | ||
2759 | ||
2760 | ||
2761 | ||
2762 | endmodule | |
2763 | ||
2764 | ||
2765 | ||
2766 | ||
2767 | ||
2768 | ||
2769 | ||
2770 | ||
2771 | ||
2772 | ||
2773 | ||
2774 | ||
2775 | ||
2776 | // any PARAMS parms go into naming of macro | |
2777 | ||
2778 | module l2t_mb0_ctl_msff_ctl_macro__width_5 ( | |
2779 | din, | |
2780 | l1clk, | |
2781 | scan_in, | |
2782 | siclk, | |
2783 | soclk, | |
2784 | dout, | |
2785 | scan_out); | |
2786 | wire [4:0] fdin; | |
2787 | wire [3:0] so; | |
2788 | ||
2789 | input [4:0] din; | |
2790 | input l1clk; | |
2791 | input scan_in; | |
2792 | ||
2793 | ||
2794 | input siclk; | |
2795 | input soclk; | |
2796 | ||
2797 | output [4:0] dout; | |
2798 | output scan_out; | |
2799 | assign fdin[4:0] = din[4:0]; | |
2800 | ||
2801 | ||
2802 | ||
2803 | ||
2804 | ||
2805 | ||
2806 | dff #(5) d0_0 ( | |
2807 | .l1clk(l1clk), | |
2808 | .siclk(siclk), | |
2809 | .soclk(soclk), | |
2810 | .d(fdin[4:0]), | |
2811 | .si({scan_in,so[3:0]}), | |
2812 | .so({so[3:0],scan_out}), | |
2813 | .q(dout[4:0]) | |
2814 | ); | |
2815 | ||
2816 | ||
2817 | ||
2818 | ||
2819 | ||
2820 | ||
2821 | ||
2822 | ||
2823 | ||
2824 | ||
2825 | ||
2826 | ||
2827 | endmodule | |
2828 | ||
2829 | ||
2830 | ||
2831 | ||
2832 | ||
2833 | ||
2834 | ||
2835 | ||
2836 | ||
2837 | ||
2838 | ||
2839 | ||
2840 | ||
2841 | // any PARAMS parms go into naming of macro | |
2842 | ||
2843 | module l2t_mb0_ctl_msff_ctl_macro__width_10 ( | |
2844 | din, | |
2845 | l1clk, | |
2846 | scan_in, | |
2847 | siclk, | |
2848 | soclk, | |
2849 | dout, | |
2850 | scan_out); | |
2851 | wire [9:0] fdin; | |
2852 | wire [8:0] so; | |
2853 | ||
2854 | input [9:0] din; | |
2855 | input l1clk; | |
2856 | input scan_in; | |
2857 | ||
2858 | ||
2859 | input siclk; | |
2860 | input soclk; | |
2861 | ||
2862 | output [9:0] dout; | |
2863 | output scan_out; | |
2864 | assign fdin[9:0] = din[9:0]; | |
2865 | ||
2866 | ||
2867 | ||
2868 | ||
2869 | ||
2870 | ||
2871 | dff #(10) d0_0 ( | |
2872 | .l1clk(l1clk), | |
2873 | .siclk(siclk), | |
2874 | .soclk(soclk), | |
2875 | .d(fdin[9:0]), | |
2876 | .si({scan_in,so[8:0]}), | |
2877 | .so({so[8:0],scan_out}), | |
2878 | .q(dout[9:0]) | |
2879 | ); | |
2880 | ||
2881 | ||
2882 | ||
2883 | ||
2884 | ||
2885 | ||
2886 | ||
2887 | ||
2888 | ||
2889 | ||
2890 | ||
2891 | ||
2892 | endmodule | |
2893 | ||
2894 | ||
2895 | ||
2896 | ||
2897 | ||
2898 | ||
2899 | ||
2900 | ||
2901 | ||
2902 | ||
2903 | ||
2904 | ||
2905 | ||
2906 | // any PARAMS parms go into naming of macro | |
2907 | ||
2908 | module l2t_mb0_ctl_msff_ctl_macro__width_21 ( | |
2909 | din, | |
2910 | l1clk, | |
2911 | scan_in, | |
2912 | siclk, | |
2913 | soclk, | |
2914 | dout, | |
2915 | scan_out); | |
2916 | wire [20:0] fdin; | |
2917 | wire [19:0] so; | |
2918 | ||
2919 | input [20:0] din; | |
2920 | input l1clk; | |
2921 | input scan_in; | |
2922 | ||
2923 | ||
2924 | input siclk; | |
2925 | input soclk; | |
2926 | ||
2927 | output [20:0] dout; | |
2928 | output scan_out; | |
2929 | assign fdin[20:0] = din[20:0]; | |
2930 | ||
2931 | ||
2932 | ||
2933 | ||
2934 | ||
2935 | ||
2936 | dff #(21) d0_0 ( | |
2937 | .l1clk(l1clk), | |
2938 | .siclk(siclk), | |
2939 | .soclk(soclk), | |
2940 | .d(fdin[20:0]), | |
2941 | .si({scan_in,so[19:0]}), | |
2942 | .so({so[19:0],scan_out}), | |
2943 | .q(dout[20:0]) | |
2944 | ); | |
2945 | ||
2946 | ||
2947 | ||
2948 | ||
2949 | ||
2950 | ||
2951 | ||
2952 | ||
2953 | ||
2954 | ||
2955 | ||
2956 | ||
2957 | endmodule | |
2958 | ||
2959 | ||
2960 | ||
2961 | ||
2962 | ||
2963 | ||
2964 | ||
2965 | ||
2966 | ||
2967 | ||
2968 | ||
2969 | ||
2970 | ||
2971 | // any PARAMS parms go into naming of macro | |
2972 | ||
2973 | module l2t_mb0_ctl_msff_ctl_macro__width_16 ( | |
2974 | din, | |
2975 | l1clk, | |
2976 | scan_in, | |
2977 | siclk, | |
2978 | soclk, | |
2979 | dout, | |
2980 | scan_out); | |
2981 | wire [15:0] fdin; | |
2982 | wire [14:0] so; | |
2983 | ||
2984 | input [15:0] din; | |
2985 | input l1clk; | |
2986 | input scan_in; | |
2987 | ||
2988 | ||
2989 | input siclk; | |
2990 | input soclk; | |
2991 | ||
2992 | output [15:0] dout; | |
2993 | output scan_out; | |
2994 | assign fdin[15:0] = din[15:0]; | |
2995 | ||
2996 | ||
2997 | ||
2998 | ||
2999 | ||
3000 | ||
3001 | dff #(16) d0_0 ( | |
3002 | .l1clk(l1clk), | |
3003 | .siclk(siclk), | |
3004 | .soclk(soclk), | |
3005 | .d(fdin[15:0]), | |
3006 | .si({scan_in,so[14:0]}), | |
3007 | .so({so[14:0],scan_out}), | |
3008 | .q(dout[15:0]) | |
3009 | ); | |
3010 | ||
3011 | ||
3012 | ||
3013 | ||
3014 | ||
3015 | ||
3016 | ||
3017 | ||
3018 | ||
3019 | ||
3020 | ||
3021 | ||
3022 | endmodule | |
3023 | ||
3024 | ||
3025 | ||
3026 | ||
3027 | ||
3028 | ||
3029 | ||
3030 | ||
3031 | ||
3032 | ||
3033 | ||
3034 | ||
3035 | ||
3036 | // any PARAMS parms go into naming of macro | |
3037 | ||
3038 | module l2t_mb0_ctl_msff_ctl_macro__width_36 ( | |
3039 | din, | |
3040 | l1clk, | |
3041 | scan_in, | |
3042 | siclk, | |
3043 | soclk, | |
3044 | dout, | |
3045 | scan_out); | |
3046 | wire [35:0] fdin; | |
3047 | wire [34:0] so; | |
3048 | ||
3049 | input [35:0] din; | |
3050 | input l1clk; | |
3051 | input scan_in; | |
3052 | ||
3053 | ||
3054 | input siclk; | |
3055 | input soclk; | |
3056 | ||
3057 | output [35:0] dout; | |
3058 | output scan_out; | |
3059 | assign fdin[35:0] = din[35:0]; | |
3060 | ||
3061 | ||
3062 | ||
3063 | ||
3064 | ||
3065 | ||
3066 | dff #(36) d0_0 ( | |
3067 | .l1clk(l1clk), | |
3068 | .siclk(siclk), | |
3069 | .soclk(soclk), | |
3070 | .d(fdin[35:0]), | |
3071 | .si({scan_in,so[34:0]}), | |
3072 | .so({so[34:0],scan_out}), | |
3073 | .q(dout[35:0]) | |
3074 | ); | |
3075 | ||
3076 | ||
3077 | ||
3078 | ||
3079 | ||
3080 | ||
3081 | ||
3082 | ||
3083 | ||
3084 | ||
3085 | ||
3086 | ||
3087 | endmodule | |
3088 | ||
3089 | ||
3090 | ||
3091 | ||
3092 | ||
3093 | ||
3094 | ||
3095 | ||
3096 | ||
3097 | ||
3098 | ||
3099 | ||
3100 | ||
3101 | // any PARAMS parms go into naming of macro | |
3102 | ||
3103 | module l2t_mb0_ctl_msff_ctl_macro__width_9 ( | |
3104 | din, | |
3105 | l1clk, | |
3106 | scan_in, | |
3107 | siclk, | |
3108 | soclk, | |
3109 | dout, | |
3110 | scan_out); | |
3111 | wire [8:0] fdin; | |
3112 | wire [7:0] so; | |
3113 | ||
3114 | input [8:0] din; | |
3115 | input l1clk; | |
3116 | input scan_in; | |
3117 | ||
3118 | ||
3119 | input siclk; | |
3120 | input soclk; | |
3121 | ||
3122 | output [8:0] dout; | |
3123 | output scan_out; | |
3124 | assign fdin[8:0] = din[8:0]; | |
3125 | ||
3126 | ||
3127 | ||
3128 | ||
3129 | ||
3130 | ||
3131 | dff #(9) d0_0 ( | |
3132 | .l1clk(l1clk), | |
3133 | .siclk(siclk), | |
3134 | .soclk(soclk), | |
3135 | .d(fdin[8:0]), | |
3136 | .si({scan_in,so[7:0]}), | |
3137 | .so({so[7:0],scan_out}), | |
3138 | .q(dout[8:0]) | |
3139 | ); | |
3140 | ||
3141 | ||
3142 | ||
3143 | ||
3144 | ||
3145 | ||
3146 | ||
3147 | ||
3148 | ||
3149 | ||
3150 | ||
3151 | ||
3152 | endmodule | |
3153 | ||
3154 | ||
3155 | ||
3156 | ||
3157 | ||
3158 | ||
3159 | ||
3160 | ||
3161 | ||
3162 | // Description: Spare gate macro for control blocks | |
3163 | // | |
3164 | // Param num controls the number of times the macro is added | |
3165 | // flops=0 can be used to use only combination spare logic | |
3166 | ||
3167 | ||
3168 | module l2t_mb0_ctl_spare_ctl_macro__num_2 ( | |
3169 | l1clk, | |
3170 | scan_in, | |
3171 | siclk, | |
3172 | soclk, | |
3173 | scan_out); | |
3174 | wire si_0; | |
3175 | wire so_0; | |
3176 | wire spare0_flop_unused; | |
3177 | wire spare0_buf_32x_unused; | |
3178 | wire spare0_nand3_8x_unused; | |
3179 | wire spare0_inv_8x_unused; | |
3180 | wire spare0_aoi22_4x_unused; | |
3181 | wire spare0_buf_8x_unused; | |
3182 | wire spare0_oai22_4x_unused; | |
3183 | wire spare0_inv_16x_unused; | |
3184 | wire spare0_nand2_16x_unused; | |
3185 | wire spare0_nor3_4x_unused; | |
3186 | wire spare0_nand2_8x_unused; | |
3187 | wire spare0_buf_16x_unused; | |
3188 | wire spare0_nor2_16x_unused; | |
3189 | wire spare0_inv_32x_unused; | |
3190 | wire si_1; | |
3191 | wire so_1; | |
3192 | wire spare1_flop_unused; | |
3193 | wire spare1_buf_32x_unused; | |
3194 | wire spare1_nand3_8x_unused; | |
3195 | wire spare1_inv_8x_unused; | |
3196 | wire spare1_aoi22_4x_unused; | |
3197 | wire spare1_buf_8x_unused; | |
3198 | wire spare1_oai22_4x_unused; | |
3199 | wire spare1_inv_16x_unused; | |
3200 | wire spare1_nand2_16x_unused; | |
3201 | wire spare1_nor3_4x_unused; | |
3202 | wire spare1_nand2_8x_unused; | |
3203 | wire spare1_buf_16x_unused; | |
3204 | wire spare1_nor2_16x_unused; | |
3205 | wire spare1_inv_32x_unused; | |
3206 | ||
3207 | ||
3208 | input l1clk; | |
3209 | input scan_in; | |
3210 | input siclk; | |
3211 | input soclk; | |
3212 | output scan_out; | |
3213 | ||
3214 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
3215 | .siclk(siclk), | |
3216 | .soclk(soclk), | |
3217 | .si(si_0), | |
3218 | .so(so_0), | |
3219 | .d(1'b0), | |
3220 | .q(spare0_flop_unused)); | |
3221 | assign si_0 = scan_in; | |
3222 | ||
3223 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
3224 | .out(spare0_buf_32x_unused)); | |
3225 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
3226 | .in1(1'b1), | |
3227 | .in2(1'b1), | |
3228 | .out(spare0_nand3_8x_unused)); | |
3229 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
3230 | .out(spare0_inv_8x_unused)); | |
3231 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
3232 | .in01(1'b1), | |
3233 | .in10(1'b1), | |
3234 | .in11(1'b1), | |
3235 | .out(spare0_aoi22_4x_unused)); | |
3236 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
3237 | .out(spare0_buf_8x_unused)); | |
3238 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
3239 | .in01(1'b1), | |
3240 | .in10(1'b1), | |
3241 | .in11(1'b1), | |
3242 | .out(spare0_oai22_4x_unused)); | |
3243 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
3244 | .out(spare0_inv_16x_unused)); | |
3245 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
3246 | .in1(1'b1), | |
3247 | .out(spare0_nand2_16x_unused)); | |
3248 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
3249 | .in1(1'b0), | |
3250 | .in2(1'b0), | |
3251 | .out(spare0_nor3_4x_unused)); | |
3252 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
3253 | .in1(1'b1), | |
3254 | .out(spare0_nand2_8x_unused)); | |
3255 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
3256 | .out(spare0_buf_16x_unused)); | |
3257 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
3258 | .in1(1'b0), | |
3259 | .out(spare0_nor2_16x_unused)); | |
3260 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
3261 | .out(spare0_inv_32x_unused)); | |
3262 | ||
3263 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
3264 | .siclk(siclk), | |
3265 | .soclk(soclk), | |
3266 | .si(si_1), | |
3267 | .so(so_1), | |
3268 | .d(1'b0), | |
3269 | .q(spare1_flop_unused)); | |
3270 | assign si_1 = so_0; | |
3271 | ||
3272 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
3273 | .out(spare1_buf_32x_unused)); | |
3274 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
3275 | .in1(1'b1), | |
3276 | .in2(1'b1), | |
3277 | .out(spare1_nand3_8x_unused)); | |
3278 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
3279 | .out(spare1_inv_8x_unused)); | |
3280 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
3281 | .in01(1'b1), | |
3282 | .in10(1'b1), | |
3283 | .in11(1'b1), | |
3284 | .out(spare1_aoi22_4x_unused)); | |
3285 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
3286 | .out(spare1_buf_8x_unused)); | |
3287 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
3288 | .in01(1'b1), | |
3289 | .in10(1'b1), | |
3290 | .in11(1'b1), | |
3291 | .out(spare1_oai22_4x_unused)); | |
3292 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
3293 | .out(spare1_inv_16x_unused)); | |
3294 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
3295 | .in1(1'b1), | |
3296 | .out(spare1_nand2_16x_unused)); | |
3297 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
3298 | .in1(1'b0), | |
3299 | .in2(1'b0), | |
3300 | .out(spare1_nor3_4x_unused)); | |
3301 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
3302 | .in1(1'b1), | |
3303 | .out(spare1_nand2_8x_unused)); | |
3304 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
3305 | .out(spare1_buf_16x_unused)); | |
3306 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
3307 | .in1(1'b0), | |
3308 | .out(spare1_nor2_16x_unused)); | |
3309 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
3310 | .out(spare1_inv_32x_unused)); | |
3311 | assign scan_out = so_1; | |
3312 | ||
3313 | ||
3314 | ||
3315 | endmodule | |
3316 |