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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / l2t / rtl / l2t_tagd_dp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: l2t_tagd_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`define ADDR_MAP_HI 39
36`define ADDR_MAP_LO 32
37`define IO_ADDR_BIT 39
38
39// CMP space
40`define DRAM_DATA_LO 8'h00
41`define DRAM_DATA_HI 8'h7f
42
43// IOP space
44`define JBUS1 8'h80
45`define HASH_TBL_NRAM_CSR 8'h81
46`define RESERVED_1 8'h82
47`define ENET_MAC_CSR 8'h83
48`define ENET_ING_CSR 8'h84
49`define ENET_EGR_CMD_CSR 8'h85
50`define ENET_EGR_DP_CSR 8'h86
51`define RESERVED_2_LO 8'h87
52`define RESERVED_2_HI 8'h92
53`define BSC_CSR 8'h93
54`define RESERVED_3 8'h94
55`define RAND_GEN_CSR 8'h95
56`define CLOCK_UNIT_CSR 8'h96
57`define DRAM_CSR 8'h97
58`define IOB_MAN_CSR 8'h98
59`define TAP_CSR 8'h99
60`define RESERVED_4_L0 8'h9a
61`define RESERVED_4_HI 8'h9d
62`define CPU_ASI 8'h9e
63`define IOB_INT_CSR 8'h9f
64
65// L2 space
66`define L2C_CSR_LO 8'ha0
67`define L2C_CSR_HI 8'hbf
68
69// More IOP space
70`define JBUS2_LO 8'hc0
71`define JBUS2_HI 8'hfe
72`define SPI_CSR 8'hff
73
74
75//Cache Crossbar Width and Field Defines
76//======================================
77`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
78`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
79`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
80`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
81`define CPX_WIDTH11 134
82`define CPX_WIDTH11c 134c
83`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
84
85`define PCX_VLD 123 //PCX packet valid
86`define PCX_RQ_HI 122 //PCX request type field
87`define PCX_RQ_LO 118
88`define PCX_NC 117 //PCX non-cacheable bit
89`define PCX_R 117 //PCX read/!write bit
90`define PCX_CP_HI 116 //PCX cpu_id field
91`define PCX_CP_LO 114
92`define PCX_TH_HI 113 //PCX Thread field
93`define PCX_TH_LO 112
94`define PCX_BF_HI 111 //PCX buffer id field
95`define PCX_INVALL 111
96`define PCX_BF_LO 109
97`define PCX_WY_HI 108 //PCX replaced L1 way field
98`define PCX_WY_LO 107
99`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
100`define PCX_P_LO 107
101`define PCX_SZ_HI 106 //PCX load/store size field
102`define PCX_SZ_LO 104
103`define PCX_ERR_HI 106 //PCX error field
104`define PCX_ERR_LO 104
105`define PCX_AD_HI 103 //PCX address field
106`define PCX_AD_LO 64
107`define PCX_DA_HI 63 //PCX Store data
108`define PCX_DA_LO 0
109
110`define PCX_SZ_1B 3'b000 // encoding for 1B access
111`define PCX_SZ_2B 3'b001 // encoding for 2B access
112`define PCX_SZ_4B 3'b010 // encoding for 4B access
113`define PCX_SZ_8B 3'b011 // encoding for 8B access
114`define PCX_SZ_16B 3'b100 // encoding for 16B access
115
116`define CPX_VLD 145 //CPX payload packet valid
117
118`define CPX_RQ_HI 144 //CPX Request type
119`define CPX_RQ_LO 141
120`define CPX_L2MISS 140
121`define CPX_ERR_HI 140 //CPX error field
122`define CPX_ERR_LO 138
123`define CPX_NC 137 //CPX non-cacheable
124`define CPX_R 137 //CPX read/!write bit
125`define CPX_TH_HI 136 //CPX thread ID field
126`define CPX_TH_LO 134
127
128//bits 133:128 are shared by different fields
129//for different packet types.
130
131`define CPX_IN_HI 133 //CPX Interrupt source
132`define CPX_IN_LO 128
133
134`define CPX_WYVLD 133 //CPX replaced way valid
135`define CPX_WY_HI 132 //CPX replaced I$/D$ way
136`define CPX_WY_LO 131
137`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
138`define CPX_BF_LO 128
139
140`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
141`define CPX_SI_LO 128 //used for invalidates
142
143`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
144`define CPX_P_LO 130
145
146`define CPX_ASI 130 //CPX forward request to ASI
147`define CPX_IF4B 130
148`define CPX_IINV 124
149`define CPX_DINV 123
150`define CPX_INVPA5 122
151`define CPX_INVPA4 121
152`define CPX_CPUID_HI 120
153`define CPX_CPUID_LO 118
154`define CPX_INV_PA_HI 116
155`define CPX_INV_PA_LO 112
156`define CPX_INV_IDX_HI 117
157`define CPX_INV_IDX_LO 112
158
159`define CPX_DA_HI 127 //CPX data payload
160`define CPX_DA_LO 0
161
162`define LOAD_RQ 5'b00000
163`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
164`define IMISS_RQ 5'b10000
165`define STORE_RQ 5'b00001
166`define CAS1_RQ 5'b00010
167`define CAS2_RQ 5'b00011
168`define SWAP_RQ 5'b00111
169`define STRLOAD_RQ 5'b00100
170`define STRST_RQ 5'b00101
171`define STQ_RQ 5'b00111
172`define INT_RQ 5'b01001
173`define FWD_RQ 5'b01101
174`define FWD_RPY 5'b01110
175`define RSVD_RQ 5'b11111
176
177`define LOAD_RET 4'b0000
178`define INV_RET 4'b0011
179`define ST_ACK 4'b0100
180`define AT_ACK 4'b0011
181`define INT_RET 4'b0111
182`define TEST_RET 4'b0101
183`define FP_RET 4'b1000
184`define IFILL_RET 4'b0001
185`define EVICT_REQ 4'b0011
186//`define INVAL_ACK 4'b1000
187`define INVAL_ACK 4'b0100
188`define ERR_RET 4'b1100
189`define STRLOAD_RET 4'b0010
190`define STRST_ACK 4'b0110
191`define FWD_RQ_RET 4'b1010
192`define FWD_RPY_RET 4'b1011
193`define RSVD_RET 4'b1111
194
195//End cache crossbar defines
196
197
198// Number of COS supported by EECU
199`define EECU_COS_NUM 2
200
201
202//
203// BSC bus sizes
204// =============
205//
206
207// General
208`define BSC_ADDRESS 40
209`define MAX_XFER_LEN 7'b0
210`define XFER_LEN_WIDTH 6
211
212// CTags
213`define BSC_CTAG_SZ 12
214`define EICU_CTAG_PRE 5'b11101
215`define EICU_CTAG_REM 7
216`define EIPU_CTAG_PRE 3'b011
217`define EIPU_CTAG_REM 9
218`define EECU_CTAG_PRE 8'b11010000
219`define EECU_CTAG_REM 4
220`define EEPU_CTAG_PRE 6'b010000
221`define EEPU_CTAG_REM 6
222`define L2C_CTAG_PRE 2'b00
223`define L2C_CTAG_REM 10
224`define JBI_CTAG_PRE 2'b10
225`define JBI_CTAG_REM 10
226// reinstated temporarily
227`define PCI_CTAG_PRE 7'b1101100
228`define PCI_CTAG_REM 5
229
230
231// CoS
232`define EICU_COS 1'b0
233`define EIPU_COS 1'b1
234`define EECU_COS 1'b0
235`define EEPU_COS 1'b1
236`define PCI_COS 1'b0
237
238// L2$ Bank
239`define BSC_L2_BNK_HI 8
240`define BSC_L2_BNK_LO 6
241
242// L2$ Req
243`define BSC_L2_REQ_SZ 62
244`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
245`define BSC_L2_BUS 64
246`define BSC_L2_CTAG_HI 61
247`define BSC_L2_CTAG_LO 50
248`define BSC_L2_ADD_HI 49
249`define BSC_L2_ADD_LO 10
250`define BSC_L2_LEN_HI 9
251`define BSC_L2_LEN_LO 3
252`define BSC_L2_ALLOC 2
253`define BSC_L2_COS 1
254`define BSC_L2_READ 0
255
256// L2$ Ack
257`define L2_BSC_ACK_SZ 16
258`define L2_BSC_BUS 64
259`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
260`define L2_BSC_CBA_LO 13
261`define L2_BSC_READ 12
262`define L2_BSC_CTAG_HI 11
263`define L2_BSC_CTAG_LO 0
264
265// Enet Egress Command Unit
266`define EECU_REQ_BUS 44
267`define EECU_REQ_SZ 44
268`define EECU_R_QID_HI 43
269`define EECU_R_QID_LO 40
270`define EECU_R_ADD_HI 39
271`define EECU_R_ADD_LO 0
272
273`define EECU_ACK_BUS 64
274`define EECU_ACK_SZ 5
275`define EECU_A_NACK 4
276`define EECU_A_QID_HI 3
277`define EECU_A_QID_LO 0
278
279
280// Enet Egress Packet Unit
281`define EEPU_REQ_BUS 55
282`define EEPU_REQ_SZ 55
283`define EEPU_R_TLEN_HI 54
284`define EEPU_R_TLEN_LO 48
285`define EEPU_R_SOF 47
286`define EEPU_R_EOF 46
287`define EEPU_R_PORT_HI 45
288`define EEPU_R_PORT_LO 44
289`define EEPU_R_QID_HI 43
290`define EEPU_R_QID_LO 40
291`define EEPU_R_ADD_HI 39
292`define EEPU_R_ADD_LO 0
293
294// This is cleaved in between Egress Datapath Ack's
295`define EEPU_ACK_BUS 6
296`define EEPU_ACK_SZ 6
297`define EEPU_A_EOF 5
298`define EEPU_A_NACK 4
299`define EEPU_A_QID_HI 3
300`define EEPU_A_QID_LO 0
301
302
303// Enet Egress Datapath
304`define EEDP_ACK_BUS 128
305`define EEDP_ACK_SZ 28
306`define EEDP_A_NACK 27
307`define EEDP_A_QID_HI 26
308`define EEDP_A_QID_LO 21
309`define EEDP_A_SOF 20
310`define EEDP_A_EOF 19
311`define EEDP_A_LEN_HI 18
312`define EEDP_A_LEN_LO 12
313`define EEDP_A_TAG_HI 11
314`define EEDP_A_TAG_LO 0
315`define EEDP_A_PORT_HI 5
316`define EEDP_A_PORT_LO 4
317`define EEDP_A_PORT_WIDTH 2
318
319
320// In-Order / Ordered Queue: EEPU
321// Tag is: TLEN, SOF, EOF, QID = 15
322`define EEPU_TAG_ARY (7+1+1+6)
323`define EEPU_ENTRIES 16
324`define EEPU_E_IDX 4
325`define EEPU_PORTS 4
326`define EEPU_P_IDX 2
327
328// Nack + Tag Info + CTag
329`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
330`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
331
332
333// ENET Ingress Queue Management Req
334`define EICU_REQ_BUS 64
335`define EICU_REQ_SZ 62
336`define EICU_R_CTAG_HI 61
337`define EICU_R_CTAG_LO 50
338`define EICU_R_ADD_HI 49
339`define EICU_R_ADD_LO 10
340`define EICU_R_LEN_HI 9
341`define EICU_R_LEN_LO 3
342`define EICU_R_COS 1
343`define EICU_R_READ 0
344
345
346// ENET Ingress Queue Management Ack
347`define EICU_ACK_BUS 64
348`define EICU_ACK_SZ 14
349`define EICU_A_NACK 13
350`define EICU_A_READ 12
351`define EICU_A_CTAG_HI 11
352`define EICU_A_CTAG_LO 0
353
354
355// Enet Ingress Packet Unit
356`define EIPU_REQ_BUS 128
357`define EIPU_REQ_SZ 59
358`define EIPU_R_CTAG_HI 58
359`define EIPU_R_CTAG_LO 50
360`define EIPU_R_ADD_HI 49
361`define EIPU_R_ADD_LO 10
362`define EIPU_R_LEN_HI 9
363`define EIPU_R_LEN_LO 3
364`define EIPU_R_COS 1
365`define EIPU_R_READ 0
366
367
368// ENET Ingress Packet Unit Ack
369`define EIPU_ACK_BUS 10
370`define EIPU_ACK_SZ 10
371`define EIPU_A_NACK 9
372`define EIPU_A_CTAG_HI 8
373`define EIPU_A_CTAG_LO 0
374
375
376// In-Order / Ordered Queue: PCI
377// Tag is: CTAG
378`define PCI_TAG_ARY 12
379`define PCI_ENTRIES 16
380`define PCI_E_IDX 4
381`define PCI_PORTS 2
382
383// PCI-X Request
384`define PCI_REQ_BUS 64
385`define PCI_REQ_SZ 62
386`define PCI_R_CTAG_HI 61
387`define PCI_R_CTAG_LO 50
388`define PCI_R_ADD_HI 49
389`define PCI_R_ADD_LO 10
390`define PCI_R_LEN_HI 9
391`define PCI_R_LEN_LO 3
392`define PCI_R_COS 1
393`define PCI_R_READ 0
394
395// PCI_X Acknowledge
396`define PCI_ACK_BUS 64
397`define PCI_ACK_SZ 14
398`define PCI_A_NACK 13
399`define PCI_A_READ 12
400`define PCI_A_CTAG_HI 11
401`define PCI_A_CTAG_LO 0
402
403
404`define BSC_MAX_REQ_SZ 62
405
406
407//
408// BSC array sizes
409//================
410//
411`define BSC_REQ_ARY_INDEX 6
412`define BSC_REQ_ARY_DEPTH 64
413`define BSC_REQ_ARY_WIDTH 62
414`define BSC_REQ_NXT_WIDTH 12
415`define BSC_ACK_ARY_INDEX 6
416`define BSC_ACK_ARY_DEPTH 64
417`define BSC_ACK_ARY_WIDTH 14
418`define BSC_ACK_NXT_WIDTH 12
419`define BSC_PAY_ARY_INDEX 6
420`define BSC_PAY_ARY_DEPTH 64
421`define BSC_PAY_ARY_WIDTH 256
422
423// ECC syndrome bits per memory element
424`define BSC_PAY_ECC 10
425`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
426
427
428//
429// BSC Port Definitions
430// ====================
431//
432// Bits 7 to 4 of curr_port_id
433`define BSC_PORT_NULL 4'h0
434`define BSC_PORT_SC 4'h1
435`define BSC_PORT_EICU 4'h2
436`define BSC_PORT_EIPU 4'h3
437`define BSC_PORT_EECU 4'h4
438`define BSC_PORT_EEPU 4'h8
439`define BSC_PORT_PCI 4'h9
440
441// Number of ports of each type
442`define BSC_PORT_SC_CNT 8
443
444// Bits needed to represent above
445`define BSC_PORT_SC_IDX 3
446
447// How wide the linked list pointers are
448// 60b for no payload (2CoS)
449// 80b for payload (2CoS)
450
451//`define BSC_OBJ_PTR 80
452//`define BSC_HD1_HI 69
453//`define BSC_HD1_LO 60
454//`define BSC_TL1_HI 59
455//`define BSC_TL1_LO 50
456//`define BSC_CT1_HI 49
457//`define BSC_CT1_LO 40
458//`define BSC_HD0_HI 29
459//`define BSC_HD0_LO 20
460//`define BSC_TL0_HI 19
461//`define BSC_TL0_LO 10
462//`define BSC_CT0_HI 9
463//`define BSC_CT0_LO 0
464
465`define BSC_OBJP_PTR 48
466`define BSC_PYP1_HI 47
467`define BSC_PYP1_LO 42
468`define BSC_HDP1_HI 41
469`define BSC_HDP1_LO 36
470`define BSC_TLP1_HI 35
471`define BSC_TLP1_LO 30
472`define BSC_CTP1_HI 29
473`define BSC_CTP1_LO 24
474`define BSC_PYP0_HI 23
475`define BSC_PYP0_LO 18
476`define BSC_HDP0_HI 17
477`define BSC_HDP0_LO 12
478`define BSC_TLP0_HI 11
479`define BSC_TLP0_LO 6
480`define BSC_CTP0_HI 5
481`define BSC_CTP0_LO 0
482
483`define BSC_PTR_WIDTH 192
484`define BSC_PTR_REQ_HI 191
485`define BSC_PTR_REQ_LO 144
486`define BSC_PTR_REQP_HI 143
487`define BSC_PTR_REQP_LO 96
488`define BSC_PTR_ACK_HI 95
489`define BSC_PTR_ACK_LO 48
490`define BSC_PTR_ACKP_HI 47
491`define BSC_PTR_ACKP_LO 0
492
493`define BSC_PORT_SC_PTR 96 // R, R+P
494`define BSC_PORT_EECU_PTR 48 // A+P
495`define BSC_PORT_EICU_PTR 96 // A, A+P
496`define BSC_PORT_EIPU_PTR 48 // A
497
498// I2C STATES in DRAMctl
499`define I2C_CMD_NOP 4'b0000
500`define I2C_CMD_START 4'b0001
501`define I2C_CMD_STOP 4'b0010
502`define I2C_CMD_WRITE 4'b0100
503`define I2C_CMD_READ 4'b1000
504
505
506//
507// IOB defines
508// ===========
509//
510`define IOB_ADDR_WIDTH 40
511`define IOB_LOCAL_ADDR_WIDTH 32
512
513`define IOB_CPU_INDEX 3
514`define IOB_CPU_WIDTH 8
515`define IOB_THR_INDEX 2
516`define IOB_THR_WIDTH 4
517`define IOB_CPUTHR_INDEX 5
518`define IOB_CPUTHR_WIDTH 32
519
520`define IOB_MONDO_DATA_INDEX 5
521`define IOB_MONDO_DATA_DEPTH 32
522`define IOB_MONDO_DATA_WIDTH 64
523`define IOB_MONDO_SRC_WIDTH 5
524`define IOB_MONDO_BUSY 5
525
526`define IOB_INT_TAB_INDEX 6
527`define IOB_INT_TAB_DEPTH 64
528
529`define IOB_INT_STAT_WIDTH 32
530`define IOB_INT_STAT_HI 31
531`define IOB_INT_STAT_LO 0
532
533`define IOB_INT_VEC_WIDTH 6
534`define IOB_INT_VEC_HI 5
535`define IOB_INT_VEC_LO 0
536
537`define IOB_INT_CPU_WIDTH 5
538`define IOB_INT_CPU_HI 12
539`define IOB_INT_CPU_LO 8
540
541`define IOB_INT_MASK 2
542`define IOB_INT_CLEAR 1
543`define IOB_INT_PEND 0
544
545`define IOB_DISP_TYPE_HI 17
546`define IOB_DISP_TYPE_LO 16
547`define IOB_DISP_THR_HI 12
548`define IOB_DISP_THR_LO 8
549`define IOB_DISP_VEC_HI 5
550`define IOB_DISP_VEC_LO 0
551
552`define IOB_JBI_RESET 1
553`define IOB_ENET_RESET 0
554
555`define IOB_RESET_STAT_WIDTH 3
556`define IOB_RESET_STAT_HI 3
557`define IOB_RESET_STAT_LO 1
558
559`define IOB_SERNUM_WIDTH 64
560
561`define IOB_FUSE_WIDTH 22
562
563`define IOB_TMSTAT_THERM 63
564
565`define IOB_POR_TT 6'b01 // power-on-reset trap type
566
567`define IOB_CPU_BUF_INDEX 4
568
569`define IOB_INT_BUF_INDEX 4
570`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
571
572`define IOB_IO_BUF_INDEX 4
573`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
574
575`define IOB_L2_VIS_BUF_INDEX 5
576`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
577
578`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
579`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
580
581// fixme - double check address mapping
582// CREG in `IOB_INT_CSR space
583`define IOB_DEV_ADDR_MASK 32'hfffffe07
584`define IOB_CREG_INTSTAT 32'h00000000
585`define IOB_CREG_MDATA0 32'h00000400
586`define IOB_CREG_MDATA1 32'h00000500
587`define IOB_CREG_MBUSY 32'h00000900
588`define IOB_THR_ADDR_MASK 32'hffffff07
589`define IOB_CREG_MDATA0_ALIAS 32'h00000600
590`define IOB_CREG_MDATA1_ALIAS 32'h00000700
591`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
592
593// CREG in `IOB_MAN_CSR space
594`define IOB_CREG_INTMAN 32'h00000000
595`define IOB_CREG_INTCTL 32'h00000400
596`define IOB_CREG_INTVECDISP 32'h00000800
597`define IOB_CREG_RESETSTAT 32'h00000810
598`define IOB_CREG_SERNUM 32'h00000820
599`define IOB_CREG_TMSTATCTRL 32'h00000828
600`define IOB_CREG_COREAVAIL 32'h00000830
601`define IOB_CREG_SSYSRESET 32'h00000838
602`define IOB_CREG_FUSESTAT 32'h00000840
603`define IOB_CREG_JINTV 32'h00000a00
604
605`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
606`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
607`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
608`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
609`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
610`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
611`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
612`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
613`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
614`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
615`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
616`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
617`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
618`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
619`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
620`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
621`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
622`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
623`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
624`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
625`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
626`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
627
628`define IOB_CREG_TESTSTUB 32'h80000000
629
630// Address map for TAP access of SPARC ASI
631`define IOB_ASI_PC 4'b0000
632`define IOB_ASI_BIST 4'b0001
633`define IOB_ASI_MARGIN 4'b0010
634`define IOB_ASI_DEFEATURE 4'b0011
635`define IOB_ASI_L1DD 4'b0100
636`define IOB_ASI_L1ID 4'b0101
637`define IOB_ASI_L1DT 4'b0110
638
639`define IOB_INT 2'b00
640`define IOB_RESET 2'b01
641`define IOB_IDLE 2'b10
642`define IOB_RESUME 2'b11
643
644//
645// CIOP UCB Bus Width
646// ==================
647//
648`define IOB_EECU_WIDTH 16 // ethernet egress command
649`define EECU_IOB_WIDTH 16
650
651`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
652`define NRAM_IOB_WIDTH 4
653
654`define IOB_JBI_WIDTH 16 // JBI
655`define JBI_IOB_WIDTH 16
656
657`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
658`define ENET_ING_IOB_WIDTH 8
659
660`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
661`define ENET_EGR_IOB_WIDTH 4
662
663`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
664`define ENET_MAC_IOB_WIDTH 4
665
666`define IOB_DRAM_WIDTH 4 // DRAM controller
667`define DRAM_IOB_WIDTH 4
668
669`define IOB_BSC_WIDTH 4 // BSC
670`define BSC_IOB_WIDTH 4
671
672`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
673`define SPI_IOB_WIDTH 4
674
675`define IOB_CLK_WIDTH 4 // clk unit
676`define CLK_IOB_WIDTH 4
677
678`define IOB_CLSP_WIDTH 4 // clk spine unit
679`define CLSP_IOB_WIDTH 4
680
681`define IOB_TAP_WIDTH 8 // TAP
682`define TAP_IOB_WIDTH 8
683
684
685//
686// CIOP UCB Buf ID Type
687// ====================
688//
689`define UCB_BID_CMP 2'b00
690`define UCB_BID_TAP 2'b01
691
692//
693// Interrupt Device ID
694// ===================
695//
696// Caution: DUMMY_DEV_ID has to be 9 bit wide
697// for fields to line up properly in the IOB.
698`define DUMMY_DEV_ID 9'h10 // 16
699`define UNCOR_ECC_DEV_ID 7'd17 // 17
700
701//
702// Soft Error related definitions
703// ==============================
704//
705`define COR_ECC_CNT_WIDTH 16
706
707
708//
709// CMP clock
710// =========
711//
712
713`define CMP_CLK_PERIOD 1333
714
715
716//
717// NRAM/IO Interface
718// =================
719//
720
721`define DRAM_CLK_PERIOD 6000
722
723`define NRAM_IO_DQ_WIDTH 32
724`define IO_NRAM_DQ_WIDTH 32
725
726`define NRAM_IO_ADDR_WIDTH 15
727`define NRAM_IO_BA_WIDTH 2
728
729
730//
731// NRAM/ENET Interface
732// ===================
733//
734
735`define NRAM_ENET_DATA_WIDTH 64
736`define ENET_NRAM_ADDR_WIDTH 20
737
738`define NRAM_DBG_DATA_WIDTH 40
739
740
741//
742// IO/FCRAM Interface
743// ==================
744//
745
746`define FCRAM_DATA1_HI 63
747`define FCRAM_DATA1_LO 32
748`define FCRAM_DATA0_HI 31
749`define FCRAM_DATA0_LO 0
750
751//
752// PCI Interface
753// ==================
754// Load/store size encodings
755// -------------------------
756// Size encoding
757// 000 - byte
758// 001 - half-word
759// 010 - word
760// 011 - double-word
761// 100 - quad
762`define LDST_SZ_BYTE 3'b000
763`define LDST_SZ_HALF_WORD 3'b001
764`define LDST_SZ_WORD 3'b010
765`define LDST_SZ_DOUBLE_WORD 3'b011
766`define LDST_SZ_QUAD 3'b100
767
768//
769// JBI<->SCTAG Interface
770// =======================
771// Outbound Header Format
772`define JBI_BTU_OUT_ADDR_LO 0
773`define JBI_BTU_OUT_ADDR_HI 42
774`define JBI_BTU_OUT_RSV0_LO 43
775`define JBI_BTU_OUT_RSV0_HI 43
776`define JBI_BTU_OUT_TYPE_LO 44
777`define JBI_BTU_OUT_TYPE_HI 48
778`define JBI_BTU_OUT_RSV1_LO 49
779`define JBI_BTU_OUT_RSV1_HI 51
780`define JBI_BTU_OUT_REPLACE_LO 52
781`define JBI_BTU_OUT_REPLACE_HI 56
782`define JBI_BTU_OUT_RSV2_LO 57
783`define JBI_BTU_OUT_RSV2_HI 59
784`define JBI_BTU_OUT_BTU_ID_LO 60
785`define JBI_BTU_OUT_BTU_ID_HI 71
786`define JBI_BTU_OUT_DATA_RTN 72
787`define JBI_BTU_OUT_RSV3_LO 73
788`define JBI_BTU_OUT_RSV3_HI 75
789`define JBI_BTU_OUT_CE 76
790`define JBI_BTU_OUT_RSV4_LO 77
791`define JBI_BTU_OUT_RSV4_HI 79
792`define JBI_BTU_OUT_UE 80
793`define JBI_BTU_OUT_RSV5_LO 81
794`define JBI_BTU_OUT_RSV5_HI 83
795`define JBI_BTU_OUT_DRAM 84
796`define JBI_BTU_OUT_RSV6_LO 85
797`define JBI_BTU_OUT_RSV6_HI 127
798
799// Inbound Header Format
800`define JBI_SCTAG_IN_ADDR_LO 0
801`define JBI_SCTAG_IN_ADDR_HI 39
802`define JBI_SCTAG_IN_SZ_LO 40
803`define JBI_SCTAG_IN_SZ_HI 42
804`define JBI_SCTAG_IN_RSV0 43
805`define JBI_SCTAG_IN_TAG_LO 44
806`define JBI_SCTAG_IN_TAG_HI 55
807`define JBI_SCTAG_IN_REQ_LO 56
808`define JBI_SCTAG_IN_REQ_HI 58
809`define JBI_SCTAG_IN_POISON 59
810`define JBI_SCTAG_IN_RSV1_LO 60
811`define JBI_SCTAG_IN_RSV1_HI 63
812
813`define JBI_SCTAG_REQ_WRI 3'b100
814`define JBI_SCTAG_REQ_WR8 3'b010
815`define JBI_SCTAG_REQ_RDD 3'b001
816`define JBI_SCTAG_REQ_WRI_BIT 2
817`define JBI_SCTAG_REQ_WR8_BIT 1
818`define JBI_SCTAG_REQ_RDD_BIT 0
819
820//
821// JBI->IOB Mondo Header Format
822// ============================
823//
824`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
825`define JBI_IOB_MONDO_RSV1_LO 13
826`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
827`define JBI_IOB_MONDO_TRG_LO 8
828`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
829`define JBI_IOB_MONDO_RSV0_LO 5
830`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
831`define JBI_IOB_MONDO_SRC_LO 0
832
833`define JBI_IOB_MONDO_RSV1_WIDTH 3
834`define JBI_IOB_MONDO_TRG_WIDTH 5
835`define JBI_IOB_MONDO_RSV0_WIDTH 3
836`define JBI_IOB_MONDO_SRC_WIDTH 5
837
838// JBI->IOB Mondo Bus Width/Cycle
839// ==============================
840// Cycle 1 Header[15:8]
841// Cycle 2 Header[ 7:0]
842// Cycle 3 J_AD[127:120]
843// Cycle 4 J_AD[119:112]
844// .....
845// Cycle 18 J_AD[ 7: 0]
846`define JBI_IOB_MONDO_BUS_WIDTH 8
847`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
848
849
850
851
852`define IQ_SIZE 8
853`define OQ_SIZE 12
854`define TAG_WIDTH 28
855`define TAG_WIDTH_LESS1 27
856`define TAG_WIDTHr 28r
857`define TAG_WIDTHc 28c
858`define TAG_WIDTH6 22
859`define TAG_WIDTH6r 22r
860`define TAG_WIDTH6c 22c
861
862
863`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
864
865// BS and SR 11/12/03 N2 Xbar Packet format change
866
867`define MBD_ECC_HI 105
868`define MBD_ECC_HI_PLUS1 106
869`define MBD_ECC_HI_PLUS5 110
870`define MBD_ECC_LO 100
871`define MBD_EVICT 99
872`define MBD_DEP 98
873`define MBD_TECC 97
874`define MBD_ENTRY_HI 96
875`define MBD_ENTRY_LO 93
876
877`define MBD_POISON 92
878`define MBD_RDMA_HI 91
879`define MBD_RDMA_LO 90
880`define MBD_RQ_HI 89
881`define MBD_RQ_LO 85
882`define MBD_NC 84
883`define MBD_RSVD 83
884`define MBD_CP_HI 82
885`define MBD_CP_LO 80
886`define MBD_TH_HI 79
887`define MBD_TH_LO 77
888`define MBD_BF_HI 76
889`define MBD_BF_LO 74
890`define MBD_WY_HI 73
891`define MBD_WY_LO 72
892`define MBD_SZ_HI 71
893`define MBD_SZ_LO 64
894`define MBD_DATA_HI 63
895`define MBD_DATA_LO 0
896
897// BS and SR 11/12/03 N2 Xbar Packet format change
898`define L2_FBF 40
899`define L2_MBF 39
900`define L2_SNP 38
901`define L2_CTRUE 37
902`define L2_EVICT 36
903`define L2_DEP 35
904`define L2_TECC 34
905`define L2_ENTRY_HI 33
906`define L2_ENTRY_LO 29
907
908`define L2_POISON 28
909`define L2_RDMA_HI 27
910`define L2_RDMA_LO 26
911// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
912`define L2_RQTYP_HI 25
913`define L2_RQTYP_LO 21
914`define L2_NC 20
915`define L2_RSVD 19
916`define L2_CPUID_HI 18
917`define L2_CPUID_LO 16
918`define L2_TID_HI 15
919`define L2_TID_LO 13
920`define L2_BUFID_HI 12
921`define L2_BUFID_LO 10
922`define L2_L1WY_HI 9
923`define L2_L1WY_LO 8
924`define L2_SZ_HI 7
925`define L2_SZ_LO 0
926
927
928`define ERR_MEU 63
929`define ERR_MEC 62
930`define ERR_RW 61
931`define ERR_ASYNC 60
932`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
933`define ERR_TID_LO 54
934`define ERR_LDAC 53
935`define ERR_LDAU 52
936`define ERR_LDWC 51
937`define ERR_LDWU 50
938`define ERR_LDRC 49
939`define ERR_LDRU 48
940`define ERR_LDSC 47
941`define ERR_LDSU 46
942`define ERR_LTC 45
943`define ERR_LRU 44
944`define ERR_LVU 43
945`define ERR_DAC 42
946`define ERR_DAU 41
947`define ERR_DRC 40
948`define ERR_DRU 39
949`define ERR_DSC 38
950`define ERR_DSU 37
951`define ERR_VEC 36
952`define ERR_VEU 35
953`define ERR_LVC 34
954`define ERR_SYN_HI 31
955`define ERR_SYN_LO 0
956
957
958
959`define ERR_MEND 51
960`define ERR_NDRW 50
961`define ERR_NDSP 49
962`define ERR_NDDM 48
963`define ERR_NDVCID_HI 45
964`define ERR_NDVCID_LO 40
965`define ERR_NDADR_HI 39
966`define ERR_NDADR_LO 4
967
968
969// Phase 2 : SIU Inteface and format change
970
971`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
972`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
973`define JBI_HDR_SZ4 23
974`define JBI_HDR_SZc 27c
975`define JBI_HDR_SZ4c 23c
976
977`define JBI_ADDR_LO 0
978`define JBI_ADDR_HI 7
979`define JBI_SZ_LO 8
980`define JBI_SZ_HI 15
981// `define JBI_RSVD 16 NOt used
982`define JBI_CTAG_LO 16
983`define JBI_CTAG_HI 23
984`define JBI_RQ_RD 24
985`define JBI_RQ_WR8 25
986`define JBI_RQ_WR64 26
987`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
988`define JBI_OPES_HI 30
989`define JBI_RQ_POISON 31
990`define JBI_ENTRY_LO 32
991`define JBI_ENTRY_HI 33
992
993// Phase 2 : SIU Inteface and format change
994// BS and SR 11/12/03 N2 Xbar Packet format change :
995`define JBINST_SZ_LO 0
996`define JBINST_SZ_HI 7
997// `define JBINST_RSVD 8 NOT used
998`define JBINST_CTAG_LO 8
999`define JBINST_CTAG_HI 15
1000`define JBINST_RQ_RD 16
1001`define JBINST_RQ_WR8 17
1002`define JBINST_RQ_WR64 18
1003`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
1004`define JBINST_OPES_HI 22
1005`define JBINST_ENTRY_LO 23
1006`define JBINST_ENTRY_HI 24
1007`define JBINST_POISON 25
1008
1009
1010`define ST_REQ_ST 1
1011`define LD_REQ_ST 2
1012`define IDLE 0
1013
1014
1015
1016module l2t_tagd_dp (
1017 tcu_pce_ov,
1018 tcu_aclk,
1019 tcu_bclk,
1020 tcu_scan_en,
1021 tcu_clk_stop,
1022 tcu_muxtest,
1023 tcu_dectest,
1024 arbadr_ncu_l2t_pm_n_dist,
1025 arbadr_2bnk_true_enbld_dist,
1026 arbadr_4bnk_true_enbld_dist,
1027 arbadr_dir_cam_addr_c3,
1028 arbadr_arbaddr_idx_c3,
1029 arbadr_arbdp_tagdata_px2,
1030 tagl_tag_quad0_c3,
1031 tagl_tag_quad1_c3,
1032 tagl_tag_quad2_c3,
1033 tagl_tag_quad3_c3,
1034 tagdp_tag_quad_muxsel_c3,
1035 tagd_dmo_evict_tag_c4,
1036 tagd_diag_data_c7,
1037 tagd_lkup_addr_c4,
1038 tagd_lkup_row_addr_dcd_c3,
1039 tagd_lkup_row_addr_icd_c3,
1040 tagd_mbdata_inst_tecc_c8,
1041 scan_out,
1042 tagd_lkup_tag_c1,
1043 arbadr_arbdp_tag_idx_px2,
1044 mbist_l2t_index,
1045 arb_tag_way_px2,
1046 mbist_l2t_dec_way,
1047 arb_tag_rd_px2,
1048 mbist_l2t_read,
1049 arb_tag_wr_px2,
1050 mbist_l2t_write,
1051 arbadr_tag_wrdata_px2,
1052 mbist_write_data,
1053 tagd_arbdp_tag_idx_px2_buf_1,
1054 tagd_arbdp_tag_idx_px2_buf_2,
1055 tagd_mbist_l2t_index_buf,
1056 tagd_arb_tag_way_px2_buf,
1057 tagd_mbist_l2t_dec_way_buf,
1058 tagd_arb_tag_rd_px2_buf,
1059 tagd_mbist_l2t_read_buf,
1060 tagd_arb_tag_wr_px2_buf,
1061 tagd_mbist_l2t_write_buf,
1062 tagd_tag_wrdata_px2_buf,
1063 tagd_mbist_write_data_buf,
1064 arb_evict_c3,
1065 l2clk,
1066 scan_in,
1067 tagd_evict_tag_c3,
1068 mbist_l2tag_fail);
1069wire stop;
1070wire pce_ov;
1071wire siclk;
1072wire soclk;
1073wire se;
1074wire muxtst;
1075wire test;
1076wire ff_wrdata_tag_c1_scanin;
1077wire ff_wrdata_tag_c1_scanout;
1078wire [29:6] tmp_lkup_tag_c1_unused;
1079wire arbadr_ncu_l2t_pm_n;
1080wire arbadr_4bnk_true_enbld;
1081wire arbadr_2bnk_true_enbld;
1082wire arb_evict_c3_n;
1083wire ff_tagd_lkup_addr_c4_scanin;
1084wire ff_tagd_lkup_addr_c4_scanout;
1085wire ff_tag_array_read_data_scanin;
1086wire ff_tag_array_read_data_scanout;
1087wire [27:0] tag_array_read_data;
1088wire [36:0] piped_vuad_data_input;
1089wire [7:0] tagd_mbist_write_data_r1;
1090wire [7:0] tagd_mbist_write_data_r2;
1091wire [7:0] tagd_mbist_write_data_r3;
1092wire mbist_l2t_read_r1;
1093wire mbist_l2t_read_r2;
1094wire mbist_l2t_read_r3;
1095wire mbist_l2tag_fail_unreg;
1096wire [7:0] tagd_mbist_write_data_r4;
1097wire mbist_l2t_read_r4;
1098wire [36:0] piped_vuad_data_output;
1099wire ff_piped_vuad0_scanin;
1100wire ff_piped_vuad0_scanout;
1101wire ff_piped_vuad1_scanin;
1102wire ff_piped_vuad1_scanout;
1103wire mbist_l2tag_fail_raw;
1104wire mbist_l2t_read_r4_n;
1105wire ff_tagd_evict_tag_c4_scanin;
1106wire ff_tagd_evict_tag_c4_scanout;
1107wire [27:0] tagd_evict_tag_c4;
1108wire ff_tagd_diag_data_c52_scanin;
1109wire ff_tagd_diag_data_c52_scanout;
1110wire ff_tagd_diag_data_c6_scanin;
1111wire ff_tagd_diag_data_c6_scanout;
1112wire ff_tagd_diag_data_c7_scanin;
1113wire ff_tagd_diag_data_c7_scanout;
1114wire ff_ecc_staging1_4_scanin;
1115wire ff_ecc_staging1_4_scanout;
1116wire ff_ecc_staging5_8_scanin;
1117wire ff_ecc_staging5_8_scanout;
1118
1119
1120 input tcu_pce_ov;
1121 input tcu_aclk;
1122 input tcu_bclk;
1123 input tcu_scan_en;
1124 input tcu_clk_stop;
1125 input tcu_muxtest;
1126 input tcu_dectest;
1127
1128input arbadr_ncu_l2t_pm_n_dist; // BS 03/25/04 for partial bank/core modes support
1129input arbadr_2bnk_true_enbld_dist;// BS 03/25/04 for partial bank/core modes support
1130input arbadr_4bnk_true_enbld_dist; // BS 03/25/04 for partial bank/core modes support
1131input [39:7] arbadr_dir_cam_addr_c3; // from arbaddr
1132input [10:0] arbadr_arbaddr_idx_c3; // from arbaddr
1133input [`TAG_WIDTH-1:6] arbadr_arbdp_tagdata_px2 ; // write data for tag.
1134
1135input [`TAG_WIDTH-1:0] tagl_tag_quad0_c3;
1136input [`TAG_WIDTH-1:0] tagl_tag_quad1_c3;
1137input [`TAG_WIDTH-1:0] tagl_tag_quad2_c3;
1138input [`TAG_WIDTH-1:0] tagl_tag_quad3_c3;
1139
1140input [3:0] tagdp_tag_quad_muxsel_c3 ; // to tagd
1141
1142output [`TAG_WIDTH-1:0] tagd_dmo_evict_tag_c4; // to wbdata.
1143output [`TAG_WIDTH-1:0] tagd_diag_data_c7; // to oque
1144
1145output [17:9] tagd_lkup_addr_c4; // to the directory, BS and SR 11/18/03 Reverse Directory change
1146output [2:0] tagd_lkup_row_addr_dcd_c3, tagd_lkup_row_addr_icd_c3;
1147
1148
1149output [5:0] tagd_mbdata_inst_tecc_c8; // to miss buffer data.
1150output scan_out;
1151
1152// tagd_lkup_tag_c1[`TAG_WIDTH-1:6] replaces wrdata_tag_c1;
1153
1154output [`TAG_WIDTH-1:1] tagd_lkup_tag_c1; // to tag.
1155
1156input [8:0] arbadr_arbdp_tag_idx_px2; // BS & SR 10/28/03
1157input [8:0] mbist_l2t_index; // BS & SR 10/28/03
1158
1159input [15:0] arb_tag_way_px2; // BS & SR 10/28/03
1160input [15:0] mbist_l2t_dec_way; // BS & SR 10/28/03
1161
1162input arb_tag_rd_px2;
1163input mbist_l2t_read;
1164
1165input arb_tag_wr_px2;
1166input mbist_l2t_write;
1167
1168input [27:0] arbadr_tag_wrdata_px2;
1169input [7:0] mbist_write_data;
1170
1171output [8:0] tagd_arbdp_tag_idx_px2_buf_1; // BS & SR 10/28/03
1172output [8:0] tagd_arbdp_tag_idx_px2_buf_2; // BS & SR 10/28/03
1173output [8:0] tagd_mbist_l2t_index_buf; // BS & SR 10/28/03
1174
1175output [15:0] tagd_arb_tag_way_px2_buf; // BS & SR 10/28/03
1176output [15:0] tagd_mbist_l2t_dec_way_buf; // BS & SR 10/28/03
1177
1178output tagd_arb_tag_rd_px2_buf;
1179output tagd_mbist_l2t_read_buf;
1180
1181output tagd_arb_tag_wr_px2_buf;
1182output tagd_mbist_l2t_write_buf;
1183
1184output [27:0] tagd_tag_wrdata_px2_buf;
1185output [7:0] tagd_mbist_write_data_buf;
1186input arb_evict_c3;
1187input l2clk;
1188input scan_in;
1189
1190output [27:0] tagd_evict_tag_c3;
1191
1192output mbist_l2tag_fail;
1193
1194assign stop = tcu_clk_stop;
1195assign pce_ov = tcu_pce_ov;
1196assign siclk = tcu_aclk;
1197assign soclk = tcu_bclk;
1198assign se = tcu_scan_en;
1199assign muxtst = tcu_muxtest;
1200assign test = tcu_dectest;
1201
1202
1203
1204wire [5:0] parity_c1;
1205wire [5:0] tag_acc_ecc_c1, tag_acc_ecc_c2, tag_acc_ecc_c3;
1206wire [5:0] tag_acc_ecc_c4, tag_acc_ecc_c5, tag_acc_ecc_c52, tag_acc_ecc_c6; // BS 03/11/04 extra cycle for mem access
1207wire [5:0] tag_acc_ecc_c7;
1208
1209wire [`TAG_WIDTH-1:0] tagd_evict_tag_c3, tagd_diag_data_c6, tagd_diag_data_c52; // to oque
1210wire [39:7] evict_addr_c3;
1211wire [21:0] tagd_evict_tag_orig_c3;
1212wire [39:7] lkup_addr_c3;
1213wire [`TAG_WIDTH-1:6] wrdata_tag_c1;
1214
1215
1216wire [8:0] lkup_addr_c3_tmp;
1217
1218//****************************************************************
1219// Changes start here.
1220
1221// reduced the width of this flop.
1222
1223l2t_tagd_dp_msff_macro__dmsff_32x__stack_22r__width_22 ff_wrdata_tag_c1 // int 5.0 changes
1224 (.din(arbadr_arbdp_tagdata_px2[`TAG_WIDTH-1:6]), .clk(l2clk),
1225 .scan_in(ff_wrdata_tag_c1_scanin),
1226 .scan_out(ff_wrdata_tag_c1_scanout),
1227 .dout(wrdata_tag_c1[`TAG_WIDTH-1:6]), .en(1'b1),
1228 .se(se),
1229 .siclk(siclk),
1230 .soclk(soclk),
1231 .pce_ov(pce_ov),
1232 .stop(stop)
1233);
1234
1235l2t_ecc24b_dp tagecc0
1236 (
1237 .din({2'b0,wrdata_tag_c1[`TAG_WIDTH-1:6]}),
1238 .dout(tmp_lkup_tag_c1_unused[29:6]),
1239 .parity(parity_c1[5:0])
1240 );
1241
1242assign tag_acc_ecc_c1 = { parity_c1[4:0], parity_c1[5] } ;
1243
1244
1245/////////////////////////////////////////////////////////
1246// To prevent the tag_acc_ecc_c1 bits from being
1247// part of the critical path in the tag compare operation,
1248// the overall parity bit P is not compared
1249//
1250// The check bits in tag_acc_ecc_c1 take 4 levels of XOR
1251// to compute whereas the overall parity P takes 5 levels.
1252//
1253// Not comparing P means that a hit could be signalled
1254// inspite of an error in the P bit. This requires the
1255// parity computation in C2 to account for this case
1256// and not cause any Miss Buffer insertions.
1257/////////////////////////////////////////////////////////
1258
1259assign tagd_lkup_tag_c1[`TAG_WIDTH-1:6] = wrdata_tag_c1[`TAG_WIDTH-1:6] ;
1260assign tagd_lkup_tag_c1[5:1] = tag_acc_ecc_c1[5:1] ;
1261
1262/////////////////////////////////////////////
1263// Directory lkup address
1264/////////////////////////////////////////////
1265
1266l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_22r__width_22 mux_tagd_evict_tag_orig_c3
1267 (.dout (tagd_evict_tag_orig_c3[21:0]) ,
1268 .din0(tagd_evict_tag_c3[`TAG_WIDTH-1:6]), // original idx , all banks enabled
1269 .din1({1'b0,tagd_evict_tag_c3[`TAG_WIDTH-1:7]}),
1270 // 1 bit shifted idx in case of 4 banks enabled
1271 .din2({2'b0,tagd_evict_tag_c3[`TAG_WIDTH-1:8]}),
1272 // 2 bit shifted idx in case of 2 banks enabled
1273 .sel0(arbadr_ncu_l2t_pm_n),
1274 .sel1(arbadr_4bnk_true_enbld),
1275 .sel2(arbadr_2bnk_true_enbld)
1276 );
1277
1278
1279assign evict_addr_c3[39:7] = { tagd_evict_tag_orig_c3[21:0],
1280 arbadr_arbaddr_idx_c3[10:0] } ;
1281
1282l2t_tagd_dp_inv_macro__width_1 arb_evict_c3_inv_slice (
1283 .dout (arb_evict_c3_n),
1284 .din (arb_evict_c3)
1285 );
1286
1287l2t_tagd_dp_mux_macro__mux_aonpe__ports_2__stack_33r__width_33 mux_cam_addr_c3
1288 ( .dout (lkup_addr_c3[39:7]),
1289 .din0(arbadr_dir_cam_addr_c3[39:7]), .din1(evict_addr_c3[39:7]),
1290 .sel0(arb_evict_c3_n), .sel1(arb_evict_c3));
1291
1292// BS 03/25/04 for partial bank/core modes support
1293// index shift before writing to Directory
1294
1295l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_10r__width_9 mux_lkup_addr_c3_tmp
1296 (.dout (lkup_addr_c3_tmp[8:0]) ,
1297 .din0(lkup_addr_c3[17:9]), // original idx , all banks enabled
1298 .din1(lkup_addr_c3[16:8]), // 1 bit shifted idx in case of 4 banks enabled
1299 .din2(lkup_addr_c3[15:7]), // 2 bit shifted idx in case of 2 banks enabled
1300 .sel0(arbadr_ncu_l2t_pm_n),
1301 .sel1(arbadr_4bnk_true_enbld),
1302 .sel2(arbadr_2bnk_true_enbld)
1303 );
1304
1305
1306l2t_tagd_dp_msff_macro__stack_9r__width_9 ff_tagd_lkup_addr_c4 // BS and SR 11/18/03 Reverse Directory change
1307 (.din(lkup_addr_c3_tmp[8:0]), .clk(l2clk),
1308 .scan_in(ff_tagd_lkup_addr_c4_scanin),
1309 .scan_out(ff_tagd_lkup_addr_c4_scanout),
1310 .dout(tagd_lkup_addr_c4[17:9]), .en(1'b1),
1311 .se(se),
1312 .siclk(siclk),
1313 .soclk(soclk),
1314 .pce_ov(pce_ov),
1315 .stop(stop)
1316);
1317
1318
1319/////////////////////////////////////////////
1320// Mbist logic
1321/////////////////////////////////////////////
1322
1323
1324l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tag_array_read_data
1325 (.din(tagd_evict_tag_c3[`TAG_WIDTH-1:0]), .clk(l2clk),
1326 .scan_in(ff_tag_array_read_data_scanin),
1327 .scan_out(ff_tag_array_read_data_scanout),
1328 .dout(tag_array_read_data[`TAG_WIDTH-1:0]), .en(1'b1),
1329 .se(se),
1330 .siclk(siclk),
1331 .soclk(soclk),
1332 .pce_ov(pce_ov),
1333 .stop(stop)
1334);
1335
1336//////////////////////////////////////////////////////////////////////////////////////////////////
1337//assign piped_vuad_data_input[36:0] = {mbist_write_data[7:0],tagd_mbist_write_data_r1[7:0],
1338// tagd_mbist_write_data_r2[7:0],tagd_mbist_write_data_r3[7:0],
1339// mbist_l2t_read,mbist_l2t_read_r1,mbist_l2t_read_r2,
1340// mbist_l2t_read_r3,mbist_l2tag_fail_unreg};
1341//
1342//assign piped_vuad_data_output[36:0] = {tagd_mbist_write_data_r1[7:0],tagd_mbist_write_data_r2[7:0],
1343// tagd_mbist_write_data_r3[7:0],tagd_mbist_write_data_r4[7:0],
1344// mbist_l2t_read_r1,mbist_l2t_read_r2,mbist_l2t_read_r3,
1345// mbist_l2t_read_r4,mbist_l2tag_fail};
1346//
1347//msff_macro ff_piped_vuad (width=37,stack=38r)
1348// (.din({mbist_write_data[7:0],tagd_mbist_write_data_r1[7:0],
1349// tagd_mbist_write_data_r2[7:0],tagd_mbist_write_data_r3[7:0],
1350// mbist_l2t_read,mbist_l2t_read_r1,mbist_l2t_read_r2,
1351// mbist_l2t_read_r3,mbist_l2tag_fail_unreg}),
1352// .scan_in(ff_piped_vuad_scanin),
1353// .scan_out(ff_piped_vuad_scanout),
1354// .clk(l2clk),
1355// .dout({tagd_mbist_write_data_r1[7:0],tagd_mbist_write_data_r2[7:0],
1356// tagd_mbist_write_data_r3[7:0],tagd_mbist_write_data_r4[7:0],
1357// mbist_l2t_read_r1,mbist_l2t_read_r2,mbist_l2t_read_r3,
1358// mbist_l2t_read_r4,mbist_l2tag_fail}),
1359// .en(1'b1),
1360// );
1361//////////////////////////////////////////////////////////////////////////////////////////////////
1362
1363assign piped_vuad_data_input[36:0] = {mbist_write_data[7:0],tagd_mbist_write_data_r1[7:0],
1364 tagd_mbist_write_data_r2[7:0],tagd_mbist_write_data_r3[7:0],
1365 mbist_l2t_read,mbist_l2t_read_r1,mbist_l2t_read_r2,
1366 mbist_l2t_read_r3,mbist_l2tag_fail_unreg};
1367
1368assign {tagd_mbist_write_data_r1[7:0],tagd_mbist_write_data_r2[7:0],
1369 tagd_mbist_write_data_r3[7:0],tagd_mbist_write_data_r4[7:0],
1370 mbist_l2t_read_r1,mbist_l2t_read_r2,mbist_l2t_read_r3,
1371 mbist_l2t_read_r4,mbist_l2tag_fail} = piped_vuad_data_output[36:0];
1372
1373
1374
1375l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_piped_vuad0
1376 (
1377 .scan_in(ff_piped_vuad0_scanin),
1378 .scan_out(ff_piped_vuad0_scanout),
1379 .din(piped_vuad_data_input[27:0]),
1380 .dout(piped_vuad_data_output[27:0]),
1381 .clk(l2clk),
1382 .en(1'b1),
1383 .se(se),
1384 .siclk(siclk),
1385 .soclk(soclk),
1386 .pce_ov(pce_ov),
1387 .stop(stop)
1388 );
1389
1390
1391l2t_tagd_dp_msff_macro__stack_10r__width_9 ff_piped_vuad1
1392 (
1393 .scan_in(ff_piped_vuad1_scanin),
1394 .scan_out(ff_piped_vuad1_scanout),
1395 .din(piped_vuad_data_input[36:28]),
1396 .dout(piped_vuad_data_output[36:28]),
1397 .clk(l2clk),
1398 .en(1'b1),
1399 .se(se),
1400 .siclk(siclk),
1401 .soclk(soclk),
1402 .pce_ov(pce_ov),
1403 .stop(stop)
1404 );
1405
1406
1407l2t_tagd_dp_cmp_macro__width_32 cmp_mbist_data
1408 (
1409 .dout (mbist_l2tag_fail_raw),
1410 .din0 ({4'b0,tag_array_read_data[`TAG_WIDTH-1:0]}),
1411 .din1 ({4'b0,tagd_mbist_write_data_r4[3:0],{3{tagd_mbist_write_data_r4[7:0]}}})
1412 );
1413
1414l2t_tagd_dp_inv_macro__width_1 inv_mbist_l2t_read_r4
1415 (
1416 .dout (mbist_l2t_read_r4_n),
1417 .din (mbist_l2t_read_r4)
1418 );
1419
1420l2t_tagd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 mux_l2tag_fail_mbist
1421 (
1422 .dout (mbist_l2tag_fail_unreg),
1423 .din0 (mbist_l2tag_fail_raw),
1424 .din1 (1'b1),
1425 .sel0 (mbist_l2t_read_r4),
1426 .sel1 (mbist_l2t_read_r4_n)
1427 );
1428
1429
1430/////////////////////////////////////////////
1431// LRU mux.
1432/////////////////////////////////////////////
1433
1434
1435l2t_tagd_dp_mux_macro__mux_pgpe__ports_4__stack_28r__width_28 mux_lru_tag // ATPG clean up
1436 (.dout (tagd_evict_tag_c3[`TAG_WIDTH-1:0]),
1437 .din0(tagl_tag_quad0_c3[`TAG_WIDTH-1:0]),
1438 .din1(tagl_tag_quad1_c3[`TAG_WIDTH-1:0]),
1439 .din2(tagl_tag_quad2_c3[`TAG_WIDTH-1:0]),
1440 .din3(tagl_tag_quad3_c3[`TAG_WIDTH-1:0]),
1441 .sel0(tagdp_tag_quad_muxsel_c3[0]),
1442 .sel1(tagdp_tag_quad_muxsel_c3[1]),
1443 .sel2(tagdp_tag_quad_muxsel_c3[2]),
1444 .muxtst(muxtst),
1445 .test(test)
1446 //.sel3(tagdp_tag_quad_muxsel_c3[3])
1447 );
1448
1449//////////////////////////////////////////////////////////////////////////////////////////////
1450// Tag Diagnostic data pipeline
1451//------------------------------------------------------------------------------------------
1452// C1 C2 C3 C4 C5 C6 C7 C8 C9
1453//------------------------------------------------------------------------------------------
1454// diag px2 rd tag prepare mux flop flop mux data ret.
1455// decode idx mux way mux out tag with
1456// sels and flop other
1457// diag data
1458//------------------------------------------------------------------------------------------
1459//////////////////////////////////////////////////////////////////////////////////////////////
1460
1461l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tagd_evict_tag_c4
1462 (.din(tagd_evict_tag_c3[`TAG_WIDTH-1:0]), .clk(l2clk),
1463 .scan_in(ff_tagd_evict_tag_c4_scanin),
1464 .scan_out(ff_tagd_evict_tag_c4_scanout),
1465 .dout(tagd_evict_tag_c4[`TAG_WIDTH-1:0]), .en(1'b1),
1466 .se(se),
1467 .siclk(siclk),
1468 .soclk(soclk),
1469 .pce_ov(pce_ov),
1470 .stop(stop)
1471);
1472
1473assign tagd_dmo_evict_tag_c4[`TAG_WIDTH-1:0] = tagd_evict_tag_c4[`TAG_WIDTH-1:0];
1474
1475l2t_tagd_dp_msff_macro__minbuff_1__stack_28r__width_28 ff_tagd_diag_data_c52
1476 (.din(tagd_evict_tag_c4[`TAG_WIDTH-1:0]), .clk(l2clk),
1477 .scan_in(ff_tagd_diag_data_c52_scanin),
1478 .scan_out(ff_tagd_diag_data_c52_scanout),
1479 .dout(tagd_diag_data_c52[`TAG_WIDTH-1:0]), .en(1'b1),
1480 .se(se),
1481 .siclk(siclk),
1482 .soclk(soclk),
1483 .pce_ov(pce_ov),
1484 .stop(stop)
1485);
1486
1487
1488l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tagd_diag_data_c6
1489 (.din(tagd_diag_data_c52[`TAG_WIDTH-1:0]), .clk(l2clk),
1490 .scan_in(ff_tagd_diag_data_c6_scanin),
1491 .scan_out(ff_tagd_diag_data_c6_scanout),
1492 .dout(tagd_diag_data_c6[`TAG_WIDTH-1:0]), .en(1'b1),
1493 .se(se),
1494 .siclk(siclk),
1495 .soclk(soclk),
1496 .pce_ov(pce_ov),
1497 .stop(stop)
1498);
1499
1500l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tagd_diag_data_c7
1501 (.din(tagd_diag_data_c6[`TAG_WIDTH-1:0]), .clk(l2clk),
1502 .scan_in(ff_tagd_diag_data_c7_scanin),
1503 .scan_out(ff_tagd_diag_data_c7_scanout),
1504 .dout(tagd_diag_data_c7[`TAG_WIDTH-1:0]), .en(1'b1),
1505 .se(se),
1506 .siclk(siclk),
1507 .soclk(soclk),
1508 .pce_ov(pce_ov),
1509 .stop(stop)
1510);
1511
1512
1513/////////////////////////////////////////////
1514// DP is 32 bits wide. The following
1515// logic and flops are pushed to one side.
1516/////////////////////////////////////////////
1517
1518
1519l2t_tagd_dp_msff_macro__stack_24r__width_24 ff_ecc_staging1_4
1520 (
1521 .scan_in(ff_ecc_staging1_4_scanin),
1522 .scan_out(ff_ecc_staging1_4_scanout),
1523 .din ({tag_acc_ecc_c1[5:0],tag_acc_ecc_c2[5:0],
1524 tag_acc_ecc_c3[5:0],tag_acc_ecc_c4[5:0]}),
1525 .dout ({tag_acc_ecc_c2[5:0],tag_acc_ecc_c3[5:0],
1526 tag_acc_ecc_c4[5:0],tag_acc_ecc_c5[5:0]}),
1527 .en ( 1'b1 ),
1528 .clk (l2clk),
1529 .se(se),
1530 .siclk(siclk),
1531 .soclk(soclk),
1532 .pce_ov(pce_ov),
1533 .stop(stop)
1534 );
1535
1536l2t_tagd_dp_msff_macro__stack_27r__width_27 ff_ecc_staging5_8
1537 (
1538 .scan_in(ff_ecc_staging5_8_scanin),
1539 .scan_out(ff_ecc_staging5_8_scanout),
1540 .din({arbadr_ncu_l2t_pm_n_dist,arbadr_2bnk_true_enbld_dist,arbadr_4bnk_true_enbld_dist,
1541 tag_acc_ecc_c5[5:0],tag_acc_ecc_c52[5:0],tag_acc_ecc_c6[5:0],tag_acc_ecc_c7[5:0]}),
1542 .dout({arbadr_ncu_l2t_pm_n,arbadr_2bnk_true_enbld,arbadr_4bnk_true_enbld,
1543 tag_acc_ecc_c52[5:0],tag_acc_ecc_c6[5:0],tag_acc_ecc_c7[5:0],tagd_mbdata_inst_tecc_c8[5:0]}),
1544 .en ( 1'b1 ),
1545 .clk (l2clk),
1546 .se(se),
1547 .siclk(siclk),
1548 .soclk(soclk),
1549 .pce_ov(pce_ov),
1550 .stop(stop)
1551 );
1552
1553assign tagd_lkup_row_addr_dcd_c3[2:0] = lkup_addr_c3[11:9];
1554assign tagd_lkup_row_addr_icd_c3[2:0] = lkup_addr_c3[11:9];
1555
1556
1557////////////////////////////////////////////////////////////
1558// The following signals need to be bufferred before
1559// the tag.
1560// INput pins are arranged on the top.
1561// Try to align with the data path cell placement information
1562// provided below.
1563////////////////////////////////////////////////////////////
1564
1565// repeater row1 ( 24 bits wide ) arranged as follows from left to right.
1566// index [0 ..... 9]
1567// way [11 .... 0 ]
1568// rd
1569// wr
1570//assign tagd_arbdp_tag_idx_px2_buf[8:0] = arbadr_arbdp_tag_idx_px2[8:0] ; // BS & SR 10/28/03
1571//assign tagd_arb_tag_way_px2_buf[15:0] = arb_tag_way_px2[15:0] ; // BS & SR 10/28/03
1572//assign tagd_arb_tag_rd_px2_buf = arb_tag_rd_px2;
1573//assign tagd_arb_tag_wr_px2_buf = arb_tag_wr_px2;
1574//
1575//buff_macro buff_tagd_arbdp_tag_idx_way_rd_wr_buf (width=36,dbuff=32x)
1576// (
1577// .dout ({tagd_arbdp_tag_idx_px2_buf_1[8:0],tagd_arbdp_tag_idx_px2_buf_2[8:0],tagd_arb_tag_way_px2_buf[15:0],
1578// tagd_arb_tag_rd_px2_buf,tagd_arb_tag_wr_px2_buf}),
1579// .din ({arbadr_arbdp_tag_idx_px2[8:0],arbadr_arbdp_tag_idx_px2[8:0],arb_tag_way_px2[15:0],
1580// arb_tag_rd_px2,arb_tag_wr_px2})
1581// );
1582
1583l2t_tagd_dp_buff_macro__dbuff_32x__width_18 buff_tagd_arbdp_tag_idx_way_rd_wr_buf
1584 (
1585 .dout ({tagd_arb_tag_way_px2_buf[15:0],tagd_arb_tag_rd_px2_buf,tagd_arb_tag_wr_px2_buf}),
1586 .din ({arb_tag_way_px2[15:0],arb_tag_rd_px2,arb_tag_wr_px2})
1587 );
1588
1589
1590l2t_tagd_dp_inv_macro__dinv_32x__width_18 inv_arbadr_arbdp_tag_idx_px2
1591 (
1592 .dout ({tagd_arbdp_tag_idx_px2_buf_1[8:0],tagd_arbdp_tag_idx_px2_buf_2[8:0]}),
1593 .din ({arbadr_arbdp_tag_idx_px2[8:0],arbadr_arbdp_tag_idx_px2[8:0]})
1594 );
1595
1596
1597// repeater row2 ( 24 bits wide ) arranged as follows from left to right.
1598// index [0 ..... 9]
1599// way [11 .... 0 ]
1600// rd
1601// wr
1602//assign tagd_mbist_l2t_index_buf[8:0] = mbist_l2t_index[8:0] ; // BS & SR 10/28/03
1603//assign tagd_mbist_l2t_dec_way_buf[15:0] = mbist_l2t_dec_way[15:0] ; // BS & SR 10/28/03
1604//assign tagd_mbist_l2t_read_buf = mbist_l2t_read;
1605//assign tagd_mbist_l2t_write_buf = mbist_l2t_write;
1606
1607l2t_tagd_dp_buff_macro__dbuff_16x__width_27 buff_mbist_tagd_arbdp_tag_idx_way_rd_wr_buf
1608 (
1609 .dout ({tagd_mbist_l2t_index_buf[8:0],tagd_mbist_l2t_dec_way_buf[15:0],
1610 tagd_mbist_l2t_read_buf,tagd_mbist_l2t_write_buf}),
1611 .din ({mbist_l2t_index[8:0],mbist_l2t_dec_way[15:0],
1612 mbist_l2t_read,mbist_l2t_write})
1613 );
1614
1615
1616
1617
1618
1619// repeater row 3 ( 28 bits wide ) arranged as follows from left to right.
1620// wr_data [0 .. 27]
1621
1622// assign tagd_tag_wrdata_px2_buf = arbadr_tag_wrdata_px2 ;
1623
1624l2t_tagd_dp_buff_macro__dbuff_16x__width_28 buff_tagd_tag_wrdata_px2_buf
1625 (
1626 .dout (tagd_tag_wrdata_px2_buf[27:0]),
1627 .din (arbadr_tag_wrdata_px2[27:0])
1628 );
1629
1630// repeater row 4 ( 8 bits wide ) arranged as follows from left to right.
1631
1632//assign tagd_mbist_write_data_buf = mbist_write_data;
1633
1634l2t_tagd_dp_buff_macro__dbuff_16x__width_8 buff_tagd_mbist_write_data_buf
1635 (
1636 .dout (tagd_mbist_write_data_buf[7:0]),
1637 .din (mbist_write_data[7:0])
1638 );
1639
1640
1641
1642// fixscan start:
1643assign ff_wrdata_tag_c1_scanin = scan_in ;
1644assign ff_tagd_lkup_addr_c4_scanin = ff_wrdata_tag_c1_scanout ;
1645assign ff_tag_array_read_data_scanin = ff_tagd_lkup_addr_c4_scanout;
1646assign ff_piped_vuad0_scanin = ff_tag_array_read_data_scanout;
1647assign ff_piped_vuad1_scanin = ff_piped_vuad0_scanout ;
1648assign ff_tagd_evict_tag_c4_scanin = ff_piped_vuad1_scanout ;
1649assign ff_tagd_diag_data_c52_scanin = ff_tagd_evict_tag_c4_scanout;
1650assign ff_tagd_diag_data_c6_scanin = ff_tagd_diag_data_c52_scanout;
1651assign ff_tagd_diag_data_c7_scanin = ff_tagd_diag_data_c6_scanout;
1652assign ff_ecc_staging1_4_scanin = ff_tagd_diag_data_c7_scanout;
1653assign ff_ecc_staging5_8_scanin = ff_ecc_staging1_4_scanout;
1654assign scan_out = ff_ecc_staging5_8_scanout;
1655// fixscan end:
1656endmodule
1657
1658
1659
1660
1661
1662
1663// any PARAMS parms go into naming of macro
1664
1665module l2t_tagd_dp_msff_macro__dmsff_32x__stack_22r__width_22 (
1666 din,
1667 clk,
1668 en,
1669 se,
1670 scan_in,
1671 siclk,
1672 soclk,
1673 pce_ov,
1674 stop,
1675 dout,
1676 scan_out);
1677wire l1clk;
1678wire siclk_out;
1679wire soclk_out;
1680wire [20:0] so;
1681
1682 input [21:0] din;
1683
1684
1685 input clk;
1686 input en;
1687 input se;
1688 input scan_in;
1689 input siclk;
1690 input soclk;
1691 input pce_ov;
1692 input stop;
1693
1694
1695
1696 output [21:0] dout;
1697
1698
1699 output scan_out;
1700
1701
1702
1703
1704cl_dp1_l1hdr_8x c0_0 (
1705.l2clk(clk),
1706.pce(en),
1707.aclk(siclk),
1708.bclk(soclk),
1709.l1clk(l1clk),
1710 .se(se),
1711 .pce_ov(pce_ov),
1712 .stop(stop),
1713 .siclk_out(siclk_out),
1714 .soclk_out(soclk_out)
1715);
1716dff #(22) d0_0 (
1717.l1clk(l1clk),
1718.siclk(siclk_out),
1719.soclk(soclk_out),
1720.d(din[21:0]),
1721.si({scan_in,so[20:0]}),
1722.so({so[20:0],scan_out}),
1723.q(dout[21:0])
1724);
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745endmodule
1746
1747
1748
1749
1750
1751
1752
1753
1754//
1755// xor macro for ports = 2,3
1756//
1757//
1758
1759
1760
1761
1762
1763module l2t_tagd_dp_xor_macro__dxor_8x__ports_3__width_1 (
1764 din0,
1765 din1,
1766 din2,
1767 dout);
1768 input [0:0] din0;
1769 input [0:0] din1;
1770 input [0:0] din2;
1771 output [0:0] dout;
1772
1773
1774
1775
1776
1777xor3 #(1) d0_0 (
1778.in0(din0[0:0]),
1779.in1(din1[0:0]),
1780.in2(din2[0:0]),
1781.out(dout[0:0])
1782);
1783
1784
1785
1786
1787
1788
1789
1790
1791endmodule
1792
1793
1794
1795
1796
1797//
1798// xor macro for ports = 2,3
1799//
1800//
1801
1802
1803
1804
1805
1806module l2t_tagd_dp_xor_macro__dxor_8x__ports_2__width_1 (
1807 din0,
1808 din1,
1809 dout);
1810 input [0:0] din0;
1811 input [0:0] din1;
1812 output [0:0] dout;
1813
1814
1815
1816
1817
1818xor2 #(1) d0_0 (
1819.in0(din0[0:0]),
1820.in1(din1[0:0]),
1821.out(dout[0:0])
1822);
1823
1824
1825
1826
1827
1828
1829
1830
1831endmodule
1832
1833
1834
1835
1836
1837//
1838// xor macro for ports = 2,3
1839//
1840//
1841
1842
1843
1844
1845
1846module l2t_tagd_dp_xor_macro__dxor_16x__ports_3__width_1 (
1847 din0,
1848 din1,
1849 din2,
1850 dout);
1851 input [0:0] din0;
1852 input [0:0] din1;
1853 input [0:0] din2;
1854 output [0:0] dout;
1855
1856
1857
1858
1859
1860xor3 #(1) d0_0 (
1861.in0(din0[0:0]),
1862.in1(din1[0:0]),
1863.in2(din2[0:0]),
1864.out(dout[0:0])
1865);
1866
1867
1868
1869
1870
1871
1872
1873
1874endmodule
1875
1876
1877
1878
1879
1880// general mux macro for pass-gate and and-or muxes with/wout priority encoders
1881// also for pass-gate with decoder
1882
1883
1884
1885
1886
1887// any PARAMS parms go into naming of macro
1888
1889module l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_22r__width_22 (
1890 din0,
1891 sel0,
1892 din1,
1893 sel1,
1894 din2,
1895 sel2,
1896 dout);
1897wire buffout0;
1898wire buffout1;
1899wire buffout2;
1900
1901 input [21:0] din0;
1902 input sel0;
1903 input [21:0] din1;
1904 input sel1;
1905 input [21:0] din2;
1906 input sel2;
1907 output [21:0] dout;
1908
1909
1910
1911
1912
1913cl_dp1_muxbuff3_8x c0_0 (
1914 .in0(sel0),
1915 .in1(sel1),
1916 .in2(sel2),
1917 .out0(buffout0),
1918 .out1(buffout1),
1919 .out2(buffout2)
1920);
1921mux3s #(22) d0_0 (
1922 .sel0(buffout0),
1923 .sel1(buffout1),
1924 .sel2(buffout2),
1925 .in0(din0[21:0]),
1926 .in1(din1[21:0]),
1927 .in2(din2[21:0]),
1928.dout(dout[21:0])
1929);
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943endmodule
1944
1945
1946//
1947// invert macro
1948//
1949//
1950
1951
1952
1953
1954
1955module l2t_tagd_dp_inv_macro__width_1 (
1956 din,
1957 dout);
1958 input [0:0] din;
1959 output [0:0] dout;
1960
1961
1962
1963
1964
1965
1966inv #(1) d0_0 (
1967.in(din[0:0]),
1968.out(dout[0:0])
1969);
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979endmodule
1980
1981
1982
1983
1984
1985// general mux macro for pass-gate and and-or muxes with/wout priority encoders
1986// also for pass-gate with decoder
1987
1988
1989
1990
1991
1992// any PARAMS parms go into naming of macro
1993
1994module l2t_tagd_dp_mux_macro__mux_aonpe__ports_2__stack_33r__width_33 (
1995 din0,
1996 sel0,
1997 din1,
1998 sel1,
1999 dout);
2000wire buffout0;
2001wire buffout1;
2002
2003 input [32:0] din0;
2004 input sel0;
2005 input [32:0] din1;
2006 input sel1;
2007 output [32:0] dout;
2008
2009
2010
2011
2012
2013cl_dp1_muxbuff2_8x c0_0 (
2014 .in0(sel0),
2015 .in1(sel1),
2016 .out0(buffout0),
2017 .out1(buffout1)
2018);
2019mux2s #(33) d0_0 (
2020 .sel0(buffout0),
2021 .sel1(buffout1),
2022 .in0(din0[32:0]),
2023 .in1(din1[32:0]),
2024.dout(dout[32:0])
2025);
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039endmodule
2040
2041
2042// general mux macro for pass-gate and and-or muxes with/wout priority encoders
2043// also for pass-gate with decoder
2044
2045
2046
2047
2048
2049// any PARAMS parms go into naming of macro
2050
2051module l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_10r__width_9 (
2052 din0,
2053 sel0,
2054 din1,
2055 sel1,
2056 din2,
2057 sel2,
2058 dout);
2059wire buffout0;
2060wire buffout1;
2061wire buffout2;
2062
2063 input [8:0] din0;
2064 input sel0;
2065 input [8:0] din1;
2066 input sel1;
2067 input [8:0] din2;
2068 input sel2;
2069 output [8:0] dout;
2070
2071
2072
2073
2074
2075cl_dp1_muxbuff3_8x c0_0 (
2076 .in0(sel0),
2077 .in1(sel1),
2078 .in2(sel2),
2079 .out0(buffout0),
2080 .out1(buffout1),
2081 .out2(buffout2)
2082);
2083mux3s #(9) d0_0 (
2084 .sel0(buffout0),
2085 .sel1(buffout1),
2086 .sel2(buffout2),
2087 .in0(din0[8:0]),
2088 .in1(din1[8:0]),
2089 .in2(din2[8:0]),
2090.dout(dout[8:0])
2091);
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105endmodule
2106
2107
2108
2109
2110
2111
2112// any PARAMS parms go into naming of macro
2113
2114module l2t_tagd_dp_msff_macro__stack_9r__width_9 (
2115 din,
2116 clk,
2117 en,
2118 se,
2119 scan_in,
2120 siclk,
2121 soclk,
2122 pce_ov,
2123 stop,
2124 dout,
2125 scan_out);
2126wire l1clk;
2127wire siclk_out;
2128wire soclk_out;
2129wire [7:0] so;
2130
2131 input [8:0] din;
2132
2133
2134 input clk;
2135 input en;
2136 input se;
2137 input scan_in;
2138 input siclk;
2139 input soclk;
2140 input pce_ov;
2141 input stop;
2142
2143
2144
2145 output [8:0] dout;
2146
2147
2148 output scan_out;
2149
2150
2151
2152
2153cl_dp1_l1hdr_8x c0_0 (
2154.l2clk(clk),
2155.pce(en),
2156.aclk(siclk),
2157.bclk(soclk),
2158.l1clk(l1clk),
2159 .se(se),
2160 .pce_ov(pce_ov),
2161 .stop(stop),
2162 .siclk_out(siclk_out),
2163 .soclk_out(soclk_out)
2164);
2165dff #(9) d0_0 (
2166.l1clk(l1clk),
2167.siclk(siclk_out),
2168.soclk(soclk_out),
2169.d(din[8:0]),
2170.si({scan_in,so[7:0]}),
2171.so({so[7:0],scan_out}),
2172.q(dout[8:0])
2173);
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194endmodule
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208// any PARAMS parms go into naming of macro
2209
2210module l2t_tagd_dp_msff_macro__stack_28r__width_28 (
2211 din,
2212 clk,
2213 en,
2214 se,
2215 scan_in,
2216 siclk,
2217 soclk,
2218 pce_ov,
2219 stop,
2220 dout,
2221 scan_out);
2222wire l1clk;
2223wire siclk_out;
2224wire soclk_out;
2225wire [26:0] so;
2226
2227 input [27:0] din;
2228
2229
2230 input clk;
2231 input en;
2232 input se;
2233 input scan_in;
2234 input siclk;
2235 input soclk;
2236 input pce_ov;
2237 input stop;
2238
2239
2240
2241 output [27:0] dout;
2242
2243
2244 output scan_out;
2245
2246
2247
2248
2249cl_dp1_l1hdr_8x c0_0 (
2250.l2clk(clk),
2251.pce(en),
2252.aclk(siclk),
2253.bclk(soclk),
2254.l1clk(l1clk),
2255 .se(se),
2256 .pce_ov(pce_ov),
2257 .stop(stop),
2258 .siclk_out(siclk_out),
2259 .soclk_out(soclk_out)
2260);
2261dff #(28) d0_0 (
2262.l1clk(l1clk),
2263.siclk(siclk_out),
2264.soclk(soclk_out),
2265.d(din[27:0]),
2266.si({scan_in,so[26:0]}),
2267.so({so[26:0],scan_out}),
2268.q(dout[27:0])
2269);
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290endmodule
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304// any PARAMS parms go into naming of macro
2305
2306module l2t_tagd_dp_msff_macro__stack_10r__width_9 (
2307 din,
2308 clk,
2309 en,
2310 se,
2311 scan_in,
2312 siclk,
2313 soclk,
2314 pce_ov,
2315 stop,
2316 dout,
2317 scan_out);
2318wire l1clk;
2319wire siclk_out;
2320wire soclk_out;
2321wire [7:0] so;
2322
2323 input [8:0] din;
2324
2325
2326 input clk;
2327 input en;
2328 input se;
2329 input scan_in;
2330 input siclk;
2331 input soclk;
2332 input pce_ov;
2333 input stop;
2334
2335
2336
2337 output [8:0] dout;
2338
2339
2340 output scan_out;
2341
2342
2343
2344
2345cl_dp1_l1hdr_8x c0_0 (
2346.l2clk(clk),
2347.pce(en),
2348.aclk(siclk),
2349.bclk(soclk),
2350.l1clk(l1clk),
2351 .se(se),
2352 .pce_ov(pce_ov),
2353 .stop(stop),
2354 .siclk_out(siclk_out),
2355 .soclk_out(soclk_out)
2356);
2357dff #(9) d0_0 (
2358.l1clk(l1clk),
2359.siclk(siclk_out),
2360.soclk(soclk_out),
2361.d(din[8:0]),
2362.si({scan_in,so[7:0]}),
2363.so({so[7:0],scan_out}),
2364.q(dout[8:0])
2365);
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386endmodule
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396//
2397// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
2398//
2399//
2400
2401
2402
2403
2404
2405module l2t_tagd_dp_cmp_macro__width_32 (
2406 din0,
2407 din1,
2408 dout);
2409 input [31:0] din0;
2410 input [31:0] din1;
2411 output dout;
2412
2413
2414
2415
2416
2417
2418cmp #(32) m0_0 (
2419.in0(din0[31:0]),
2420.in1(din1[31:0]),
2421.out(dout)
2422);
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433endmodule
2434
2435
2436
2437
2438
2439// general mux macro for pass-gate and and-or muxes with/wout priority encoders
2440// also for pass-gate with decoder
2441
2442
2443
2444
2445
2446// any PARAMS parms go into naming of macro
2447
2448module l2t_tagd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 (
2449 din0,
2450 sel0,
2451 din1,
2452 sel1,
2453 dout);
2454wire buffout0;
2455wire buffout1;
2456
2457 input [0:0] din0;
2458 input sel0;
2459 input [0:0] din1;
2460 input sel1;
2461 output [0:0] dout;
2462
2463
2464
2465
2466
2467cl_dp1_muxbuff2_8x c0_0 (
2468 .in0(sel0),
2469 .in1(sel1),
2470 .out0(buffout0),
2471 .out1(buffout1)
2472);
2473mux2s #(1) d0_0 (
2474 .sel0(buffout0),
2475 .sel1(buffout1),
2476 .in0(din0[0:0]),
2477 .in1(din1[0:0]),
2478.dout(dout[0:0])
2479);
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493endmodule
2494
2495
2496// general mux macro for pass-gate and and-or muxes with/wout priority encoders
2497// also for pass-gate with decoder
2498
2499
2500
2501
2502
2503// any PARAMS parms go into naming of macro
2504
2505module l2t_tagd_dp_mux_macro__mux_pgpe__ports_4__stack_28r__width_28 (
2506 din0,
2507 din1,
2508 din2,
2509 din3,
2510 sel0,
2511 sel1,
2512 sel2,
2513 muxtst,
2514 test,
2515 dout);
2516wire psel0;
2517wire psel1;
2518wire psel2;
2519wire psel3;
2520
2521 input [27:0] din0;
2522 input [27:0] din1;
2523 input [27:0] din2;
2524 input [27:0] din3;
2525 input sel0;
2526 input sel1;
2527 input sel2;
2528 input muxtst;
2529 input test;
2530 output [27:0] dout;
2531
2532
2533
2534
2535
2536cl_dp1_penc4_8x c0_0 (
2537 .sel0(sel0),
2538 .sel1(sel1),
2539 .sel2(sel2),
2540 .psel0(psel0),
2541 .psel1(psel1),
2542 .psel2(psel2),
2543 .psel3(psel3),
2544 .test(test)
2545);
2546
2547mux4 #(28) d0_0 (
2548 .sel0(psel0),
2549 .sel1(psel1),
2550 .sel2(psel2),
2551 .sel3(psel3),
2552 .in0(din0[27:0]),
2553 .in1(din1[27:0]),
2554 .in2(din2[27:0]),
2555 .in3(din3[27:0]),
2556.dout(dout[27:0]),
2557 .muxtst(muxtst)
2558);
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572endmodule
2573
2574
2575
2576
2577
2578
2579// any PARAMS parms go into naming of macro
2580
2581module l2t_tagd_dp_msff_macro__minbuff_1__stack_28r__width_28 (
2582 din,
2583 clk,
2584 en,
2585 se,
2586 scan_in,
2587 siclk,
2588 soclk,
2589 pce_ov,
2590 stop,
2591 dout,
2592 scan_out);
2593wire l1clk;
2594wire siclk_out;
2595wire soclk_out;
2596wire [26:0] so;
2597
2598 input [27:0] din;
2599
2600
2601 input clk;
2602 input en;
2603 input se;
2604 input scan_in;
2605 input siclk;
2606 input soclk;
2607 input pce_ov;
2608 input stop;
2609
2610
2611
2612 output [27:0] dout;
2613
2614
2615 output scan_out;
2616
2617
2618
2619
2620cl_dp1_l1hdr_8x c0_0 (
2621.l2clk(clk),
2622.pce(en),
2623.aclk(siclk),
2624.bclk(soclk),
2625.l1clk(l1clk),
2626 .se(se),
2627 .pce_ov(pce_ov),
2628 .stop(stop),
2629 .siclk_out(siclk_out),
2630 .soclk_out(soclk_out)
2631);
2632dff #(28) d0_0 (
2633.l1clk(l1clk),
2634.siclk(siclk_out),
2635.soclk(soclk_out),
2636.d(din[27:0]),
2637.si({scan_in,so[26:0]}),
2638.so({so[26:0],scan_out}),
2639.q(dout[27:0])
2640);
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661endmodule
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675// any PARAMS parms go into naming of macro
2676
2677module l2t_tagd_dp_msff_macro__stack_24r__width_24 (
2678 din,
2679 clk,
2680 en,
2681 se,
2682 scan_in,
2683 siclk,
2684 soclk,
2685 pce_ov,
2686 stop,
2687 dout,
2688 scan_out);
2689wire l1clk;
2690wire siclk_out;
2691wire soclk_out;
2692wire [22:0] so;
2693
2694 input [23:0] din;
2695
2696
2697 input clk;
2698 input en;
2699 input se;
2700 input scan_in;
2701 input siclk;
2702 input soclk;
2703 input pce_ov;
2704 input stop;
2705
2706
2707
2708 output [23:0] dout;
2709
2710
2711 output scan_out;
2712
2713
2714
2715
2716cl_dp1_l1hdr_8x c0_0 (
2717.l2clk(clk),
2718.pce(en),
2719.aclk(siclk),
2720.bclk(soclk),
2721.l1clk(l1clk),
2722 .se(se),
2723 .pce_ov(pce_ov),
2724 .stop(stop),
2725 .siclk_out(siclk_out),
2726 .soclk_out(soclk_out)
2727);
2728dff #(24) d0_0 (
2729.l1clk(l1clk),
2730.siclk(siclk_out),
2731.soclk(soclk_out),
2732.d(din[23:0]),
2733.si({scan_in,so[22:0]}),
2734.so({so[22:0],scan_out}),
2735.q(dout[23:0])
2736);
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757endmodule
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771// any PARAMS parms go into naming of macro
2772
2773module l2t_tagd_dp_msff_macro__stack_27r__width_27 (
2774 din,
2775 clk,
2776 en,
2777 se,
2778 scan_in,
2779 siclk,
2780 soclk,
2781 pce_ov,
2782 stop,
2783 dout,
2784 scan_out);
2785wire l1clk;
2786wire siclk_out;
2787wire soclk_out;
2788wire [25:0] so;
2789
2790 input [26:0] din;
2791
2792
2793 input clk;
2794 input en;
2795 input se;
2796 input scan_in;
2797 input siclk;
2798 input soclk;
2799 input pce_ov;
2800 input stop;
2801
2802
2803
2804 output [26:0] dout;
2805
2806
2807 output scan_out;
2808
2809
2810
2811
2812cl_dp1_l1hdr_8x c0_0 (
2813.l2clk(clk),
2814.pce(en),
2815.aclk(siclk),
2816.bclk(soclk),
2817.l1clk(l1clk),
2818 .se(se),
2819 .pce_ov(pce_ov),
2820 .stop(stop),
2821 .siclk_out(siclk_out),
2822 .soclk_out(soclk_out)
2823);
2824dff #(27) d0_0 (
2825.l1clk(l1clk),
2826.siclk(siclk_out),
2827.soclk(soclk_out),
2828.d(din[26:0]),
2829.si({scan_in,so[25:0]}),
2830.so({so[25:0],scan_out}),
2831.q(dout[26:0])
2832);
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853endmodule
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863//
2864// buff macro
2865//
2866//
2867
2868
2869
2870
2871
2872module l2t_tagd_dp_buff_macro__dbuff_32x__width_18 (
2873 din,
2874 dout);
2875 input [17:0] din;
2876 output [17:0] dout;
2877
2878
2879
2880
2881
2882
2883buff #(18) d0_0 (
2884.in(din[17:0]),
2885.out(dout[17:0])
2886);
2887
2888
2889
2890
2891
2892
2893
2894
2895endmodule
2896
2897
2898
2899
2900
2901//
2902// invert macro
2903//
2904//
2905
2906
2907
2908
2909
2910module l2t_tagd_dp_inv_macro__dinv_32x__width_18 (
2911 din,
2912 dout);
2913 input [17:0] din;
2914 output [17:0] dout;
2915
2916
2917
2918
2919
2920
2921inv #(18) d0_0 (
2922.in(din[17:0]),
2923.out(dout[17:0])
2924);
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934endmodule
2935
2936
2937
2938
2939
2940//
2941// buff macro
2942//
2943//
2944
2945
2946
2947
2948
2949module l2t_tagd_dp_buff_macro__dbuff_16x__width_27 (
2950 din,
2951 dout);
2952 input [26:0] din;
2953 output [26:0] dout;
2954
2955
2956
2957
2958
2959
2960buff #(27) d0_0 (
2961.in(din[26:0]),
2962.out(dout[26:0])
2963);
2964
2965
2966
2967
2968
2969
2970
2971
2972endmodule
2973
2974
2975
2976
2977
2978//
2979// buff macro
2980//
2981//
2982
2983
2984
2985
2986
2987module l2t_tagd_dp_buff_macro__dbuff_16x__width_28 (
2988 din,
2989 dout);
2990 input [27:0] din;
2991 output [27:0] dout;
2992
2993
2994
2995
2996
2997
2998buff #(28) d0_0 (
2999.in(din[27:0]),
3000.out(dout[27:0])
3001);
3002
3003
3004
3005
3006
3007
3008
3009
3010endmodule
3011
3012
3013
3014
3015
3016//
3017// buff macro
3018//
3019//
3020
3021
3022
3023
3024
3025module l2t_tagd_dp_buff_macro__dbuff_16x__width_8 (
3026 din,
3027 dout);
3028 input [7:0] din;
3029 output [7:0] dout;
3030
3031
3032
3033
3034
3035
3036buff #(8) d0_0 (
3037.in(din[7:0]),
3038.out(dout[7:0])
3039);
3040
3041
3042
3043
3044
3045
3046
3047
3048endmodule
3049
3050
3051
3052
Full OpenSPARC design & verification tarball including full HDL.