Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / l2t / synopsys / script / user_cfg.scr

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: user_cfg.scr
# Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
# 4150 Network Circle, Santa Clara, California 95054, U.S.A.
#
# * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
#
# For the avoidance of doubt, and except that if any non-GPL license 
# choice is available it will apply instead, Sun elects to use only 
# the General Public License version 2 (GPLv2) at this time for any 
# software where a choice of GPL license versions is made 
# available with the language indicating that GPLv2 or any later version 
# may be used, or where a choice of which version of the GPL is applied is 
# otherwise unspecified. 
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# Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
# CA 95054 USA or visit www.sun.com if you need additional information or 
# have any questions. 
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# ========== Copyright Header End ============================================
source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_u1lvt/cl_u1lvt.behV
libs/cl/cl_u1gb/cl_u1gb.behV
libs/cl/cl_dp1lvt/cl_dp1lvt.behV
libs/cl/cl_sc1lvt/cl_sc1lvt.behV
libs/cl/cl_sc1gb/cl_sc1gb.behV
libs/cl/cl_mc1/cl_mc1.v

libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v
libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2t_cmp_cust/rtl/n2_clk_l2t_cmp_cust.v

libs/n2sram/cams/n2_com_cm_64x64_cust_l/n2_com_cm_64x64_cust/rtl/n2_com_cm_64x64_cust.v
libs/n2sram/cams/n2_com_cm_32x40_cust_l/n2_com_cm_32x40_cust/rtl/n2_com_cm_32x40_cust.v
libs/n2sram/cams/n2_com_cm_8x40_cust_l/n2_com_cm_8x40_cust/rtl/n2_com_cm_8x40_cust.v
libs/n2sram/dp/n2_l2t_dp_32x128_cust_l/n2_l2t_dp_32x128_cust/rtl/n2_l2t_dp_32x128_cust.v
libs/n2sram/dp/n2_l2t_dp_16x160_cust_l/n2_l2t_dp_16x160_cust/rtl/n2_l2t_dp_16x160_cust.v
libs/n2sram/dp/n2_l2t_dp_32x160_cust_l/n2_l2t_dp_32x160_cust/rtl/n2_l2t_dp_32x160_cust.v
libs/tisram/soc/n2_l2t_sp_28kb_cust_l/n2_l2t_sp_28kb_cust/rtl/n2_l2t_sp_28kb_cust.v

libs/clk/rtl/clkgen_l2t_cmp.v
libs/rtl/n2_efuhdr1_ctl.v

design/sys/iop/l2t/rtl/l2t_arb_ctl.v
design/sys/iop/l2t/rtl/l2t_arbadr_dp.v
design/sys/iop/l2t/rtl/l2t_arbdat_dp.v
design/sys/iop/l2t/rtl/l2t_arbdec_dp.v
design/sys/iop/l2t/rtl/l2t_csr_ctl.v
design/sys/iop/l2t/rtl/l2t_csreg_ctl.v
design/sys/iop/l2t/rtl/l2t_decc_dp.v
design/sys/iop/l2t/rtl/l2t_deccck_ctl.v
design/sys/iop/l2t/rtl/l2t_dir_ctl.v
design/sys/iop/l2t/rtl/l2t_dirbuf_ctl.v
design/sys/iop/l2t/rtl/l2t_dirout_dp.v
design/sys/iop/l2t/rtl/l2t_dirrep_ctl.v
design/sys/iop/l2t/rtl/l2t_dirtop_ctl.v
design/sys/iop/l2t/rtl/l2t_dirvec_ctl.v
design/sys/iop/l2t/rtl/l2t_dmo_dp.v
design/sys/iop/l2t/rtl/l2t_dmorpt_dp.v
design/sys/iop/l2t/rtl/l2t_ecc24b_dp.v
design/sys/iop/l2t/rtl/l2t_ecc30b_dp.v
design/sys/iop/l2t/rtl/l2t_ecc39_dp.v
design/sys/iop/l2t/rtl/l2t_ecc39a_dp.v
design/sys/iop/l2t/rtl/l2t_evctag_dp.v
design/sys/iop/l2t/rtl/l2t_ffrpt_dp.v
design/sys/iop/l2t/rtl/l2t_filbuf_ctl.v
design/sys/iop/l2t/rtl/l2t_iqu_ctl.v
design/sys/iop/l2t/rtl/l2t_ique_dp.v
design/sys/iop/l2t/rtl/l2t_l2drpt_dp.v
design/sys/iop/l2t/rtl/l2t_mb0_ctl.v
design/sys/iop/l2t/rtl/l2t_mb2_ctl.v
design/sys/iop/l2t/rtl/l2t_mbist_ctl.v
design/sys/iop/l2t/rtl/l2t_misbuf_ctl.v
design/sys/iop/l2t/rtl/l2t_mrep4x6_dp.v
design/sys/iop/l2t/rtl/l2t_mrep8x16_dp.v
design/sys/iop/l2t/rtl/l2t_mrep16x8_dp.v
design/sys/iop/l2t/rtl/l2t_mrep2x64_dp.v
design/sys/iop/l2t/rtl/l2t_mrep32x3_dp.v
design/sys/iop/l2t/rtl/l2t_oqu_ctl.v
design/sys/iop/l2t/rtl/l2t_oque_dp.v
design/sys/iop/l2t/rtl/l2t_pgen32b_dp.v
design/sys/iop/l2t/rtl/l2t_rdmarpt_dp.v
design/sys/iop/l2t/rtl/l2t_rdmat_ctl.v
design/sys/iop/l2t/rtl/l2t_rep_dp.v
design/sys/iop/l2t/rtl/l2t_shdwscn_dp.v
design/sys/iop/l2t/rtl/l2t_snp_ctl.v
design/sys/iop/l2t/rtl/l2t_snpd_dp.v
design/sys/iop/l2t/rtl/l2t_tag_ctl.v
design/sys/iop/l2t/rtl/l2t_tagd_dp.v
design/sys/iop/l2t/rtl/l2t_tagdp_ctl.v
design/sys/iop/l2t/rtl/l2t_taghdr_ctl.v
design/sys/iop/l2t/rtl/l2t_tagl_dp.v
design/sys/iop/l2t/rtl/l2t_usaloc_dp.v
design/sys/iop/l2t/rtl/l2t_vlddir_dp.v
design/sys/iop/l2t/rtl/l2t_vuad_ctl.v
design/sys/iop/l2t/rtl/l2t_vuadcl_dp.v
design/sys/iop/l2t/rtl/l2t_vuadio_dp.v
design/sys/iop/l2t/rtl/l2t_vuadpm_dp.v
design/sys/iop/l2t/rtl/l2t_wbuf_ctl.v
design/sys/iop/l2t/rtl/l2t_wbufrpt_dp.v
design/sys/iop/l2t/rtl/l2t.v
}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module l2t

set include_paths {\
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {\
n2_com_cm_32x40_cust \
n2_com_cm_8x40_cust \
n2_com_cm_8x40_cust_array \
n2_com_cm_64x64_cust \
n2_l2t_dp_32x128_cust \
n2_l2t_dp_32x160_cust \
n2_l2t_dp_16x160_cust \
n2_l2t_sp_28kb_cust \
n2_l2t_array \
n2_l2t_sr_latch \
}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk gclk
set default_clk_freq  1400
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { gclk          1400.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}