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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / mcu / rtl / mcu_fbd_dp.v
CommitLineData
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcu_fbd_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module mcu_fbd_dp (
36 fbd_data,
37 fbd_elect_idle,
38 fbd_frame_lock,
39 fbd_testfail,
40 fsr_data,
41 fsr_stsrx_losdtct,
42 fsr_stsrx_sync,
43 fsr_stsrx_testfail,
44 fsr_rxbclk,
45 fdout_frame_lock,
46 fbdic_enable_sync_count,
47 fdout_rptr0,
48 fdout_rptr1,
49 fdout_rptr2,
50 fdout_rptr3,
51 fdout_rptr4,
52 fdout_rptr5,
53 fdout_rptr6,
54 fdout_rptr7,
55 fdout_rptr8,
56 fdout_rptr9,
57 fdout_rptr10,
58 fdout_rptr11,
59 fdout_rptr12,
60 fdout_rptr13,
61 drl2clk,
62 tcu_pce_ov,
63 tcu_aclk,
64 tcu_bclk,
65 tcu_scan_en,
66 scan_in,
67 scan_out,
68 tcu_mcu_fbd_clk_stop,
69 tcu_mcu_testmode,
70 tcu_atpg_mode);
71wire rdbuf0_scanin;
72wire rdbuf0_scanout;
73wire rdbuf1_scanin;
74wire rdbuf1_scanout;
75wire rdbuf2_scanin;
76wire rdbuf2_scanout;
77wire rdbuf3_scanin;
78wire rdbuf3_scanout;
79wire rdbuf4_scanin;
80wire rdbuf4_scanout;
81wire rdbuf5_scanin;
82wire rdbuf5_scanout;
83wire rdbuf6_scanin;
84wire rdbuf6_scanout;
85wire rdbuf7_scanin;
86wire rdbuf7_scanout;
87wire rdbuf8_scanin;
88wire rdbuf8_scanout;
89wire rdbuf9_scanin;
90wire rdbuf9_scanout;
91wire rdbuf10_scanin;
92wire rdbuf10_scanout;
93wire rdbuf11_scanin;
94wire rdbuf11_scanout;
95wire rdbuf12_scanin;
96wire rdbuf12_scanout;
97wire rdbuf13_scanin;
98wire rdbuf13_scanout;
99
100
101output [167:0] fbd_data;
102output [13:0] fbd_elect_idle;
103output [13:0] fbd_frame_lock;
104output [13:0] fbd_testfail;
105
106input [167:0] fsr_data;
107input [13:0] fsr_stsrx_losdtct;
108input [13:0] fsr_stsrx_sync;
109input [13:0] fsr_stsrx_testfail;
110input [13:0] fsr_rxbclk;
111input [13:0] fdout_frame_lock;
112
113input fbdic_enable_sync_count;
114
115input [1:0] fdout_rptr0;
116input [1:0] fdout_rptr1;
117input [1:0] fdout_rptr2;
118input [1:0] fdout_rptr3;
119input [1:0] fdout_rptr4;
120input [1:0] fdout_rptr5;
121input [1:0] fdout_rptr6;
122input [1:0] fdout_rptr7;
123input [1:0] fdout_rptr8;
124input [1:0] fdout_rptr9;
125input [1:0] fdout_rptr10;
126input [1:0] fdout_rptr11;
127input [1:0] fdout_rptr12;
128input [1:0] fdout_rptr13;
129
130input drl2clk;
131input tcu_pce_ov;
132input tcu_aclk;
133input tcu_bclk;
134input tcu_scan_en;
135input scan_in;
136output scan_out;
137
138input tcu_mcu_fbd_clk_stop;
139input tcu_mcu_testmode;
140input tcu_atpg_mode;
141
142// Northbound SERDES
143
144mcu_frdbuf_dp frdbuf0 (
145 .scan_in(rdbuf0_scanin),
146 .scan_out(rdbuf0_scanout),
147 .drl2clk(drl2clk),
148 .rxbclk(fsr_rxbclk[0]),
149 .fsr_data(fsr_data[11:0]),
150 .fsr_stsrx_sync(fsr_stsrx_sync[0]),
151 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[0]),
152 .fsr_stsrx_testfail(fsr_stsrx_testfail[0]),
153 .frdbuf_testfail_sync(fbd_testfail[0]),
154 .frdbuf_data(fbd_data[11:0]),
155 .frdbuf_elect_idle_sync(fbd_elect_idle[0]),
156 .frdbuf_frame_lock(fbd_frame_lock[0]),
157 .fdout_frame_lock(fdout_frame_lock[0]),
158 .fdout_rptr(fdout_rptr0[1:0]),
159 .fbdic_enable_sync_count(fbdic_enable_sync_count),
160 .tcu_pce_ov(tcu_pce_ov),
161 .tcu_aclk(tcu_aclk),
162 .tcu_bclk(tcu_bclk),
163 .tcu_scan_en(tcu_scan_en),
164 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
165 .tcu_mcu_testmode(tcu_mcu_testmode),
166 .tcu_atpg_mode(tcu_atpg_mode)
167);
168
169mcu_frdbuf_dp frdbuf1 (
170 .scan_in(rdbuf1_scanin),
171 .scan_out(rdbuf1_scanout),
172 .drl2clk(drl2clk),
173 .rxbclk(fsr_rxbclk[1]),
174 .fsr_data(fsr_data[23:12]),
175 .fsr_stsrx_sync(fsr_stsrx_sync[1]),
176 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[1]),
177 .fsr_stsrx_testfail(fsr_stsrx_testfail[1]),
178 .frdbuf_testfail_sync(fbd_testfail[1]),
179 .frdbuf_data(fbd_data[23:12]),
180 .frdbuf_elect_idle_sync(fbd_elect_idle[1]),
181 .frdbuf_frame_lock(fbd_frame_lock[1]),
182 .fdout_frame_lock(fdout_frame_lock[1]),
183 .fdout_rptr(fdout_rptr1[1:0]),
184 .fbdic_enable_sync_count(fbdic_enable_sync_count),
185 .tcu_pce_ov(tcu_pce_ov),
186 .tcu_aclk(tcu_aclk),
187 .tcu_bclk(tcu_bclk),
188 .tcu_scan_en(tcu_scan_en),
189 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
190 .tcu_mcu_testmode(tcu_mcu_testmode),
191 .tcu_atpg_mode(tcu_atpg_mode)
192);
193
194mcu_frdbuf_dp frdbuf2 (
195 .scan_in(rdbuf2_scanin),
196 .scan_out(rdbuf2_scanout),
197 .drl2clk(drl2clk),
198 .rxbclk(fsr_rxbclk[2]),
199 .fsr_data(fsr_data[35:24]),
200 .fsr_stsrx_sync(fsr_stsrx_sync[2]),
201 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[2]),
202 .fsr_stsrx_testfail(fsr_stsrx_testfail[2]),
203 .frdbuf_testfail_sync(fbd_testfail[2]),
204 .frdbuf_data(fbd_data[35:24]),
205 .frdbuf_elect_idle_sync(fbd_elect_idle[2]),
206 .frdbuf_frame_lock(fbd_frame_lock[2]),
207 .fdout_frame_lock(fdout_frame_lock[2]),
208 .fdout_rptr(fdout_rptr2[1:0]),
209 .fbdic_enable_sync_count(fbdic_enable_sync_count),
210 .tcu_pce_ov(tcu_pce_ov),
211 .tcu_aclk(tcu_aclk),
212 .tcu_bclk(tcu_bclk),
213 .tcu_scan_en(tcu_scan_en),
214 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
215 .tcu_mcu_testmode(tcu_mcu_testmode),
216 .tcu_atpg_mode(tcu_atpg_mode)
217);
218
219mcu_frdbuf_dp frdbuf3 (
220 .scan_in(rdbuf3_scanin),
221 .scan_out(rdbuf3_scanout),
222 .drl2clk(drl2clk),
223 .rxbclk(fsr_rxbclk[3]),
224 .fsr_data(fsr_data[47:36]),
225 .fsr_stsrx_sync(fsr_stsrx_sync[3]),
226 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[3]),
227 .fsr_stsrx_testfail(fsr_stsrx_testfail[3]),
228 .frdbuf_testfail_sync(fbd_testfail[3]),
229 .frdbuf_data(fbd_data[47:36]),
230 .frdbuf_elect_idle_sync(fbd_elect_idle[3]),
231 .frdbuf_frame_lock(fbd_frame_lock[3]),
232 .fdout_frame_lock(fdout_frame_lock[3]),
233 .fdout_rptr(fdout_rptr3[1:0]),
234 .fbdic_enable_sync_count(fbdic_enable_sync_count),
235 .tcu_pce_ov(tcu_pce_ov),
236 .tcu_aclk(tcu_aclk),
237 .tcu_bclk(tcu_bclk),
238 .tcu_scan_en(tcu_scan_en),
239 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
240 .tcu_mcu_testmode(tcu_mcu_testmode),
241 .tcu_atpg_mode(tcu_atpg_mode)
242);
243
244mcu_frdbuf_dp frdbuf4 (
245 .scan_in(rdbuf4_scanin),
246 .scan_out(rdbuf4_scanout),
247 .drl2clk(drl2clk),
248 .rxbclk(fsr_rxbclk[4]),
249 .fsr_data(fsr_data[59:48]),
250 .fsr_stsrx_sync(fsr_stsrx_sync[4]),
251 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[4]),
252 .fsr_stsrx_testfail(fsr_stsrx_testfail[4]),
253 .frdbuf_testfail_sync(fbd_testfail[4]),
254 .frdbuf_data(fbd_data[59:48]),
255 .frdbuf_elect_idle_sync(fbd_elect_idle[4]),
256 .frdbuf_frame_lock(fbd_frame_lock[4]),
257 .fdout_frame_lock(fdout_frame_lock[4]),
258 .fdout_rptr(fdout_rptr4[1:0]),
259 .fbdic_enable_sync_count(fbdic_enable_sync_count),
260 .tcu_pce_ov(tcu_pce_ov),
261 .tcu_aclk(tcu_aclk),
262 .tcu_bclk(tcu_bclk),
263 .tcu_scan_en(tcu_scan_en),
264 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
265 .tcu_mcu_testmode(tcu_mcu_testmode),
266 .tcu_atpg_mode(tcu_atpg_mode)
267);
268
269mcu_frdbuf_dp frdbuf5 (
270 .scan_in(rdbuf5_scanin),
271 .scan_out(rdbuf5_scanout),
272 .drl2clk(drl2clk),
273 .rxbclk(fsr_rxbclk[5]),
274 .fsr_data(fsr_data[71:60]),
275 .fsr_stsrx_sync(fsr_stsrx_sync[5]),
276 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[5]),
277 .fsr_stsrx_testfail(fsr_stsrx_testfail[5]),
278 .frdbuf_testfail_sync(fbd_testfail[5]),
279 .frdbuf_data(fbd_data[71:60]),
280 .frdbuf_elect_idle_sync(fbd_elect_idle[5]),
281 .frdbuf_frame_lock(fbd_frame_lock[5]),
282 .fdout_frame_lock(fdout_frame_lock[5]),
283 .fdout_rptr(fdout_rptr5[1:0]),
284 .fbdic_enable_sync_count(fbdic_enable_sync_count),
285 .tcu_pce_ov(tcu_pce_ov),
286 .tcu_aclk(tcu_aclk),
287 .tcu_bclk(tcu_bclk),
288 .tcu_scan_en(tcu_scan_en),
289 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
290 .tcu_mcu_testmode(tcu_mcu_testmode),
291 .tcu_atpg_mode(tcu_atpg_mode)
292);
293
294mcu_frdbuf_dp frdbuf6 (
295 .scan_in(rdbuf6_scanin),
296 .scan_out(rdbuf6_scanout),
297 .drl2clk(drl2clk),
298 .rxbclk(fsr_rxbclk[6]),
299 .fsr_data(fsr_data[83:72]),
300 .fsr_stsrx_sync(fsr_stsrx_sync[6]),
301 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[6]),
302 .fsr_stsrx_testfail(fsr_stsrx_testfail[6]),
303 .frdbuf_testfail_sync(fbd_testfail[6]),
304 .frdbuf_data(fbd_data[83:72]),
305 .frdbuf_elect_idle_sync(fbd_elect_idle[6]),
306 .frdbuf_frame_lock(fbd_frame_lock[6]),
307 .fdout_frame_lock(fdout_frame_lock[6]),
308 .fdout_rptr(fdout_rptr6[1:0]),
309 .fbdic_enable_sync_count(fbdic_enable_sync_count),
310 .tcu_pce_ov(tcu_pce_ov),
311 .tcu_aclk(tcu_aclk),
312 .tcu_bclk(tcu_bclk),
313 .tcu_scan_en(tcu_scan_en),
314 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
315 .tcu_mcu_testmode(tcu_mcu_testmode),
316 .tcu_atpg_mode(tcu_atpg_mode)
317);
318
319mcu_frdbuf_dp frdbuf7 (
320 .scan_in(rdbuf7_scanin),
321 .scan_out(rdbuf7_scanout),
322 .drl2clk(drl2clk),
323 .rxbclk(fsr_rxbclk[7]),
324 .fsr_data(fsr_data[95:84]),
325 .fsr_stsrx_sync(fsr_stsrx_sync[7]),
326 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[7]),
327 .fsr_stsrx_testfail(fsr_stsrx_testfail[7]),
328 .frdbuf_testfail_sync(fbd_testfail[7]),
329 .frdbuf_data(fbd_data[95:84]),
330 .frdbuf_elect_idle_sync(fbd_elect_idle[7]),
331 .frdbuf_frame_lock(fbd_frame_lock[7]),
332 .fdout_frame_lock(fdout_frame_lock[7]),
333 .fdout_rptr(fdout_rptr7[1:0]),
334 .fbdic_enable_sync_count(fbdic_enable_sync_count),
335 .tcu_pce_ov(tcu_pce_ov),
336 .tcu_aclk(tcu_aclk),
337 .tcu_bclk(tcu_bclk),
338 .tcu_scan_en(tcu_scan_en),
339 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
340 .tcu_mcu_testmode(tcu_mcu_testmode),
341 .tcu_atpg_mode(tcu_atpg_mode)
342);
343
344mcu_frdbuf_dp frdbuf8 (
345 .scan_in(rdbuf8_scanin),
346 .scan_out(rdbuf8_scanout),
347 .drl2clk(drl2clk),
348 .rxbclk(fsr_rxbclk[8]),
349 .fsr_data(fsr_data[107:96]),
350 .fsr_stsrx_sync(fsr_stsrx_sync[8]),
351 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[8]),
352 .fsr_stsrx_testfail(fsr_stsrx_testfail[8]),
353 .frdbuf_testfail_sync(fbd_testfail[8]),
354 .frdbuf_data(fbd_data[107:96]),
355 .frdbuf_elect_idle_sync(fbd_elect_idle[8]),
356 .frdbuf_frame_lock(fbd_frame_lock[8]),
357 .fdout_frame_lock(fdout_frame_lock[8]),
358 .fdout_rptr(fdout_rptr8[1:0]),
359 .fbdic_enable_sync_count(fbdic_enable_sync_count),
360 .tcu_pce_ov(tcu_pce_ov),
361 .tcu_aclk(tcu_aclk),
362 .tcu_bclk(tcu_bclk),
363 .tcu_scan_en(tcu_scan_en),
364 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
365 .tcu_mcu_testmode(tcu_mcu_testmode),
366 .tcu_atpg_mode(tcu_atpg_mode)
367);
368
369mcu_frdbuf_dp frdbuf9 (
370 .scan_in(rdbuf9_scanin),
371 .scan_out(rdbuf9_scanout),
372 .drl2clk(drl2clk),
373 .rxbclk(fsr_rxbclk[9]),
374 .fsr_data(fsr_data[119:108]),
375 .fsr_stsrx_sync(fsr_stsrx_sync[9]),
376 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[9]),
377 .fsr_stsrx_testfail(fsr_stsrx_testfail[9]),
378 .frdbuf_testfail_sync(fbd_testfail[9]),
379 .frdbuf_data(fbd_data[119:108]),
380 .frdbuf_elect_idle_sync(fbd_elect_idle[9]),
381 .frdbuf_frame_lock(fbd_frame_lock[9]),
382 .fdout_frame_lock(fdout_frame_lock[9]),
383 .fdout_rptr(fdout_rptr9[1:0]),
384 .fbdic_enable_sync_count(fbdic_enable_sync_count),
385 .tcu_pce_ov(tcu_pce_ov),
386 .tcu_aclk(tcu_aclk),
387 .tcu_bclk(tcu_bclk),
388 .tcu_scan_en(tcu_scan_en),
389 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
390 .tcu_mcu_testmode(tcu_mcu_testmode),
391 .tcu_atpg_mode(tcu_atpg_mode)
392);
393
394mcu_frdbuf_dp frdbuf10 (
395 .scan_in(rdbuf10_scanin),
396 .scan_out(rdbuf10_scanout),
397 .drl2clk(drl2clk),
398 .rxbclk(fsr_rxbclk[10]),
399 .fsr_data(fsr_data[131:120]),
400 .fsr_stsrx_sync(fsr_stsrx_sync[10]),
401 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[10]),
402 .fsr_stsrx_testfail(fsr_stsrx_testfail[10]),
403 .frdbuf_testfail_sync(fbd_testfail[10]),
404 .frdbuf_data(fbd_data[131:120]),
405 .frdbuf_elect_idle_sync(fbd_elect_idle[10]),
406 .frdbuf_frame_lock(fbd_frame_lock[10]),
407 .fdout_frame_lock(fdout_frame_lock[10]),
408 .fdout_rptr(fdout_rptr10[1:0]),
409 .fbdic_enable_sync_count(fbdic_enable_sync_count),
410 .tcu_pce_ov(tcu_pce_ov),
411 .tcu_aclk(tcu_aclk),
412 .tcu_bclk(tcu_bclk),
413 .tcu_scan_en(tcu_scan_en),
414 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
415 .tcu_mcu_testmode(tcu_mcu_testmode),
416 .tcu_atpg_mode(tcu_atpg_mode)
417);
418
419mcu_frdbuf_dp frdbuf11 (
420 .scan_in(rdbuf11_scanin),
421 .scan_out(rdbuf11_scanout),
422 .drl2clk(drl2clk),
423 .rxbclk(fsr_rxbclk[11]),
424 .fsr_data(fsr_data[143:132]),
425 .fsr_stsrx_sync(fsr_stsrx_sync[11]),
426 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[11]),
427 .fsr_stsrx_testfail(fsr_stsrx_testfail[11]),
428 .frdbuf_testfail_sync(fbd_testfail[11]),
429 .frdbuf_data(fbd_data[143:132]),
430 .frdbuf_elect_idle_sync(fbd_elect_idle[11]),
431 .frdbuf_frame_lock(fbd_frame_lock[11]),
432 .fdout_frame_lock(fdout_frame_lock[11]),
433 .fdout_rptr(fdout_rptr11[1:0]),
434 .fbdic_enable_sync_count(fbdic_enable_sync_count),
435 .tcu_pce_ov(tcu_pce_ov),
436 .tcu_aclk(tcu_aclk),
437 .tcu_bclk(tcu_bclk),
438 .tcu_scan_en(tcu_scan_en),
439 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
440 .tcu_mcu_testmode(tcu_mcu_testmode),
441 .tcu_atpg_mode(tcu_atpg_mode)
442);
443
444mcu_frdbuf_dp frdbuf12 (
445 .scan_in(rdbuf12_scanin),
446 .scan_out(rdbuf12_scanout),
447 .drl2clk(drl2clk),
448 .rxbclk(fsr_rxbclk[12]),
449 .fsr_data(fsr_data[155:144]),
450 .fsr_stsrx_sync(fsr_stsrx_sync[12]),
451 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[12]),
452 .fsr_stsrx_testfail(fsr_stsrx_testfail[12]),
453 .frdbuf_testfail_sync(fbd_testfail[12]),
454 .frdbuf_data(fbd_data[155:144]),
455 .frdbuf_elect_idle_sync(fbd_elect_idle[12]),
456 .frdbuf_frame_lock(fbd_frame_lock[12]),
457 .fdout_frame_lock(fdout_frame_lock[12]),
458 .fdout_rptr(fdout_rptr12[1:0]),
459 .fbdic_enable_sync_count(fbdic_enable_sync_count),
460 .tcu_pce_ov(tcu_pce_ov),
461 .tcu_aclk(tcu_aclk),
462 .tcu_bclk(tcu_bclk),
463 .tcu_scan_en(tcu_scan_en),
464 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
465 .tcu_mcu_testmode(tcu_mcu_testmode),
466 .tcu_atpg_mode(tcu_atpg_mode)
467);
468
469mcu_frdbuf_dp frdbuf13 (
470 .scan_in(rdbuf13_scanin),
471 .scan_out(rdbuf13_scanout),
472 .drl2clk(drl2clk),
473 .rxbclk(fsr_rxbclk[13]),
474 .fsr_data(fsr_data[167:156]),
475 .fsr_stsrx_sync(fsr_stsrx_sync[13]),
476 .fsr_stsrx_losdtct(fsr_stsrx_losdtct[13]),
477 .fsr_stsrx_testfail(fsr_stsrx_testfail[13]),
478 .frdbuf_testfail_sync(fbd_testfail[13]),
479 .frdbuf_data(fbd_data[167:156]),
480 .frdbuf_elect_idle_sync(fbd_elect_idle[13]),
481 .frdbuf_frame_lock(fbd_frame_lock[13]),
482 .fdout_frame_lock(fdout_frame_lock[13]),
483 .fdout_rptr(fdout_rptr13[1:0]),
484 .fbdic_enable_sync_count(fbdic_enable_sync_count),
485 .tcu_pce_ov(tcu_pce_ov),
486 .tcu_aclk(tcu_aclk),
487 .tcu_bclk(tcu_bclk),
488 .tcu_scan_en(tcu_scan_en),
489 .tcu_mcu_fbd_clk_stop(tcu_mcu_fbd_clk_stop),
490 .tcu_mcu_testmode(tcu_mcu_testmode),
491 .tcu_atpg_mode(tcu_atpg_mode)
492);
493
494// fixscan start:
495assign rdbuf0_scanin = scan_in ;
496assign rdbuf1_scanin = rdbuf0_scanout ;
497assign rdbuf2_scanin = rdbuf1_scanout ;
498assign rdbuf3_scanin = rdbuf2_scanout ;
499assign rdbuf4_scanin = rdbuf3_scanout ;
500assign rdbuf5_scanin = rdbuf4_scanout ;
501assign rdbuf6_scanin = rdbuf5_scanout ;
502assign rdbuf7_scanin = rdbuf6_scanout ;
503assign rdbuf8_scanin = rdbuf7_scanout ;
504assign rdbuf9_scanin = rdbuf8_scanout ;
505assign rdbuf10_scanin = rdbuf9_scanout ;
506assign rdbuf11_scanin = rdbuf10_scanout ;
507assign rdbuf12_scanin = rdbuf11_scanout ;
508assign rdbuf13_scanin = rdbuf12_scanout ;
509assign scan_out = rdbuf13_scanout ;
510// fixscan end:
511endmodule
512
513
514//
515// and macro for ports = 2,3,4
516//
517//
518
519
520
521
522
523module mcu_fbd_dp_and_macro (
524 din0,
525 din1,
526 dout);
527 input [0:0] din0;
528 input [0:0] din1;
529 output [0:0] dout;
530
531
532
533
534
535
536and2 #(1) d0_0 (
537.in0(din0[0:0]),
538.in1(din1[0:0]),
539.out(dout[0:0])
540);
541
542
543
544
545
546
547
548
549
550endmodule
551
552
553
554
555
556
557
558
559
560// any PARAMS parms go into naming of macro
561
562module mcu_fbd_dp_msff_macro__stack_11r__width_4 (
563 din,
564 clk,
565 en,
566 se,
567 scan_in,
568 siclk,
569 soclk,
570 pce_ov,
571 stop,
572 dout,
573 scan_out);
574wire l1clk;
575wire siclk_out;
576wire soclk_out;
577wire [2:0] so;
578
579 input [3:0] din;
580
581
582 input clk;
583 input en;
584 input se;
585 input scan_in;
586 input siclk;
587 input soclk;
588 input pce_ov;
589 input stop;
590
591
592
593 output [3:0] dout;
594
595
596 output scan_out;
597
598
599
600
601cl_dp1_l1hdr_8x c0_0 (
602.l2clk(clk),
603.pce(en),
604.aclk(siclk),
605.bclk(soclk),
606.l1clk(l1clk),
607 .se(se),
608 .pce_ov(pce_ov),
609 .stop(stop),
610 .siclk_out(siclk_out),
611 .soclk_out(soclk_out)
612);
613dff #(4) d0_0 (
614.l1clk(l1clk),
615.siclk(siclk_out),
616.soclk(soclk_out),
617.d(din[3:0]),
618.si({scan_in,so[2:0]}),
619.so({so[2:0],scan_out}),
620.q(dout[3:0])
621);
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642endmodule
643
644
645
646
647
648
649
650
651
652//
653// invert macro
654//
655//
656
657
658
659
660
661module mcu_fbd_dp_inv_macro (
662 din,
663 dout);
664 input [0:0] din;
665 output [0:0] dout;
666
667
668
669
670
671
672inv #(1) d0_0 (
673.in(din[0:0]),
674.out(dout[0:0])
675);
676
677
678
679
680
681
682
683
684
685endmodule
686
687
688
689
690
691//
692// nor macro for ports = 2,3
693//
694//
695
696
697
698
699
700module mcu_fbd_dp_nor_macro (
701 din0,
702 din1,
703 dout);
704 input [0:0] din0;
705 input [0:0] din1;
706 output [0:0] dout;
707
708
709
710
711
712
713nor2 #(1) d0_0 (
714.in0(din0[0:0]),
715.in1(din1[0:0]),
716.out(dout[0:0])
717);
718
719
720
721
722
723
724
725endmodule
726
727
728
729
730
731//
732// buff macro
733//
734//
735
736
737
738
739
740module mcu_fbd_dp_buff_macro__minbuff_1__stack_12r__width_12 (
741 din,
742 dout);
743 input [11:0] din;
744 output [11:0] dout;
745
746
747
748
749
750
751buff #(12) d0_0 (
752.in(din[11:0]),
753.out(dout[11:0])
754);
755
756
757
758
759
760
761
762
763endmodule
764
765
766
767
768
769//
770// increment macro
771//
772//
773
774
775
776
777
778module mcu_fbd_dp_increment_macro__width_4 (
779 din,
780 cin,
781 dout,
782 cout);
783 input [3:0] din;
784 input cin;
785 output [3:0] dout;
786 output cout;
787
788
789
790
791
792
793incr #(4) m0_0 (
794.cin(cin),
795.in(din[3:0]),
796.out(dout[3:0]),
797.cout(cout)
798);
799
800
801
802
803
804
805
806
807
808
809
810endmodule
811
812
813
814
815
816//
817// and macro for ports = 2,3,4
818//
819//
820
821
822
823
824
825module mcu_fbd_dp_and_macro__ports_3__width_4 (
826 din0,
827 din1,
828 din2,
829 dout);
830 input [3:0] din0;
831 input [3:0] din1;
832 input [3:0] din2;
833 output [3:0] dout;
834
835
836
837
838
839
840and3 #(4) d0_0 (
841.in0(din0[3:0]),
842.in1(din1[3:0]),
843.in2(din2[3:0]),
844.out(dout[3:0])
845);
846
847
848
849
850
851
852
853
854
855endmodule
856
857
858
859
860
861//
862// or macro for ports = 2,3
863//
864//
865
866
867
868
869
870module mcu_fbd_dp_or_macro__ports_2__width_1 (
871 din0,
872 din1,
873 dout);
874 input [0:0] din0;
875 input [0:0] din1;
876 output [0:0] dout;
877
878
879
880
881
882
883or2 #(1) d0_0 (
884.in0(din0[0:0]),
885.in1(din1[0:0]),
886.out(dout[0:0])
887);
888
889
890
891
892
893
894
895
896
897endmodule
898
899
900
901
902
903//
904// invert macro
905//
906//
907
908
909
910
911
912module mcu_fbd_dp_inv_macro__width_1 (
913 din,
914 dout);
915 input [0:0] din;
916 output [0:0] dout;
917
918
919
920
921
922
923inv #(1) d0_0 (
924.in(din[0:0]),
925.out(dout[0:0])
926);
927
928
929
930
931
932
933
934
935
936endmodule
937
938
939
940
941
942//
943// and macro for ports = 2,3,4
944//
945//
946
947
948
949
950
951module mcu_fbd_dp_and_macro__ports_2__width_1 (
952 din0,
953 din1,
954 dout);
955 input [0:0] din0;
956 input [0:0] din1;
957 output [0:0] dout;
958
959
960
961
962
963
964and2 #(1) d0_0 (
965.in0(din0[0:0]),
966.in1(din1[0:0]),
967.out(dout[0:0])
968);
969
970
971
972
973
974
975
976
977
978endmodule
979
980
981
982
983
984//
985// invert macro
986//
987//
988
989
990
991
992
993module mcu_fbd_dp_inv_macro__width_2 (
994 din,
995 dout);
996 input [1:0] din;
997 output [1:0] dout;
998
999
1000
1001
1002
1003
1004inv #(2) d0_0 (
1005.in(din[1:0]),
1006.out(dout[1:0])
1007);
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017endmodule
1018
1019
1020
1021
1022
1023//
1024// and macro for ports = 2,3,4
1025//
1026//
1027
1028
1029
1030
1031
1032module mcu_fbd_dp_and_macro__width_2 (
1033 din0,
1034 din1,
1035 dout);
1036 input [1:0] din0;
1037 input [1:0] din1;
1038 output [1:0] dout;
1039
1040
1041
1042
1043
1044
1045and2 #(2) d0_0 (
1046.in0(din0[1:0]),
1047.in1(din1[1:0]),
1048.out(dout[1:0])
1049);
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059endmodule
1060
1061
1062
1063
1064
1065//
1066// nor macro for ports = 2,3
1067//
1068//
1069
1070
1071
1072
1073
1074module mcu_fbd_dp_nor_macro__ports_3__width_1 (
1075 din0,
1076 din1,
1077 din2,
1078 dout);
1079 input [0:0] din0;
1080 input [0:0] din1;
1081 input [0:0] din2;
1082 output [0:0] dout;
1083
1084
1085
1086
1087
1088
1089nor3 #(1) d0_0 (
1090.in0(din0[0:0]),
1091.in1(din1[0:0]),
1092.in2(din2[0:0]),
1093.out(dout[0:0])
1094);
1095
1096
1097
1098
1099
1100
1101
1102endmodule
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112// any PARAMS parms go into naming of macro
1113
1114module mcu_fbd_dp_msff_macro__stack_12r__width_12 (
1115 din,
1116 clk,
1117 en,
1118 se,
1119 scan_in,
1120 siclk,
1121 soclk,
1122 pce_ov,
1123 stop,
1124 dout,
1125 scan_out);
1126wire l1clk;
1127wire siclk_out;
1128wire soclk_out;
1129wire [10:0] so;
1130
1131 input [11:0] din;
1132
1133
1134 input clk;
1135 input en;
1136 input se;
1137 input scan_in;
1138 input siclk;
1139 input soclk;
1140 input pce_ov;
1141 input stop;
1142
1143
1144
1145 output [11:0] dout;
1146
1147
1148 output scan_out;
1149
1150
1151
1152
1153cl_dp1_l1hdr_8x c0_0 (
1154.l2clk(clk),
1155.pce(en),
1156.aclk(siclk),
1157.bclk(soclk),
1158.l1clk(l1clk),
1159 .se(se),
1160 .pce_ov(pce_ov),
1161 .stop(stop),
1162 .siclk_out(siclk_out),
1163 .soclk_out(soclk_out)
1164);
1165dff #(12) d0_0 (
1166.l1clk(l1clk),
1167.siclk(siclk_out),
1168.soclk(soclk_out),
1169.d(din[11:0]),
1170.si({scan_in,so[10:0]}),
1171.so({so[10:0],scan_out}),
1172.q(dout[11:0])
1173);
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194endmodule
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208// any PARAMS parms go into naming of macro
1209
1210module mcu_fbd_dp_msff_macro__stack_12r__width_4 (
1211 din,
1212 clk,
1213 en,
1214 se,
1215 scan_in,
1216 siclk,
1217 soclk,
1218 pce_ov,
1219 stop,
1220 dout,
1221 scan_out);
1222wire l1clk;
1223wire siclk_out;
1224wire soclk_out;
1225wire [2:0] so;
1226
1227 input [3:0] din;
1228
1229
1230 input clk;
1231 input en;
1232 input se;
1233 input scan_in;
1234 input siclk;
1235 input soclk;
1236 input pce_ov;
1237 input stop;
1238
1239
1240
1241 output [3:0] dout;
1242
1243
1244 output scan_out;
1245
1246
1247
1248
1249cl_dp1_l1hdr_8x c0_0 (
1250.l2clk(clk),
1251.pce(en),
1252.aclk(siclk),
1253.bclk(soclk),
1254.l1clk(l1clk),
1255 .se(se),
1256 .pce_ov(pce_ov),
1257 .stop(stop),
1258 .siclk_out(siclk_out),
1259 .soclk_out(soclk_out)
1260);
1261dff #(4) d0_0 (
1262.l1clk(l1clk),
1263.siclk(siclk_out),
1264.soclk(soclk_out),
1265.d(din[3:0]),
1266.si({scan_in,so[2:0]}),
1267.so({so[2:0],scan_out}),
1268.q(dout[3:0])
1269);
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290endmodule
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300//
1301// nor macro for ports = 2,3
1302//
1303//
1304
1305
1306
1307
1308
1309module mcu_fbd_dp_nor_macro__ports_2__width_1 (
1310 din0,
1311 din1,
1312 dout);
1313 input [0:0] din0;
1314 input [0:0] din1;
1315 output [0:0] dout;
1316
1317
1318
1319
1320
1321
1322nor2 #(1) d0_0 (
1323.in0(din0[0:0]),
1324.in1(din1[0:0]),
1325.out(dout[0:0])
1326);
1327
1328
1329
1330
1331
1332
1333
1334endmodule
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344// any PARAMS parms go into naming of macro
1345
1346module mcu_fbd_dp_msff_macro__mux_aonpe__ports_4__stack_12r__width_12 (
1347 din0,
1348 sel0,
1349 din1,
1350 sel1,
1351 din2,
1352 sel2,
1353 din3,
1354 sel3,
1355 clk,
1356 en,
1357 se,
1358 scan_in,
1359 siclk,
1360 soclk,
1361 pce_ov,
1362 stop,
1363 dout,
1364 scan_out);
1365wire buffout0;
1366wire buffout1;
1367wire buffout2;
1368wire buffout3;
1369wire [11:0] muxout;
1370wire l1clk;
1371wire siclk_out;
1372wire soclk_out;
1373wire [10:0] so;
1374
1375 input [11:0] din0;
1376 input sel0;
1377 input [11:0] din1;
1378 input sel1;
1379 input [11:0] din2;
1380 input sel2;
1381 input [11:0] din3;
1382 input sel3;
1383
1384
1385 input clk;
1386 input en;
1387 input se;
1388 input scan_in;
1389 input siclk;
1390 input soclk;
1391 input pce_ov;
1392 input stop;
1393
1394
1395
1396 output [11:0] dout;
1397
1398
1399 output scan_out;
1400
1401
1402
1403
1404cl_dp1_muxbuff4_8x c1_0 (
1405 .in0(sel0),
1406 .in1(sel1),
1407 .in2(sel2),
1408 .in3(sel3),
1409 .out0(buffout0),
1410 .out1(buffout1),
1411 .out2(buffout2),
1412 .out3(buffout3)
1413);
1414mux4s #(12) d1_0 (
1415 .sel0(buffout0),
1416 .sel1(buffout1),
1417 .sel2(buffout2),
1418 .sel3(buffout3),
1419 .in0(din0[11:0]),
1420 .in1(din1[11:0]),
1421 .in2(din2[11:0]),
1422 .in3(din3[11:0]),
1423.dout(muxout[11:0])
1424);
1425cl_dp1_l1hdr_8x c0_0 (
1426.l2clk(clk),
1427.pce(en),
1428.aclk(siclk),
1429.bclk(soclk),
1430.l1clk(l1clk),
1431 .se(se),
1432 .pce_ov(pce_ov),
1433 .stop(stop),
1434 .siclk_out(siclk_out),
1435 .soclk_out(soclk_out)
1436);
1437dff #(12) d0_0 (
1438.l1clk(l1clk),
1439.siclk(siclk_out),
1440.soclk(soclk_out),
1441.d(muxout[11:0]),
1442.si({scan_in,so[10:0]}),
1443.so({so[10:0],scan_out}),
1444.q(dout[11:0])
1445);
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466endmodule
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476// general mux macro for pass-gate and and-or muxes with/wout priority encoders
1477// also for pass-gate with decoder
1478
1479
1480
1481
1482
1483// any PARAMS parms go into naming of macro
1484
1485module mcu_fbd_dp_mux_macro__buffsel_none__mux_aonpe (
1486 din0,
1487 sel0,
1488 din1,
1489 sel1,
1490 dout);
1491 input [0:0] din0;
1492 input sel0;
1493 input [0:0] din1;
1494 input sel1;
1495 output [0:0] dout;
1496
1497
1498
1499
1500
1501mux2s #(1) d0_0 (
1502 .sel0(sel0),
1503 .sel1(sel1),
1504 .in0(din0[0:0]),
1505 .in1(din1[0:0]),
1506.dout(dout[0:0])
1507);
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521endmodule
1522
Full OpenSPARC design & verification tarball including full HDL.