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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mcu_l2rdmx_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mcu_l2rdmx_dp ( | |
36 | bank0_l2wr_data, | |
37 | bank1_l2wr_data, | |
38 | l2_secc_err_dly1, | |
39 | l2_mecc_err_dly1, | |
40 | mcu_rddata, | |
41 | mcu_rdecc, | |
42 | mcu_l2t0_qword_id_r0, | |
43 | mcu_l2t0_data_vld_r0, | |
44 | mcu_l2t0_rd_req_id_r0, | |
45 | mcu_l2t1_qword_id_r0, | |
46 | mcu_l2t1_data_vld_r0, | |
47 | mcu_l2t1_rd_req_id_r0, | |
48 | l2b0_rd_rank_adr, | |
49 | l2b0_rd_dimm_adr, | |
50 | l2b0_rd_bank_adr, | |
51 | l2b0_rd_ras_adr, | |
52 | l2b0_rd_cas_adr, | |
53 | l2b0_rd_addr_err, | |
54 | l2b0_rd_addr_par, | |
55 | l2b0_l2rd_req_id, | |
56 | l2b0_wr_rank_adr, | |
57 | l2b0_wr_dimm_adr, | |
58 | l2b0_wr_bank_adr, | |
59 | l2b0_wr_ras_adr, | |
60 | l2b0_wr_cas_adr, | |
61 | l2b0_wr_addr_err, | |
62 | l2b0_wr_addr_par, | |
63 | l2b1_rd_rank_adr, | |
64 | l2b1_rd_dimm_adr, | |
65 | l2b1_rd_bank_adr, | |
66 | l2b1_rd_ras_adr, | |
67 | l2b1_rd_cas_adr, | |
68 | l2b1_rd_addr_err, | |
69 | l2b1_rd_addr_par, | |
70 | l2b1_l2rd_req_id, | |
71 | l2b1_wr_rank_adr, | |
72 | l2b1_wr_dimm_adr, | |
73 | l2b1_wr_bank_adr, | |
74 | l2b1_wr_ras_adr, | |
75 | l2b1_wr_cas_adr, | |
76 | l2b1_wr_addr_err, | |
77 | l2b1_wr_addr_par, | |
78 | mbist_run_d1, | |
79 | mbist_run_d1_l, | |
80 | mbist_wdata, | |
81 | l2b0_mcu_wr_data_r5, | |
82 | l2b1_mcu_wr_data_r5, | |
83 | rddata_sel, | |
84 | pa_err, | |
85 | dr_secc_err, | |
86 | dr_mecc_err, | |
87 | rddata, | |
88 | rdpctl_l2t0_data_valid, | |
89 | rdpctl_l2t1_data_valid, | |
90 | rdpctl_qword_id, | |
91 | rdpctl_rd_req_id, | |
92 | l2if0_rd_rank_adr, | |
93 | l2if0_rd_dimm_adr, | |
94 | l2if0_rd_bank_adr, | |
95 | l2if0_rd_ras_adr, | |
96 | l2if0_rd_cas_adr, | |
97 | l2if0_rd_addr_err, | |
98 | l2if0_rd_addr_parity, | |
99 | l2if0_rd_req_id, | |
100 | l2if0_wr_rank_adr, | |
101 | l2if0_wr_dimm_adr, | |
102 | l2if0_wr_bank_adr, | |
103 | l2if0_wr_ras_adr, | |
104 | l2if0_wr_cas_adr, | |
105 | l2if0_wr_addr_err, | |
106 | l2if0_wr_addr_parity, | |
107 | l2if1_rd_rank_adr, | |
108 | l2if1_rd_dimm_adr, | |
109 | l2if1_rd_bank_adr, | |
110 | l2if1_rd_ras_adr, | |
111 | l2if1_rd_cas_adr, | |
112 | l2if1_rd_addr_err, | |
113 | l2if1_rd_addr_parity, | |
114 | l2if1_rd_req_id, | |
115 | l2if1_wr_rank_adr, | |
116 | l2if1_wr_dimm_adr, | |
117 | l2if1_wr_bank_adr, | |
118 | l2if1_wr_ras_adr, | |
119 | l2if1_wr_cas_adr, | |
120 | l2if1_wr_addr_err, | |
121 | l2if1_wr_addr_parity, | |
122 | l2clk, | |
123 | ddr_cmp_sync_en, | |
124 | cmp_ddr_sync_en, | |
125 | scan_in, | |
126 | scan_out, | |
127 | tcu_pce_ov, | |
128 | tcu_aclk, | |
129 | tcu_bclk, | |
130 | tcu_scan_en); | |
131 | wire pce_ov; | |
132 | wire stop; | |
133 | wire siclk; | |
134 | wire soclk; | |
135 | wire se; | |
136 | wire u_bank0_l2wr_data_scanin; | |
137 | wire u_bank0_l2wr_data_scanout; | |
138 | wire [63:0] l2b0_mcu_wr_data_r6; | |
139 | wire [7:0] mbist_wdata_d1; | |
140 | wire u_bank1_l2wr_data_scanin; | |
141 | wire u_bank1_l2wr_data_scanout; | |
142 | wire [63:0] l2b1_mcu_wr_data_r6; | |
143 | wire u_l2_rd_data_255_192_scanin; | |
144 | wire u_l2_rd_data_255_192_scanout; | |
145 | wire [255:0] l2_rddata; | |
146 | wire [1:0] l2_secc_err; | |
147 | wire u_l2_rd_data_191_128_scanin; | |
148 | wire u_l2_rd_data_191_128_scanout; | |
149 | wire [1:0] l2_mecc_err; | |
150 | wire u_l2_rd_data_127_64_scanin; | |
151 | wire u_l2_rd_data_127_64_scanout; | |
152 | wire u_l2_rd_data_64_0_scanin; | |
153 | wire u_l2_rd_data_64_0_scanout; | |
154 | wire u_l2_rd_data_127_64_dly1_scanin; | |
155 | wire u_l2_rd_data_127_64_dly1_scanout; | |
156 | wire [127:0] l2_rddata_dly1; | |
157 | wire u_l2_rd_data_64_0_dly1_scanin; | |
158 | wire u_l2_rd_data_64_0_dly1_scanout; | |
159 | wire u_l2_rd_data_127_64_dly2_scanin; | |
160 | wire u_l2_rd_data_127_64_dly2_scanout; | |
161 | wire [127:0] l2_rddata_dly2; | |
162 | wire l2_secc_err_dly2; | |
163 | wire u_l2_rd_data_64_0_dly2_scanin; | |
164 | wire u_l2_rd_data_64_0_dly2_scanout; | |
165 | wire l2_mecc_err_dly2; | |
166 | wire [27:0] l2_ecc; | |
167 | wire u_rddata_127_64_p3_scanin; | |
168 | wire u_rddata_127_64_p3_scanout; | |
169 | wire u_rddata_63_0_p3_scanin; | |
170 | wire u_rddata_63_0_p3_scanout; | |
171 | wire u_l2ecc_mbist_wdata_scanin; | |
172 | wire u_l2ecc_mbist_wdata_scanout; | |
173 | wire ddr_cmp_sync_en_d1; | |
174 | wire ddr_cmp_sync_en_d01; | |
175 | wire [24:0] spare; | |
176 | wire ddr_cmp_sync_en_d2; | |
177 | wire ddr_cmp_sync_en_d12; | |
178 | wire u_l2t_cntl_scanin; | |
179 | wire u_l2t_cntl_scanout; | |
180 | wire l2rdmx_l2t0_data_valid; | |
181 | wire l2rdmx_l2t1_data_valid; | |
182 | wire l2rdmx_qword_id; | |
183 | wire [2:0] l2rdmx_rd_req_id; | |
184 | wire [13:0] spare_nand_unused; | |
185 | wire u_l2if0_ras_cas_addr_scanin; | |
186 | wire u_l2if0_ras_cas_addr_scanout; | |
187 | wire u_l2if1_ras_cas_addr_scanin; | |
188 | wire u_l2if1_ras_cas_addr_scanout; | |
189 | wire u_l2if_bank_rank_addr_scanin; | |
190 | wire u_l2if_bank_rank_addr_scanout; | |
191 | ||
192 | ||
193 | output [63:0] bank0_l2wr_data; // L2 bank0 write data to write data queue | |
194 | output [63:0] bank1_l2wr_data; // L2 bank0 write data to write data queue | |
195 | ||
196 | output l2_secc_err_dly1; // single bit error detected in l2clk domain | |
197 | output l2_mecc_err_dly1; // multi bits error detected in l2clk domain | |
198 | output [127:0] mcu_rddata; // memory read data to L2 | |
199 | output [27:0] mcu_rdecc; // memory read ECC data to L2 | |
200 | ||
201 | output [1:0] mcu_l2t0_qword_id_r0; // quad word id to l2 cache bank 0 | |
202 | output mcu_l2t0_data_vld_r0; // data valid to l2 cache bank 0 | |
203 | output [2:0] mcu_l2t0_rd_req_id_r0; // read request id to l2 cache bank 0 | |
204 | output [1:0] mcu_l2t1_qword_id_r0; // quad word id to l2 cache bank 1 | |
205 | output mcu_l2t1_data_vld_r0; // data valid to l2 cache bank 1 | |
206 | output [2:0] mcu_l2t1_rd_req_id_r0; // read request id to l2 cache bank 1 | |
207 | ||
208 | output l2b0_rd_rank_adr; | |
209 | output [2:0] l2b0_rd_dimm_adr; | |
210 | output [2:0] l2b0_rd_bank_adr; | |
211 | output [14:0] l2b0_rd_ras_adr; | |
212 | output [10:0] l2b0_rd_cas_adr; | |
213 | output l2b0_rd_addr_err; | |
214 | output l2b0_rd_addr_par; | |
215 | output [2:0] l2b0_l2rd_req_id; | |
216 | ||
217 | output l2b0_wr_rank_adr; | |
218 | output [2:0] l2b0_wr_dimm_adr; | |
219 | output [2:0] l2b0_wr_bank_adr; | |
220 | output [14:0] l2b0_wr_ras_adr; | |
221 | output [10:0] l2b0_wr_cas_adr; | |
222 | output l2b0_wr_addr_err; | |
223 | output l2b0_wr_addr_par; | |
224 | ||
225 | output l2b1_rd_rank_adr; | |
226 | output [2:0] l2b1_rd_dimm_adr; | |
227 | output [2:0] l2b1_rd_bank_adr; | |
228 | output [14:0] l2b1_rd_ras_adr; | |
229 | output [10:0] l2b1_rd_cas_adr; | |
230 | output l2b1_rd_addr_err; | |
231 | output l2b1_rd_addr_par; | |
232 | output [2:0] l2b1_l2rd_req_id; | |
233 | ||
234 | output l2b1_wr_rank_adr; | |
235 | output [2:0] l2b1_wr_dimm_adr; | |
236 | output [2:0] l2b1_wr_bank_adr; | |
237 | output [14:0] l2b1_wr_ras_adr; | |
238 | output [10:0] l2b1_wr_cas_adr; | |
239 | output l2b1_wr_addr_err; | |
240 | output l2b1_wr_addr_par; | |
241 | ||
242 | input mbist_run_d1; | |
243 | input mbist_run_d1_l; | |
244 | input [7:0] mbist_wdata; | |
245 | input [63:0] l2b0_mcu_wr_data_r5; // L2 bank0 write data | |
246 | input [63:0] l2b1_mcu_wr_data_r5; // L2 bank1 write data | |
247 | ||
248 | input [1:0] rddata_sel; // dummy read data select | |
249 | input pa_err; // physical address error | |
250 | ||
251 | input [1:0] dr_secc_err; // single bit error detected in drl2clk domain | |
252 | input [1:0] dr_mecc_err; // multi bits error detected in drl2clk domain | |
253 | input [255:0] rddata; // Read data from drl2clk domain | |
254 | ||
255 | input rdpctl_l2t0_data_valid; // data valid for returning l2t0 read data | |
256 | input rdpctl_l2t1_data_valid; // data valid for returning l2t1 read data | |
257 | input rdpctl_qword_id; // qword id for returning transaction | |
258 | input [2:0] rdpctl_rd_req_id; // read request id for returning transaction | |
259 | ||
260 | input l2if0_rd_rank_adr; | |
261 | input [2:0] l2if0_rd_dimm_adr; | |
262 | input [2:0] l2if0_rd_bank_adr; | |
263 | input [14:0] l2if0_rd_ras_adr; | |
264 | input [10:0] l2if0_rd_cas_adr; | |
265 | input l2if0_rd_addr_err; | |
266 | input l2if0_rd_addr_parity; | |
267 | input [2:0] l2if0_rd_req_id; | |
268 | ||
269 | input l2if0_wr_rank_adr; | |
270 | input [2:0] l2if0_wr_dimm_adr; | |
271 | input [2:0] l2if0_wr_bank_adr; | |
272 | input [14:0] l2if0_wr_ras_adr; | |
273 | input [10:0] l2if0_wr_cas_adr; | |
274 | input l2if0_wr_addr_err; | |
275 | input l2if0_wr_addr_parity; | |
276 | ||
277 | input l2if1_rd_rank_adr; | |
278 | input [2:0] l2if1_rd_dimm_adr; | |
279 | input [2:0] l2if1_rd_bank_adr; | |
280 | input [14:0] l2if1_rd_ras_adr; | |
281 | input [10:0] l2if1_rd_cas_adr; | |
282 | input l2if1_rd_addr_err; | |
283 | input l2if1_rd_addr_parity; | |
284 | input [2:0] l2if1_rd_req_id; | |
285 | ||
286 | input l2if1_wr_rank_adr; | |
287 | input [2:0] l2if1_wr_dimm_adr; | |
288 | input [2:0] l2if1_wr_bank_adr; | |
289 | input [14:0] l2if1_wr_ras_adr; | |
290 | input [10:0] l2if1_wr_cas_adr; | |
291 | input l2if1_wr_addr_err; | |
292 | input l2if1_wr_addr_parity; | |
293 | ||
294 | input l2clk; | |
295 | input ddr_cmp_sync_en; | |
296 | input cmp_ddr_sync_en; | |
297 | ||
298 | input scan_in; | |
299 | output scan_out; | |
300 | input tcu_pce_ov; | |
301 | input tcu_aclk; | |
302 | input tcu_bclk; | |
303 | input tcu_scan_en; | |
304 | ||
305 | // Scan reassigns | |
306 | assign pce_ov = tcu_pce_ov; | |
307 | assign stop = 1'b0; | |
308 | assign siclk = tcu_aclk; | |
309 | assign soclk = tcu_bclk; | |
310 | assign se = tcu_scan_en; | |
311 | ||
312 | // Write data from L2 bank0 | |
313 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_64 u_bank0_l2wr_data ( | |
314 | .scan_in(u_bank0_l2wr_data_scanin), | |
315 | .scan_out(u_bank0_l2wr_data_scanout), | |
316 | .clk ( l2clk ), | |
317 | .en ( 1'b1 ), | |
318 | .din ( l2b0_mcu_wr_data_r5[63:0] ), | |
319 | .dout ( l2b0_mcu_wr_data_r6[63:0] ), | |
320 | .se(se), | |
321 | .siclk(siclk), | |
322 | .soclk(soclk), | |
323 | .pce_ov(pce_ov), | |
324 | .stop(stop)); | |
325 | ||
326 | ||
327 | mcu_l2rdmx_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_64 u_bank0_mbist_mux ( | |
328 | .din0 ( l2b0_mcu_wr_data_r6[63:0] ), | |
329 | .din1 ( {8{mbist_wdata_d1[7:0]}} ), | |
330 | .sel0 ( mbist_run_d1_l ), | |
331 | .sel1 ( mbist_run_d1 ), | |
332 | .dout ( bank0_l2wr_data[63:0] )); | |
333 | ||
334 | ||
335 | // Write data from L2 bank1 | |
336 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_64 u_bank1_l2wr_data ( | |
337 | .scan_in(u_bank1_l2wr_data_scanin), | |
338 | .scan_out(u_bank1_l2wr_data_scanout), | |
339 | .clk ( l2clk ), | |
340 | .en ( 1'b1 ), | |
341 | .din ( l2b1_mcu_wr_data_r5[63:0] ), | |
342 | .dout ( l2b1_mcu_wr_data_r6[63:0] ), | |
343 | .se(se), | |
344 | .siclk(siclk), | |
345 | .soclk(soclk), | |
346 | .pce_ov(pce_ov), | |
347 | .stop(stop)); | |
348 | ||
349 | mcu_l2rdmx_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_64 u_bank1_mbist_mux ( | |
350 | .din0 ( l2b1_mcu_wr_data_r6[63:0] ), | |
351 | .din1 ( {8{mbist_wdata_d1[7:0]}} ), | |
352 | .sel0 ( mbist_run_d1_l ), | |
353 | .sel1 ( mbist_run_d1 ), | |
354 | .dout ( bank1_l2wr_data[63:0] )); | |
355 | ||
356 | //////////////////////////////////////////////////////////////////////////////// | |
357 | // | |
358 | // Cross_Clock_Domain: drl2clk -> l2clk | |
359 | // | |
360 | //////////////////////////////////////////////////////////////////////////////// | |
361 | ||
362 | ||
363 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_65 u_l2_rd_data_255_192 ( | |
364 | .scan_in(u_l2_rd_data_255_192_scanin), | |
365 | .scan_out(u_l2_rd_data_255_192_scanout), | |
366 | .clk ( l2clk ), | |
367 | .en ( ddr_cmp_sync_en ), | |
368 | .din ( {rddata[255:192], dr_secc_err[1] } ), | |
369 | .dout ( {l2_rddata[255:192], l2_secc_err[1]} ), | |
370 | .se(se), | |
371 | .siclk(siclk), | |
372 | .soclk(soclk), | |
373 | .pce_ov(pce_ov), | |
374 | .stop(stop)); | |
375 | ||
376 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_65 u_l2_rd_data_191_128 ( | |
377 | .scan_in(u_l2_rd_data_191_128_scanin), | |
378 | .scan_out(u_l2_rd_data_191_128_scanout), | |
379 | .clk ( l2clk ), | |
380 | .en ( ddr_cmp_sync_en ), | |
381 | .din ( {rddata[191:128], dr_mecc_err[1] } ), | |
382 | .dout ( {l2_rddata[191:128], l2_mecc_err[1]} ), | |
383 | .se(se), | |
384 | .siclk(siclk), | |
385 | .soclk(soclk), | |
386 | .pce_ov(pce_ov), | |
387 | .stop(stop)); | |
388 | ||
389 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_65 u_l2_rd_data_127_64 ( | |
390 | .scan_in(u_l2_rd_data_127_64_scanin), | |
391 | .scan_out(u_l2_rd_data_127_64_scanout), | |
392 | .clk ( l2clk ), | |
393 | .en ( ddr_cmp_sync_en ), | |
394 | .din ( {rddata[127:64], dr_secc_err[0] } ), | |
395 | .dout ( {l2_rddata[127:64], l2_secc_err[0]} ), | |
396 | .se(se), | |
397 | .siclk(siclk), | |
398 | .soclk(soclk), | |
399 | .pce_ov(pce_ov), | |
400 | .stop(stop)); | |
401 | ||
402 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_65 u_l2_rd_data_64_0 ( | |
403 | .scan_in(u_l2_rd_data_64_0_scanin), | |
404 | .scan_out(u_l2_rd_data_64_0_scanout), | |
405 | .clk ( l2clk ), | |
406 | .en ( ddr_cmp_sync_en ), | |
407 | .din ( { rddata[63:0], dr_mecc_err[0]} ), | |
408 | .dout ( { l2_rddata[63:0], l2_mecc_err[0] } ), | |
409 | .se(se), | |
410 | .siclk(siclk), | |
411 | .soclk(soclk), | |
412 | .pce_ov(pce_ov), | |
413 | .stop(stop)); | |
414 | ||
415 | // | |
416 | // Multiplex between two incoming data streams and | |
417 | // delay memory read data to L2 for 2 l2clk cycles | |
418 | // | |
419 | mcu_l2rdmx_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_65 u_l2_rd_data_127_64_dly1 ( | |
420 | .scan_in(u_l2_rd_data_127_64_dly1_scanin), | |
421 | .scan_out(u_l2_rd_data_127_64_dly1_scanout), | |
422 | .clk ( l2clk ), | |
423 | .en ( 1'b1 ), | |
424 | .din0 ( { l2_rddata[127:64], l2_secc_err[1] } ), | |
425 | .din1 ( { l2_rddata[255:192], l2_secc_err[0] } ), | |
426 | .sel0 ( rddata_sel[0] ), | |
427 | .sel1 ( rddata_sel[1] ), | |
428 | .dout ( { l2_rddata_dly1[127:64], l2_secc_err_dly1 } ), | |
429 | .se(se), | |
430 | .siclk(siclk), | |
431 | .soclk(soclk), | |
432 | .pce_ov(pce_ov), | |
433 | .stop(stop)); | |
434 | ||
435 | mcu_l2rdmx_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_65 u_l2_rd_data_64_0_dly1 ( | |
436 | .scan_in(u_l2_rd_data_64_0_dly1_scanin), | |
437 | .scan_out(u_l2_rd_data_64_0_dly1_scanout), | |
438 | .clk ( l2clk ), | |
439 | .en ( 1'b1 ), | |
440 | .din0 ( { l2_rddata[63:0], l2_mecc_err[1]} ), | |
441 | .din1 ( { l2_rddata[191:128], l2_mecc_err[0]} ), | |
442 | .sel0 ( rddata_sel[0] ), | |
443 | .sel1 ( rddata_sel[1] ), | |
444 | .dout ( { l2_rddata_dly1[63:0], l2_mecc_err_dly1 } ), | |
445 | .se(se), | |
446 | .siclk(siclk), | |
447 | .soclk(soclk), | |
448 | .pce_ov(pce_ov), | |
449 | .stop(stop)); | |
450 | ||
451 | // | |
452 | // Second memory read delay cycle | |
453 | // | |
454 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_65 u_l2_rd_data_127_64_dly2 ( | |
455 | .scan_in(u_l2_rd_data_127_64_dly2_scanin), | |
456 | .scan_out(u_l2_rd_data_127_64_dly2_scanout), | |
457 | .clk ( l2clk ), | |
458 | .en ( 1'b1 ), | |
459 | .din ( { l2_rddata_dly1[127:64], l2_secc_err_dly1 } ), | |
460 | .dout ( { l2_rddata_dly2[127:64], l2_secc_err_dly2 } ), | |
461 | .se(se), | |
462 | .siclk(siclk), | |
463 | .soclk(soclk), | |
464 | .pce_ov(pce_ov), | |
465 | .stop(stop)); | |
466 | ||
467 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_65 u_l2_rd_data_64_0_dly2 ( | |
468 | .scan_in(u_l2_rd_data_64_0_dly2_scanin), | |
469 | .scan_out(u_l2_rd_data_64_0_dly2_scanout), | |
470 | .clk ( l2clk ), | |
471 | .en ( 1'b1 ), | |
472 | .din ( { l2_rddata_dly1[63:0], l2_mecc_err_dly1 } ), | |
473 | .dout ( { l2_rddata_dly2[63:0], l2_mecc_err_dly2 } ), | |
474 | .se(se), | |
475 | .siclk(siclk), | |
476 | .soclk(soclk), | |
477 | .pce_ov(pce_ov), | |
478 | .stop(stop)); | |
479 | ||
480 | // | |
481 | // Generate L2 parity. Flip 2 low order parity[1:0] incase of mecc_err | |
482 | // | |
483 | mcu_l2ecc_dp u_l2ecc_6_0 ( | |
484 | .din ( l2_rddata_dly2[31:0] ), | |
485 | .mecc_err ( l2_mecc_err_dly2 ), | |
486 | .pa_err ( pa_err ), | |
487 | .parity ( l2_ecc[6:0] )); | |
488 | ||
489 | mcu_l2ecc_dp u_l2ecc_13_7 ( | |
490 | .din ( l2_rddata_dly2[63:32] ), | |
491 | .mecc_err ( l2_mecc_err_dly2 ), | |
492 | .pa_err ( pa_err ), | |
493 | .parity ( l2_ecc[13:7] )); | |
494 | ||
495 | mcu_l2ecc_dp u_l2ecc_20_14 ( | |
496 | .din ( l2_rddata_dly2[95:64] ), | |
497 | .mecc_err ( l2_mecc_err_dly2 ), | |
498 | .pa_err ( pa_err ), | |
499 | .parity ( l2_ecc[20:14] )); | |
500 | ||
501 | mcu_l2ecc_dp u_l2ecc_27_21 ( | |
502 | .din ( l2_rddata_dly2[127:96]), | |
503 | .mecc_err ( l2_mecc_err_dly2 ), | |
504 | .pa_err ( pa_err ), | |
505 | .parity ( l2_ecc[27:21])); | |
506 | ||
507 | // | |
508 | // L2 read data registers | |
509 | // | |
510 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_64 u_rddata_127_64_p3 ( | |
511 | .scan_in(u_rddata_127_64_p3_scanin), | |
512 | .scan_out(u_rddata_127_64_p3_scanout), | |
513 | .clk ( l2clk ), | |
514 | .en ( 1'b1 ), | |
515 | .din ( l2_rddata_dly2[127:64] ), | |
516 | .dout ( mcu_rddata[127:64] ), | |
517 | .se(se), | |
518 | .siclk(siclk), | |
519 | .soclk(soclk), | |
520 | .pce_ov(pce_ov), | |
521 | .stop(stop)); | |
522 | ||
523 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_64 u_rddata_63_0_p3 ( | |
524 | .scan_in(u_rddata_63_0_p3_scanin), | |
525 | .scan_out(u_rddata_63_0_p3_scanout), | |
526 | .clk ( l2clk ), | |
527 | .en ( 1'b1 ), | |
528 | .din ( l2_rddata_dly2[63:0] ), | |
529 | .dout ( mcu_rddata[63:0] ), | |
530 | .se(se), | |
531 | .siclk(siclk), | |
532 | .soclk(soclk), | |
533 | .pce_ov(pce_ov), | |
534 | .stop(stop)); | |
535 | ||
536 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_64 u_l2ecc_mbist_wdata ( | |
537 | .scan_in(u_l2ecc_mbist_wdata_scanin), | |
538 | .scan_out(u_l2ecc_mbist_wdata_scanout), | |
539 | .clk ( l2clk ), | |
540 | .en ( 1'b1 ), | |
541 | .din ( {25'h0, l2_ecc[27:0], mbist_wdata[7:0], ddr_cmp_sync_en, ddr_cmp_sync_en_d1, ddr_cmp_sync_en_d01} ), | |
542 | .dout ( {spare[24:0], mcu_rdecc[27:0], mbist_wdata_d1[7:0], ddr_cmp_sync_en_d1, ddr_cmp_sync_en_d2, ddr_cmp_sync_en_d12} ), | |
543 | .se(se), | |
544 | .siclk(siclk), | |
545 | .soclk(soclk), | |
546 | .pce_ov(pce_ov), | |
547 | .stop(stop)); | |
548 | ||
549 | // | |
550 | // Data valid, req ID and qword ID to l2t | |
551 | // | |
552 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_6 u_l2t_cntl ( | |
553 | .scan_in(u_l2t_cntl_scanin), | |
554 | .scan_out(u_l2t_cntl_scanout), | |
555 | .clk ( l2clk ), | |
556 | .en ( ddr_cmp_sync_en ), | |
557 | .din ( {rdpctl_l2t0_data_valid, rdpctl_l2t1_data_valid, rdpctl_qword_id, rdpctl_rd_req_id[2:0]} ), | |
558 | .dout ( {l2rdmx_l2t0_data_valid, l2rdmx_l2t1_data_valid, l2rdmx_qword_id, l2rdmx_rd_req_id[2:0]} ), | |
559 | .se(se), | |
560 | .siclk(siclk), | |
561 | .soclk(soclk), | |
562 | .pce_ov(pce_ov), | |
563 | .stop(stop)); | |
564 | ||
565 | //assign mcu_l2t0_rd_req_id_r0[2:0] = l2rdmx_rd_req_id[2:0]; | |
566 | //assign mcu_l2t1_rd_req_id_r0[2:0] = l2rdmx_rd_req_id[2:0]; | |
567 | //assign mcu_l2t0_qword_id_r0[1] = l2rdmx_qword_id; | |
568 | //assign mcu_l2t1_qword_id_r0[1] = l2rdmx_qword_id; | |
569 | ||
570 | mcu_l2rdmx_dp_buff_macro__width_6 u_req_id_buf ( | |
571 | .din ( {l2rdmx_rd_req_id[2:0], l2rdmx_rd_req_id[2:0]} ), | |
572 | .dout( {mcu_l2t0_rd_req_id_r0[2:0], mcu_l2t1_rd_req_id_r0[2:0]} )); | |
573 | ||
574 | mcu_l2rdmx_dp_buff_macro__width_2 u_qword_id_buf ( | |
575 | .din ( {l2rdmx_qword_id, l2rdmx_qword_id} ), | |
576 | .dout( {mcu_l2t0_qword_id_r0[1], mcu_l2t1_qword_id_r0[1]} )); | |
577 | ||
578 | mcu_l2rdmx_dp_and_macro__width_4 u_l2t_data_valid ( | |
579 | .din0( {l2rdmx_l2t0_data_valid, l2rdmx_l2t0_data_valid, l2rdmx_l2t1_data_valid, l2rdmx_l2t1_data_valid} ), | |
580 | .din1( {ddr_cmp_sync_en_d2, ddr_cmp_sync_en_d12, ddr_cmp_sync_en_d2, ddr_cmp_sync_en_d12 } ), | |
581 | .dout( {mcu_l2t0_qword_id_r0[0], mcu_l2t0_data_vld_r0, mcu_l2t1_qword_id_r0[0], mcu_l2t1_data_vld_r0 } )); | |
582 | ||
583 | mcu_l2rdmx_dp_or_macro u_ddr_cmp_sync_en_d01 ( | |
584 | .din0( ddr_cmp_sync_en ), | |
585 | .din1( ddr_cmp_sync_en_d1 ), | |
586 | .dout( ddr_cmp_sync_en_d01 )); | |
587 | ||
588 | mcu_l2rdmx_dp_nand_macro__width_14 spare_nand ( | |
589 | .din0( 14'h0 ), | |
590 | .din1( 14'h0 ), | |
591 | .dout( spare_nand_unused[13:0] )); | |
592 | ||
593 | // | |
594 | // address to addrdp | |
595 | // | |
596 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_52 u_l2if0_ras_cas_addr ( | |
597 | .scan_in(u_l2if0_ras_cas_addr_scanin), | |
598 | .scan_out(u_l2if0_ras_cas_addr_scanout), | |
599 | .clk ( l2clk ), | |
600 | .en ( cmp_ddr_sync_en ), | |
601 | .din ( {l2if0_rd_ras_adr[14:0], l2if0_rd_cas_adr[10:0], l2if0_wr_ras_adr[14:0], l2if0_wr_cas_adr[10:0]} ), | |
602 | .dout ( {l2b0_rd_ras_adr[14:0], l2b0_rd_cas_adr[10:0], l2b0_wr_ras_adr[14:0], l2b0_wr_cas_adr[10:0]}), | |
603 | .se(se), | |
604 | .siclk(siclk), | |
605 | .soclk(soclk), | |
606 | .pce_ov(pce_ov), | |
607 | .stop(stop)); | |
608 | ||
609 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_52 u_l2if1_ras_cas_addr ( | |
610 | .scan_in(u_l2if1_ras_cas_addr_scanin), | |
611 | .scan_out(u_l2if1_ras_cas_addr_scanout), | |
612 | .clk ( l2clk ), | |
613 | .en ( cmp_ddr_sync_en ), | |
614 | .din ( {l2if1_rd_ras_adr[14:0], l2if1_rd_cas_adr[10:0], l2if1_wr_ras_adr[14:0], l2if1_wr_cas_adr[10:0]} ), | |
615 | .dout ( {l2b1_rd_ras_adr[14:0], l2b1_rd_cas_adr[10:0], l2b1_wr_ras_adr[14:0], l2b1_wr_cas_adr[10:0]}), | |
616 | .se(se), | |
617 | .siclk(siclk), | |
618 | .soclk(soclk), | |
619 | .pce_ov(pce_ov), | |
620 | .stop(stop)); | |
621 | ||
622 | mcu_l2rdmx_dp_msff_macro__stack_66c__width_42 u_l2if_bank_rank_addr ( | |
623 | .scan_in(u_l2if_bank_rank_addr_scanin), | |
624 | .scan_out(u_l2if_bank_rank_addr_scanout), | |
625 | .clk ( l2clk ), | |
626 | .en ( cmp_ddr_sync_en ), | |
627 | .din ( {l2if0_rd_rank_adr, l2if0_rd_dimm_adr[2:0], l2if0_rd_bank_adr[2:0], l2if0_rd_addr_parity, l2if0_rd_addr_err, l2if0_rd_req_id[2:0], | |
628 | l2if1_rd_rank_adr, l2if1_rd_dimm_adr[2:0], l2if1_rd_bank_adr[2:0], l2if1_rd_addr_parity, l2if1_rd_addr_err, l2if1_rd_req_id[2:0], | |
629 | l2if0_wr_rank_adr, l2if0_wr_dimm_adr[2:0], l2if0_wr_bank_adr[2:0], l2if0_wr_addr_parity, l2if0_wr_addr_err, | |
630 | l2if1_wr_rank_adr, l2if1_wr_dimm_adr[2:0], l2if1_wr_bank_adr[2:0], l2if1_wr_addr_parity, l2if1_wr_addr_err} ), | |
631 | .dout ( {l2b0_rd_rank_adr, l2b0_rd_dimm_adr[2:0], l2b0_rd_bank_adr[2:0], l2b0_rd_addr_par, l2b0_rd_addr_err, l2b0_l2rd_req_id[2:0], | |
632 | l2b1_rd_rank_adr, l2b1_rd_dimm_adr[2:0], l2b1_rd_bank_adr[2:0], l2b1_rd_addr_par, l2b1_rd_addr_err, l2b1_l2rd_req_id[2:0], | |
633 | l2b0_wr_rank_adr, l2b0_wr_dimm_adr[2:0], l2b0_wr_bank_adr[2:0], l2b0_wr_addr_par, l2b0_wr_addr_err, | |
634 | l2b1_wr_rank_adr, l2b1_wr_dimm_adr[2:0], l2b1_wr_bank_adr[2:0], l2b1_wr_addr_par, l2b1_wr_addr_err} ), | |
635 | .se(se), | |
636 | .siclk(siclk), | |
637 | .soclk(soclk), | |
638 | .pce_ov(pce_ov), | |
639 | .stop(stop)); | |
640 | ||
641 | ||
642 | // fixscan start: | |
643 | assign u_bank0_l2wr_data_scanin = scan_in ; | |
644 | assign u_bank1_l2wr_data_scanin = u_bank0_l2wr_data_scanout; | |
645 | assign u_l2_rd_data_255_192_scanin = u_bank1_l2wr_data_scanout; | |
646 | assign u_l2_rd_data_191_128_scanin = u_l2_rd_data_255_192_scanout; | |
647 | assign u_l2_rd_data_127_64_scanin = u_l2_rd_data_191_128_scanout; | |
648 | assign u_l2_rd_data_64_0_scanin = u_l2_rd_data_127_64_scanout; | |
649 | assign u_l2_rd_data_127_64_dly1_scanin = u_l2_rd_data_64_0_scanout; | |
650 | assign u_l2_rd_data_64_0_dly1_scanin = u_l2_rd_data_127_64_dly1_scanout; | |
651 | assign u_l2_rd_data_127_64_dly2_scanin = u_l2_rd_data_64_0_dly1_scanout; | |
652 | assign u_l2_rd_data_64_0_dly2_scanin = u_l2_rd_data_127_64_dly2_scanout; | |
653 | assign u_rddata_127_64_p3_scanin = u_l2_rd_data_64_0_dly2_scanout; | |
654 | assign u_rddata_63_0_p3_scanin = u_rddata_127_64_p3_scanout; | |
655 | assign u_l2ecc_mbist_wdata_scanin = u_rddata_63_0_p3_scanout ; | |
656 | assign u_l2t_cntl_scanin = u_l2ecc_mbist_wdata_scanout; | |
657 | assign u_l2if0_ras_cas_addr_scanin = u_l2t_cntl_scanout ; | |
658 | assign u_l2if1_ras_cas_addr_scanin = u_l2if0_ras_cas_addr_scanout; | |
659 | assign u_l2if_bank_rank_addr_scanin = u_l2if1_ras_cas_addr_scanout; | |
660 | assign scan_out = u_l2if_bank_rank_addr_scanout; | |
661 | // fixscan end: | |
662 | endmodule // mcu_readdp_dp; | |
663 | ||
664 | ||
665 | ||
666 | ||
667 | ||
668 | ||
669 | ||
670 | // any PARAMS parms go into naming of macro | |
671 | ||
672 | module mcu_l2rdmx_dp_msff_macro__stack_66c__width_64 ( | |
673 | din, | |
674 | clk, | |
675 | en, | |
676 | se, | |
677 | scan_in, | |
678 | siclk, | |
679 | soclk, | |
680 | pce_ov, | |
681 | stop, | |
682 | dout, | |
683 | scan_out); | |
684 | wire l1clk; | |
685 | wire siclk_out; | |
686 | wire soclk_out; | |
687 | wire [62:0] so; | |
688 | ||
689 | input [63:0] din; | |
690 | ||
691 | ||
692 | input clk; | |
693 | input en; | |
694 | input se; | |
695 | input scan_in; | |
696 | input siclk; | |
697 | input soclk; | |
698 | input pce_ov; | |
699 | input stop; | |
700 | ||
701 | ||
702 | ||
703 | output [63:0] dout; | |
704 | ||
705 | ||
706 | output scan_out; | |
707 | ||
708 | ||
709 | ||
710 | ||
711 | cl_dp1_l1hdr_8x c0_0 ( | |
712 | .l2clk(clk), | |
713 | .pce(en), | |
714 | .aclk(siclk), | |
715 | .bclk(soclk), | |
716 | .l1clk(l1clk), | |
717 | .se(se), | |
718 | .pce_ov(pce_ov), | |
719 | .stop(stop), | |
720 | .siclk_out(siclk_out), | |
721 | .soclk_out(soclk_out) | |
722 | ); | |
723 | dff #(64) d0_0 ( | |
724 | .l1clk(l1clk), | |
725 | .siclk(siclk_out), | |
726 | .soclk(soclk_out), | |
727 | .d(din[63:0]), | |
728 | .si({scan_in,so[62:0]}), | |
729 | .so({so[62:0],scan_out}), | |
730 | .q(dout[63:0]) | |
731 | ); | |
732 | ||
733 | ||
734 | ||
735 | ||
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | ||
744 | ||
745 | ||
746 | ||
747 | ||
748 | ||
749 | ||
750 | ||
751 | ||
752 | endmodule | |
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | ||
760 | ||
761 | ||
762 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
763 | // also for pass-gate with decoder | |
764 | ||
765 | ||
766 | ||
767 | ||
768 | ||
769 | // any PARAMS parms go into naming of macro | |
770 | ||
771 | module mcu_l2rdmx_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_64 ( | |
772 | din0, | |
773 | sel0, | |
774 | din1, | |
775 | sel1, | |
776 | dout); | |
777 | wire buffout0; | |
778 | wire buffout1; | |
779 | ||
780 | input [63:0] din0; | |
781 | input sel0; | |
782 | input [63:0] din1; | |
783 | input sel1; | |
784 | output [63:0] dout; | |
785 | ||
786 | ||
787 | ||
788 | ||
789 | ||
790 | cl_dp1_muxbuff2_8x c0_0 ( | |
791 | .in0(sel0), | |
792 | .in1(sel1), | |
793 | .out0(buffout0), | |
794 | .out1(buffout1) | |
795 | ); | |
796 | mux2s #(64) d0_0 ( | |
797 | .sel0(buffout0), | |
798 | .sel1(buffout1), | |
799 | .in0(din0[63:0]), | |
800 | .in1(din1[63:0]), | |
801 | .dout(dout[63:0]) | |
802 | ); | |
803 | ||
804 | ||
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | ||
813 | ||
814 | ||
815 | ||
816 | endmodule | |
817 | ||
818 | ||
819 | ||
820 | ||
821 | ||
822 | ||
823 | // any PARAMS parms go into naming of macro | |
824 | ||
825 | module mcu_l2rdmx_dp_msff_macro__stack_66c__width_65 ( | |
826 | din, | |
827 | clk, | |
828 | en, | |
829 | se, | |
830 | scan_in, | |
831 | siclk, | |
832 | soclk, | |
833 | pce_ov, | |
834 | stop, | |
835 | dout, | |
836 | scan_out); | |
837 | wire l1clk; | |
838 | wire siclk_out; | |
839 | wire soclk_out; | |
840 | wire [63:0] so; | |
841 | ||
842 | input [64:0] din; | |
843 | ||
844 | ||
845 | input clk; | |
846 | input en; | |
847 | input se; | |
848 | input scan_in; | |
849 | input siclk; | |
850 | input soclk; | |
851 | input pce_ov; | |
852 | input stop; | |
853 | ||
854 | ||
855 | ||
856 | output [64:0] dout; | |
857 | ||
858 | ||
859 | output scan_out; | |
860 | ||
861 | ||
862 | ||
863 | ||
864 | cl_dp1_l1hdr_8x c0_0 ( | |
865 | .l2clk(clk), | |
866 | .pce(en), | |
867 | .aclk(siclk), | |
868 | .bclk(soclk), | |
869 | .l1clk(l1clk), | |
870 | .se(se), | |
871 | .pce_ov(pce_ov), | |
872 | .stop(stop), | |
873 | .siclk_out(siclk_out), | |
874 | .soclk_out(soclk_out) | |
875 | ); | |
876 | dff #(65) d0_0 ( | |
877 | .l1clk(l1clk), | |
878 | .siclk(siclk_out), | |
879 | .soclk(soclk_out), | |
880 | .d(din[64:0]), | |
881 | .si({scan_in,so[63:0]}), | |
882 | .so({so[63:0],scan_out}), | |
883 | .q(dout[64:0]) | |
884 | ); | |
885 | ||
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | ||
894 | ||
895 | ||
896 | ||
897 | ||
898 | ||
899 | ||
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | endmodule | |
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | ||
916 | ||
917 | ||
918 | ||
919 | // any PARAMS parms go into naming of macro | |
920 | ||
921 | module mcu_l2rdmx_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_65 ( | |
922 | din0, | |
923 | sel0, | |
924 | din1, | |
925 | sel1, | |
926 | clk, | |
927 | en, | |
928 | se, | |
929 | scan_in, | |
930 | siclk, | |
931 | soclk, | |
932 | pce_ov, | |
933 | stop, | |
934 | dout, | |
935 | scan_out); | |
936 | wire buffout0; | |
937 | wire buffout1; | |
938 | wire [64:0] muxout; | |
939 | wire l1clk; | |
940 | wire siclk_out; | |
941 | wire soclk_out; | |
942 | wire [63:0] so; | |
943 | ||
944 | input [64:0] din0; | |
945 | input sel0; | |
946 | input [64:0] din1; | |
947 | input sel1; | |
948 | ||
949 | ||
950 | input clk; | |
951 | input en; | |
952 | input se; | |
953 | input scan_in; | |
954 | input siclk; | |
955 | input soclk; | |
956 | input pce_ov; | |
957 | input stop; | |
958 | ||
959 | ||
960 | ||
961 | output [64:0] dout; | |
962 | ||
963 | ||
964 | output scan_out; | |
965 | ||
966 | ||
967 | ||
968 | ||
969 | cl_dp1_muxbuff2_8x c1_0 ( | |
970 | .in0(sel0), | |
971 | .in1(sel1), | |
972 | .out0(buffout0), | |
973 | .out1(buffout1) | |
974 | ); | |
975 | mux2s #(65) d1_0 ( | |
976 | .sel0(buffout0), | |
977 | .sel1(buffout1), | |
978 | .in0(din0[64:0]), | |
979 | .in1(din1[64:0]), | |
980 | .dout(muxout[64:0]) | |
981 | ); | |
982 | cl_dp1_l1hdr_8x c0_0 ( | |
983 | .l2clk(clk), | |
984 | .pce(en), | |
985 | .aclk(siclk), | |
986 | .bclk(soclk), | |
987 | .l1clk(l1clk), | |
988 | .se(se), | |
989 | .pce_ov(pce_ov), | |
990 | .stop(stop), | |
991 | .siclk_out(siclk_out), | |
992 | .soclk_out(soclk_out) | |
993 | ); | |
994 | dff #(65) d0_0 ( | |
995 | .l1clk(l1clk), | |
996 | .siclk(siclk_out), | |
997 | .soclk(soclk_out), | |
998 | .d(muxout[64:0]), | |
999 | .si({scan_in,so[63:0]}), | |
1000 | .so({so[63:0],scan_out}), | |
1001 | .q(dout[64:0]) | |
1002 | ); | |
1003 | ||
1004 | ||
1005 | endmodule | |
1006 | ||
1007 | ||
1008 | ||
1009 | // | |
1010 | // or macro for ports = 2,3 | |
1011 | // | |
1012 | // | |
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | module mcu_l2rdmx_dp_or_macro__ports_2__width_1 ( | |
1019 | din0, | |
1020 | din1, | |
1021 | dout); | |
1022 | input [0:0] din0; | |
1023 | input [0:0] din1; | |
1024 | output [0:0] dout; | |
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | or2 #(1) d0_0 ( | |
1032 | .in0(din0[0:0]), | |
1033 | .in1(din1[0:0]), | |
1034 | .out(dout[0:0]) | |
1035 | ); | |
1036 | ||
1037 | ||
1038 | ||
1039 | ||
1040 | ||
1041 | ||
1042 | ||
1043 | ||
1044 | ||
1045 | endmodule | |
1046 | ||
1047 | ||
1048 | ||
1049 | ||
1050 | ||
1051 | // | |
1052 | // xor macro for ports = 2,3 | |
1053 | // | |
1054 | // | |
1055 | ||
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | module mcu_l2rdmx_dp_xor_macro__ports_3__width_1 ( | |
1061 | din0, | |
1062 | din1, | |
1063 | din2, | |
1064 | dout); | |
1065 | input [0:0] din0; | |
1066 | input [0:0] din1; | |
1067 | input [0:0] din2; | |
1068 | output [0:0] dout; | |
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | xor3 #(1) d0_0 ( | |
1075 | .in0(din0[0:0]), | |
1076 | .in1(din1[0:0]), | |
1077 | .in2(din2[0:0]), | |
1078 | .out(dout[0:0]) | |
1079 | ); | |
1080 | ||
1081 | ||
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | endmodule | |
1089 | ||
1090 | ||
1091 | ||
1092 | ||
1093 | ||
1094 | // | |
1095 | // xor macro for ports = 2,3 | |
1096 | // | |
1097 | // | |
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | module mcu_l2rdmx_dp_xor_macro__ports_2__width_1 ( | |
1104 | din0, | |
1105 | din1, | |
1106 | dout); | |
1107 | input [0:0] din0; | |
1108 | input [0:0] din1; | |
1109 | output [0:0] dout; | |
1110 | ||
1111 | ||
1112 | ||
1113 | ||
1114 | ||
1115 | xor2 #(1) d0_0 ( | |
1116 | .in0(din0[0:0]), | |
1117 | .in1(din1[0:0]), | |
1118 | .out(dout[0:0]) | |
1119 | ); | |
1120 | ||
1121 | ||
1122 | ||
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | endmodule | |
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | // any PARAMS parms go into naming of macro | |
1139 | ||
1140 | module mcu_l2rdmx_dp_msff_macro__stack_66c__width_6 ( | |
1141 | din, | |
1142 | clk, | |
1143 | en, | |
1144 | se, | |
1145 | scan_in, | |
1146 | siclk, | |
1147 | soclk, | |
1148 | pce_ov, | |
1149 | stop, | |
1150 | dout, | |
1151 | scan_out); | |
1152 | wire l1clk; | |
1153 | wire siclk_out; | |
1154 | wire soclk_out; | |
1155 | wire [4:0] so; | |
1156 | ||
1157 | input [5:0] din; | |
1158 | ||
1159 | ||
1160 | input clk; | |
1161 | input en; | |
1162 | input se; | |
1163 | input scan_in; | |
1164 | input siclk; | |
1165 | input soclk; | |
1166 | input pce_ov; | |
1167 | input stop; | |
1168 | ||
1169 | ||
1170 | ||
1171 | output [5:0] dout; | |
1172 | ||
1173 | ||
1174 | output scan_out; | |
1175 | ||
1176 | ||
1177 | ||
1178 | ||
1179 | cl_dp1_l1hdr_8x c0_0 ( | |
1180 | .l2clk(clk), | |
1181 | .pce(en), | |
1182 | .aclk(siclk), | |
1183 | .bclk(soclk), | |
1184 | .l1clk(l1clk), | |
1185 | .se(se), | |
1186 | .pce_ov(pce_ov), | |
1187 | .stop(stop), | |
1188 | .siclk_out(siclk_out), | |
1189 | .soclk_out(soclk_out) | |
1190 | ); | |
1191 | dff #(6) d0_0 ( | |
1192 | .l1clk(l1clk), | |
1193 | .siclk(siclk_out), | |
1194 | .soclk(soclk_out), | |
1195 | .d(din[5:0]), | |
1196 | .si({scan_in,so[4:0]}), | |
1197 | .so({so[4:0],scan_out}), | |
1198 | .q(dout[5:0]) | |
1199 | ); | |
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | endmodule | |
1221 | ||
1222 | ||
1223 | ||
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | ||
1229 | ||
1230 | // | |
1231 | // buff macro | |
1232 | // | |
1233 | // | |
1234 | ||
1235 | ||
1236 | ||
1237 | ||
1238 | ||
1239 | module mcu_l2rdmx_dp_buff_macro__width_6 ( | |
1240 | din, | |
1241 | dout); | |
1242 | input [5:0] din; | |
1243 | output [5:0] dout; | |
1244 | ||
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | ||
1250 | buff #(6) d0_0 ( | |
1251 | .in(din[5:0]), | |
1252 | .out(dout[5:0]) | |
1253 | ); | |
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | endmodule | |
1263 | ||
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | // | |
1269 | // buff macro | |
1270 | // | |
1271 | // | |
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | module mcu_l2rdmx_dp_buff_macro__width_2 ( | |
1278 | din, | |
1279 | dout); | |
1280 | input [1:0] din; | |
1281 | output [1:0] dout; | |
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | ||
1288 | buff #(2) d0_0 ( | |
1289 | .in(din[1:0]), | |
1290 | .out(dout[1:0]) | |
1291 | ); | |
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | ||
1299 | ||
1300 | endmodule | |
1301 | ||
1302 | ||
1303 | ||
1304 | ||
1305 | ||
1306 | // | |
1307 | // and macro for ports = 2,3,4 | |
1308 | // | |
1309 | // | |
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | module mcu_l2rdmx_dp_and_macro__width_4 ( | |
1316 | din0, | |
1317 | din1, | |
1318 | dout); | |
1319 | input [3:0] din0; | |
1320 | input [3:0] din1; | |
1321 | output [3:0] dout; | |
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | and2 #(4) d0_0 ( | |
1329 | .in0(din0[3:0]), | |
1330 | .in1(din1[3:0]), | |
1331 | .out(dout[3:0]) | |
1332 | ); | |
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | endmodule | |
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | // | |
1349 | // or macro for ports = 2,3 | |
1350 | // | |
1351 | // | |
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | module mcu_l2rdmx_dp_or_macro ( | |
1358 | din0, | |
1359 | din1, | |
1360 | dout); | |
1361 | input [0:0] din0; | |
1362 | input [0:0] din1; | |
1363 | output [0:0] dout; | |
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | ||
1370 | or2 #(1) d0_0 ( | |
1371 | .in0(din0[0:0]), | |
1372 | .in1(din1[0:0]), | |
1373 | .out(dout[0:0]) | |
1374 | ); | |
1375 | ||
1376 | ||
1377 | ||
1378 | ||
1379 | ||
1380 | ||
1381 | ||
1382 | ||
1383 | ||
1384 | endmodule | |
1385 | ||
1386 | ||
1387 | ||
1388 | ||
1389 | ||
1390 | // | |
1391 | // nand macro for ports = 2,3,4 | |
1392 | // | |
1393 | // | |
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | module mcu_l2rdmx_dp_nand_macro__width_14 ( | |
1400 | din0, | |
1401 | din1, | |
1402 | dout); | |
1403 | input [13:0] din0; | |
1404 | input [13:0] din1; | |
1405 | output [13:0] dout; | |
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | nand2 #(14) d0_0 ( | |
1413 | .in0(din0[13:0]), | |
1414 | .in1(din1[13:0]), | |
1415 | .out(dout[13:0]) | |
1416 | ); | |
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | endmodule | |
1427 | ||
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | ||
1435 | ||
1436 | // any PARAMS parms go into naming of macro | |
1437 | ||
1438 | module mcu_l2rdmx_dp_msff_macro__stack_66c__width_52 ( | |
1439 | din, | |
1440 | clk, | |
1441 | en, | |
1442 | se, | |
1443 | scan_in, | |
1444 | siclk, | |
1445 | soclk, | |
1446 | pce_ov, | |
1447 | stop, | |
1448 | dout, | |
1449 | scan_out); | |
1450 | wire l1clk; | |
1451 | wire siclk_out; | |
1452 | wire soclk_out; | |
1453 | wire [50:0] so; | |
1454 | ||
1455 | input [51:0] din; | |
1456 | ||
1457 | ||
1458 | input clk; | |
1459 | input en; | |
1460 | input se; | |
1461 | input scan_in; | |
1462 | input siclk; | |
1463 | input soclk; | |
1464 | input pce_ov; | |
1465 | input stop; | |
1466 | ||
1467 | ||
1468 | ||
1469 | output [51:0] dout; | |
1470 | ||
1471 | ||
1472 | output scan_out; | |
1473 | ||
1474 | ||
1475 | ||
1476 | ||
1477 | cl_dp1_l1hdr_8x c0_0 ( | |
1478 | .l2clk(clk), | |
1479 | .pce(en), | |
1480 | .aclk(siclk), | |
1481 | .bclk(soclk), | |
1482 | .l1clk(l1clk), | |
1483 | .se(se), | |
1484 | .pce_ov(pce_ov), | |
1485 | .stop(stop), | |
1486 | .siclk_out(siclk_out), | |
1487 | .soclk_out(soclk_out) | |
1488 | ); | |
1489 | dff #(52) d0_0 ( | |
1490 | .l1clk(l1clk), | |
1491 | .siclk(siclk_out), | |
1492 | .soclk(soclk_out), | |
1493 | .d(din[51:0]), | |
1494 | .si({scan_in,so[50:0]}), | |
1495 | .so({so[50:0],scan_out}), | |
1496 | .q(dout[51:0]) | |
1497 | ); | |
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | ||
1511 | ||
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | endmodule | |
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | // any PARAMS parms go into naming of macro | |
1533 | ||
1534 | module mcu_l2rdmx_dp_msff_macro__stack_66c__width_42 ( | |
1535 | din, | |
1536 | clk, | |
1537 | en, | |
1538 | se, | |
1539 | scan_in, | |
1540 | siclk, | |
1541 | soclk, | |
1542 | pce_ov, | |
1543 | stop, | |
1544 | dout, | |
1545 | scan_out); | |
1546 | wire l1clk; | |
1547 | wire siclk_out; | |
1548 | wire soclk_out; | |
1549 | wire [40:0] so; | |
1550 | ||
1551 | input [41:0] din; | |
1552 | ||
1553 | ||
1554 | input clk; | |
1555 | input en; | |
1556 | input se; | |
1557 | input scan_in; | |
1558 | input siclk; | |
1559 | input soclk; | |
1560 | input pce_ov; | |
1561 | input stop; | |
1562 | ||
1563 | ||
1564 | ||
1565 | output [41:0] dout; | |
1566 | ||
1567 | ||
1568 | output scan_out; | |
1569 | ||
1570 | ||
1571 | ||
1572 | ||
1573 | cl_dp1_l1hdr_8x c0_0 ( | |
1574 | .l2clk(clk), | |
1575 | .pce(en), | |
1576 | .aclk(siclk), | |
1577 | .bclk(soclk), | |
1578 | .l1clk(l1clk), | |
1579 | .se(se), | |
1580 | .pce_ov(pce_ov), | |
1581 | .stop(stop), | |
1582 | .siclk_out(siclk_out), | |
1583 | .soclk_out(soclk_out) | |
1584 | ); | |
1585 | dff #(42) d0_0 ( | |
1586 | .l1clk(l1clk), | |
1587 | .siclk(siclk_out), | |
1588 | .soclk(soclk_out), | |
1589 | .d(din[41:0]), | |
1590 | .si({scan_in,so[40:0]}), | |
1591 | .so({so[40:0],scan_out}), | |
1592 | .q(dout[41:0]) | |
1593 | ); | |
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | ||
1610 | ||
1611 | ||
1612 | ||
1613 | ||
1614 | endmodule | |
1615 | ||
1616 | ||
1617 | ||
1618 | ||
1619 | ||
1620 | ||
1621 | ||
1622 |