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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: MDIO2P.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | //////////////////////////////////////////////////////////////////////////////// | |
36 | // | |
37 | // Copyright (c) 2002 Texas Instruments, Inc. | |
38 | // All rights reserved | |
39 | // | |
40 | // This is an unpublished work created in the year stated above. | |
41 | // Texas Instruments owns all rights in and to the work and intends to | |
42 | // maintain it and protect it as unpublished copyright. In the event | |
43 | // of either inadvertant or deliberate publication, the above stated | |
44 | // date shall be treated as the year of first publication. In the event | |
45 | // of such publication, Texas Instruments intends to enforce its rights | |
46 | // in the work under the copyright laws as a published work. | |
47 | // | |
48 | // These commodities are under U.S. Government distribution license | |
49 | // control. As such, they are not be re-exported without prior approval | |
50 | // from the U.S. Department of Commerce. | |
51 | // | |
52 | //////////////////////////////////////////////////////////////////////////////// | |
53 | ||
54 | //////////////////////////////////////////////////////////////////////////////// | |
55 | // | |
56 | // FUNCTION: MDIO Interface to Serial Test and Configuration Interface | |
57 | // Top Level | |
58 | // COMMENTS: Allows devices on STCI scan chain to be accessed using an | |
59 | // MDIO interface. Connects to P2STCI using SRAM like interface, | |
60 | // synchronous to MDCLK: | |
61 | // | |
62 | // ____ ____ ___ | |
63 | // MDCLK ___/ \____/ \____/ | |
64 | // _________ | |
65 | // PW XXXXX_________/ XXX | |
66 | // _________ _________ | |
67 | // PA XXXXX____A1___X____A2___XXX | |
68 | // _________ | |
69 | // PR XXXXX_________/ XXX | |
70 | // _________ | |
71 | // PQ XXXXXXXXXXXXXXX____Q1___XXX | |
72 | // ___ | |
73 | // PD XXXXXXXXXXXXXXXXXXXXX<D2_>X | |
74 | // | |
75 | // VERSION: #VERSION# | |
76 | // DATE: #DATE# | |
77 | // | |
78 | //////////////////////////////////////////////////////////////////////////////// | |
79 | ||
80 | `timescale 1ns / 1ps | |
81 | ||
82 | module MDIO2P | |
83 | ( | |
84 | ||
85 | tcu_clk_stop, | |
86 | tcu_scan_mode, | |
87 | io_mdclk, | |
88 | ||
89 | RESET, | |
90 | MDCLK, | |
91 | MDIN, | |
92 | MDOUT, | |
93 | MDOE, | |
94 | CFG, | |
95 | PD, | |
96 | PW, | |
97 | PR, | |
98 | PA, | |
99 | PQ, | |
100 | SCANEN, | |
101 | SCANCLK | |
102 | ); | |
103 | ||
104 | //////////////////////////////////////////////////////////////////////////////// | |
105 | // | |
106 | // Port Declarations | |
107 | // | |
108 | //////////////////////////////////////////////////////////////////////////////// | |
109 | ||
110 | input tcu_clk_stop; | |
111 | input tcu_scan_mode; | |
112 | output io_mdclk; // clock after scan mux | |
113 | ||
114 | input RESET; // Global reset | |
115 | ||
116 | // Parallel Interface | |
117 | input[15:0] PD; // Data in | |
118 | output PW; // Write enable | |
119 | output PR; // Read indicator | |
120 | output[9:0] PA; // Address | |
121 | output[15:0] PQ; // Data out | |
122 | ||
123 | // MDIO Interface | |
124 | input MDCLK; // Clock | |
125 | input MDIN; // Data in | |
126 | output MDOUT; // Data out | |
127 | output MDOE; // Output enable | |
128 | ||
129 | // Configuration Interface | |
130 | input[15:0] CFG; // Configuration | |
131 | ||
132 | // Scan Interface | |
133 | input SCANEN; // Bypass MDIO2P clocks for scan | |
134 | input SCANCLK; // Scan clock source | |
135 | ||
136 | ||
137 | //////////////////////////////////////////////////////////////////////////////// | |
138 | // | |
139 | // Internal Declarations | |
140 | // | |
141 | //////////////////////////////////////////////////////////////////////////////// | |
142 | ||
143 | // Interface to Framer | |
144 | wire[5:0] frmr_state; // LFSR encoded frame state | |
145 | ||
146 | // Configuration | |
147 | wire io_clause45; // Clause45 | |
148 | wire[4:0] io_prtid; // Port address ID | |
149 | wire[4:0] io_devid; // Device address ID | |
150 | wire[4:0] io_basead; // Base address | |
151 | wire[3:0] io_acrad; // AddrCtl register address | |
152 | wire[3:0] io_iprad; // Indirect port register address | |
153 | ||
154 | // Clocking and reset | |
155 | wire io_mdclk; // Clock | |
156 | wire io_reset; // Reset | |
157 | ||
158 | ||
159 | //////////////////////////////////////////////////////////////////////////////// | |
160 | // | |
161 | // Instances | |
162 | // | |
163 | //////////////////////////////////////////////////////////////////////////////// | |
164 | ||
165 | MDIO2P_IO I_MDIO2P_IO | |
166 | ( | |
167 | ||
168 | .tcu_clk_stop(tcu_clk_stop), | |
169 | .tcu_scan_mode(tcu_scan_mode), | |
170 | ||
171 | .RESET(RESET), | |
172 | .MDCLK(MDCLK), | |
173 | .SCANEN(SCANEN), | |
174 | .SCANCLK(SCANCLK), | |
175 | .CFG(CFG), | |
176 | .IO_MDCLK(io_mdclk), | |
177 | .IO_RESET(io_reset), | |
178 | .IO_CLAUSE45(io_clause45), | |
179 | .IO_PRTID(io_prtid), | |
180 | .IO_DEVID(io_devid), | |
181 | .IO_BASEAD(io_basead), | |
182 | .IO_ACRAD(io_acrad), | |
183 | .IO_IPRAD(io_iprad) | |
184 | ); | |
185 | ||
186 | MDIO2P_FRMR I_MDIO2P_FRMR | |
187 | ( | |
188 | .IO_MDCLK(io_mdclk), | |
189 | .IO_RESET(io_reset), | |
190 | .MDIN(MDIN), | |
191 | .FRMR_STATE(frmr_state) | |
192 | ); | |
193 | ||
194 | MDIO2P_REGS I_MDIO2P_REGS | |
195 | ( | |
196 | .MDIN(MDIN), | |
197 | .MDOUT(MDOUT), | |
198 | .MDOE(MDOE), | |
199 | .IO_MDCLK(io_mdclk), | |
200 | .IO_RESET(io_reset), | |
201 | .IO_CLAUSE45(io_clause45), | |
202 | .IO_PRTID(io_prtid), | |
203 | .IO_DEVID(io_devid), | |
204 | .IO_BASEAD(io_basead), | |
205 | .IO_ACRAD(io_acrad), | |
206 | .IO_IPRAD(io_iprad), | |
207 | .PD(PD), | |
208 | .PW(PW), | |
209 | .PR(PR), | |
210 | .PA(PA), | |
211 | .PQ(PQ), | |
212 | .FRMR_STATE(frmr_state) | |
213 | ); | |
214 | ||
215 | endmodule |