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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fflp_cam_sched.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /**********************************************************************/ | |
36 | /*project name: NIU */ | |
37 | /*module name: fflp_cam_sched */ | |
38 | /*description: Aabitration between CPU access and packet */ | |
39 | /* classification */ | |
40 | /* */ | |
41 | /*parent module in: none */ | |
42 | /*child modules in: none */ | |
43 | /*interface modules: */ | |
44 | /*author name: Jeanne Cai */ | |
45 | /*date created: 16-03-2004 */ | |
46 | /* */ | |
47 | /* Copyright (c) 2004, Sun Microsystems, Inc. */ | |
48 | /* Sun Proprietary and Confidential */ | |
49 | /* */ | |
50 | /*modifications: */ | |
51 | /**********************************************************************/ | |
52 | ||
53 | ||
54 | module fflp_cam_sched | |
55 | ( | |
56 | cclk, | |
57 | reset, | |
58 | cam_srch_latency, | |
59 | cam_srch_ratio, | |
60 | fwd_req, | |
61 | cpu_req_cam_acc, | |
62 | fc_fifo_space_avail, | |
63 | ||
64 | fwd_sched, | |
65 | cpu_sched | |
66 | ); | |
67 | ||
68 | input cclk; | |
69 | input reset; | |
70 | input[3:0] cam_srch_latency; | |
71 | input[3:0] cam_srch_ratio; | |
72 | input fwd_req; | |
73 | input cpu_req_cam_acc; | |
74 | input fc_fifo_space_avail; | |
75 | ||
76 | output fwd_sched; | |
77 | output cpu_sched; | |
78 | ||
79 | reg fwd_sched_sm; | |
80 | reg cpu_sched_sm; | |
81 | reg inc_fwd_wait_cnt; | |
82 | reg reset_fwd_cnt; | |
83 | reg[1:0] next_state; | |
84 | ||
85 | wire fwd_sched; | |
86 | wire cpu_sched; | |
87 | wire[3:0] fwd_wait_cnt_in; | |
88 | wire[3:0] fwd_wait_cnt; | |
89 | wire fwd_sched_cnt_en; | |
90 | wire[3:0] fwd_sched_cnt_in; | |
91 | wire[3:0] fwd_sched_cnt; | |
92 | wire[1:0] state; | |
93 | ||
94 | wire fwd_wait_done; | |
95 | wire fwd_reqs_served; | |
96 | ||
97 | //state machine states | |
98 | parameter | |
99 | FWD_ARB = 2'b00, | |
100 | FWD_IDLE = 2'b01, | |
101 | CPU_ARB = 2'b10, | |
102 | CPU_IDLE = 2'b11; | |
103 | ||
104 | always @ (state or fwd_req or cpu_req_cam_acc or fc_fifo_space_avail or | |
105 | fwd_wait_done or fwd_reqs_served) | |
106 | ||
107 | begin | |
108 | ||
109 | fwd_sched_sm = 1'b0; | |
110 | cpu_sched_sm = 1'b0; | |
111 | inc_fwd_wait_cnt= 1'b0; | |
112 | reset_fwd_cnt = 1'b0; | |
113 | next_state = 2'b0; | |
114 | ||
115 | case (state) //synopsys parallel_case full_case | |
116 | // 0in < case -full -parallel -message "0in ERROR: case check in fflp_cam_sched:state" | |
117 | ||
118 | FWD_ARB: | |
119 | begin | |
120 | if (fwd_req & fc_fifo_space_avail) | |
121 | begin | |
122 | fwd_sched_sm = 1'b1; | |
123 | inc_fwd_wait_cnt= 1'b1; | |
124 | next_state = FWD_IDLE; | |
125 | end | |
126 | else if (cpu_req_cam_acc) | |
127 | begin | |
128 | cpu_sched_sm = 1'b1; | |
129 | inc_fwd_wait_cnt= 1'b1; | |
130 | next_state = CPU_IDLE; | |
131 | end | |
132 | else | |
133 | next_state = state; | |
134 | ||
135 | end | |
136 | ||
137 | FWD_IDLE: | |
138 | begin | |
139 | if (fwd_wait_done & fwd_reqs_served) | |
140 | begin | |
141 | inc_fwd_wait_cnt= 1'b0; | |
142 | reset_fwd_cnt = 1'b1; | |
143 | next_state = CPU_ARB; | |
144 | end | |
145 | else if (fwd_wait_done) | |
146 | begin | |
147 | inc_fwd_wait_cnt= 1'b0; | |
148 | next_state = FWD_ARB; | |
149 | end | |
150 | else | |
151 | begin | |
152 | inc_fwd_wait_cnt= 1'b1; | |
153 | next_state = state; | |
154 | end | |
155 | end | |
156 | ||
157 | CPU_ARB: | |
158 | begin | |
159 | if (cpu_req_cam_acc) | |
160 | begin | |
161 | cpu_sched_sm = 1'b1; | |
162 | inc_fwd_wait_cnt= 1'b1; | |
163 | next_state = CPU_IDLE; | |
164 | end | |
165 | else if (fwd_req & fc_fifo_space_avail) | |
166 | begin | |
167 | fwd_sched_sm = 1'b1; | |
168 | inc_fwd_wait_cnt= 1'b1; | |
169 | next_state = FWD_IDLE; | |
170 | end | |
171 | else | |
172 | next_state = FWD_ARB; | |
173 | end | |
174 | ||
175 | CPU_IDLE: | |
176 | begin | |
177 | if (fwd_wait_done) //use same counter is fine here since | |
178 | //cpu_srch and cam pio_wr_cost pretty much the same cycles | |
179 | begin | |
180 | inc_fwd_wait_cnt= 1'b0; | |
181 | next_state = FWD_ARB; | |
182 | end | |
183 | else | |
184 | begin | |
185 | inc_fwd_wait_cnt= 1'b1; | |
186 | next_state = state; | |
187 | end | |
188 | end | |
189 | ||
190 | default: next_state = FWD_ARB; | |
191 | ||
192 | endcase | |
193 | ||
194 | end | |
195 | ||
196 | ||
197 | dffr #(2) state_reg (cclk, reset, next_state, state); | |
198 | dffr #(1) fwd_sched_reg (cclk, reset, fwd_sched_sm, fwd_sched); | |
199 | dffr #(1) cpu_sched_reg (cclk, reset, cpu_sched_sm, cpu_sched); | |
200 | dffr #(4) fwd_wait_cnt_reg (cclk, reset, fwd_wait_cnt_in, fwd_wait_cnt); | |
201 | ||
202 | assign fwd_wait_cnt_in = {4{inc_fwd_wait_cnt}} & (fwd_wait_cnt[3:0] + 4'd1); | |
203 | assign fwd_wait_done = (fwd_wait_cnt == cam_srch_latency); | |
204 | ||
205 | ||
206 | /*********************************************************************/ | |
207 | //allocate load balance, cpu bandwidth | |
208 | /*********************************************************************/ | |
209 | assign fwd_reqs_served = (fwd_sched_cnt == cam_srch_ratio); | |
210 | assign fwd_sched_cnt_en = fwd_sched_sm | cpu_sched_sm; | |
211 | assign fwd_sched_cnt_in = (cpu_sched_sm | reset_fwd_cnt) ? 4'b0000 : (fwd_sched_cnt + 1); | |
212 | ||
213 | dffre #(4) fwd_sched_cnt_reg (cclk, reset, fwd_sched_cnt_en, fwd_sched_cnt_in, fwd_sched_cnt); | |
214 | ||
215 | ||
216 | endmodule |