[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / fflp_ram_cntl.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fflp_ram_cntl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
/**********************************************************************/
/*project name:  NIU                                                  */
/*module name:   fflp_ram_cntl                                        */
/*description:                                                        */
/*               Controls SRAM accesses for both CPU commands and     */
/*               packet classification                                */
/*                                                                    */
/*child modules in:  none                                             */
/*author name:       Jeanne Cai                                       */
/*date created:      03-16-04                                         */
/*                                                                    */
/*              Copyright (c) 2004, Sun Microsystems, Inc.            */
/*                   Sun Proprietary and Confidential                 */
/*                                                                    */
/*modifications:                                                      */
/*                                                                    */
/**********************************************************************/
`include "fflp.h"
module fflp_ram_cntl
		(cclk,
		reset,
		ram_acc_type,
		kick_off_ram_ctrl,
		cam_index,
		cam_haddr_reg1_dout,
		cam_key_reg1_dout,
		am_din,
		
		am_rd,
		am_wr,
		am_addr,
		am_dout,
		am_din_reg_dout
		);

input		cclk;
input		reset;
input[1:0]	ram_acc_type;
input		kick_off_ram_ctrl;
input[9:0]	cam_index;
input[9:0]	cam_haddr_reg1_dout;
input[41:0]	cam_key_reg1_dout;
input[41:0]	am_din;

output		am_rd;
output		am_wr;
output[9:0]	am_addr;
output[41:0]	am_dout;
output[41:0]	am_din_reg_dout;

reg		am_din_reg_en_sm;
reg		am_addr_sel_sm;
reg		am_rd_sm;
reg		am_wr_sm;
reg		am_dout_reg_sel_sm;
reg[1:0]	next_state;

wire		am_din_reg_en;
wire		am_din_reg_en_1;
//wire		am_din_reg_en_2;
wire		am_rd;
wire		am_wr;
wire[9:0]	am_addr;
wire[41:0]	am_dout;
wire[41:0]	am_din_reg_dout;

wire[1:0]	state;

wire[9:0]	am_addr_in;
wire[41:0]	am_dout_in;


//state machine states
parameter
	IDLE		= 2'b00,
	RAM_RMW_CYC_2	= 2'b01,
	RAM_RMW_CYC_3	= 2'b10,
	RAM_RMW_CYC_4	= 2'b11;

always @ (state or kick_off_ram_ctrl or ram_acc_type)
begin

am_din_reg_en_sm	= 1'b0;
am_addr_sel_sm		= 1'b0;	
am_rd_sm		= 1'b0;
am_wr_sm		= 1'b0;
am_dout_reg_sel_sm	= 1'b0;
next_state		= 2'b00;

case (state)	//synopsys parallel_case full_case
// 0in < case -full -parallel -message "0in ERROR: case check in fflp_ram_cntl:state"

IDLE:
begin
	if (kick_off_ram_ctrl)
	begin
		case (ram_acc_type)	//synopsys parallel_case full_case
		`RAM_R:	//RD_ASSOC_D
			begin
			am_din_reg_en_sm	= 1'b1;
			am_addr_sel_sm		= 1'b1;
			am_rd_sm		= 1'b1;
			am_wr_sm		= 1'b0;
			am_dout_reg_sel_sm	= 1'b0;
			next_state		= IDLE;
			end

		`RAM_W: //WR_ASSOC_D
			begin
			am_din_reg_en_sm	= 1'b0;
			am_addr_sel_sm		= 1'b1;
                        am_rd_sm                = 1'b0;
                        am_wr_sm                = 1'b1;
                        am_dout_reg_sel_sm      = 1'b1;
                        next_state              = IDLE;
                        end

		`RAM_RMW: 
                        begin
                        am_din_reg_en_sm        = 1'b1;
                        am_addr_sel_sm          = 1'b0;
                        am_rd_sm                = 1'b1;
                        am_wr_sm                = 1'b0;
                        am_dout_reg_sel_sm      = 1'b0;
                        next_state              = RAM_RMW_CYC_2;
                        end

		default:
			begin
                        am_din_reg_en_sm        = 1'b0;
                        am_addr_sel_sm          = 1'b0;
                        am_rd_sm                = 1'b0;
                        am_wr_sm                = 1'b0;
                        am_dout_reg_sel_sm      = 1'b0;
                        next_state              = IDLE;
                        end

		endcase
	end
	else
			next_state		= state;
end //IDLE

RAM_RMW_CYC_2:
begin
			am_din_reg_en_sm        = 1'b0;
                        am_addr_sel_sm          = 1'b0;
                        am_rd_sm                = 1'b0;
                        am_wr_sm                = 1'b0;
                        am_dout_reg_sel_sm      = 1'b0;
			next_state		= RAM_RMW_CYC_3;
end

RAM_RMW_CYC_3:
begin
			am_din_reg_en_sm        = 1'b0;
                        am_addr_sel_sm          = 1'b0;
                        am_rd_sm                = 1'b0;
                        am_wr_sm                = 1'b0;
                        am_dout_reg_sel_sm      = 1'b0;
                        next_state              = RAM_RMW_CYC_4;
end

RAM_RMW_CYC_4:
begin
                        am_din_reg_en_sm        = 1'b0;
                        am_addr_sel_sm          = 1'b0;
                        am_rd_sm                = 1'b0;
                        am_wr_sm                = 1'b1;
                        am_dout_reg_sel_sm      = 1'b0;
                        next_state              = IDLE;
end


default:		next_state		= IDLE;

endcase

end


assign am_addr_in 	= am_addr_sel_sm ? cam_index : cam_haddr_reg1_dout;
assign am_dout_in	= am_dout_reg_sel_sm ? cam_key_reg1_dout[41:0] : {am_din_reg_dout[41:1], 1'b0};   

dffr #(2) state_reg		(cclk, reset, next_state,	state);
dffr #(1) am_din_reg_en_reg	(cclk, reset, am_din_reg_en_sm, am_din_reg_en);
dffr #(1) am_din_reg_en_1_reg	(cclk, reset, am_din_reg_en,	am_din_reg_en_1);
//dffr #(1) am_din_reg_en_2_reg	(cclk, reset, am_din_reg_en_1,	am_din_reg_en_2);
dffr #(1) am_rd_reg		(cclk, reset, am_rd_sm,		am_rd);
dffr #(1) am_wr_reg		(cclk, reset, am_wr_sm,		am_wr);
dffr #(10) am_addr_reg		(cclk, reset, am_addr_in,	am_addr);
dffr #(42) am_dout_reg		(cclk, reset, am_dout_in,	am_dout);

dffre #(42) am_din_reg		(cclk, reset, am_din_reg_en_1, am_din, am_din_reg_dout);


//use am_din_reg_en_2 to log the parity error, am_addr is the address

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: fflp_ram_cntl.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/**********************************************************************/
	36	/project name: NIU /
	37	/module name: fflp_ram_cntl /
	38	/description: /
	39	/* Controls SRAM accesses for both CPU commands and */
	40	/* packet classification */
	41	/* */
	42	/child modules in: none /
	43	/author name: Jeanne Cai /
	44	/date created: 03-16-04 /
	45	/* */
	46	/* Copyright (c) 2004, Sun Microsystems, Inc. */
	47	/* Sun Proprietary and Confidential */
	48	/* */
	49	/modifications: /
	50	/* */
	51	/**********************************************************************/
	52	`include "fflp.h"
	53	module fflp_ram_cntl
	54	(cclk,
	55	reset,
	56	ram_acc_type,
	57	kick_off_ram_ctrl,
	58	cam_index,
	59	cam_haddr_reg1_dout,
	60	cam_key_reg1_dout,
	61	am_din,
	62
	63	am_rd,
	64	am_wr,
65	am_addr,
66	am_dout,
67	am_din_reg_dout
68	);
69
70	input cclk;
71	input reset;
72	input[1:0] ram_acc_type;
73	input kick_off_ram_ctrl;
74	input[9:0] cam_index;
75	input[9:0] cam_haddr_reg1_dout;
76	input[41:0] cam_key_reg1_dout;
77	input[41:0] am_din;
78
79	output am_rd;
80	output am_wr;
81	output[9:0] am_addr;
82	output[41:0] am_dout;
83	output[41:0] am_din_reg_dout;
84
85	reg am_din_reg_en_sm;
86	reg am_addr_sel_sm;
87	reg am_rd_sm;
88	reg am_wr_sm;
89	reg am_dout_reg_sel_sm;
90	reg[1:0] next_state;
91
92	wire am_din_reg_en;
93	wire am_din_reg_en_1;
94	//wire am_din_reg_en_2;
95	wire am_rd;
96	wire am_wr;
97	wire[9:0] am_addr;
98	wire[41:0] am_dout;
99	wire[41:0] am_din_reg_dout;
100
101	wire[1:0] state;
102
103	wire[9:0] am_addr_in;
104	wire[41:0] am_dout_in;
105
106
107	//state machine states
108	parameter
109	IDLE = 2'b00,
110	RAM_RMW_CYC_2 = 2'b01,
111	RAM_RMW_CYC_3 = 2'b10,
112	RAM_RMW_CYC_4 = 2'b11;
113
114	always @ (state or kick_off_ram_ctrl or ram_acc_type)
115	begin
116
117	am_din_reg_en_sm = 1'b0;
118	am_addr_sel_sm = 1'b0;
119	am_rd_sm = 1'b0;
120	am_wr_sm = 1'b0;
121	am_dout_reg_sel_sm = 1'b0;
122	next_state = 2'b00;
123
124	case (state) //synopsys parallel_case full_case
125	// 0in < case -full -parallel -message "0in ERROR: case check in fflp_ram_cntl:state"
126
127	IDLE:
128	begin
129	if (kick_off_ram_ctrl)
130	begin
131	case (ram_acc_type) //synopsys parallel_case full_case
132	`RAM_R: //RD_ASSOC_D
133	begin
134	am_din_reg_en_sm = 1'b1;
135	am_addr_sel_sm = 1'b1;
136	am_rd_sm = 1'b1;
137	am_wr_sm = 1'b0;
138	am_dout_reg_sel_sm = 1'b0;
139	next_state = IDLE;
140	end
141
142	`RAM_W: //WR_ASSOC_D
143	begin
144	am_din_reg_en_sm = 1'b0;
145	am_addr_sel_sm = 1'b1;
146	am_rd_sm = 1'b0;
147	am_wr_sm = 1'b1;
148	am_dout_reg_sel_sm = 1'b1;
149	next_state = IDLE;
150	end
151
152	`RAM_RMW:
153	begin
154	am_din_reg_en_sm = 1'b1;
155	am_addr_sel_sm = 1'b0;
156	am_rd_sm = 1'b1;
157	am_wr_sm = 1'b0;
158	am_dout_reg_sel_sm = 1'b0;
159	next_state = RAM_RMW_CYC_2;
160	end
161
162	default:
163	begin
164	am_din_reg_en_sm = 1'b0;
165	am_addr_sel_sm = 1'b0;
166	am_rd_sm = 1'b0;
167	am_wr_sm = 1'b0;
168	am_dout_reg_sel_sm = 1'b0;
169	next_state = IDLE;
170	end
171
172	endcase
173	end
174	else
175	next_state = state;
176	end //IDLE
177
178	RAM_RMW_CYC_2:
179	begin
180	am_din_reg_en_sm = 1'b0;
181	am_addr_sel_sm = 1'b0;
182	am_rd_sm = 1'b0;
183	am_wr_sm = 1'b0;
184	am_dout_reg_sel_sm = 1'b0;
185	next_state = RAM_RMW_CYC_3;
186	end
187
188	RAM_RMW_CYC_3:
189	begin
190	am_din_reg_en_sm = 1'b0;
191	am_addr_sel_sm = 1'b0;
192	am_rd_sm = 1'b0;
193	am_wr_sm = 1'b0;
194	am_dout_reg_sel_sm = 1'b0;
195	next_state = RAM_RMW_CYC_4;
196	end
197
198	RAM_RMW_CYC_4:
199	begin
200	am_din_reg_en_sm = 1'b0;
201	am_addr_sel_sm = 1'b0;
202	am_rd_sm = 1'b0;
203	am_wr_sm = 1'b1;
204	am_dout_reg_sel_sm = 1'b0;
205	next_state = IDLE;
206	end
207
208
209	default: next_state = IDLE;
210
211	endcase
212
213	end
214
215
216	assign am_addr_in = am_addr_sel_sm ? cam_index : cam_haddr_reg1_dout;
217	assign am_dout_in = am_dout_reg_sel_sm ? cam_key_reg1_dout[41:0] : {am_din_reg_dout[41:1], 1'b0};
218
219	dffr #(2) state_reg (cclk, reset, next_state, state);
220	dffr #(1) am_din_reg_en_reg (cclk, reset, am_din_reg_en_sm, am_din_reg_en);
221	dffr #(1) am_din_reg_en_1_reg (cclk, reset, am_din_reg_en, am_din_reg_en_1);
222	//dffr #(1) am_din_reg_en_2_reg (cclk, reset, am_din_reg_en_1, am_din_reg_en_2);
223	dffr #(1) am_rd_reg (cclk, reset, am_rd_sm, am_rd);
224	dffr #(1) am_wr_reg (cclk, reset, am_wr_sm, am_wr);
225	dffr #(10) am_addr_reg (cclk, reset, am_addr_in, am_addr);
226	dffr #(42) am_dout_reg (cclk, reset, am_dout_in, am_dout);
227
228	dffre #(42) am_din_reg (cclk, reset, am_din_reg_en_1, am_din, am_din_reg_dout);
229
230
231	//use am_din_reg_en_2 to log the parity error, am_addr is the address
232
233	endmodule