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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / mac_2ports.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mac_2ports.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
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16// GNU General Public License for more details.
17//
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21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*%W% %G%*/
36
37/*****************************************************************
38 *
39 * File Name : mac_2ports.v
40 * Author Name : John Lo
41 * Description : mac_clk_driver
42 * + mac_pio_intf
43 * + 2 xmac_2pcs_core
44 * + sphy_dpath2
45 * + esr_ctrl
46 * + mif
47 *
48 * Parent Module: mac
49 * Child Module:
50 * Interface Mod: IPPs,OPPs,ethernet serdes, PIO.
51 * Date Created : 3/23/04
52 *
53 * Design Notes: 1. channel 0 of each serdes is used as 1G
54 * port respectively.
55 * Used esr_mac_oddcg0_0 and esr_mac_oddcg0_1
56 * to for odd_rx0 and odd_rx1.
57 * 2. xpcs needs signal_detect and serdes_rdy
58 *
59 * Copyright (c) 2020, Sun Microsystems, Inc.
60 * Sun Proprietary and Confidential
61 *
62 * Modification : 4/1/2004 -by John Lo
63 * 1. Changed address bus width from
64 * 16 bits to 19 bits for pio_clients_addr.
65 * 2. Support both 32 bit and 64 bit addressing.
66 * 3. Changed PIO read/write data bus from
67 * 32 bits to 64 bits.
68 * The MSB 32 bits are "0".
69 * 7/14/2004 -by John Lo
70 * 1. used esr_mac_oddcg0_0 and esr_mac_oddcg0_1
71 * to for odd_rx0 and odd_rx1.
72 *
73 * 11/23/2004 -by JOhn Lo
74 * 1. used ch1 esr_mac_oddcg1_0 and esr_mac_oddcg1_1
75 * to for odd_rx0 and odd_rx1.
76 *
77 * 3/4/2005 -by John Lo
78 * 1. Changed back to esr_mac_oddcg0_0 and esr_mac_oddcg0_1
79 * to for odd_rx0 and odd_rx1.
80 *
81 *
82 * Synthesis Notes:
83 *
84 *
85 ****************************************************************/
86
87module mac_2ports(/*AUTOARG*/
88 // Outputs
89 reset, clk, mac_debug_port, mac_pio_ack, mac_pio_rdata,
90 mac_pio_intr0, mac_pio_intr1, mac_pio_err, tx_heart_beat_timer0,
91 rx_heart_beat_timer0, mac_txc_req0, mac_rxc_ack0, mac_rxc_tag0,
92 mac_rxc_data0, mac_rxc_ctrl0, mac_rxc_stat0, loopback0,
93 sel_por_clk_src0, sel_clk_25mhz0, mii_mode0, gmii_mode0,
94 xgmii_mode0, pcs_bypass0, xpcs_loopback0, xaui_act_led_0,
95 xaui_link_led_0, tx_heart_beat_timer1, rx_heart_beat_timer1,
96 mac_txc_req1, mac_rxc_ack1, mac_rxc_tag1, mac_rxc_data1,
97 mac_rxc_ctrl1, mac_rxc_stat1, loopback1, sel_por_clk_src1,
98 sel_clk_25mhz1, mii_mode1, gmii_mode1, xgmii_mode1, pcs_bypass1,
99 xpcs_loopback1, xaui_act_led_1, xaui_link_led_1, mdclk, mdo, mdoe,
100 serdes_reset_0, serdes_reset_1, mac_esr_tclk_0, mac_esr_txd0_0,
101 mac_esr_txd1_0, mac_esr_txd2_0, mac_esr_txd3_0, mac_esr_tclk_1,
102 mac_esr_txd0_1, mac_esr_txd1_1, mac_esr_txd2_1, mac_esr_txd3_1,
103 mif_pio_intr,
104 // Inputs
105 niu_clk, niu_reset_l, pio_clients_addr, pio_clients_rd,
106 pio_clients_wdata, pio_mac_sel, mac_reset0, mac_reset1,
107 tcu_scan_mode, tcu_scan_en, tcu_mac_312tx_clk_stop,
108 tcu_mac_312rx_clk_stop, tcu_mac_156tx_clk_stop,
109 tcu_mac_156rx_clk_stop, tcu_mac_125tx_clk_stop,
110 tcu_mac_125rx_clk_stop, tx_clk_muxd0, tx_nbclk_muxd0,
111 tx_clk_312mhz_muxd0, rx_clk_muxd0, rx_nbclk_muxd0, txc_mac_ack0,
112 txc_mac_tag0, txc_mac_data0, txc_mac_stat0, txc_mac_abort0,
113 rxc_mac_req0, rbc0_a_muxd0, rbc0_b_muxd0, rbc0_c_muxd0,
114 rbc0_d_muxd0, tx_clk_muxd1, tx_nbclk_muxd1, tx_clk_312mhz_muxd1,
115 rx_clk_muxd1, rx_nbclk_muxd1, txc_mac_ack1, txc_mac_tag1,
116 txc_mac_data1, txc_mac_stat1, txc_mac_abort1, rxc_mac_req1,
117 rbc0_a_muxd1, rbc0_b_muxd1, rbc0_c_muxd1, rbc0_d_muxd1, mdi,
118 mdi_0, mdi_1, xaui_mdint0_l, xaui_mdint1_l, esr_mac_rxd0_0,
119 esr_mac_rxd1_0, esr_mac_rxd2_0, esr_mac_rxd3_0, esr_mac_lock_0,
120 esr_mac_los_0, esr_mac_oddcg0_0, esr_mac_rxd0_1, esr_mac_rxd1_1,
121 esr_mac_rxd2_1, esr_mac_rxd3_1, esr_mac_lock_1, esr_mac_los_1,
122 esr_mac_oddcg0_1
123 );
124
125/* ------------- global signals ------------------------------- */
126 input niu_clk;
127 input niu_reset_l;
128 output reset;
129 output clk;
130 output [31:0] mac_debug_port;
131 input [19:0] pio_clients_addr;
132 input pio_clients_rd;
133 input [31:0] pio_clients_wdata;
134 // designated signals
135 input pio_mac_sel;
136 output mac_pio_ack;
137 output [63:0] mac_pio_rdata;
138 output mac_pio_intr0;// port 0 interrupt
139 output mac_pio_intr1;// port 1 interrupt
140 output mac_pio_err;
141 // per port mac_reset
142 input mac_reset0;
143 input mac_reset1;
144 // DFT signals
145 input tcu_scan_mode;
146 input tcu_scan_en; // NEW INPUT PIN
147 input tcu_mac_312tx_clk_stop; // NEW INPUT PIN
148 input tcu_mac_312rx_clk_stop; // NEW INPUT PIN
149 input tcu_mac_156tx_clk_stop; // NEW INPUT PIN
150 input tcu_mac_156rx_clk_stop; // NEW INPUT PIN
151 input tcu_mac_125tx_clk_stop; // NEW INPUT PIN
152 input tcu_mac_125rx_clk_stop; // NEW INPUT PIN
153/****************************************************************
154 * port0: xmac_2pcs_core
155 ****************************************************************/
156/* ------------- xmac_core clocks ----------------------------- */
157 input tx_clk_muxd0; // from clock mux
158 input tx_nbclk_muxd0; // from clock mux
159 input tx_clk_312mhz_muxd0; // esr_mac_tclk_0 is from Channel 1 transmit clock.
160 input rx_clk_muxd0; // from clock mux
161 input rx_nbclk_muxd0; // from clock mux
162 output [3:0] tx_heart_beat_timer0;
163 output [3:0] rx_heart_beat_timer0;
164/* ------------- shared MII/GMII Interface -------------------- */
165// input gmii_rx_dv0;
166// input [7:0] gmii_rxd0;
167// input gmii_rx_err0;
168// output gmii_tx_en0;
169// output [7:0] gmii_txd0;
170// output gmii_tx_err0;
171/* ------------- XGMII Interface ------------------------------ */
172// input [3:0] xgmii_rxc0;
173// input [31:0] xgmii_rxd0;
174// output [3:0] xgmii_txc0;
175// output [31:0] xgmii_txd0;
176/* ------------- Tx DMA Interface ----------------------------- */
177 output mac_txc_req0;
178 input txc_mac_ack0;
179 input txc_mac_tag0;
180 input [63:0] txc_mac_data0;
181 input [3:0] txc_mac_stat0;
182 input txc_mac_abort0;
183/* ------------- Rx DMA Interface ----------------------------- */
184 input rxc_mac_req0;
185 output mac_rxc_ack0;
186 output mac_rxc_tag0; // output of rxfifo. non-registered.
187 output [63:0] mac_rxc_data0; // {64bit data}
188 output mac_rxc_ctrl0;
189 output [22:0] mac_rxc_stat0; // {24bit data}
190
191/****************************
192 * phy_clock signals
193 ***************************/
194 output loopback0;
195 output sel_por_clk_src0;
196 output sel_clk_25mhz0;
197 output mii_mode0;
198 output gmii_mode0;
199 output xgmii_mode0;
200 output pcs_bypass0;
201 output xpcs_loopback0;
202
203/* ------------- xPCS Interface ------------------------------- */
204 input rbc0_a_muxd0; //
205 input rbc0_b_muxd0; //
206 input rbc0_c_muxd0; //
207 input rbc0_d_muxd0; //
208/************
209 * led
210 * ***********/
211 output xaui_act_led_0;
212 output xaui_link_led_0;
213
214/****************************************************************
215 * end of port0
216 ****************************************************************/
217/****************************************************************
218 * port1: xmac_2pcs_core
219 ****************************************************************/
220/* ------------- xmac_core clocks ----------------------------- */
221 input tx_clk_muxd1; // from clock mux
222 input tx_nbclk_muxd1; // from clock mux
223 input tx_clk_312mhz_muxd1; // esr_mac_tclk_0 is from Channel 1 transmit clock.
224 input rx_clk_muxd1; // from clock mux
225 input rx_nbclk_muxd1; // from clock mux
226 output [3:0] tx_heart_beat_timer1;
227 output [3:0] rx_heart_beat_timer1;
228/* ------------- shared MII/GMII Interface -------------------- */
229// input gmii_rx_dv1;
230// input [7:0] gmii_rxd1;
231// input gmii_rx_err1;
232// output gmii_tx_en1;
233// output [7:0] gmii_txd1;
234// output gmii_tx_err1;
235/* ------------- XGMII Interface ------------------------------ */
236// input [3:0] xgmii_rxc1;
237// input [31:0] xgmii_rxd1;
238// output [3:0] xgmii_txc1;
239// output [31:0] xgmii_txd1;
240/* ------------- Tx DMA Interface ----------------------------- */
241 output mac_txc_req1;
242 input txc_mac_ack1;
243 input txc_mac_tag1;
244 input [63:0] txc_mac_data1;
245 input [3:0] txc_mac_stat1;
246 input txc_mac_abort1;
247/* ------------- Rx DMA Interface ----------------------------- */
248 input rxc_mac_req1;
249 output mac_rxc_ack1;
250 output mac_rxc_tag1; // output of rxfifo. non-registered.
251 output [63:0] mac_rxc_data1; // {64bit data}
252 output mac_rxc_ctrl1;
253 output [22:0] mac_rxc_stat1; // {24bit data}
254
255/****************************
256 * phy_clock signals
257 ***************************/
258 output loopback1;
259 output sel_por_clk_src1;
260 output sel_clk_25mhz1;
261 output mii_mode1;
262 output gmii_mode1;
263 output xgmii_mode1;
264 output pcs_bypass1;
265 output xpcs_loopback1;
266
267/* ------------- xPCS Interface ------------------------------- */
268 input rbc0_a_muxd1; //
269 input rbc0_b_muxd1; //
270 input rbc0_c_muxd1; //
271 input rbc0_d_muxd1; //
272/************
273 * led
274 * ***********/
275 output xaui_act_led_1;
276 output xaui_link_led_1;
277
278/****************************************************************
279 * end of port1
280 ****************************************************************/
281
282/****************************************
283 * mif related
284 ****************************************/
285 input mdi;
286 input mdi_0;
287 input mdi_1;
288 input xaui_mdint0_l;
289 input xaui_mdint1_l;
290 // outputs
291 output mdclk;
292 output mdo;
293 output mdoe;
294
295 output serdes_reset_0;
296 output serdes_reset_1;
297
298/****************************************
299 * top level esr data path (sphy_dpath2)
300 ****************************************/
301 // rx serdes 0
302 input [9:0] esr_mac_rxd0_0;
303 input [9:0] esr_mac_rxd1_0;
304 input [9:0] esr_mac_rxd2_0;
305 input [9:0] esr_mac_rxd3_0;
306 input esr_mac_lock_0;
307 input [3:0] esr_mac_los_0;
308 input esr_mac_oddcg0_0;
309 // tx serdes 0
310 output [3:0] mac_esr_tclk_0;
311 output [9:0] mac_esr_txd0_0;
312 output [9:0] mac_esr_txd1_0;
313 output [9:0] mac_esr_txd2_0;
314 output [9:0] mac_esr_txd3_0;
315 // rx serdes 1
316 input [9:0] esr_mac_rxd0_1;
317 input [9:0] esr_mac_rxd1_1;
318 input [9:0] esr_mac_rxd2_1;
319 input [9:0] esr_mac_rxd3_1;
320 input esr_mac_lock_1;
321 input [3:0] esr_mac_los_1;
322 input esr_mac_oddcg0_1;
323 // tx serdes 1
324 output [3:0] mac_esr_tclk_1;
325 output [9:0] mac_esr_txd0_1;
326 output [9:0] mac_esr_txd1_1;
327 output [9:0] mac_esr_txd2_1;
328 output [9:0] mac_esr_txd3_1;
329 //
330 output mif_pio_intr;
331
332/*AUTOWIRE*/
333// Beginning of automatic wires (for undeclared instantiated-module outputs)
334// End of automatics
335
336/****************************
337 * internal signals
338 ***************************/
339 wire blunt_end_loopback;
340 wire [19:0] pio_clients_addr;
341 wire pio_clients_rd;
342 wire [31:0] pio_clients_wdata;
343 // vlint flag_dangling_net_within_module off
344 // vlint flag_net_has_no_load off
345 wire [16:0] pio_addr;
346 // vlint flag_net_has_no_load on
347 // vlint flag_dangling_net_within_module on
348 wire pio_rd;
349 wire [31:0] pio_wdata;
350 // 10G
351 wire [31:0] rdata_xmac0;
352 wire [31:0] rdata_xpcs0;
353 wire [31:0] rdata_pcs0;
354 wire [31:0] rdata_xmac1;
355 wire [31:0] rdata_xpcs1;
356 wire [31:0] rdata_pcs1;
357 wire [31:0] rdata_esr;
358 wire [31:0] rdata_mif;
359 wire [31:0] mac_debug_port;
360 wire [31:0] xmac_debug0;
361 wire [31:0] xpcs_debug0;
362 wire [2:0] mac_debug_sel0;
363 wire [31:0] xmac_debug1;
364 wire [31:0] xpcs_debug1;
365 // vlint flag_dangling_net_within_module off
366 // vlint flag_net_has_no_load off
367 wire [2:0] mac_debug_sel1;
368 // vlint flag_net_has_no_load on
369 // vlint flag_dangling_net_within_module on
370
371 wire gmii_rx_dv0 = 0;
372 wire [7:0] gmii_rxd0 = 0;
373 wire gmii_rx_err0 = 0;
374 // vlint flag_dangling_net_within_module off
375 // vlint flag_net_has_no_load off
376 wire gmii_tx_en0;
377 wire [7:0] gmii_txd0;
378 wire gmii_tx_err0;
379 // vlint flag_net_has_no_load on
380 // vlint flag_dangling_net_within_module on
381
382 wire gmii_rx_dv1 = 0;
383 wire [7:0] gmii_rxd1 = 0;
384 wire gmii_rx_err1 = 0;
385 // vlint flag_dangling_net_within_module off
386 // vlint flag_net_has_no_load off
387 wire gmii_tx_en1;
388 wire [7:0] gmii_txd1;
389 wire gmii_tx_err1;
390 // vlint flag_net_has_no_load on
391 // vlint flag_dangling_net_within_module on
392 wire [31:0] esrctl_debug;
393 wire serdes_reset_0;
394 wire serdes_reset_1;
395
396// port 2
397 wire pio_err_bmac2 = 0;
398 wire ack_bmac2 = 0;
399 wire [31:0] rdata_bmac2 = 32'b0;
400 wire pio_err_pcs2 = 0;
401 wire ack_pcs2 = 0;
402 wire [31:0] rdata_pcs2 = 32'b0;
403 wire bm_tx_interrupt2 = 0;
404 wire bm_rx_interrupt2 = 0;
405 wire bm_control_interrupt2 = 0;
406 wire pcs_int2 = 0;
407// port 3
408 wire pio_err_bmac3 = 0;
409 wire ack_bmac3 = 0;
410 wire [31:0] rdata_bmac3 = 32'b0;
411 wire pio_err_pcs3 = 0;
412 wire ack_pcs3 = 0;
413 wire [31:0] rdata_pcs3 = 32'b0;
414 wire bm_tx_interrupt3 = 0;
415 wire bm_rx_interrupt3 = 0;
416 wire bm_control_interrupt3 = 0;
417 wire pcs_int3 = 0;
418 // sphy_dpath2
419 // ----- port 0 serdes 0
420 wire xgmii_mode0;
421 wire tx_clk_312mhz0;
422 wire [39:0] xtx_code_group0;
423 wire [9:0] tx_code_group0;
424 wire [9:0] mac_esr_txd0_0;
425 wire [9:0] mac_esr_txd1_0;
426 wire [9:0] mac_esr_txd2_0;
427 wire [9:0] mac_esr_txd3_0;
428 // rx side signals
429 wire [9:0] esr_mac_rxd0_0;
430 wire [9:0] esr_mac_rxd1_0;
431 wire [9:0] esr_mac_rxd2_0;
432 wire [9:0] esr_mac_rxd3_0;
433 wire [39:0] xrx_code_group0;
434 wire [9:0] rx_code_group0;
435 wire odd_rx0;
436 // ----- port 1 serdes 1
437 wire xgmii_mode1;
438 wire tx_clk_312mhz1;
439 // tx side signals
440 wire [39:0] xtx_code_group1;
441 wire [9:0] tx_code_group1;
442 wire [9:0] mac_esr_txd0_1;
443 wire [9:0] mac_esr_txd1_1;
444 wire [9:0] mac_esr_txd2_1;
445 wire [9:0] mac_esr_txd3_1;
446 // rx side signals
447 wire [9:0] esr_mac_rxd0_1;
448 wire [9:0] esr_mac_rxd1_1;
449 wire [9:0] esr_mac_rxd2_1;
450 wire [9:0] esr_mac_rxd3_1;
451 wire [39:0] xrx_code_group1;
452 wire [9:0] rx_code_group1;
453 wire odd_rx1;
454 // esr_ctrl
455 // port0 xpcs, pcs signals
456 wire esr_mac_lock_0;
457 wire [3:0] esr_mac_los_0;
458 wire serdes_rdy0_0;
459 wire signal_detect0_0;
460 wire xserdes_rdy_0;
461 wire [3:0] xsignal_detect_0;
462 // port1 xpcs, pcs signals
463 wire esr_mac_lock_1;
464 wire [3:0] esr_mac_los_1;
465 wire serdes_rdy0_1;
466 wire signal_detect0_1;
467 wire xserdes_rdy_1;
468 wire [3:0] xsignal_detect_1;
469 // global signals
470 wire tx_nbclk0;
471 wire tx_nbclk1;
472 wire mdclk;
473 wire mdo;
474 wire mdoe = mdo;
475 wire rbc0_a0,rbc0_b0,rbc0_c0,rbc0_d0,rx_clk0,rx_nbclk0,tx_clk0,
476 rbc0_a1,rbc0_b1,rbc0_c1,rbc0_d1,rx_clk1,rx_nbclk1,tx_clk1,
477 pio_err_xmac0,ack_xmac0,pio_err_xpcs0,ack_xpcs0,pio_err_pcs0,ack_pcs0,
478 pio_err_xmac1,ack_xmac1,pio_err_xpcs1,ack_xpcs1,pio_err_pcs1,ack_pcs1,
479 pio_err_esr,ack_esr,pio_err_mif,ack_mif,
480 txmac_interrupt0,rxmac_interrupt0,xmac_fc_interrupt0,xpcs_interrupt0,pcs_int0,
481 txmac_interrupt1,rxmac_interrupt1,xmac_fc_interrupt1,xpcs_interrupt1,pcs_int1,
482 sel_xmac0,sel_xpcs0,sel_pcs0,
483 sel_xmac1,sel_xpcs1,sel_pcs1;
484 // vlint flag_dangling_net_within_module off
485 // vlint flag_net_has_no_load off
486 wire sel_bmac2,sel_pcs2,mac_pio_intr2,
487 sel_bmac3,sel_pcs3,mac_pio_intr3;
488 // vlint flag_net_has_no_load on
489 // vlint flag_dangling_net_within_module on
490
491 wire sel_esr,sel_mif;
492 wire clk;
493 wire MDINT0;
494 wire MDINT1;
495
496// vlint flag_net_has_no_load off
497// vlint flag_dangling_net_within_module off
498 wire [2:0] sys_clk_count0;
499 wire [3:0] xgmii_txc0;
500 wire [31:0] xgmii_txd0;
501 wire [2:0] sys_clk_count1;
502 wire [3:0] xgmii_txc1;
503 wire [31:0] xgmii_txd1;
504 wire atca_GE;
505// vlint flag_dangling_net_within_module on
506// vlint flag_net_has_no_load on
507
508// \\\\\\\\\\ glue logic \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
509
510/* ----------- clock muxes ------------- */
511 wire p1_mac_esr_tclk_0;
512 wire p1_mac_esr_tclk_1;
513 wire [3:0] mac_esr_tclk_0;
514 wire [3:0] mac_esr_tclk_1;
515
516func_mux1 p1_mac_esr_tclk_0_func_mux1 (.din0(tx_nbclk0),.din1(tx_clk_312mhz0),.select(xgmii_mode0),.dout(p1_mac_esr_tclk_0));
517func_mux1 p1_mac_esr_tclk_1_func_mux1 (.din0(tx_nbclk1),.din1(tx_clk_312mhz1),.select(xgmii_mode1),.dout(p1_mac_esr_tclk_1));
518// blunt_end_loopback is ment for 10G only
519func_mux1 mac_esr_tclk_0_0_func_mux1(.din0(p1_mac_esr_tclk_0),.din1(~rbc0_a0),.select(blunt_end_loopback),.dout(mac_esr_tclk_0[0]));
520func_mux1 mac_esr_tclk_0_1_func_mux1(.din0(p1_mac_esr_tclk_0),.din1(~rbc0_b0),.select(blunt_end_loopback),.dout(mac_esr_tclk_0[1]));
521func_mux1 mac_esr_tclk_0_2_func_mux1(.din0(p1_mac_esr_tclk_0),.din1(~rbc0_c0),.select(blunt_end_loopback),.dout(mac_esr_tclk_0[2]));
522func_mux1 mac_esr_tclk_0_3_func_mux1(.din0(p1_mac_esr_tclk_0),.din1(~rbc0_d0),.select(blunt_end_loopback),.dout(mac_esr_tclk_0[3]));
523func_mux1 mac_esr_tclk_1_0_func_mux1(.din0(p1_mac_esr_tclk_1),.din1(~rbc0_a1),.select(blunt_end_loopback),.dout(mac_esr_tclk_1[0]));
524func_mux1 mac_esr_tclk_1_1_func_mux1(.din0(p1_mac_esr_tclk_1),.din1(~rbc0_b1),.select(blunt_end_loopback),.dout(mac_esr_tclk_1[1]));
525func_mux1 mac_esr_tclk_1_2_func_mux1(.din0(p1_mac_esr_tclk_1),.din1(~rbc0_c1),.select(blunt_end_loopback),.dout(mac_esr_tclk_1[2]));
526func_mux1 mac_esr_tclk_1_3_func_mux1(.din0(p1_mac_esr_tclk_1),.din1(~rbc0_d1),.select(blunt_end_loopback),.dout(mac_esr_tclk_1[3]));
527
528/* ----------- regiser reset ----------- */
529 reg mac_reset_port0;
530 reg mac_reset_port1;
531
532always @ (posedge clk)
533 begin
534 mac_reset_port0 <= mac_reset0;
535 mac_reset_port1 <= mac_reset1;
536 end
537
538// \\\\\\\\\\ begin instantiation \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
539
540/****************************************************************
541 * mac_clk_driver isntantiation
542 ****************************************************************/
543mac_clk_driver mac_clk_driver(
544// port0
545.rbc0_a0(rbc0_a0),
546.rbc0_b0(rbc0_b0),
547.rbc0_c0(rbc0_c0),
548.rbc0_d0(rbc0_d0),
549.rx_clk0(rx_clk0), // output of clock tree
550.rx_nbclk0(rx_nbclk0), // output of clock tree
551.tx_clk0(tx_clk0), // output of clock tree
552.tx_nbclk0(tx_nbclk0), // output of clock tree
553.tx_clk_312mhz0(tx_clk_312mhz0),
554.rbc0_a_muxd0(rbc0_a_muxd0),
555.rbc0_b_muxd0(rbc0_b_muxd0),
556.rbc0_c_muxd0(rbc0_c_muxd0),
557.rbc0_d_muxd0(rbc0_d_muxd0),
558.rx_nbclk_muxd0(rx_nbclk_muxd0),
559.rx_clk_muxd0(rx_clk_muxd0),
560.tx_nbclk_muxd0(tx_nbclk_muxd0),
561.tx_clk_muxd0(tx_clk_muxd0),
562.tx_clk_312mhz_muxd0(tx_clk_312mhz_muxd0),
563// port1
564.rbc0_a1(rbc0_a1),
565.rbc0_b1(rbc0_b1),
566.rbc0_c1(rbc0_c1),
567.rbc0_d1(rbc0_d1),
568.rx_clk1(rx_clk1), // output of clock tree
569.rx_nbclk1(rx_nbclk1), // output of clock tree
570.tx_clk1(tx_clk1), // output of clock tree
571.tx_nbclk1(tx_nbclk1), // output of clock tree
572.tx_clk_312mhz1(tx_clk_312mhz1),
573.rbc0_a_muxd1(rbc0_a_muxd1),
574.rbc0_b_muxd1(rbc0_b_muxd1),
575.rbc0_c_muxd1(rbc0_c_muxd1),
576.rbc0_d_muxd1(rbc0_d_muxd1),
577.rx_nbclk_muxd1(rx_nbclk_muxd1),
578.rx_clk_muxd1(rx_clk_muxd1),
579.tx_nbclk_muxd1(tx_nbclk_muxd1),
580.tx_clk_muxd1(tx_clk_muxd1),
581.tx_clk_312mhz_muxd1(tx_clk_312mhz_muxd1),
582//
583.tcu_scan_mode(tcu_scan_mode),
584.tcu_scan_en(tcu_scan_en),
585.tcu_mac_312tx_clk_stop(tcu_mac_312tx_clk_stop),
586.tcu_mac_312rx_clk_stop(tcu_mac_312rx_clk_stop),
587.tcu_mac_156tx_clk_stop(tcu_mac_156tx_clk_stop),
588.tcu_mac_156rx_clk_stop(tcu_mac_156rx_clk_stop),
589.tcu_mac_125tx_clk_stop(tcu_mac_125tx_clk_stop),
590.tcu_mac_125rx_clk_stop(tcu_mac_125rx_clk_stop),
591// core clock
592.clk(clk),
593.niu_clk(niu_clk)
594 );
595// end of mac_clk_driver isntantiation
596
597/****************************************************************
598 * mac_pio_intf isntantiation
599 ****************************************************************/
600mac_pio_intf mac_pio_intf(
601.clk(clk),
602.niu_reset_l(niu_reset_l),
603// global broadcast signals
604.pio_clients_addr(pio_clients_addr[19:0]),
605.pio_clients_rd(pio_clients_rd),
606.pio_clients_wdata(pio_clients_wdata[31:0]),
607// designated signals
608.pio_mac_sel(pio_mac_sel),
609.mac_pio_ack(mac_pio_ack),
610.mac_pio_rdata(mac_pio_rdata[63:0]),
611// individual internal inputs
612// port 0
613.pio_err_xmac0(pio_err_xmac0),
614.ack_xmac0(ack_xmac0),
615.rdata_xmac0(rdata_xmac0),
616.pio_err_xpcs0(pio_err_xpcs0),
617.ack_xpcs0(ack_xpcs0),
618.rdata_xpcs0(rdata_xpcs0),
619.pio_err_pcs0(pio_err_pcs0),
620.ack_pcs0(ack_pcs0),
621.rdata_pcs0(rdata_pcs0),
622// port 1
623.pio_err_xmac1(pio_err_xmac1),
624.ack_xmac1(ack_xmac1),
625.rdata_xmac1(rdata_xmac1),
626.pio_err_xpcs1(pio_err_xpcs1),
627.ack_xpcs1(ack_xpcs1),
628.rdata_xpcs1(rdata_xpcs1),
629.pio_err_pcs1(pio_err_pcs1),
630.ack_pcs1(ack_pcs1),
631.rdata_pcs1(rdata_pcs1),
632// port 2
633.pio_err_bmac2(pio_err_bmac2),
634.ack_bmac2(ack_bmac2),
635.rdata_bmac2(rdata_bmac2),
636.pio_err_pcs2(pio_err_pcs2),
637.ack_pcs2(ack_pcs2),
638.rdata_pcs2(rdata_pcs2),
639// port 3
640.pio_err_bmac3(pio_err_bmac3),
641.ack_bmac3(ack_bmac3),
642.rdata_bmac3(rdata_bmac3),
643.pio_err_pcs3(pio_err_pcs3),
644.ack_pcs3(ack_pcs3),
645.rdata_pcs3(rdata_pcs3),
646// esr
647.pio_err_esr(pio_err_esr),
648.ack_esr(ack_esr),
649.rdata_esr(rdata_esr),
650// mif
651.pio_err_mif(pio_err_mif),
652.ack_mif(ack_mif),
653.rdata_mif(rdata_mif[31:0]),
654// port 0 interrupts
655.txmac_interrupt0(txmac_interrupt0),
656.rxmac_interrupt0(rxmac_interrupt0),
657.xmac_fc_interrupt0(xmac_fc_interrupt0),
658.xpcs_interrupt0(xpcs_interrupt0),
659.pcs_int0(pcs_int0), // pcs link down interrupt, secondary interrupt
660// port 1 interrupts
661.txmac_interrupt1(txmac_interrupt1),
662.rxmac_interrupt1(rxmac_interrupt1),
663.xmac_fc_interrupt1(xmac_fc_interrupt1),
664.xpcs_interrupt1(xpcs_interrupt1),
665.pcs_int1(pcs_int1), // pcs link down interrupt, secondary interrupt
666// port 2 interrupts
667.bm_tx_interrupt2(bm_tx_interrupt2),
668.bm_rx_interrupt2(bm_rx_interrupt2),
669.bm_control_interrupt2(bm_control_interrupt2),
670.pcs_int2(pcs_int2), // pcs link down interrupt, secondary interrupt
671// port 3 interrupts
672.bm_tx_interrupt3(bm_tx_interrupt3),
673.bm_rx_interrupt3(bm_rx_interrupt3),
674.bm_control_interrupt3(bm_control_interrupt3),
675.pcs_int3(pcs_int3), // pcs link down interrupt, secondary interrupt
676//
677.xmac_debug0(xmac_debug0),
678.xpcs_debug0(xpcs_debug0),
679.mac_debug_sel0(mac_debug_sel0),
680.xmac_debug1(xmac_debug1),
681.xpcs_debug1(xpcs_debug1),
682.esrctl_debug(esrctl_debug[31:0]),
683// outputs
684.reset(reset),
685.mac_debug_port(mac_debug_port[31:0]),
686.sel_xmac0(sel_xmac0),
687.sel_xpcs0(sel_xpcs0),
688.sel_pcs0 (sel_pcs0 ),
689.sel_xmac1(sel_xmac1),
690.sel_xpcs1(sel_xpcs1),
691.sel_pcs1 (sel_pcs1 ),
692.sel_bmac2(sel_bmac2),
693.sel_pcs2 (sel_pcs2 ),
694.sel_bmac3(sel_bmac3),
695.sel_pcs3 (sel_pcs3 ),
696.sel_esr(sel_esr),
697.sel_mif(sel_mif),
698.pio_addr(pio_addr[16:0]),
699.pio_rd(pio_rd),
700.pio_wdata(pio_wdata),
701.mac_pio_intr0(mac_pio_intr0),// port 0 interrupt
702.mac_pio_intr1(mac_pio_intr1),// port 1 interrupt
703.mac_pio_intr2(mac_pio_intr2),// port 2 interrupt
704.mac_pio_intr3(mac_pio_intr3),// port 3 interrupt
705.mac_pio_err(mac_pio_err)
706 );
707// end of mac_pio_intf isntantiation
708
709/****************************************************************
710 * port0: xmac_2pcs_core
711 ****************************************************************/
712 xmac_2pcs_core xmac_2pcs_core_port0(
713// xmac_core signals
714/* ------------- xmac clocks ---------------------------------- */
715.clk(clk), // from system clock
716.tx_clk(tx_clk0), // from clock mux
717.tx_clk_312mhz(tx_clk_312mhz0),
718.tx_nbclk(tx_nbclk0), // from clock mux
719.rx_clk(rx_clk0), // from clock mux
720.rx_nbclk(rx_nbclk0), // from clock mux
721.sys_clk_count(sys_clk_count0[2:0]),
722.tx_heart_beat_timer(tx_heart_beat_timer0),
723.rx_heart_beat_timer(rx_heart_beat_timer0),
724/* ------------- shared MII/GMII Interface ------------------- */
725.gmii_rxd(gmii_rxd0),
726.gmii_rx_dv(gmii_rx_dv0),
727.gmii_rx_err(gmii_rx_err0),
728.gmii_txd(gmii_txd0),
729.gmii_tx_en(gmii_tx_en0),
730.gmii_tx_err(gmii_tx_err0),
731/* ------------- XGMII Interface ------------------------------ */
732.xgmii_rxc(4'b0),
733.xgmii_rxd(32'b0),
734.xgmii_txc(xgmii_txc0[3:0]),
735.xgmii_txd(xgmii_txd0[31:0]),
736/* ------------- xmac pio Interface --------------------------- */
737.pio_core_reset(reset|mac_reset_port0),// becomes hw_reset
738.pio_core_sel_xmac(sel_xmac0), // sel
739.pio_ack_xmac(ack_xmac0), // ack
740.pio_rd(pio_rd), // r/w_
741.pio_addr(pio_addr[11:3]), // address
742.pio_wr_data(pio_wdata), // wr_data
743.pio_rd_data_xmac(rdata_xmac0), // rd_data
744.pio_err_xmac(pio_err_xmac0),
745.txmac_interrupt(txmac_interrupt0),
746.rxmac_interrupt(rxmac_interrupt0),
747.xmac_fc_interrupt(xmac_fc_interrupt0),
748/* ------------- xpcs pio Interface --------------------------- */
749.rdata_xpcs(rdata_xpcs0), // rd_data
750.sel_xpcs(sel_xpcs0), // sel
751.ack_xpcs(ack_xpcs0), // ack
752.pio_err_xpcs(pio_err_xpcs0),
753.xpcs_interrupt(xpcs_interrupt0),
754/* ------------- Tx DMA Interface ----------------------------- */
755.txmac_opp_req(mac_txc_req0),
756.opp_txmac_ack(txc_mac_ack0),
757.opp_txmac_tag(txc_mac_tag0),
758.opp_txmac_data(txc_mac_data0),
759.opp_txmac_stat(txc_mac_stat0),
760.opp_txmac_abort(txc_mac_abort0),
761/* ------------- Rx DMA Interface ----------------------------- */
762.ipp_rxmac_req(rxc_mac_req0),
763.rxmac_ipp_ack(mac_rxc_ack0),
764.rxmac_ipp_tag(mac_rxc_tag0),
765.rxmac_ipp_data(mac_rxc_data0), // {64 bit data}
766.rxmac_ipp_ctrl(mac_rxc_ctrl0),
767.rxmac_ipp_stat(mac_rxc_stat0),
768/* ------------- xmac_xpcs_clk_mux control signals ------------ */
769.sel_clk_25mhz(sel_clk_25mhz0),
770.loopback(loopback0),
771.sel_por_clk_src(sel_por_clk_src0),
772.mii_mode(mii_mode0),
773.gmii_mode(gmii_mode0),
774.xgmii_mode(xgmii_mode0),
775.pcs_bypass(pcs_bypass0),
776.xpcs_loopback(xpcs_loopback0),
777/* ------------- PCS related Interface ------------------------ */
778/*************
779 * phy_dpath signals
780 *************/
781.gmii_crs(1'b0), // from external gmii interface
782.gmii_col(1'b0), // from external gmii interface
783/************
784 * pcs signals
785 ************/
786.odd_rx(odd_rx0),
787.serdes_rdy(serdes_rdy0_0), // ch0 serdes 0
788.signal_detect(signal_detect0_0),// ch0 serdes 0
789.rx_code_group(rx_code_group0), // from internal serdes
790.tx_code_group(tx_code_group0), // to internal serdes
791.pcs_pio_req(sel_pcs0),
792.pcs_pio_err(pio_err_pcs0),
793.pcs_pio_ack(ack_pcs0), // pio acknowledge
794.pcs_pio_rd_data(rdata_pcs0), // pio read data out
795.pcs_int(pcs_int0), // pcs link down interrupt, secondary interrupt
796/* ------------- xPCS Interface ------------------------------- */
797// rx xpcs signals
798.xserdes_rdy(xserdes_rdy_0),
799.xsignal_detect(xsignal_detect_0[3:0]),
800.rbc0_a(rbc0_a0),
801.rbc0_b(rbc0_b0),
802.rbc0_c(rbc0_c0),
803.rbc0_d(rbc0_d0),
804// rx PMD related signals
805.link_up_led(xaui_link_led_0), // signal to on-board LED, low pulse elongated
806.activity_led(xaui_act_led_0),
807.xrx_code_group(xrx_code_group0[39:0]), // symbol received from link
808.xtx_code_group(xtx_code_group0[39:0]), // symbol to send over link
809.MDINT(MDINT0),
810/* ------------- debug Interface ------------------------------ */
811.xmac_debug(xmac_debug0),
812.xpcs_debug(xpcs_debug0),
813.mac_debug_sel(mac_debug_sel0)
814 );
815// end of xmac_2pcs_core port0 instantiation
816
817
818/****************************************************************
819 * port1: xmac_2pcs_core
820 ****************************************************************/
821 xmac_2pcs_core xmac_2pcs_core_port1(
822// xmac_core signals
823/* ------------- xmac clocks ---------------------------------- */
824.clk(clk), // from system clock
825.tx_clk(tx_clk1), // from clock mux
826.tx_clk_312mhz(tx_clk_312mhz1),
827.tx_nbclk(tx_nbclk1), // from clock mux
828.rx_clk(rx_clk1), // from clock mux
829.rx_nbclk(rx_nbclk1), // from clock mux
830.sys_clk_count(sys_clk_count1[2:0]),
831.tx_heart_beat_timer(tx_heart_beat_timer1),
832.rx_heart_beat_timer(rx_heart_beat_timer1),
833/* ------------- shared MII/GMII Interface ------------------- */
834.gmii_rxd(gmii_rxd1),
835.gmii_rx_dv(gmii_rx_dv1),
836.gmii_rx_err(gmii_rx_err1),
837.gmii_txd(gmii_txd1),
838.gmii_tx_en(gmii_tx_en1),
839.gmii_tx_err(gmii_tx_err1),
840/* ------------- XGMII Interface ------------------------------ */
841.xgmii_rxc(4'b0),
842.xgmii_rxd(32'b0),
843.xgmii_txc(xgmii_txc1[3:0]),
844.xgmii_txd(xgmii_txd1[31:0]),
845/* ------------- xmac pio Interface --------------------------- */
846.pio_core_reset(reset|mac_reset_port1),// becomes hw_reset
847.pio_core_sel_xmac(sel_xmac1), // sel
848.pio_ack_xmac(ack_xmac1), // ack
849.pio_rd(pio_rd), // r/w_
850.pio_addr(pio_addr[11:3]), // address
851.pio_wr_data(pio_wdata), // wr_data
852.pio_rd_data_xmac(rdata_xmac1), // rd_data
853.pio_err_xmac(pio_err_xmac1),
854.txmac_interrupt(txmac_interrupt1),
855.rxmac_interrupt(rxmac_interrupt1),
856.xmac_fc_interrupt(xmac_fc_interrupt1),
857/* ------------- xpcs pio Interface --------------------------- */
858.rdata_xpcs(rdata_xpcs1), // rd_data
859.sel_xpcs(sel_xpcs1), // sel
860.ack_xpcs(ack_xpcs1), // ack
861.pio_err_xpcs(pio_err_xpcs1),
862.xpcs_interrupt(xpcs_interrupt1),
863/* ------------- Tx DMA Interface ----------------------------- */
864.txmac_opp_req(mac_txc_req1),
865.opp_txmac_ack(txc_mac_ack1),
866.opp_txmac_tag(txc_mac_tag1),
867.opp_txmac_data(txc_mac_data1),
868.opp_txmac_stat(txc_mac_stat1),
869.opp_txmac_abort(txc_mac_abort1),
870/* ------------- Rx DMA Interface ----------------------------- */
871.ipp_rxmac_req(rxc_mac_req1),
872.rxmac_ipp_ack(mac_rxc_ack1),
873.rxmac_ipp_tag(mac_rxc_tag1),
874.rxmac_ipp_data(mac_rxc_data1), // {64 bit data}
875.rxmac_ipp_ctrl(mac_rxc_ctrl1),
876.rxmac_ipp_stat(mac_rxc_stat1),
877/* ------------- xmac_xpcs_clk_mux control signals ------------ */
878.sel_clk_25mhz(sel_clk_25mhz1),
879.loopback(loopback1),
880.sel_por_clk_src(sel_por_clk_src1),
881.mii_mode(mii_mode1),
882.gmii_mode(gmii_mode1),
883.xgmii_mode(xgmii_mode1),
884.pcs_bypass(pcs_bypass1),
885.xpcs_loopback(xpcs_loopback1),
886/* ------------- PCS related Interface ------------------------ */
887/*************
888 * phy_dpath signals
889 *************/
890.gmii_crs(1'b1), // from external gmii interface
891.gmii_col(1'b1), // from external gmii interface
892/************
893 * pcs signals
894 ************/
895.odd_rx(odd_rx1),
896.serdes_rdy(serdes_rdy0_1), // ch0 serdes 1
897.signal_detect(signal_detect0_1),// ch0 serdes 1
898.rx_code_group(rx_code_group1), // from internal serdes
899.tx_code_group(tx_code_group1), // to internal serdes
900.pcs_pio_req(sel_pcs1),
901.pcs_pio_err(pio_err_pcs1),
902.pcs_pio_ack(ack_pcs1), // pio acknowledge
903.pcs_pio_rd_data(rdata_pcs1), // pio read data out
904.pcs_int(pcs_int1), // pcs link down interrupt, secondary interrupt
905/* ------------- xPCS Interface ------------------------------- */
906// rx xpcs signals
907.xserdes_rdy(xserdes_rdy_1),
908.xsignal_detect(xsignal_detect_1[3:0]),
909.rbc0_a(rbc0_a1),
910.rbc0_b(rbc0_b1),
911.rbc0_c(rbc0_c1),
912.rbc0_d(rbc0_d1),
913// rx PMD related signals
914.link_up_led(xaui_link_led_1), // signal to on-board LED, low pulse elongated
915.activity_led(xaui_act_led_1),
916.xrx_code_group(xrx_code_group1[39:0]), // symbol received from link
917.xtx_code_group(xtx_code_group1[39:0]), // symbol to send over link
918.MDINT(MDINT1),
919/* ------------- debug Interface ------------------------------ */
920.xmac_debug(xmac_debug1),
921.xpcs_debug(xpcs_debug1),
922.mac_debug_sel(mac_debug_sel1)
923 );
924// end of xmac_2pcs_core port1 instantiation
925
926
927/****************************************************************
928 * ethernet serdes data path
929 ****************************************************************/
930
931sphy_dpath2 sphy_dpath2(
932.blunt_end_loopback(blunt_end_loopback),
933.tcu_scan_en(tcu_scan_en),
934// ---- port 0 serdes 0
935.xgmii_mode0(xgmii_mode0),
936// tx side signals
937.tx_nbclk0(tx_nbclk0),
938.tx_clk_312mhz0(tx_clk_312mhz0),
939.xtx_code_group0(xtx_code_group0),
940.tx_code_group0(tx_code_group0),
941.mac_esr_txd0_0(mac_esr_txd0_0),
942.mac_esr_txd1_0(mac_esr_txd1_0),
943.mac_esr_txd2_0(mac_esr_txd2_0),
944.mac_esr_txd3_0(mac_esr_txd3_0),
945// rx side signals
946.rbc0_a0(rbc0_a0),
947.rbc0_b0(rbc0_b0),
948.rbc0_c0(rbc0_c0),
949.rbc0_d0(rbc0_d0),
950.rx_nbclk0(rx_nbclk0),
951.esr_mac_rxd0_0(esr_mac_rxd0_0),
952.esr_mac_rxd1_0(esr_mac_rxd1_0),
953.esr_mac_rxd2_0(esr_mac_rxd2_0),
954.esr_mac_rxd3_0(esr_mac_rxd3_0),
955.esr_mac_oddcg0_0(esr_mac_oddcg0_0),
956.odd_rx0(odd_rx0),
957.xrx_code_group0(xrx_code_group0),
958.rx_code_group0(rx_code_group0),
959// ---- port 1 serdes1
960.xgmii_mode1(xgmii_mode1),
961// tx side signals
962.tx_nbclk1(tx_nbclk1),
963.tx_clk_312mhz1(tx_clk_312mhz1),
964.xtx_code_group1(xtx_code_group1),
965.tx_code_group1(tx_code_group1),
966.mac_esr_txd0_1(mac_esr_txd0_1),
967.mac_esr_txd1_1(mac_esr_txd1_1),
968.mac_esr_txd2_1(mac_esr_txd2_1),
969.mac_esr_txd3_1(mac_esr_txd3_1),
970// rx side signals
971.rbc0_a1(rbc0_a1),
972.rbc0_b1(rbc0_b1),
973.rbc0_c1(rbc0_c1),
974.rbc0_d1(rbc0_d1),
975.rx_nbclk1(rx_nbclk1),
976.esr_mac_rxd0_1(esr_mac_rxd0_1),
977.esr_mac_rxd1_1(esr_mac_rxd1_1),
978.esr_mac_rxd2_1(esr_mac_rxd2_1),
979.esr_mac_rxd3_1(esr_mac_rxd3_1),
980.esr_mac_oddcg0_1(esr_mac_oddcg0_1),
981.odd_rx1(odd_rx1),
982.xrx_code_group1(xrx_code_group1),
983.rx_code_group1(rx_code_group1)
984 );
985// end of serdes dpath2 instantiation
986
987
988/****************************************************************
989 * esr control instantiation
990 ****************************************************************/
991esr_ctl2 esr_ctl2(
992.pio_core_reset(reset),
993.clk(clk),
994.blunt_end_loopback(blunt_end_loopback),
995// pio interface
996.pio_addr(pio_addr[11:3]), // pio global signal
997.pio_rd(pio_rd), // pio global signal
998.pio_wdata(pio_wdata), // pio global signal
999.sel_esr(sel_esr),
1000.ack_esr(ack_esr),
1001.rdata_esr(rdata_esr),
1002.pio_err_esr(pio_err_esr),
1003.serdes_reset_0(serdes_reset_0),
1004.serdes_reset_1(serdes_reset_1),
1005// port0 xpcs, pcs signals
1006.esr_mac_lock_0(esr_mac_lock_0),
1007.esr_mac_los_0(esr_mac_los_0[3:0]),
1008.serdes_rdy0_0(serdes_rdy0_0),
1009.signal_detect0_0(signal_detect0_0),
1010.xserdes_rdy_0(xserdes_rdy_0),
1011.xsignal_detect_0(xsignal_detect_0[3:0]),
1012// port1 xpcs, pcs signals
1013.esr_mac_lock_1(esr_mac_lock_1),
1014.esr_mac_los_1(esr_mac_los_1[3:0]),
1015.serdes_rdy0_1(serdes_rdy0_1),
1016.signal_detect0_1(signal_detect0_1),
1017.xserdes_rdy_1(xserdes_rdy_1),
1018.xsignal_detect_1(xsignal_detect_1[3:0]),
1019/* ----- debug data ----- */
1020// ---- port 0 serdes 0
1021// tx side signals
1022.xtx_code_group0(xtx_code_group0),
1023.tx_code_group0(tx_code_group0),
1024.mac_esr_txd0_0(mac_esr_txd0_0),
1025.mac_esr_txd1_0(mac_esr_txd1_0),
1026.mac_esr_txd2_0(mac_esr_txd2_0),
1027.mac_esr_txd3_0(mac_esr_txd3_0),
1028// rx side signals
1029.esr_mac_rxd0_0(esr_mac_rxd0_0),
1030.esr_mac_rxd1_0(esr_mac_rxd1_0),
1031.esr_mac_rxd2_0(esr_mac_rxd2_0),
1032.esr_mac_rxd3_0(esr_mac_rxd3_0),
1033.xrx_code_group0(xrx_code_group0),
1034.rx_code_group0(rx_code_group0),
1035// ---- port 1 serdes1
1036// tx side signals
1037.xtx_code_group1(xtx_code_group1),
1038.tx_code_group1(tx_code_group1),
1039.mac_esr_txd0_1(mac_esr_txd0_1),
1040.mac_esr_txd1_1(mac_esr_txd1_1),
1041.mac_esr_txd2_1(mac_esr_txd2_1),
1042.mac_esr_txd3_1(mac_esr_txd3_1),
1043// rx side signals
1044.esr_mac_rxd0_1(esr_mac_rxd0_1),
1045.esr_mac_rxd1_1(esr_mac_rxd1_1),
1046.esr_mac_rxd2_1(esr_mac_rxd2_1),
1047.esr_mac_rxd3_1(esr_mac_rxd3_1),
1048.xrx_code_group1(xrx_code_group1),
1049.rx_code_group1(rx_code_group1),
1050.esrctl_debug(esrctl_debug[31:0])
1051 );
1052// end of esr control instantiation
1053
1054mif mif
1055 (
1056 .clk (clk),
1057 .pio_core_reset (reset),
1058 .sel_mif (sel_mif),
1059 .pio_rd (pio_rd),
1060 .pio_addr (pio_addr[11:3]),
1061 .pio_wdata (pio_wdata[31:0]),
1062 .ack_mif (ack_mif),
1063 .rdata_mif (rdata_mif[31:0]),
1064 .pio_err_mif (pio_err_mif),
1065 .atca_GE (atca_GE),
1066 .MDINT0 (MDINT0),
1067 .MDINT1 (MDINT1),
1068 .PHY_MDINT0_L (xaui_mdint0_l),
1069 .PHY_MDINT1_L (xaui_mdint1_l),
1070 // mdio output signals
1071 .mdclk (mdclk),
1072 .mdo (mdo),
1073 .mif_pio_intr (mif_pio_intr),
1074 // mdio input signals
1075 .mdi (mdi),
1076 .mdi_0 (mdi_0),
1077 .mdi_1 (mdi_1),
1078 .mdi_2 (1'b0));
1079
1080
1081endmodule // mac_2ports
Full OpenSPARC design & verification tarball including full HDL.