[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_ipp_ffl_arbiter.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_ipp_ffl_arbiter.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================

/**********************************************************
***********************************************************

    Project         : Niu

    File name       : niu_ipp_ffl_arbiter.v

    Module(s) name  : niu_ipp_ffl_arbiter
    Original:       : ipp_arbiter.v main.32, label: IPP_RTL_2.3 IPP_VERIF_2.5 

    Parent modules  : niu_ipp_top.v

    Child modules   :           

    Author's name   : Jonathan Shen, George Chu

    Date            : Jan. 2002

    Description     : 4_to_1 round-robin arbiter for fflp.

    Synthesis Notes:

    Modification History:

    Date       Description
    ----       -----------

************************************************************
***********************************************************/

module niu_ipp_ffl_arbiter(
/****** input ******/
		  ipp_ffl_req0,
		  ipp_fflp_data0,
		  ipp_fflp_mac_default0,
		  ipp_fflp_dvalid0,
		  ipp_ffl_req1,
		  ipp_fflp_data1,
		  ipp_fflp_mac_default1,
		  ipp_fflp_dvalid1,
`ifdef NEPTUNE
		  ipp_ffl_req2,
		  ipp_fflp_data2,
		  ipp_fflp_mac_default2,
		  ipp_fflp_dvalid2,
		  ipp_ffl_req3,
		  ipp_fflp_data3,
		  ipp_fflp_mac_default3,
		  ipp_fflp_dvalid3,
`endif
                  reset, clk,
/****** output ******/
		  ffl_arb_ack0, 
		  ffl_arb_ack1, 
`ifdef NEPTUNE
		  ffl_arb_ack2, 
		  ffl_arb_ack3, 
`endif
		  ipp_fflp_dvalid,
		  ipp_fflp_data,
		  ipp_fflp_port,
		  ipp_fflp_mac_default
		  );

/* Zin arbiter
 -req ipp_ffl_req0 ipp_ffl_req1 ipp_ffl_req2 ipp_ffl_req3 
 -gnt ffl_arb_ack0_pre ffl_arb_ack1_pre ffl_arb_ack2_pre ffl_arb_ack3_pre 
 -clock clk -reset reset -message "IPP_FFL arbiter"
*/

input           ipp_ffl_req0;
input	[127:0]	ipp_fflp_data0;
input	[11:0]	ipp_fflp_mac_default0;
input		ipp_fflp_dvalid0;

input           ipp_ffl_req1;
input	[127:0]	ipp_fflp_data1;
input	[11:0]	ipp_fflp_mac_default1;
input		ipp_fflp_dvalid1;

`ifdef NEPTUNE
input           ipp_ffl_req2;
input	[127:0]	ipp_fflp_data2;
input	[11:0]	ipp_fflp_mac_default2;
input		ipp_fflp_dvalid2;

input           ipp_ffl_req3;
input	[127:0]	ipp_fflp_data3;
input	[11:0]	ipp_fflp_mac_default3;
input		ipp_fflp_dvalid3;
`endif

input           reset;
input		clk;

output		ffl_arb_ack0;
output		ffl_arb_ack1;
`ifdef NEPTUNE
output		ffl_arb_ack2;
output		ffl_arb_ack3;
`endif

output		ipp_fflp_dvalid;
output	[127:0]	ipp_fflp_data;
output	[1:0]	ipp_fflp_port;
output	[11:0]	ipp_fflp_mac_default;

reg		ffl_arb_ack0_pre;
reg		ffl_arb_ack1_pre;
`ifdef NEPTUNE
reg		ffl_arb_ack2_pre;
reg		ffl_arb_ack3_pre;
`endif
reg		ipp_fflp_dvalid_pre;
reg	[127:0] ipp_fflp_data_pre;
reg	[1:0]   ipp_fflp_port_pre;
reg	[11:0]	ipp_fflp_mac_default_pre;

wire            ffl_arb_ack0;
wire            ffl_arb_ack1;
`ifdef NEPTUNE
wire            ffl_arb_ack2;
wire            ffl_arb_ack3;
`endif
wire            ipp_fflp_dvalid;
wire    [127:0] ipp_fflp_data;
wire    [1:0]   ipp_fflp_port;
wire    [11:0]  ipp_fflp_mac_default;

`ifdef NEPTUNE
reg	[1:0]	cur_state;
reg     [1:0]   nex_state;

wire    [3:0]   sel;
assign  sel[0] = ffl_arb_ack0;
assign  sel[1] = ffl_arb_ack1;
assign  sel[2] = ffl_arb_ack2;
assign  sel[3] = ffl_arb_ack3;

parameter
StIpp0          = 2'h0,
StIpp1          = 2'h1,
StIpp2          = 2'h2,
StIpp3          = 2'h3;

/****** state machine ******/
// comb part

always @ (ipp_ffl_req0 or ipp_ffl_req1 or ipp_ffl_req2 or 
	  ipp_ffl_req3 or cur_state)
  begin
    ffl_arb_ack0_pre = 0;
    ffl_arb_ack1_pre = 0;
    ffl_arb_ack2_pre = 0;
    ffl_arb_ack3_pre = 0;

    case (cur_state)	// synopsys parallel_case full_case

      StIpp0:
	if (ipp_ffl_req0 == 1'h1)
	  begin
            ffl_arb_ack0_pre = 1;
            nex_state = cur_state;
          end
	else if (ipp_ffl_req1 == 1'h1)
            nex_state = StIpp1;
        else if (ipp_ffl_req2 == 1'h1)
            nex_state = StIpp2;
        else if (ipp_ffl_req3 == 1'h1)
            nex_state = StIpp3;
        else
            nex_state = StIpp0;

      StIpp1:
	if (ipp_ffl_req1 == 1'h1)
          begin
            ffl_arb_ack1_pre = 1;
            nex_state = cur_state;
          end
        else if (ipp_ffl_req2 == 1'h1)
            nex_state = StIpp2;
        else if (ipp_ffl_req3 == 1'h1)
            nex_state = StIpp3;
        else if (ipp_ffl_req0 == 1'h1)
            nex_state = StIpp0;
        else
            nex_state = StIpp1;

      StIpp2:
	if (ipp_ffl_req2 == 1'h1)
          begin
            ffl_arb_ack2_pre = 1;
            nex_state = cur_state;
          end
        else if (ipp_ffl_req3 == 1'h1)
            nex_state = StIpp3;
        else if (ipp_ffl_req0 == 1'h1)
            nex_state = StIpp0;
        else if (ipp_ffl_req1 == 1'h1)
            nex_state = StIpp1;
        else
            nex_state = StIpp2;

      StIpp3:
	if (ipp_ffl_req3 == 1'h1)
          begin
            ffl_arb_ack3_pre = 1;
            nex_state = cur_state;
          end
        else if (ipp_ffl_req0 == 1'h1)
            nex_state = StIpp0;
        else if (ipp_ffl_req1 == 1'h1)
            nex_state = StIpp1;
        else if (ipp_ffl_req2 == 1'h1)
            nex_state = StIpp2;
        else
            nex_state = StIpp3;

    endcase
  end

// seq part
always @ (posedge clk)
   if (reset)
      cur_state[1:0] <= 2'h0;
   else
      cur_state[1:0] <= nex_state[1:0];

/****** end of state machine ******/

/****** 4:1 mux for ipp_fflp_dvalid ******/
always @ (sel or ipp_fflp_dvalid0 or ipp_fflp_dvalid1 or ipp_fflp_dvalid2
	  or ipp_fflp_dvalid3)
  case (sel[3:0])       // synopsys parallel_case full_case
    4'b0001: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
    4'b0010: ipp_fflp_dvalid_pre = ipp_fflp_dvalid1;
    4'b0100: ipp_fflp_dvalid_pre = ipp_fflp_dvalid2;
    4'b1000: ipp_fflp_dvalid_pre = ipp_fflp_dvalid3;
    default: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
  endcase

/****** 4:1 mux for data ******/
always @ (sel or ipp_fflp_data0 or ipp_fflp_data1 or ipp_fflp_data2
	  or ipp_fflp_data3)
  case (sel[3:0])       // synopsys parallel_case full_case
    4'b0001: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
    4'b0010: ipp_fflp_data_pre[127:0] = ipp_fflp_data1[127:0];
    4'b0100: ipp_fflp_data_pre[127:0] = ipp_fflp_data2[127:0];
    4'b1000: ipp_fflp_data_pre[127:0] = ipp_fflp_data3[127:0];
    default: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
  endcase

/****** 4:1 mux port ******/
always @ (sel) 
  case (sel[3:0])       // synopsys parallel_case full_case
    4'b0001: ipp_fflp_port_pre[1:0] = 2'b00; 
    4'b0010: ipp_fflp_port_pre[1:0] = 2'b01;
    4'b0100: ipp_fflp_port_pre[1:0] = 2'b10;
    4'b1000: ipp_fflp_port_pre[1:0] = 2'b11;
    default: ipp_fflp_port_pre[1:0] = 2'b00;
  endcase

/****** 4:1 mux for mac_default ******/
always @ (sel or ipp_fflp_mac_default0 or ipp_fflp_mac_default1 or
	  ipp_fflp_mac_default2 or ipp_fflp_mac_default3)
  case (sel[3:0])       // synopsys parallel_case full_case
    4'b0001: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
    4'b0010: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default1[11:0];
    4'b0100: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default2[11:0];
    4'b1000: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default3[11:0];
    default: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
  endcase

  assign ffl_arb_ack0         = ffl_arb_ack0_pre;
  assign ffl_arb_ack1         = ffl_arb_ack1_pre;
  assign ffl_arb_ack2         = ffl_arb_ack2_pre;
  assign ffl_arb_ack3         = ffl_arb_ack3_pre;
`else
reg	     	cur_state;
reg             nex_state;

wire    [1:0]   sel;
assign  sel[0] = ffl_arb_ack0;
assign  sel[1] = ffl_arb_ack1;

parameter
StIpp0          = 1'h0,
StIpp1          = 1'h1;

/****** state machine ******/
// comb part

always @ (ipp_ffl_req0 or ipp_ffl_req1 or 
	  cur_state)
  begin
    ffl_arb_ack0_pre = 0;
    ffl_arb_ack1_pre = 0;

    case (cur_state)	// synopsys parallel_case full_case

      StIpp0:
	if (ipp_ffl_req0 == 1'h1)
	  begin
            ffl_arb_ack0_pre = 1;
            nex_state = cur_state;
          end
	else if (ipp_ffl_req1 == 1'h1)
            nex_state = StIpp1;
        else
            nex_state = StIpp0;

      StIpp1:
	if (ipp_ffl_req1 == 1'h1)
          begin
            ffl_arb_ack1_pre = 1;
            nex_state = cur_state;
          end
        else if (ipp_ffl_req0 == 1'h1)
            nex_state = StIpp0;
        else
            nex_state = StIpp1;
    endcase
  end

// seq part
always @ (posedge clk)
   if (reset)
      cur_state      <= 1'h0;
   else
      cur_state      <= nex_state;

/****** end of state machine ******/

/****** 2:1 mux for ipp_fflp_dvalid ******/
always @ (sel or ipp_fflp_dvalid0 or ipp_fflp_dvalid1) 
  case (sel[1:0])       // synopsys parallel_case 
    2'b01: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
    2'b10: ipp_fflp_dvalid_pre = ipp_fflp_dvalid1;
    default: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
  endcase

/****** 2:1 mux for data ******/
always @ (sel or ipp_fflp_data0 or ipp_fflp_data1)
  case (sel[1:0])       // synopsys parallel_case 
    2'b01: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
    2'b10: ipp_fflp_data_pre[127:0] = ipp_fflp_data1[127:0];
    default: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
  endcase

/****** 2:1 mux port ******/
always @ (sel) 
  case (sel[1:0])       // synopsys parallel_case 
    2'b01: ipp_fflp_port_pre[1:0] = 2'b0; 
    2'b10: ipp_fflp_port_pre[1:0] = 2'b1;
    default: ipp_fflp_port_pre[1:0] = 2'b0;
  endcase

/****** 2:1 mux for mac_default ******/
always @ (sel or ipp_fflp_mac_default0 or ipp_fflp_mac_default1) 
  case (sel[1:0])       // synopsys parallel_case full_case
    2'b01: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
    2'b10: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default1[11:0];
    default: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
  endcase

  assign ffl_arb_ack0         = ffl_arb_ack0_pre;
  assign ffl_arb_ack1         = ffl_arb_ack1_pre;
`endif

  ipp_reg_r_1   reg_r_1_dva   (.di(ipp_fflp_dvalid_pre),           .rs(reset),.ck(clk),.qo(ipp_fflp_dvalid));
  ipp_reg_r_128 reg_r_128_dat (.di(ipp_fflp_data_pre[127:0]),      .rs(reset),.ck(clk),.qo(ipp_fflp_data[127:0]));
  ipp_reg_r_2   reg_r_2_por   (.di(ipp_fflp_port_pre[1:0]),        .rs(reset),.ck(clk),.qo(ipp_fflp_port[1:0]));
  ipp_reg_r_12  reg_r_12_def  (.di(ipp_fflp_mac_default_pre[11:0]),.rs(reset),.ck(clk),.qo(ipp_fflp_mac_default[11:0]));

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_ipp_ffl_arbiter.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35
	36	/**********************************************************
	37	***********************************************************
	38
	39	Project : Niu
	40
	41	File name : niu_ipp_ffl_arbiter.v
	42
	43	Module(s) name : niu_ipp_ffl_arbiter
	44	Original: : ipp_arbiter.v main.32, label: IPP_RTL_2.3 IPP_VERIF_2.5
	45
	46	Parent modules : niu_ipp_top.v
	47
	48	Child modules :
	49
	50	Author's name : Jonathan Shen, George Chu
	51
	52	Date : Jan. 2002
	53
	54	Description : 4_to_1 round-robin arbiter for fflp.
	55
	56	Synthesis Notes:
	57
	58	Modification History:
	59
	60	Date Description
	61	---- -----------
	62
	63	************************************************************
	64	***********************************************************/
65
66	module niu_ipp_ffl_arbiter(
67	/**** input ****/
68	ipp_ffl_req0,
69	ipp_fflp_data0,
70	ipp_fflp_mac_default0,
71	ipp_fflp_dvalid0,
72	ipp_ffl_req1,
73	ipp_fflp_data1,
74	ipp_fflp_mac_default1,
75	ipp_fflp_dvalid1,
76	`ifdef NEPTUNE
77	ipp_ffl_req2,
78	ipp_fflp_data2,
79	ipp_fflp_mac_default2,
80	ipp_fflp_dvalid2,
81	ipp_ffl_req3,
82	ipp_fflp_data3,
83	ipp_fflp_mac_default3,
84	ipp_fflp_dvalid3,
85	`endif
86	reset, clk,
87	/**** output ****/
88	ffl_arb_ack0,
89	ffl_arb_ack1,
90	`ifdef NEPTUNE
91	ffl_arb_ack2,
92	ffl_arb_ack3,
93	`endif
94	ipp_fflp_dvalid,
95	ipp_fflp_data,
96	ipp_fflp_port,
97	ipp_fflp_mac_default
98	);
99
100	/* Zin arbiter
101	-req ipp_ffl_req0 ipp_ffl_req1 ipp_ffl_req2 ipp_ffl_req3
102	-gnt ffl_arb_ack0_pre ffl_arb_ack1_pre ffl_arb_ack2_pre ffl_arb_ack3_pre
103	-clock clk -reset reset -message "IPP_FFL arbiter"
104	*/
105
106	input ipp_ffl_req0;
107	input [127:0] ipp_fflp_data0;
108	input [11:0] ipp_fflp_mac_default0;
109	input ipp_fflp_dvalid0;
110
111	input ipp_ffl_req1;
112	input [127:0] ipp_fflp_data1;
113	input [11:0] ipp_fflp_mac_default1;
114	input ipp_fflp_dvalid1;
115
116	`ifdef NEPTUNE
117	input ipp_ffl_req2;
118	input [127:0] ipp_fflp_data2;
119	input [11:0] ipp_fflp_mac_default2;
120	input ipp_fflp_dvalid2;
121
122	input ipp_ffl_req3;
123	input [127:0] ipp_fflp_data3;
124	input [11:0] ipp_fflp_mac_default3;
125	input ipp_fflp_dvalid3;
126	`endif
127
128	input reset;
129	input clk;
130
131	output ffl_arb_ack0;
132	output ffl_arb_ack1;
133	`ifdef NEPTUNE
134	output ffl_arb_ack2;
135	output ffl_arb_ack3;
136	`endif
137
138	output ipp_fflp_dvalid;
139	output [127:0] ipp_fflp_data;
140	output [1:0] ipp_fflp_port;
141	output [11:0] ipp_fflp_mac_default;
142
143	reg ffl_arb_ack0_pre;
144	reg ffl_arb_ack1_pre;
145	`ifdef NEPTUNE
146	reg ffl_arb_ack2_pre;
147	reg ffl_arb_ack3_pre;
148	`endif
149	reg ipp_fflp_dvalid_pre;
150	reg [127:0] ipp_fflp_data_pre;
151	reg [1:0] ipp_fflp_port_pre;
152	reg [11:0] ipp_fflp_mac_default_pre;
153
154	wire ffl_arb_ack0;
155	wire ffl_arb_ack1;
156	`ifdef NEPTUNE
157	wire ffl_arb_ack2;
158	wire ffl_arb_ack3;
159	`endif
160	wire ipp_fflp_dvalid;
161	wire [127:0] ipp_fflp_data;
162	wire [1:0] ipp_fflp_port;
163	wire [11:0] ipp_fflp_mac_default;
164
165	`ifdef NEPTUNE
166	reg [1:0] cur_state;
167	reg [1:0] nex_state;
168
169	wire [3:0] sel;
170	assign sel[0] = ffl_arb_ack0;
171	assign sel[1] = ffl_arb_ack1;
172	assign sel[2] = ffl_arb_ack2;
173	assign sel[3] = ffl_arb_ack3;
174
175	parameter
176	StIpp0 = 2'h0,
177	StIpp1 = 2'h1,
178	StIpp2 = 2'h2,
179	StIpp3 = 2'h3;
180
181	/**** state machine ****/
182	// comb part
183
184	always @ (ipp_ffl_req0 or ipp_ffl_req1 or ipp_ffl_req2 or
185	ipp_ffl_req3 or cur_state)
186	begin
187	ffl_arb_ack0_pre = 0;
188	ffl_arb_ack1_pre = 0;
189	ffl_arb_ack2_pre = 0;
190	ffl_arb_ack3_pre = 0;
191
192	case (cur_state) // synopsys parallel_case full_case
193
194	StIpp0:
195	if (ipp_ffl_req0 == 1'h1)
196	begin
197	ffl_arb_ack0_pre = 1;
198	nex_state = cur_state;
199	end
200	else if (ipp_ffl_req1 == 1'h1)
201	nex_state = StIpp1;
202	else if (ipp_ffl_req2 == 1'h1)
203	nex_state = StIpp2;
204	else if (ipp_ffl_req3 == 1'h1)
205	nex_state = StIpp3;
206	else
207	nex_state = StIpp0;
208
209	StIpp1:
210	if (ipp_ffl_req1 == 1'h1)
211	begin
212	ffl_arb_ack1_pre = 1;
213	nex_state = cur_state;
214	end
215	else if (ipp_ffl_req2 == 1'h1)
216	nex_state = StIpp2;
217	else if (ipp_ffl_req3 == 1'h1)
218	nex_state = StIpp3;
219	else if (ipp_ffl_req0 == 1'h1)
220	nex_state = StIpp0;
221	else
222	nex_state = StIpp1;
223
224	StIpp2:
225	if (ipp_ffl_req2 == 1'h1)
226	begin
227	ffl_arb_ack2_pre = 1;
228	nex_state = cur_state;
229	end
230	else if (ipp_ffl_req3 == 1'h1)
231	nex_state = StIpp3;
232	else if (ipp_ffl_req0 == 1'h1)
233	nex_state = StIpp0;
234	else if (ipp_ffl_req1 == 1'h1)
235	nex_state = StIpp1;
236	else
237	nex_state = StIpp2;
238
239	StIpp3:
240	if (ipp_ffl_req3 == 1'h1)
241	begin
242	ffl_arb_ack3_pre = 1;
243	nex_state = cur_state;
244	end
245	else if (ipp_ffl_req0 == 1'h1)
246	nex_state = StIpp0;
247	else if (ipp_ffl_req1 == 1'h1)
248	nex_state = StIpp1;
249	else if (ipp_ffl_req2 == 1'h1)
250	nex_state = StIpp2;
251	else
252	nex_state = StIpp3;
253
254	endcase
255	end
256
257	// seq part
258	always @ (posedge clk)
259	if (reset)
260	cur_state[1:0] <= 2'h0;
261	else
262	cur_state[1:0] <= nex_state[1:0];
263
264	/**** end of state machine ****/
265
266	/**** 4:1 mux for ipp_fflp_dvalid ****/
267	always @ (sel or ipp_fflp_dvalid0 or ipp_fflp_dvalid1 or ipp_fflp_dvalid2
268	or ipp_fflp_dvalid3)
269	case (sel[3:0]) // synopsys parallel_case full_case
270	4'b0001: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
271	4'b0010: ipp_fflp_dvalid_pre = ipp_fflp_dvalid1;
272	4'b0100: ipp_fflp_dvalid_pre = ipp_fflp_dvalid2;
273	4'b1000: ipp_fflp_dvalid_pre = ipp_fflp_dvalid3;
274	default: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
275	endcase
276
277	/**** 4:1 mux for data ****/
278	always @ (sel or ipp_fflp_data0 or ipp_fflp_data1 or ipp_fflp_data2
279	or ipp_fflp_data3)
280	case (sel[3:0]) // synopsys parallel_case full_case
281	4'b0001: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
282	4'b0010: ipp_fflp_data_pre[127:0] = ipp_fflp_data1[127:0];
283	4'b0100: ipp_fflp_data_pre[127:0] = ipp_fflp_data2[127:0];
284	4'b1000: ipp_fflp_data_pre[127:0] = ipp_fflp_data3[127:0];
285	default: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
286	endcase
287
288	/**** 4:1 mux port ****/
289	always @ (sel)
290	case (sel[3:0]) // synopsys parallel_case full_case
291	4'b0001: ipp_fflp_port_pre[1:0] = 2'b00;
292	4'b0010: ipp_fflp_port_pre[1:0] = 2'b01;
293	4'b0100: ipp_fflp_port_pre[1:0] = 2'b10;
294	4'b1000: ipp_fflp_port_pre[1:0] = 2'b11;
295	default: ipp_fflp_port_pre[1:0] = 2'b00;
296	endcase
297
298	/**** 4:1 mux for mac_default ****/
299	always @ (sel or ipp_fflp_mac_default0 or ipp_fflp_mac_default1 or
300	ipp_fflp_mac_default2 or ipp_fflp_mac_default3)
301	case (sel[3:0]) // synopsys parallel_case full_case
302	4'b0001: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
303	4'b0010: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default1[11:0];
304	4'b0100: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default2[11:0];
305	4'b1000: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default3[11:0];
306	default: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
307	endcase
308
309	assign ffl_arb_ack0 = ffl_arb_ack0_pre;
310	assign ffl_arb_ack1 = ffl_arb_ack1_pre;
311	assign ffl_arb_ack2 = ffl_arb_ack2_pre;
312	assign ffl_arb_ack3 = ffl_arb_ack3_pre;
313	`else
314	reg cur_state;
315	reg nex_state;
316
317	wire [1:0] sel;
318	assign sel[0] = ffl_arb_ack0;
319	assign sel[1] = ffl_arb_ack1;
320
321	parameter
322	StIpp0 = 1'h0,
323	StIpp1 = 1'h1;
324
325	/**** state machine ****/
326	// comb part
327
328	always @ (ipp_ffl_req0 or ipp_ffl_req1 or
329	cur_state)
330	begin
331	ffl_arb_ack0_pre = 0;
332	ffl_arb_ack1_pre = 0;
333
334	case (cur_state) // synopsys parallel_case full_case
335
336	StIpp0:
337	if (ipp_ffl_req0 == 1'h1)
338	begin
339	ffl_arb_ack0_pre = 1;
340	nex_state = cur_state;
341	end
342	else if (ipp_ffl_req1 == 1'h1)
343	nex_state = StIpp1;
344	else
345	nex_state = StIpp0;
346
347	StIpp1:
348	if (ipp_ffl_req1 == 1'h1)
349	begin
350	ffl_arb_ack1_pre = 1;
351	nex_state = cur_state;
352	end
353	else if (ipp_ffl_req0 == 1'h1)
354	nex_state = StIpp0;
355	else
356	nex_state = StIpp1;
357	endcase
358	end
359
360	// seq part
361	always @ (posedge clk)
362	if (reset)
363	cur_state <= 1'h0;
364	else
365	cur_state <= nex_state;
366
367	/**** end of state machine ****/
368
369	/**** 2:1 mux for ipp_fflp_dvalid ****/
370	always @ (sel or ipp_fflp_dvalid0 or ipp_fflp_dvalid1)
371	case (sel[1:0]) // synopsys parallel_case
372	2'b01: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
373	2'b10: ipp_fflp_dvalid_pre = ipp_fflp_dvalid1;
374	default: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
375	endcase
376
377	/**** 2:1 mux for data ****/
378	always @ (sel or ipp_fflp_data0 or ipp_fflp_data1)
379	case (sel[1:0]) // synopsys parallel_case
380	2'b01: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
381	2'b10: ipp_fflp_data_pre[127:0] = ipp_fflp_data1[127:0];
382	default: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
383	endcase
384
385	/**** 2:1 mux port ****/
386	always @ (sel)
387	case (sel[1:0]) // synopsys parallel_case
388	2'b01: ipp_fflp_port_pre[1:0] = 2'b0;
389	2'b10: ipp_fflp_port_pre[1:0] = 2'b1;
390	default: ipp_fflp_port_pre[1:0] = 2'b0;
391	endcase
392
393	/**** 2:1 mux for mac_default ****/
394	always @ (sel or ipp_fflp_mac_default0 or ipp_fflp_mac_default1)
395	case (sel[1:0]) // synopsys parallel_case full_case
396	2'b01: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
397	2'b10: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default1[11:0];
398	default: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
399	endcase
400
401	assign ffl_arb_ack0 = ffl_arb_ack0_pre;
402	assign ffl_arb_ack1 = ffl_arb_ack1_pre;
403	`endif
404
405	ipp_reg_r_1 reg_r_1_dva (.di(ipp_fflp_dvalid_pre), .rs(reset),.ck(clk),.qo(ipp_fflp_dvalid));
406	ipp_reg_r_128 reg_r_128_dat (.di(ipp_fflp_data_pre[127:0]), .rs(reset),.ck(clk),.qo(ipp_fflp_data[127:0]));
407	ipp_reg_r_2 reg_r_2_por (.di(ipp_fflp_port_pre[1:0]), .rs(reset),.ck(clk),.qo(ipp_fflp_port[1:0]));
408	ipp_reg_r_12 reg_r_12_def (.di(ipp_fflp_mac_default_pre[11:0]),.rs(reset),.ck(clk),.qo(ipp_fflp_mac_default[11:0]));
409
410	endmodule