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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_mb4.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | /////////////////////////////////////////////////////////////////////////////// | |
37 | // | |
38 | // | |
39 | // Released: 1/16/05 | |
40 | // Contacts: carlos.castil@sun.com / shahryar.aryani@sun.com | |
41 | // Description: Memory BIST Controller for Niagara2 NIU core | |
42 | // Block Type: Control Block | |
43 | // Chip Name: | |
44 | // Unit Name: | |
45 | // Module: | |
46 | // Where Instantiated: | |
47 | // | |
48 | // | |
49 | // (c) 2005 Sun Microsystems, Inc. | |
50 | // Sun Proprietary/Confidential | |
51 | // Internal use only. | |
52 | // | |
53 | // All rights reserved. No part of this design may be reproduced stored | |
54 | // in a retrieval system, or transmitted, in any form or by any means, | |
55 | // electronic, mechanical, photocopying, recording, or otherwise, without | |
56 | // prior written permission of Sun Microsystems, Inc. | |
57 | // | |
58 | /////////////////////////////////////////////////////////////////////////////// | |
59 | ||
60 | ||
61 | module niu_mb4 ( | |
62 | niu_mb4_desc_rd_en, | |
63 | niu_mb4_desc_wr_en, | |
64 | niu_mb4_comp_rd_en, | |
65 | niu_mb4_comp_wr_en, | |
66 | niu_mb4_addr, | |
67 | niu_mb4_wdata, | |
68 | niu_mb4_run, | |
69 | niu_tcu_mbist_fail_4, | |
70 | niu_tcu_mbist_done_4, | |
71 | mb4_scan_out, | |
72 | mb4_dmo_dout, | |
73 | l1clk, | |
74 | rst, | |
75 | tcu_mbist_user_mode, | |
76 | mb4_scan_in, | |
77 | tcu_aclk, | |
78 | tcu_bclk, | |
79 | tcu_niu_mbist_start_4, | |
80 | niu_mb4_rdmc_desc_data_out, | |
81 | niu_mb4_rdmc_comp_data_out, | |
82 | tcu_mbist_bisi_en); | |
83 | wire siclk; | |
84 | wire soclk; | |
85 | wire reset; | |
86 | wire config_reg_scanin; | |
87 | wire config_reg_scanout; | |
88 | wire [8:0] config_in; | |
89 | wire [8:0] config_out; | |
90 | wire start_transition; | |
91 | wire reset_engine; | |
92 | wire mbist_user_loop_mode; | |
93 | wire mbist_done; | |
94 | wire run; | |
95 | wire bisi; | |
96 | wire user_mode; | |
97 | wire user_data_mode; | |
98 | wire user_addr_mode; | |
99 | wire user_loop_mode; | |
100 | wire user_cmpsel_hold; | |
101 | wire ten_n_mode; | |
102 | wire mbist_user_data_mode; | |
103 | wire mbist_user_addr_mode; | |
104 | wire mbist_user_cmpsel_hold; | |
105 | wire mbist_ten_n_mode; | |
106 | wire user_data_reg_scanin; | |
107 | wire user_data_reg_scanout; | |
108 | wire [7:0] user_data_in; | |
109 | wire [7:0] user_data_out; | |
110 | wire user_start_addr_reg_scanin; | |
111 | wire user_start_addr_reg_scanout; | |
112 | wire [7:0] user_start_addr_in; | |
113 | wire [7:0] user_start_addr; | |
114 | wire user_stop_addr_reg_scanin; | |
115 | wire user_stop_addr_reg_scanout; | |
116 | wire [7:0] user_stop_addr_in; | |
117 | wire [7:0] user_stop_addr; | |
118 | wire user_incr_addr_reg_scanin; | |
119 | wire user_incr_addr_reg_scanout; | |
120 | wire [7:0] user_incr_addr_in; | |
121 | wire [7:0] user_incr_addr; | |
122 | wire user_array_sel_reg_scanin; | |
123 | wire user_array_sel_reg_scanout; | |
124 | wire user_array_sel_in; | |
125 | wire user_array_sel; | |
126 | wire user_cmpsel_reg_scanin; | |
127 | wire user_cmpsel_reg_scanout; | |
128 | wire [1:0] user_cmpsel_in; | |
129 | wire [1:0] user_cmpsel; | |
130 | wire user_bisi_wr_reg_scanin; | |
131 | wire user_bisi_wr_reg_scanout; | |
132 | wire user_bisi_wr_mode_in; | |
133 | wire user_bisi_wr_mode; | |
134 | wire user_bisi_rd_reg_scanin; | |
135 | wire user_bisi_rd_reg_scanout; | |
136 | wire user_bisi_rd_mode_in; | |
137 | wire user_bisi_rd_mode; | |
138 | wire mbist_user_bisi_wr_mode; | |
139 | wire mbist_user_bisi_wr_rd_mode; | |
140 | wire start_transition_reg_scanin; | |
141 | wire start_transition_reg_scanout; | |
142 | wire start_transition_piped; | |
143 | wire run_reg_scanin; | |
144 | wire run_reg_scanout; | |
145 | wire run1_reg_scanin; | |
146 | wire run1_reg_scanout; | |
147 | wire run1_in; | |
148 | wire run1_out; | |
149 | wire run2_reg_scanin; | |
150 | wire run2_reg_scanout; | |
151 | wire run2_in; | |
152 | wire run2_out; | |
153 | wire run_piped3; | |
154 | wire msb; | |
155 | wire control_reg_scanin; | |
156 | wire control_reg_scanout; | |
157 | wire [22:0] control_in; | |
158 | wire [22:0] control_out; | |
159 | wire bisi_wr_rd; | |
160 | wire array_sel; | |
161 | wire [1:0] cmpsel; | |
162 | wire [1:0] data_control; | |
163 | wire address_mix; | |
164 | wire [3:0] march_element; | |
165 | wire [7:0] array_address; | |
166 | wire upaddress_march; | |
167 | wire [2:0] read_write_control; | |
168 | wire five_cycle_march; | |
169 | wire increment_addr; | |
170 | wire [7:0] start_addr; | |
171 | wire [7:0] next_array_address; | |
172 | wire next_upaddr_march; | |
173 | wire next_downaddr_march; | |
174 | wire [7:0] stop_addr; | |
175 | wire [8:0] overflow_addr; | |
176 | wire [7:0] incr_addr; | |
177 | wire overflow; | |
178 | wire [8:0] compare_addr; | |
179 | wire [7:0] add; | |
180 | wire [7:0] adj_address; | |
181 | wire [7:0] mbist_address; | |
182 | wire increment_march_elem; | |
183 | wire next_array_sel; | |
184 | wire [1:0] next_cmpsel; | |
185 | wire [1:0] next_data_control; | |
186 | wire next_address_mix; | |
187 | wire [3:0] next_march_element; | |
188 | wire array_write; | |
189 | wire one_op_march; | |
190 | wire array_read; | |
191 | wire [7:0] mbist_wdata; | |
192 | wire true_data; | |
193 | wire [7:0] data_pattern; | |
194 | wire array_sel0; | |
195 | wire array_sel1; | |
196 | wire [7:0] exp_read_data; | |
197 | wire done_counter_reg_scanin; | |
198 | wire done_counter_reg_scanout; | |
199 | wire [2:0] done_counter_in; | |
200 | wire [2:0] done_counter_out; | |
201 | wire done_reg_in; | |
202 | wire done_reg_out; | |
203 | wire done_reg_scanin; | |
204 | wire done_reg_scanout; | |
205 | wire data_pipe_reg1_scanin; | |
206 | wire data_pipe_reg1_scanout; | |
207 | wire [7:0] data_pipe_reg1_in; | |
208 | wire [7:0] data_pipe_out1; | |
209 | wire data_pipe_reg2_scanin; | |
210 | wire data_pipe_reg2_scanout; | |
211 | wire [7:0] data_pipe_reg2_in; | |
212 | wire [7:0] data_pipe_out2; | |
213 | wire [7:0] old_piped_data; | |
214 | wire cmpsel_reg1_scanin; | |
215 | wire cmpsel_reg1_scanout; | |
216 | wire [1:0] cmpsel_reg1_in; | |
217 | wire [1:0] cmpsel_reg1_out1; | |
218 | wire [1:0] cmpsel_pipe1; | |
219 | wire ren_pipe_reg1_scanin; | |
220 | wire ren_pipe_reg1_scanout; | |
221 | wire ren_pipe_reg1_in; | |
222 | wire ren_pipe_out1; | |
223 | wire ren_pipe_reg2_scanin; | |
224 | wire ren_pipe_reg2_scanout; | |
225 | wire ren_pipe_reg2_in; | |
226 | wire ren_pipe_out2; | |
227 | wire old_piped_ren; | |
228 | wire sel_pipe_reg1_scanin; | |
229 | wire sel_pipe_reg1_scanout; | |
230 | wire sel_pipe_reg1_in; | |
231 | wire sel_pipe_out1; | |
232 | wire sel_pipe_reg2_scanin; | |
233 | wire sel_pipe_reg2_scanout; | |
234 | wire sel_pipe_reg2_in; | |
235 | wire sel_pipe_out2; | |
236 | wire old_piped_sel; | |
237 | wire old_piped_sel1; | |
238 | wire fail_out_reg_in; | |
239 | wire fail; | |
240 | wire fail_out_reg_out; | |
241 | wire fail_out_reg_scanin; | |
242 | wire fail_out_reg_scanout; | |
243 | wire [39:0] read_data_reg_in; | |
244 | wire [39:0] read_data_mux2; | |
245 | wire [39:0] read_data_reg_out; | |
246 | wire read_data_pipe_reg_scanin; | |
247 | wire read_data_pipe_reg_scanout; | |
248 | wire fail_reg_scanin; | |
249 | wire fail_reg_scanout; | |
250 | wire [1:0] fail_reg_in; | |
251 | wire [1:0] fail_reg_out; | |
252 | wire qual_old_fail1; | |
253 | wire qual_old_fail0; | |
254 | wire fail_detect; | |
255 | wire qual_old_fail; | |
256 | wire [147:0] read_data_mux1; | |
257 | ||
258 | ||
259 | ||
260 | ||
261 | ||
262 | // ///////////////////////////////////////////////////////////////////////////// | |
263 | // Outputs | |
264 | // ///////////////////////////////////////////////////////////////////////////// | |
265 | ||
266 | output niu_mb4_desc_rd_en; | |
267 | output niu_mb4_desc_wr_en; | |
268 | ||
269 | output niu_mb4_comp_rd_en; | |
270 | output niu_mb4_comp_wr_en; | |
271 | ||
272 | output [7:0] niu_mb4_addr; | |
273 | output [7:0] niu_mb4_wdata; | |
274 | ||
275 | output niu_mb4_run; | |
276 | ||
277 | output niu_tcu_mbist_fail_4; | |
278 | output niu_tcu_mbist_done_4; | |
279 | ||
280 | output mb4_scan_out; | |
281 | ||
282 | output [39:0] mb4_dmo_dout; | |
283 | ||
284 | ||
285 | // ///////////////////////////////////////////////////////////////////////////// | |
286 | // Inputs | |
287 | // ///////////////////////////////////////////////////////////////////////////// | |
288 | ||
289 | input l1clk; | |
290 | input rst; | |
291 | input tcu_mbist_user_mode; | |
292 | ||
293 | input mb4_scan_in; | |
294 | ||
295 | input tcu_aclk; | |
296 | input tcu_bclk; | |
297 | ||
298 | input tcu_niu_mbist_start_4; | |
299 | ||
300 | input [147:0] niu_mb4_rdmc_desc_data_out; | |
301 | input [147:0] niu_mb4_rdmc_comp_data_out; | |
302 | ||
303 | input tcu_mbist_bisi_en; | |
304 | ||
305 | ||
306 | // ///////////////////////////////////////////////////////////////////////////// | |
307 | // Scan Renames | |
308 | // ///////////////////////////////////////////////////////////////////////////// | |
309 | ||
310 | // assign se = tcu_scan_en; | |
311 | // assign pce_ov = tcu_pce_ov; | |
312 | // assign stop = tcu_clk_stop; | |
313 | ||
314 | assign siclk = tcu_aclk; | |
315 | assign soclk = tcu_bclk; | |
316 | ||
317 | // ///////////////////////////////////////////////////////////////////////////// | |
318 | // Invert reset | |
319 | // ///////////////////////////////////////////////////////////////////////////// | |
320 | ||
321 | assign reset = ~rst; | |
322 | ||
323 | //////////////////////////////////////////////////////////////////////////////// | |
324 | // Clock header | |
325 | ||
326 | // l1clkhdr_ctl_macro clkgen ( | |
327 | // .l2clk (iol2clk ), | |
328 | // .l1en (1'b1 ), | |
329 | // .l1clk (l1clk ) | |
330 | // ); | |
331 | //assign siclk = 1'b0; | |
332 | //assign soclk = 1'b0; | |
333 | ||
334 | ||
335 | // ///////////////////////////////////////////////////////////////////////////// | |
336 | // | |
337 | // MBIST Config Register | |
338 | // | |
339 | // ///////////////////////////////////////////////////////////////////////////// | |
340 | // | |
341 | // A low to high transition on mbist_start will reset and start the engine. | |
342 | // mbist_start must remain active high for the duration of MBIST. | |
343 | // If mbist_start deasserts the engine will stop but not reset. | |
344 | // Once MBIST has completed niu_tcu_mbist_done_4 will assert and the fail status | |
345 | // signals will be valid. | |
346 | // To run MBIST again the mbist_start signal must transition low then high. | |
347 | // | |
348 | // Loop on Address will disable the address mix function. | |
349 | // | |
350 | // ///////////////////////////////////////////////////////////////////////////// | |
351 | ||
352 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_9 config_reg ( | |
353 | .scan_in(config_reg_scanin), | |
354 | .scan_out(config_reg_scanout), | |
355 | .din ( config_in[8:0] ), | |
356 | .dout ( config_out[8:0] ), | |
357 | .reset(reset), | |
358 | .l1clk(l1clk), | |
359 | .siclk(siclk), | |
360 | .soclk(soclk)); | |
361 | ||
362 | assign config_in[0] = tcu_niu_mbist_start_4; | |
363 | assign config_in[1] = config_out[0]; | |
364 | assign start_transition = config_out[0] & ~config_out[1]; | |
365 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); | |
366 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! | |
367 | ||
368 | assign config_in[2] = start_transition ? tcu_mbist_bisi_en: config_out[2]; | |
369 | assign bisi = config_out[2]; | |
370 | ||
371 | assign config_in[3] = start_transition ? tcu_mbist_user_mode : config_out[3]; | |
372 | assign user_mode = config_out[3]; | |
373 | ||
374 | assign config_in[4] = config_out[4]; | |
375 | assign user_data_mode = config_out[4]; | |
376 | ||
377 | assign config_in[5] = config_out[5]; | |
378 | assign user_addr_mode = config_out[5]; | |
379 | ||
380 | assign config_in[6] = config_out[6]; | |
381 | assign user_loop_mode = config_out[6]; | |
382 | ||
383 | assign config_in[7] = config_out[7]; | |
384 | assign user_cmpsel_hold = config_out[7]; //cmpsel_hold = 0 : Default, All cominations | |
385 | // = 1 : | |
386 | // User-specified cmpsel | |
387 | ||
388 | assign config_in[8] = config_out[8]; | |
389 | assign ten_n_mode = config_out[8]; | |
390 | ||
391 | assign mbist_user_data_mode = user_mode & user_data_mode; | |
392 | assign mbist_user_addr_mode = user_mode & user_addr_mode; | |
393 | assign mbist_user_loop_mode = user_mode & user_loop_mode; | |
394 | assign mbist_user_cmpsel_hold = user_mode & user_cmpsel_hold; | |
395 | assign mbist_ten_n_mode = user_mode & ten_n_mode; | |
396 | ||
397 | ||
398 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_8 user_data_reg ( | |
399 | .scan_in(user_data_reg_scanin), | |
400 | .scan_out(user_data_reg_scanout), | |
401 | .din ( user_data_in[7:0] ), | |
402 | .dout ( user_data_out[7:0] ), | |
403 | .reset(reset), | |
404 | .l1clk(l1clk), | |
405 | .siclk(siclk), | |
406 | .soclk(soclk)); | |
407 | ||
408 | assign user_data_in[7:0] = user_data_out[7:0]; | |
409 | ||
410 | // Defining User start, stop, and increment addresses. | |
411 | ||
412 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_8 user_start_addr_reg ( | |
413 | .scan_in(user_start_addr_reg_scanin), | |
414 | .scan_out(user_start_addr_reg_scanout), | |
415 | .din ( user_start_addr_in[7:0] ), | |
416 | .dout ( user_start_addr[7:0] ), | |
417 | .reset(reset), | |
418 | .l1clk(l1clk), | |
419 | .siclk(siclk), | |
420 | .soclk(soclk)); | |
421 | ||
422 | assign user_start_addr_in[7:0] = user_start_addr[7:0]; | |
423 | ||
424 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_8 user_stop_addr_reg ( | |
425 | .scan_in(user_stop_addr_reg_scanin), | |
426 | .scan_out(user_stop_addr_reg_scanout), | |
427 | .din ( user_stop_addr_in[7:0] ), | |
428 | .dout ( user_stop_addr[7:0] ), | |
429 | .reset(reset), | |
430 | .l1clk(l1clk), | |
431 | .siclk(siclk), | |
432 | .soclk(soclk)); | |
433 | ||
434 | assign user_stop_addr_in[7:0] = user_stop_addr[7:0]; | |
435 | ||
436 | ||
437 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_8 user_incr_addr_reg ( | |
438 | .scan_in(user_incr_addr_reg_scanin), | |
439 | .scan_out(user_incr_addr_reg_scanout), | |
440 | .din ( user_incr_addr_in[7:0] ), | |
441 | .dout ( user_incr_addr[7:0] ), | |
442 | .reset(reset), | |
443 | .l1clk(l1clk), | |
444 | .siclk(siclk), | |
445 | .soclk(soclk)); | |
446 | ||
447 | assign user_incr_addr_in[7:0] = user_incr_addr[7:0]; | |
448 | ||
449 | // Defining User array_sel. | |
450 | ||
451 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 user_array_sel_reg ( | |
452 | .scan_in(user_array_sel_reg_scanin), | |
453 | .scan_out(user_array_sel_reg_scanout), | |
454 | .din ( user_array_sel_in ), | |
455 | .dout ( user_array_sel ), | |
456 | .reset(reset), | |
457 | .l1clk(l1clk), | |
458 | .siclk(siclk), | |
459 | .soclk(soclk)); | |
460 | ||
461 | assign user_array_sel_in = user_array_sel; | |
462 | ||
463 | // Defining User cmpsel. | |
464 | ||
465 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_2 user_cmpsel_reg ( | |
466 | .scan_in(user_cmpsel_reg_scanin), | |
467 | .scan_out(user_cmpsel_reg_scanout), | |
468 | .din ( user_cmpsel_in[1:0] ), | |
469 | .dout ( user_cmpsel[1:0] ), | |
470 | .reset(reset), | |
471 | .l1clk(l1clk), | |
472 | .siclk(siclk), | |
473 | .soclk(soclk)); | |
474 | ||
475 | assign user_cmpsel_in[1:0] = user_cmpsel[1:0]; | |
476 | ||
477 | // Defining user_bisi write and read registers | |
478 | ||
479 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_wr_reg ( | |
480 | .scan_in(user_bisi_wr_reg_scanin), | |
481 | .scan_out(user_bisi_wr_reg_scanout), | |
482 | .din ( user_bisi_wr_mode_in ), | |
483 | .dout ( user_bisi_wr_mode ), | |
484 | .reset(reset), | |
485 | .l1clk(l1clk), | |
486 | .siclk(siclk), | |
487 | .soclk(soclk)); | |
488 | ||
489 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; | |
490 | ||
491 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 user_bisi_rd_reg ( | |
492 | .scan_in(user_bisi_rd_reg_scanin), | |
493 | .scan_out(user_bisi_rd_reg_scanout), | |
494 | .din ( user_bisi_rd_mode_in ), | |
495 | .dout ( user_bisi_rd_mode ), | |
496 | .reset(reset), | |
497 | .l1clk(l1clk), | |
498 | .siclk(siclk), | |
499 | .soclk(soclk)); | |
500 | ||
501 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; | |
502 | ||
503 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; | |
504 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; | |
505 | ||
506 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & | |
507 | ((user_bisi_wr_mode & user_bisi_rd_mode) | | |
508 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); | |
509 | ||
510 | ||
511 | //////////////////////////////////////////////////////////////////////////////// | |
512 | // Piping start_transition | |
513 | //////////////////////////////////////////////////////////////////////////////// | |
514 | ||
515 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 start_transition_reg ( | |
516 | .scan_in(start_transition_reg_scanin), | |
517 | .scan_out(start_transition_reg_scanout), | |
518 | .din ( start_transition ), | |
519 | .dout ( start_transition_piped ), | |
520 | .reset(reset), | |
521 | .l1clk(l1clk), | |
522 | .siclk(siclk), | |
523 | .soclk(soclk)); | |
524 | ||
525 | ||
526 | //////////////////////////////////////////////////////////////////////////////// | |
527 | // Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. | |
528 | //////////////////////////////////////////////////////////////////////////////// | |
529 | ||
530 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 run_reg ( | |
531 | .scan_in(run_reg_scanin), | |
532 | .scan_out(run_reg_scanout), | |
533 | .din ( run ), | |
534 | .dout ( niu_mb4_run ), | |
535 | .reset(reset), | |
536 | .l1clk(l1clk), | |
537 | .siclk(siclk), | |
538 | .soclk(soclk)); | |
539 | ||
540 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 run1_reg ( | |
541 | .scan_in(run1_reg_scanin), | |
542 | .scan_out(run1_reg_scanout), | |
543 | .din ( run1_in ), | |
544 | .dout ( run1_out ), | |
545 | .reset(reset), | |
546 | .l1clk(l1clk), | |
547 | .siclk(siclk), | |
548 | .soclk(soclk)); | |
549 | ||
550 | assign run1_in = reset_engine ? 1'b0: niu_mb4_run; | |
551 | ||
552 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 run2_reg ( | |
553 | .scan_in(run2_reg_scanin), | |
554 | .scan_out(run2_reg_scanout), | |
555 | .din ( run2_in ), | |
556 | .dout ( run2_out ), | |
557 | .reset(reset), | |
558 | .l1clk(l1clk), | |
559 | .siclk(siclk), | |
560 | .soclk(soclk)); | |
561 | ||
562 | assign run2_in = reset_engine ? 1'b0: run1_out; | |
563 | assign run_piped3 = config_out[0] & run2_out & ~msb; | |
564 | ||
565 | ||
566 | // ///////////////////////////////////////////////////////////////////////////// | |
567 | // | |
568 | // MBIST Control Register | |
569 | // | |
570 | // ///////////////////////////////////////////////////////////////////////////// | |
571 | // Remove Address mix disable before delivery | |
572 | // ///////////////////////////////////////////////////////////////////////////// | |
573 | ||
574 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_23 control_reg ( | |
575 | .scan_in(control_reg_scanin), | |
576 | .scan_out(control_reg_scanout), | |
577 | .din ( control_in[22:0] ), | |
578 | .dout ( control_out[22:0] ), | |
579 | .reset(reset), | |
580 | .l1clk(l1clk), | |
581 | .siclk(siclk), | |
582 | .soclk(soclk)); | |
583 | ||
584 | ||
585 | assign msb = control_out[22]; | |
586 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[21] : 1'b1; | |
587 | assign array_sel = user_mode ? user_array_sel : control_out[20]; | |
588 | assign cmpsel[1:0] = mbist_user_cmpsel_hold ? user_cmpsel[1:0] : control_out[19:18]; | |
589 | assign data_control[1:0] = control_out[17:16]; | |
590 | assign address_mix = (bisi | mbist_user_addr_mode) ? 1'b0 : control_out[15]; | |
591 | assign march_element[3:0] = control_out[14:11]; | |
592 | ||
593 | assign array_address[7:0] = upaddress_march ? control_out[10:3] : ~control_out[10:3]; | |
594 | ||
595 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : | |
596 | control_out[2:0]; | |
597 | ||
598 | assign control_in[2:0] = reset_engine ? 3'b0: | |
599 | ~run_piped3 ? control_out[2:0]: | |
600 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: | |
601 | (read_write_control[2:0] == 3'b110 ) ? 3'b000: | |
602 | control_out[2:0] + 3'b001; | |
603 | ||
604 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || | |
605 | (read_write_control[2:0] == 3'b110); | |
606 | ||
607 | // start_transition_piped was added to have the correct start_addr at the start | |
608 | // of mbist during user_addr_mode | |
609 | assign control_in[10:3] = start_transition_piped || reset_engine ? start_addr[7:0]: | |
610 | ~run_piped3 || ~increment_addr ? control_out[10:3]: | |
611 | next_array_address[7:0]; | |
612 | ||
613 | assign next_array_address[7:0] = next_upaddr_march ? start_addr[7:0]: | |
614 | next_downaddr_march ? ~stop_addr[7:0]: | |
615 | (overflow_addr[7:0]); // array_addr + incr_addr | |
616 | ||
617 | assign start_addr[7:0] = mbist_user_addr_mode ? user_start_addr[7:0]: 8'b00000000; | |
618 | assign stop_addr[7:0] = mbist_user_addr_mode ? user_stop_addr[7:0] : 8'b11111111; | |
619 | ||
620 | assign incr_addr[7:0] = mbist_user_addr_mode ? user_incr_addr[7:0] : 8'b00000001; | |
621 | ||
622 | assign overflow_addr[8:0] = {1'b0,control_out[10:3]} + {1'b0,incr_addr[7:0]}; | |
623 | assign overflow = compare_addr[8:0] < overflow_addr[8:0]; | |
624 | ||
625 | assign compare_addr[8:0] = upaddress_march ? {1'b0, stop_addr[7:0]} : | |
626 | {1'b0, ~start_addr[7:0]}; | |
627 | ||
628 | ||
629 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
630 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || | |
631 | (march_element[3:0] == 4'h8) ) && overflow; | |
632 | ||
633 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || | |
634 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && | |
635 | overflow; | |
636 | ||
637 | ||
638 | assign add[7:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || | |
639 | (read_write_control[2:0] == 3'h3)) ? | |
640 | adj_address[7:0]: array_address[7:0]; | |
641 | ||
642 | // cc 051505 question ? | |
643 | // is niu_mb4 testing 2 bit col addr arrays ???? cc 051505 | |
644 | // assign adj_address[5:0] = array_sel1 ? { array_address[5:3], ~array_address[2], array_address[1:0]} : //2 bit col addr | |
645 | ||
646 | assign adj_address[7:0] = address_mix ? { array_address[7:1], ~array_address[0] } : | |
647 | { array_address[7:3], ~array_address[2], array_address[1:0]}; | |
648 | ||
649 | // cc 011505 question? | |
650 | // is niu_mb4 testing "Fast bank" or "Fast row" arrays ? assume Random | |
651 | // assign mbist_address[5:0] = address_mix & tdb_sel ? {add[1:0],add[8:2]}: // Fast row | |
652 | // address_mix & diu_sel ? {add[8], add[5:0], add[7:6]}: // Fast bank | |
653 | // address_mix & dma_data_sel ? {add[8:7], add[5:0], add[6]}: // Fast bank | |
654 | // address_mix & pio_data_sel ? {add[8:4], add[2:0], add[3]}: // Random | |
655 | // address_mix & dev_sel ? {add[8:4], add[2:0], add[3]}: // Random | |
656 | // address_mix & tsb_sel ? {add[8:5], add[3:0], add[4]}: // Fast bank | |
657 | // add[8:0]; // Needs to be verified!!! | |
658 | ||
659 | assign mbist_address[7:0] = address_mix ? {add[5:0], add[7:6]} : // Fast row | |
660 | add[7:0]; // Fast column | |
661 | ||
662 | ||
663 | // Definition of the rest of the control register | |
664 | ||
665 | assign increment_march_elem = increment_addr && overflow; | |
666 | ||
667 | assign control_in[22:11] = reset_engine ? 12'b0: | |
668 | ~run_piped3 ? control_out[22:11]: | |
669 | {msb, bisi_wr_rd, next_array_sel, next_cmpsel[1:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} + | |
670 | {11'b0, increment_march_elem}; | |
671 | ||
672 | assign next_address_mix = ( bisi | mbist_user_addr_mode) ? 1'b1 : address_mix; | |
673 | ||
674 | assign next_array_sel = user_mode ? 1'b1 : control_out[20]; | |
675 | ||
676 | assign next_cmpsel[1:0] = ( mbist_user_cmpsel_hold || (~bisi_wr_rd) || mbist_user_bisi_wr_mode ) ? 2'b11 : control_out[19:18]; | |
677 | ||
678 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: | |
679 | data_control[1:0]; | |
680 | ||
681 | // Incorporated ten_n_mode! | |
682 | assign next_march_element[3:0] = ( bisi || | |
683 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || | |
684 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
685 | && overflow ? 4'b1111: march_element[3:0]; | |
686 | ||
687 | ||
688 | assign array_write = ~run_piped3 ? 1'b0: | |
689 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || | |
690 | (read_write_control[2:0] == 3'h1) || | |
691 | (read_write_control[2:0] == 3'h4): | |
692 | (~five_cycle_march & ~one_op_march) ? (read_write_control[0] == 1'b0) : | |
693 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7) ); | |
694 | ||
695 | assign array_read = (~five_cycle_march & ~one_op_march) ? run_piped3 : | |
696 | (~array_write) && run_piped3; | |
697 | ||
698 | ||
699 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; | |
700 | ||
701 | ||
702 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); | |
703 | assign one_op_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || | |
704 | (march_element[3:0] == 4'h7); | |
705 | ||
706 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
707 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || | |
708 | (march_element[3:0] == 4'h7); | |
709 | ||
710 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? | |
711 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): | |
712 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? | |
713 | ((read_write_control[2:0] == 3'h1) || | |
714 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): | |
715 | one_op_march ? (march_element[3:0] == 4'h7) : | |
716 | (march_element[3:0] == 4'h1) || (march_element[3:0] == 4'h3); | |
717 | ||
718 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: | |
719 | mbist_user_data_mode ? user_data_out[7:0]: | |
720 | bisi ? 8'hFF: // true_data function will invert to 8'h00 | |
721 | (data_control[1:0] == 2'h0) ? 8'hAA: | |
722 | (data_control[1:0] == 2'h1) ? 8'h99: | |
723 | (data_control[1:0] == 2'h2) ? 8'hCC: | |
724 | 8'h00; | |
725 | ||
726 | // ///////////////////////////////////////////////////////////////////////////// | |
727 | // Write data and address may need pipelining !!! | |
728 | // ///////////////////////////////////////////////////////////////////////////// | |
729 | ||
730 | assign niu_mb4_wdata[7:0] = mbist_wdata[7:0]; | |
731 | assign niu_mb4_addr[7:0] = mbist_address[7:0]; | |
732 | ||
733 | ||
734 | // ///////////////////////////////////////////////////////////////////////////// | |
735 | // Read and write selects | |
736 | // ///////////////////////////////////////////////////////////////////////////// | |
737 | ||
738 | assign array_sel0 = ~array_sel; | |
739 | assign array_sel1 = array_sel; | |
740 | ||
741 | assign niu_mb4_comp_rd_en = (array_sel0 && array_read); | |
742 | assign niu_mb4_comp_wr_en = ((array_sel0) && array_write); | |
743 | ||
744 | assign niu_mb4_desc_rd_en = (array_sel1 && array_read); | |
745 | assign niu_mb4_desc_wr_en = (array_sel1 && array_write); | |
746 | ||
747 | assign exp_read_data[7:0] = (~five_cycle_march & ~one_op_march) ? ~mbist_wdata[7:0] : mbist_wdata[7:0]; | |
748 | ||
749 | ///////////////////////////////////////////////////////////////////////// | |
750 | // Creating the mbist_done signal | |
751 | ///////////////////////////////////////////////////////////////////////// | |
752 | // Delaying mbist_done 8 clock signals after msb going high, to provide | |
753 | // a generic solution for done going high after the last fail has come back! | |
754 | ||
755 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_3 done_counter_reg ( | |
756 | .scan_in(done_counter_reg_scanin), | |
757 | .scan_out(done_counter_reg_scanout), | |
758 | .din ( done_counter_in[2:0] ), | |
759 | .dout ( done_counter_out[2:0] ), | |
760 | .reset(reset), | |
761 | .l1clk(l1clk), | |
762 | .siclk(siclk), | |
763 | .soclk(soclk)); | |
764 | ||
765 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start | |
766 | // goes low. | |
767 | ||
768 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; | |
769 | assign done_counter_in[2:0] = reset_engine ? 3'b000: | |
770 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: | |
771 | done_counter_out[2:0]; | |
772 | ||
773 | // ///////////////////////////////////////////////////////////////////////////// | |
774 | // Done Detection | |
775 | // ///////////////////////////////////////////////////////////////////////////// | |
776 | ||
777 | assign done_reg_in = mbist_done; | |
778 | assign niu_tcu_mbist_done_4 = done_reg_out; | |
779 | ||
780 | ||
781 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 done_reg ( | |
782 | .scan_in(done_reg_scanin), | |
783 | .scan_out(done_reg_scanout), | |
784 | .din ( done_reg_in ), | |
785 | .dout ( done_reg_out ), | |
786 | .reset(reset), | |
787 | .l1clk(l1clk), | |
788 | .siclk(siclk), | |
789 | .soclk(soclk)); | |
790 | ||
791 | ||
792 | // ///////////////////////////////////////////////////////////////////////////// | |
793 | // Pipeline for wdata, and Read_en | |
794 | // ///////////////////////////////////////////////////////////////////////////// | |
795 | ||
796 | // ///////////////////////////////////////////////////////////////////////////// | |
797 | // Pipeline for wdata | |
798 | // ///////////////////////////////////////////////////////////////////////////// | |
799 | ||
800 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg1 ( | |
801 | .scan_in(data_pipe_reg1_scanin), | |
802 | .scan_out(data_pipe_reg1_scanout), | |
803 | .din ( data_pipe_reg1_in[7:0] ), | |
804 | .dout ( data_pipe_out1[7:0] ), | |
805 | .reset(reset), | |
806 | .l1clk(l1clk), | |
807 | .siclk(siclk), | |
808 | .soclk(soclk)); | |
809 | ||
810 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_8 data_pipe_reg2 ( | |
811 | .scan_in(data_pipe_reg2_scanin), | |
812 | .scan_out(data_pipe_reg2_scanout), | |
813 | .din ( data_pipe_reg2_in[7:0] ), | |
814 | .dout ( data_pipe_out2[7:0] ), | |
815 | .reset(reset), | |
816 | .l1clk(l1clk), | |
817 | .siclk(siclk), | |
818 | .soclk(soclk)); | |
819 | ||
820 | //Adding an extra level of pipe since piping the read_data | |
821 | //msff_ctl_macro data_pipe_reg3 (width=8)( | |
822 | // .scan_in(data_pipe_reg3_scanin), | |
823 | // .scan_out(data_pipe_reg3_scanout), | |
824 | // .din ( data_pipe_reg3_in[7:0] ), | |
825 | // .dout ( data_pipe_out3[7:0] )); | |
826 | ||
827 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: exp_read_data[7:0]; | |
828 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; | |
829 | //assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; | |
830 | //assign old_piped_data[7:0] = data_pipe_out3[7:0]; | |
831 | assign old_piped_data[7:0] = data_pipe_out2[7:0]; | |
832 | ||
833 | // ///////////////////////////////////////////////////////////////////////////// | |
834 | // Pipeline for comp sel | |
835 | // ///////////////////////////////////////////////////////////////////////////// | |
836 | ||
837 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_2 cmpsel_reg1 ( | |
838 | .scan_in(cmpsel_reg1_scanin), | |
839 | .scan_out(cmpsel_reg1_scanout), | |
840 | .din ( cmpsel_reg1_in[ 1 : 0 ] ), | |
841 | .dout ( cmpsel_reg1_out1[ 1 : 0 ] ), | |
842 | .reset(reset), | |
843 | .l1clk(l1clk), | |
844 | .siclk(siclk), | |
845 | .soclk(soclk)); | |
846 | ||
847 | assign cmpsel_reg1_in[ 1 : 0 ] = cmpsel[ 1 : 0 ]; | |
848 | ||
849 | assign cmpsel_pipe1[ 1 : 0 ] = cmpsel_reg1_out1[ 1 : 0 ]; | |
850 | ||
851 | // ///////////////////////////////////////////////////////////////////////////// | |
852 | // Pipeline for Read_en | |
853 | // ///////////////////////////////////////////////////////////////////////////// | |
854 | ||
855 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg1 ( | |
856 | .scan_in(ren_pipe_reg1_scanin), | |
857 | .scan_out(ren_pipe_reg1_scanout), | |
858 | .din ( ren_pipe_reg1_in ), | |
859 | .dout ( ren_pipe_out1 ), | |
860 | .reset(reset), | |
861 | .l1clk(l1clk), | |
862 | .siclk(siclk), | |
863 | .soclk(soclk)); | |
864 | ||
865 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 ren_pipe_reg2 ( | |
866 | .scan_in(ren_pipe_reg2_scanin), | |
867 | .scan_out(ren_pipe_reg2_scanout), | |
868 | .din ( ren_pipe_reg2_in ), | |
869 | .dout ( ren_pipe_out2 ), | |
870 | .reset(reset), | |
871 | .l1clk(l1clk), | |
872 | .siclk(siclk), | |
873 | .soclk(soclk)); | |
874 | ||
875 | //Adding an extra level of pipe since piping the read_data | |
876 | //msff_ctl_macro ren_pipe_reg3 (width=1)( | |
877 | // .scan_in(ren_pipe_reg3_scanin), | |
878 | // .scan_out(ren_pipe_reg3_scanout), | |
879 | // .din ( ren_pipe_reg3_in ), | |
880 | // .dout ( ren_pipe_out3 )); | |
881 | ||
882 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; | |
883 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; | |
884 | //assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; | |
885 | //assign old_piped_ren = ren_pipe_out3; | |
886 | assign old_piped_ren = ren_pipe_out2; | |
887 | ||
888 | // piped sel | |
889 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 sel_pipe_reg1 ( | |
890 | .scan_in(sel_pipe_reg1_scanin), | |
891 | .scan_out(sel_pipe_reg1_scanout), | |
892 | .din ( sel_pipe_reg1_in ), | |
893 | .dout ( sel_pipe_out1 ), | |
894 | .reset(reset), | |
895 | .l1clk(l1clk), | |
896 | .siclk(siclk), | |
897 | .soclk(soclk)); | |
898 | ||
899 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 sel_pipe_reg2 ( | |
900 | .scan_in(sel_pipe_reg2_scanin), | |
901 | .scan_out(sel_pipe_reg2_scanout), | |
902 | .din ( sel_pipe_reg2_in ), | |
903 | .dout ( sel_pipe_out2 ), | |
904 | .reset(reset), | |
905 | .l1clk(l1clk), | |
906 | .siclk(siclk), | |
907 | .soclk(soclk)); | |
908 | ||
909 | assign sel_pipe_reg1_in = reset_engine ? 1'b0: array_sel; | |
910 | assign sel_pipe_reg2_in = reset_engine ? 1'b0: sel_pipe_out1; | |
911 | assign old_piped_sel = sel_pipe_out2; | |
912 | assign old_piped_sel1 = sel_pipe_out1; | |
913 | ||
914 | // ///////////////////////////////////////////////////////////////////////////// | |
915 | // Fail Detection | |
916 | // ///////////////////////////////////////////////////////////////////////////// | |
917 | ||
918 | assign fail_out_reg_in = fail; | |
919 | assign niu_tcu_mbist_fail_4 = fail_out_reg_out; | |
920 | ||
921 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 fail_out_reg ( | |
922 | .scan_in(fail_out_reg_scanin), | |
923 | .scan_out(fail_out_reg_scanout), | |
924 | .din ( fail_out_reg_in ), | |
925 | .dout ( fail_out_reg_out ), | |
926 | .reset(reset), | |
927 | .l1clk(l1clk), | |
928 | .siclk(siclk), | |
929 | .soclk(soclk)); | |
930 | ||
931 | // ///////////////////////////////////////////////////////////////////////////// | |
932 | // Fail Detection | |
933 | // ///////////////////////////////////////////////////////////////////////////// | |
934 | ||
935 | assign read_data_reg_in[39:0] = read_data_mux2[39:0]; | |
936 | assign mb4_dmo_dout[39:0] = read_data_reg_out[39:0]; | |
937 | ||
938 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_40 read_data_pipe_reg ( | |
939 | .scan_in(read_data_pipe_reg_scanin), | |
940 | .scan_out(read_data_pipe_reg_scanout), | |
941 | .din ( read_data_reg_in[39:0] ), | |
942 | .dout ( read_data_reg_out[39:0] ), | |
943 | .reset(reset), | |
944 | .l1clk(l1clk), | |
945 | .siclk(siclk), | |
946 | .soclk(soclk)); | |
947 | ||
948 | ||
949 | niu_mb4_msff_ctl_macro__library_a1__reset_1__width_2 fail_reg ( | |
950 | .scan_in(fail_reg_scanin), | |
951 | .scan_out(fail_reg_scanout), | |
952 | .din ( fail_reg_in ), | |
953 | .dout ( fail_reg_out ), | |
954 | .reset(reset), | |
955 | .l1clk(l1clk), | |
956 | .siclk(siclk), | |
957 | .soclk(soclk)); | |
958 | ||
959 | assign fail_reg_in[1:0] = reset_engine ? 2'b00 : {qual_old_fail1, qual_old_fail0} | fail_reg_out[1:0]; | |
960 | ||
961 | assign qual_old_fail0 = fail_detect && !old_piped_sel; | |
962 | assign qual_old_fail1 = fail_detect && old_piped_sel; | |
963 | assign qual_old_fail = qual_old_fail0 || qual_old_fail1; | |
964 | ||
965 | assign fail_detect = ({old_piped_data[ 7 : 0 ], | |
966 | old_piped_data[ 7 : 0 ], | |
967 | old_piped_data[ 7 : 0 ], | |
968 | old_piped_data[ 7 : 0 ], | |
969 | old_piped_data[ 7 : 0 ]}) != mb4_dmo_dout[ 39 : 0 ] && old_piped_ren; | |
970 | ||
971 | assign fail = mbist_done ? |fail_reg_out[1:0] : qual_old_fail; | |
972 | ||
973 | // Pipelining the read_data to meet the timing requirement | |
974 | // Check if need to reset?? | |
975 | ||
976 | assign read_data_mux1[147:0] = old_piped_sel1 ? niu_mb4_rdmc_desc_data_out[147:0] : | |
977 | niu_mb4_rdmc_comp_data_out[147:0]; | |
978 | ||
979 | assign read_data_mux2[39:0] = (cmpsel_pipe1[1:0] == 2'b00) ? read_data_mux1[39:0] : | |
980 | (cmpsel_pipe1[1:0] == 2'b01) ? read_data_mux1[79:40] : | |
981 | (cmpsel_pipe1[1:0] == 2'b10) ? read_data_mux1[119:80] : | |
982 | {data_pipe_out1[ 7 : 0 ], data_pipe_out1[ 7 : 4 ], read_data_mux1[ 147 : 120 ]} ; | |
983 | ||
984 | supply0 vss; // <- port for ground | |
985 | supply1 vdd; // <- port for power | |
986 | // ///////////////////////////////////////////////////////////////////////////// | |
987 | // fixscan start: | |
988 | assign config_reg_scanin = mb4_scan_in ; | |
989 | assign user_data_reg_scanin = config_reg_scanout ; | |
990 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; | |
991 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
992 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
993 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; | |
994 | assign user_cmpsel_reg_scanin = user_array_sel_reg_scanout; | |
995 | assign user_bisi_wr_reg_scanin = user_cmpsel_reg_scanout ; | |
996 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; | |
997 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; | |
998 | assign run_reg_scanin = start_transition_reg_scanout; | |
999 | assign run1_reg_scanin = run_reg_scanout ; | |
1000 | assign run2_reg_scanin = run1_reg_scanout ; | |
1001 | assign control_reg_scanin = run2_reg_scanout ; | |
1002 | assign done_counter_reg_scanin = control_reg_scanout ; | |
1003 | assign done_reg_scanin = done_counter_reg_scanout ; | |
1004 | assign data_pipe_reg1_scanin = done_reg_scanout ; | |
1005 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; | |
1006 | assign cmpsel_reg1_scanin = data_pipe_reg2_scanout ; | |
1007 | assign ren_pipe_reg1_scanin = cmpsel_reg1_scanout ; | |
1008 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; | |
1009 | assign sel_pipe_reg1_scanin = ren_pipe_reg2_scanout ; | |
1010 | assign sel_pipe_reg2_scanin = sel_pipe_reg1_scanout ; | |
1011 | assign fail_out_reg_scanin = sel_pipe_reg2_scanout ; | |
1012 | assign read_data_pipe_reg_scanin = fail_out_reg_scanout ; | |
1013 | assign fail_reg_scanin = read_data_pipe_reg_scanout; | |
1014 | assign mb4_scan_out = fail_reg_scanout ; | |
1015 | // fixscan end: | |
1016 | endmodule | |
1017 | // ///////////////////////////////////////////////////////////////////////////// | |
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | // any PARAMS parms go into naming of macro | |
1025 | ||
1026 | module niu_mb4_msff_ctl_macro__library_a1__reset_1__width_9 ( | |
1027 | din, | |
1028 | reset, | |
1029 | l1clk, | |
1030 | scan_in, | |
1031 | siclk, | |
1032 | soclk, | |
1033 | dout, | |
1034 | scan_out); | |
1035 | wire [8:0] fdin; | |
1036 | wire [8:1] sout; | |
1037 | ||
1038 | input [8:0] din; | |
1039 | input reset; | |
1040 | input l1clk; | |
1041 | input scan_in; | |
1042 | ||
1043 | ||
1044 | input siclk; | |
1045 | input soclk; | |
1046 | ||
1047 | output [8:0] dout; | |
1048 | output scan_out; | |
1049 | assign fdin[8:0] = din[8:0] & {9 {reset}}; | |
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | ||
1061 | ||
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | cl_a1_msff_syrst_4x d0_0 ( | |
1068 | .l1clk(l1clk), | |
1069 | .siclk(siclk), | |
1070 | .soclk(soclk), | |
1071 | .d(fdin[0]), | |
1072 | .si(sout[1]), | |
1073 | .so(scan_out), | |
1074 | .reset(reset), | |
1075 | .q(dout[0]) | |
1076 | ); | |
1077 | cl_a1_msff_syrst_4x d0_1 ( | |
1078 | .l1clk(l1clk), | |
1079 | .siclk(siclk), | |
1080 | .soclk(soclk), | |
1081 | .d(fdin[1]), | |
1082 | .si(sout[2]), | |
1083 | .so(sout[1]), | |
1084 | .reset(reset), | |
1085 | .q(dout[1]) | |
1086 | ); | |
1087 | cl_a1_msff_syrst_4x d0_2 ( | |
1088 | .l1clk(l1clk), | |
1089 | .siclk(siclk), | |
1090 | .soclk(soclk), | |
1091 | .d(fdin[2]), | |
1092 | .si(sout[3]), | |
1093 | .so(sout[2]), | |
1094 | .reset(reset), | |
1095 | .q(dout[2]) | |
1096 | ); | |
1097 | cl_a1_msff_syrst_4x d0_3 ( | |
1098 | .l1clk(l1clk), | |
1099 | .siclk(siclk), | |
1100 | .soclk(soclk), | |
1101 | .d(fdin[3]), | |
1102 | .si(sout[4]), | |
1103 | .so(sout[3]), | |
1104 | .reset(reset), | |
1105 | .q(dout[3]) | |
1106 | ); | |
1107 | cl_a1_msff_syrst_4x d0_4 ( | |
1108 | .l1clk(l1clk), | |
1109 | .siclk(siclk), | |
1110 | .soclk(soclk), | |
1111 | .d(fdin[4]), | |
1112 | .si(sout[5]), | |
1113 | .so(sout[4]), | |
1114 | .reset(reset), | |
1115 | .q(dout[4]) | |
1116 | ); | |
1117 | cl_a1_msff_syrst_4x d0_5 ( | |
1118 | .l1clk(l1clk), | |
1119 | .siclk(siclk), | |
1120 | .soclk(soclk), | |
1121 | .d(fdin[5]), | |
1122 | .si(sout[6]), | |
1123 | .so(sout[5]), | |
1124 | .reset(reset), | |
1125 | .q(dout[5]) | |
1126 | ); | |
1127 | cl_a1_msff_syrst_4x d0_6 ( | |
1128 | .l1clk(l1clk), | |
1129 | .siclk(siclk), | |
1130 | .soclk(soclk), | |
1131 | .d(fdin[6]), | |
1132 | .si(sout[7]), | |
1133 | .so(sout[6]), | |
1134 | .reset(reset), | |
1135 | .q(dout[6]) | |
1136 | ); | |
1137 | cl_a1_msff_syrst_4x d0_7 ( | |
1138 | .l1clk(l1clk), | |
1139 | .siclk(siclk), | |
1140 | .soclk(soclk), | |
1141 | .d(fdin[7]), | |
1142 | .si(sout[8]), | |
1143 | .so(sout[7]), | |
1144 | .reset(reset), | |
1145 | .q(dout[7]) | |
1146 | ); | |
1147 | cl_a1_msff_syrst_4x d0_8 ( | |
1148 | .l1clk(l1clk), | |
1149 | .siclk(siclk), | |
1150 | .soclk(soclk), | |
1151 | .d(fdin[8]), | |
1152 | .si(scan_in), | |
1153 | .so(sout[8]), | |
1154 | .reset(reset), | |
1155 | .q(dout[8]) | |
1156 | ); | |
1157 | ||
1158 | ||
1159 | ||
1160 | ||
1161 | endmodule | |
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | ||
1171 | ||
1172 | ||
1173 | ||
1174 | ||
1175 | // any PARAMS parms go into naming of macro | |
1176 | ||
1177 | module niu_mb4_msff_ctl_macro__library_a1__reset_1__width_8 ( | |
1178 | din, | |
1179 | reset, | |
1180 | l1clk, | |
1181 | scan_in, | |
1182 | siclk, | |
1183 | soclk, | |
1184 | dout, | |
1185 | scan_out); | |
1186 | wire [7:0] fdin; | |
1187 | wire [7:1] sout; | |
1188 | ||
1189 | input [7:0] din; | |
1190 | input reset; | |
1191 | input l1clk; | |
1192 | input scan_in; | |
1193 | ||
1194 | ||
1195 | input siclk; | |
1196 | input soclk; | |
1197 | ||
1198 | output [7:0] dout; | |
1199 | output scan_out; | |
1200 | assign fdin[7:0] = din[7:0] & {8 {reset}}; | |
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | cl_a1_msff_syrst_4x d0_0 ( | |
1219 | .l1clk(l1clk), | |
1220 | .siclk(siclk), | |
1221 | .soclk(soclk), | |
1222 | .d(fdin[0]), | |
1223 | .si(sout[1]), | |
1224 | .so(scan_out), | |
1225 | .reset(reset), | |
1226 | .q(dout[0]) | |
1227 | ); | |
1228 | cl_a1_msff_syrst_4x d0_1 ( | |
1229 | .l1clk(l1clk), | |
1230 | .siclk(siclk), | |
1231 | .soclk(soclk), | |
1232 | .d(fdin[1]), | |
1233 | .si(sout[2]), | |
1234 | .so(sout[1]), | |
1235 | .reset(reset), | |
1236 | .q(dout[1]) | |
1237 | ); | |
1238 | cl_a1_msff_syrst_4x d0_2 ( | |
1239 | .l1clk(l1clk), | |
1240 | .siclk(siclk), | |
1241 | .soclk(soclk), | |
1242 | .d(fdin[2]), | |
1243 | .si(sout[3]), | |
1244 | .so(sout[2]), | |
1245 | .reset(reset), | |
1246 | .q(dout[2]) | |
1247 | ); | |
1248 | cl_a1_msff_syrst_4x d0_3 ( | |
1249 | .l1clk(l1clk), | |
1250 | .siclk(siclk), | |
1251 | .soclk(soclk), | |
1252 | .d(fdin[3]), | |
1253 | .si(sout[4]), | |
1254 | .so(sout[3]), | |
1255 | .reset(reset), | |
1256 | .q(dout[3]) | |
1257 | ); | |
1258 | cl_a1_msff_syrst_4x d0_4 ( | |
1259 | .l1clk(l1clk), | |
1260 | .siclk(siclk), | |
1261 | .soclk(soclk), | |
1262 | .d(fdin[4]), | |
1263 | .si(sout[5]), | |
1264 | .so(sout[4]), | |
1265 | .reset(reset), | |
1266 | .q(dout[4]) | |
1267 | ); | |
1268 | cl_a1_msff_syrst_4x d0_5 ( | |
1269 | .l1clk(l1clk), | |
1270 | .siclk(siclk), | |
1271 | .soclk(soclk), | |
1272 | .d(fdin[5]), | |
1273 | .si(sout[6]), | |
1274 | .so(sout[5]), | |
1275 | .reset(reset), | |
1276 | .q(dout[5]) | |
1277 | ); | |
1278 | cl_a1_msff_syrst_4x d0_6 ( | |
1279 | .l1clk(l1clk), | |
1280 | .siclk(siclk), | |
1281 | .soclk(soclk), | |
1282 | .d(fdin[6]), | |
1283 | .si(sout[7]), | |
1284 | .so(sout[6]), | |
1285 | .reset(reset), | |
1286 | .q(dout[6]) | |
1287 | ); | |
1288 | cl_a1_msff_syrst_4x d0_7 ( | |
1289 | .l1clk(l1clk), | |
1290 | .siclk(siclk), | |
1291 | .soclk(soclk), | |
1292 | .d(fdin[7]), | |
1293 | .si(scan_in), | |
1294 | .so(sout[7]), | |
1295 | .reset(reset), | |
1296 | .q(dout[7]) | |
1297 | ); | |
1298 | ||
1299 | ||
1300 | ||
1301 | ||
1302 | endmodule | |
1303 | ||
1304 | ||
1305 | ||
1306 | ||
1307 | ||
1308 | ||
1309 | ||
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | ||
1316 | // any PARAMS parms go into naming of macro | |
1317 | ||
1318 | module niu_mb4_msff_ctl_macro__library_a1__reset_1__width_1 ( | |
1319 | din, | |
1320 | reset, | |
1321 | l1clk, | |
1322 | scan_in, | |
1323 | siclk, | |
1324 | soclk, | |
1325 | dout, | |
1326 | scan_out); | |
1327 | wire [0:0] fdin; | |
1328 | ||
1329 | input [0:0] din; | |
1330 | input reset; | |
1331 | input l1clk; | |
1332 | input scan_in; | |
1333 | ||
1334 | ||
1335 | input siclk; | |
1336 | input soclk; | |
1337 | ||
1338 | output [0:0] dout; | |
1339 | output scan_out; | |
1340 | assign fdin[0:0] = din[0:0] & {1 {reset}}; | |
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | ||
1349 | ||
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | cl_a1_msff_syrst_4x d0_0 ( | |
1359 | .l1clk(l1clk), | |
1360 | .siclk(siclk), | |
1361 | .soclk(soclk), | |
1362 | .d(fdin[0]), | |
1363 | .si(scan_in), | |
1364 | .so(scan_out), | |
1365 | .reset(reset), | |
1366 | .q(dout[0]) | |
1367 | ); | |
1368 | ||
1369 | ||
1370 | ||
1371 | ||
1372 | endmodule | |
1373 | ||
1374 | ||
1375 | ||
1376 | ||
1377 | ||
1378 | ||
1379 | ||
1380 | ||
1381 | ||
1382 | ||
1383 | ||
1384 | ||
1385 | ||
1386 | // any PARAMS parms go into naming of macro | |
1387 | ||
1388 | module niu_mb4_msff_ctl_macro__library_a1__reset_1__width_2 ( | |
1389 | din, | |
1390 | reset, | |
1391 | l1clk, | |
1392 | scan_in, | |
1393 | siclk, | |
1394 | soclk, | |
1395 | dout, | |
1396 | scan_out); | |
1397 | wire [1:0] fdin; | |
1398 | wire [1:1] sout; | |
1399 | ||
1400 | input [1:0] din; | |
1401 | input reset; | |
1402 | input l1clk; | |
1403 | input scan_in; | |
1404 | ||
1405 | ||
1406 | input siclk; | |
1407 | input soclk; | |
1408 | ||
1409 | output [1:0] dout; | |
1410 | output scan_out; | |
1411 | assign fdin[1:0] = din[1:0] & {2 {reset}}; | |
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | ||
1429 | cl_a1_msff_syrst_4x d0_0 ( | |
1430 | .l1clk(l1clk), | |
1431 | .siclk(siclk), | |
1432 | .soclk(soclk), | |
1433 | .d(fdin[0]), | |
1434 | .si(sout[1]), | |
1435 | .so(scan_out), | |
1436 | .reset(reset), | |
1437 | .q(dout[0]) | |
1438 | ); | |
1439 | cl_a1_msff_syrst_4x d0_1 ( | |
1440 | .l1clk(l1clk), | |
1441 | .siclk(siclk), | |
1442 | .soclk(soclk), | |
1443 | .d(fdin[1]), | |
1444 | .si(scan_in), | |
1445 | .so(sout[1]), | |
1446 | .reset(reset), | |
1447 | .q(dout[1]) | |
1448 | ); | |
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | endmodule | |
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | // any PARAMS parms go into naming of macro | |
1468 | ||
1469 | module niu_mb4_msff_ctl_macro__library_a1__reset_1__width_23 ( | |
1470 | din, | |
1471 | reset, | |
1472 | l1clk, | |
1473 | scan_in, | |
1474 | siclk, | |
1475 | soclk, | |
1476 | dout, | |
1477 | scan_out); | |
1478 | wire [22:0] fdin; | |
1479 | wire [22:1] sout; | |
1480 | ||
1481 | input [22:0] din; | |
1482 | input reset; | |
1483 | input l1clk; | |
1484 | input scan_in; | |
1485 | ||
1486 | ||
1487 | input siclk; | |
1488 | input soclk; | |
1489 | ||
1490 | output [22:0] dout; | |
1491 | output scan_out; | |
1492 | assign fdin[22:0] = din[22:0] & {23 {reset}}; | |
1493 | ||
1494 | ||
1495 | ||
1496 | ||
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | cl_a1_msff_syrst_4x d0_0 ( | |
1511 | .l1clk(l1clk), | |
1512 | .siclk(siclk), | |
1513 | .soclk(soclk), | |
1514 | .d(fdin[0]), | |
1515 | .si(sout[1]), | |
1516 | .so(scan_out), | |
1517 | .reset(reset), | |
1518 | .q(dout[0]) | |
1519 | ); | |
1520 | cl_a1_msff_syrst_4x d0_1 ( | |
1521 | .l1clk(l1clk), | |
1522 | .siclk(siclk), | |
1523 | .soclk(soclk), | |
1524 | .d(fdin[1]), | |
1525 | .si(sout[2]), | |
1526 | .so(sout[1]), | |
1527 | .reset(reset), | |
1528 | .q(dout[1]) | |
1529 | ); | |
1530 | cl_a1_msff_syrst_4x d0_2 ( | |
1531 | .l1clk(l1clk), | |
1532 | .siclk(siclk), | |
1533 | .soclk(soclk), | |
1534 | .d(fdin[2]), | |
1535 | .si(sout[3]), | |
1536 | .so(sout[2]), | |
1537 | .reset(reset), | |
1538 | .q(dout[2]) | |
1539 | ); | |
1540 | cl_a1_msff_syrst_4x d0_3 ( | |
1541 | .l1clk(l1clk), | |
1542 | .siclk(siclk), | |
1543 | .soclk(soclk), | |
1544 | .d(fdin[3]), | |
1545 | .si(sout[4]), | |
1546 | .so(sout[3]), | |
1547 | .reset(reset), | |
1548 | .q(dout[3]) | |
1549 | ); | |
1550 | cl_a1_msff_syrst_4x d0_4 ( | |
1551 | .l1clk(l1clk), | |
1552 | .siclk(siclk), | |
1553 | .soclk(soclk), | |
1554 | .d(fdin[4]), | |
1555 | .si(sout[5]), | |
1556 | .so(sout[4]), | |
1557 | .reset(reset), | |
1558 | .q(dout[4]) | |
1559 | ); | |
1560 | cl_a1_msff_syrst_4x d0_5 ( | |
1561 | .l1clk(l1clk), | |
1562 | .siclk(siclk), | |
1563 | .soclk(soclk), | |
1564 | .d(fdin[5]), | |
1565 | .si(sout[6]), | |
1566 | .so(sout[5]), | |
1567 | .reset(reset), | |
1568 | .q(dout[5]) | |
1569 | ); | |
1570 | cl_a1_msff_syrst_4x d0_6 ( | |
1571 | .l1clk(l1clk), | |
1572 | .siclk(siclk), | |
1573 | .soclk(soclk), | |
1574 | .d(fdin[6]), | |
1575 | .si(sout[7]), | |
1576 | .so(sout[6]), | |
1577 | .reset(reset), | |
1578 | .q(dout[6]) | |
1579 | ); | |
1580 | cl_a1_msff_syrst_4x d0_7 ( | |
1581 | .l1clk(l1clk), | |
1582 | .siclk(siclk), | |
1583 | .soclk(soclk), | |
1584 | .d(fdin[7]), | |
1585 | .si(sout[8]), | |
1586 | .so(sout[7]), | |
1587 | .reset(reset), | |
1588 | .q(dout[7]) | |
1589 | ); | |
1590 | cl_a1_msff_syrst_4x d0_8 ( | |
1591 | .l1clk(l1clk), | |
1592 | .siclk(siclk), | |
1593 | .soclk(soclk), | |
1594 | .d(fdin[8]), | |
1595 | .si(sout[9]), | |
1596 | .so(sout[8]), | |
1597 | .reset(reset), | |
1598 | .q(dout[8]) | |
1599 | ); | |
1600 | cl_a1_msff_syrst_4x d0_9 ( | |
1601 | .l1clk(l1clk), | |
1602 | .siclk(siclk), | |
1603 | .soclk(soclk), | |
1604 | .d(fdin[9]), | |
1605 | .si(sout[10]), | |
1606 | .so(sout[9]), | |
1607 | .reset(reset), | |
1608 | .q(dout[9]) | |
1609 | ); | |
1610 | cl_a1_msff_syrst_4x d0_10 ( | |
1611 | .l1clk(l1clk), | |
1612 | .siclk(siclk), | |
1613 | .soclk(soclk), | |
1614 | .d(fdin[10]), | |
1615 | .si(sout[11]), | |
1616 | .so(sout[10]), | |
1617 | .reset(reset), | |
1618 | .q(dout[10]) | |
1619 | ); | |
1620 | cl_a1_msff_syrst_4x d0_11 ( | |
1621 | .l1clk(l1clk), | |
1622 | .siclk(siclk), | |
1623 | .soclk(soclk), | |
1624 | .d(fdin[11]), | |
1625 | .si(sout[12]), | |
1626 | .so(sout[11]), | |
1627 | .reset(reset), | |
1628 | .q(dout[11]) | |
1629 | ); | |
1630 | cl_a1_msff_syrst_4x d0_12 ( | |
1631 | .l1clk(l1clk), | |
1632 | .siclk(siclk), | |
1633 | .soclk(soclk), | |
1634 | .d(fdin[12]), | |
1635 | .si(sout[13]), | |
1636 | .so(sout[12]), | |
1637 | .reset(reset), | |
1638 | .q(dout[12]) | |
1639 | ); | |
1640 | cl_a1_msff_syrst_4x d0_13 ( | |
1641 | .l1clk(l1clk), | |
1642 | .siclk(siclk), | |
1643 | .soclk(soclk), | |
1644 | .d(fdin[13]), | |
1645 | .si(sout[14]), | |
1646 | .so(sout[13]), | |
1647 | .reset(reset), | |
1648 | .q(dout[13]) | |
1649 | ); | |
1650 | cl_a1_msff_syrst_4x d0_14 ( | |
1651 | .l1clk(l1clk), | |
1652 | .siclk(siclk), | |
1653 | .soclk(soclk), | |
1654 | .d(fdin[14]), | |
1655 | .si(sout[15]), | |
1656 | .so(sout[14]), | |
1657 | .reset(reset), | |
1658 | .q(dout[14]) | |
1659 | ); | |
1660 | cl_a1_msff_syrst_4x d0_15 ( | |
1661 | .l1clk(l1clk), | |
1662 | .siclk(siclk), | |
1663 | .soclk(soclk), | |
1664 | .d(fdin[15]), | |
1665 | .si(sout[16]), | |
1666 | .so(sout[15]), | |
1667 | .reset(reset), | |
1668 | .q(dout[15]) | |
1669 | ); | |
1670 | cl_a1_msff_syrst_4x d0_16 ( | |
1671 | .l1clk(l1clk), | |
1672 | .siclk(siclk), | |
1673 | .soclk(soclk), | |
1674 | .d(fdin[16]), | |
1675 | .si(sout[17]), | |
1676 | .so(sout[16]), | |
1677 | .reset(reset), | |
1678 | .q(dout[16]) | |
1679 | ); | |
1680 | cl_a1_msff_syrst_4x d0_17 ( | |
1681 | .l1clk(l1clk), | |
1682 | .siclk(siclk), | |
1683 | .soclk(soclk), | |
1684 | .d(fdin[17]), | |
1685 | .si(sout[18]), | |
1686 | .so(sout[17]), | |
1687 | .reset(reset), | |
1688 | .q(dout[17]) | |
1689 | ); | |
1690 | cl_a1_msff_syrst_4x d0_18 ( | |
1691 | .l1clk(l1clk), | |
1692 | .siclk(siclk), | |
1693 | .soclk(soclk), | |
1694 | .d(fdin[18]), | |
1695 | .si(sout[19]), | |
1696 | .so(sout[18]), | |
1697 | .reset(reset), | |
1698 | .q(dout[18]) | |
1699 | ); | |
1700 | cl_a1_msff_syrst_4x d0_19 ( | |
1701 | .l1clk(l1clk), | |
1702 | .siclk(siclk), | |
1703 | .soclk(soclk), | |
1704 | .d(fdin[19]), | |
1705 | .si(sout[20]), | |
1706 | .so(sout[19]), | |
1707 | .reset(reset), | |
1708 | .q(dout[19]) | |
1709 | ); | |
1710 | cl_a1_msff_syrst_4x d0_20 ( | |
1711 | .l1clk(l1clk), | |
1712 | .siclk(siclk), | |
1713 | .soclk(soclk), | |
1714 | .d(fdin[20]), | |
1715 | .si(sout[21]), | |
1716 | .so(sout[20]), | |
1717 | .reset(reset), | |
1718 | .q(dout[20]) | |
1719 | ); | |
1720 | cl_a1_msff_syrst_4x d0_21 ( | |
1721 | .l1clk(l1clk), | |
1722 | .siclk(siclk), | |
1723 | .soclk(soclk), | |
1724 | .d(fdin[21]), | |
1725 | .si(sout[22]), | |
1726 | .so(sout[21]), | |
1727 | .reset(reset), | |
1728 | .q(dout[21]) | |
1729 | ); | |
1730 | cl_a1_msff_syrst_4x d0_22 ( | |
1731 | .l1clk(l1clk), | |
1732 | .siclk(siclk), | |
1733 | .soclk(soclk), | |
1734 | .d(fdin[22]), | |
1735 | .si(scan_in), | |
1736 | .so(sout[22]), | |
1737 | .reset(reset), | |
1738 | .q(dout[22]) | |
1739 | ); | |
1740 | ||
1741 | ||
1742 | ||
1743 | ||
1744 | endmodule | |
1745 | ||
1746 | ||
1747 | ||
1748 | ||
1749 | ||
1750 | ||
1751 | ||
1752 | ||
1753 | ||
1754 | ||
1755 | ||
1756 | ||
1757 | ||
1758 | // any PARAMS parms go into naming of macro | |
1759 | ||
1760 | module niu_mb4_msff_ctl_macro__library_a1__reset_1__width_3 ( | |
1761 | din, | |
1762 | reset, | |
1763 | l1clk, | |
1764 | scan_in, | |
1765 | siclk, | |
1766 | soclk, | |
1767 | dout, | |
1768 | scan_out); | |
1769 | wire [2:0] fdin; | |
1770 | wire [2:1] sout; | |
1771 | ||
1772 | input [2:0] din; | |
1773 | input reset; | |
1774 | input l1clk; | |
1775 | input scan_in; | |
1776 | ||
1777 | ||
1778 | input siclk; | |
1779 | input soclk; | |
1780 | ||
1781 | output [2:0] dout; | |
1782 | output scan_out; | |
1783 | assign fdin[2:0] = din[2:0] & {3 {reset}}; | |
1784 | ||
1785 | ||
1786 | ||
1787 | ||
1788 | ||
1789 | ||
1790 | ||
1791 | ||
1792 | ||
1793 | ||
1794 | ||
1795 | ||
1796 | ||
1797 | ||
1798 | ||
1799 | ||
1800 | ||
1801 | cl_a1_msff_syrst_4x d0_0 ( | |
1802 | .l1clk(l1clk), | |
1803 | .siclk(siclk), | |
1804 | .soclk(soclk), | |
1805 | .d(fdin[0]), | |
1806 | .si(sout[1]), | |
1807 | .so(scan_out), | |
1808 | .reset(reset), | |
1809 | .q(dout[0]) | |
1810 | ); | |
1811 | cl_a1_msff_syrst_4x d0_1 ( | |
1812 | .l1clk(l1clk), | |
1813 | .siclk(siclk), | |
1814 | .soclk(soclk), | |
1815 | .d(fdin[1]), | |
1816 | .si(sout[2]), | |
1817 | .so(sout[1]), | |
1818 | .reset(reset), | |
1819 | .q(dout[1]) | |
1820 | ); | |
1821 | cl_a1_msff_syrst_4x d0_2 ( | |
1822 | .l1clk(l1clk), | |
1823 | .siclk(siclk), | |
1824 | .soclk(soclk), | |
1825 | .d(fdin[2]), | |
1826 | .si(scan_in), | |
1827 | .so(sout[2]), | |
1828 | .reset(reset), | |
1829 | .q(dout[2]) | |
1830 | ); | |
1831 | ||
1832 | ||
1833 | ||
1834 | ||
1835 | endmodule | |
1836 | ||
1837 | ||
1838 | ||
1839 | ||
1840 | ||
1841 | ||
1842 | ||
1843 | ||
1844 | ||
1845 | ||
1846 | ||
1847 | ||
1848 | ||
1849 | // any PARAMS parms go into naming of macro | |
1850 | ||
1851 | module niu_mb4_msff_ctl_macro__library_a1__reset_1__width_40 ( | |
1852 | din, | |
1853 | reset, | |
1854 | l1clk, | |
1855 | scan_in, | |
1856 | siclk, | |
1857 | soclk, | |
1858 | dout, | |
1859 | scan_out); | |
1860 | wire [39:0] fdin; | |
1861 | wire [39:1] sout; | |
1862 | ||
1863 | input [39:0] din; | |
1864 | input reset; | |
1865 | input l1clk; | |
1866 | input scan_in; | |
1867 | ||
1868 | ||
1869 | input siclk; | |
1870 | input soclk; | |
1871 | ||
1872 | output [39:0] dout; | |
1873 | output scan_out; | |
1874 | assign fdin[39:0] = din[39:0] & {40 {reset}}; | |
1875 | ||
1876 | ||
1877 | ||
1878 | ||
1879 | ||
1880 | ||
1881 | ||
1882 | ||
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | cl_a1_msff_syrst_4x d0_0 ( | |
1893 | .l1clk(l1clk), | |
1894 | .siclk(siclk), | |
1895 | .soclk(soclk), | |
1896 | .d(fdin[0]), | |
1897 | .si(sout[1]), | |
1898 | .so(scan_out), | |
1899 | .reset(reset), | |
1900 | .q(dout[0]) | |
1901 | ); | |
1902 | cl_a1_msff_syrst_4x d0_1 ( | |
1903 | .l1clk(l1clk), | |
1904 | .siclk(siclk), | |
1905 | .soclk(soclk), | |
1906 | .d(fdin[1]), | |
1907 | .si(sout[2]), | |
1908 | .so(sout[1]), | |
1909 | .reset(reset), | |
1910 | .q(dout[1]) | |
1911 | ); | |
1912 | cl_a1_msff_syrst_4x d0_2 ( | |
1913 | .l1clk(l1clk), | |
1914 | .siclk(siclk), | |
1915 | .soclk(soclk), | |
1916 | .d(fdin[2]), | |
1917 | .si(sout[3]), | |
1918 | .so(sout[2]), | |
1919 | .reset(reset), | |
1920 | .q(dout[2]) | |
1921 | ); | |
1922 | cl_a1_msff_syrst_4x d0_3 ( | |
1923 | .l1clk(l1clk), | |
1924 | .siclk(siclk), | |
1925 | .soclk(soclk), | |
1926 | .d(fdin[3]), | |
1927 | .si(sout[4]), | |
1928 | .so(sout[3]), | |
1929 | .reset(reset), | |
1930 | .q(dout[3]) | |
1931 | ); | |
1932 | cl_a1_msff_syrst_4x d0_4 ( | |
1933 | .l1clk(l1clk), | |
1934 | .siclk(siclk), | |
1935 | .soclk(soclk), | |
1936 | .d(fdin[4]), | |
1937 | .si(sout[5]), | |
1938 | .so(sout[4]), | |
1939 | .reset(reset), | |
1940 | .q(dout[4]) | |
1941 | ); | |
1942 | cl_a1_msff_syrst_4x d0_5 ( | |
1943 | .l1clk(l1clk), | |
1944 | .siclk(siclk), | |
1945 | .soclk(soclk), | |
1946 | .d(fdin[5]), | |
1947 | .si(sout[6]), | |
1948 | .so(sout[5]), | |
1949 | .reset(reset), | |
1950 | .q(dout[5]) | |
1951 | ); | |
1952 | cl_a1_msff_syrst_4x d0_6 ( | |
1953 | .l1clk(l1clk), | |
1954 | .siclk(siclk), | |
1955 | .soclk(soclk), | |
1956 | .d(fdin[6]), | |
1957 | .si(sout[7]), | |
1958 | .so(sout[6]), | |
1959 | .reset(reset), | |
1960 | .q(dout[6]) | |
1961 | ); | |
1962 | cl_a1_msff_syrst_4x d0_7 ( | |
1963 | .l1clk(l1clk), | |
1964 | .siclk(siclk), | |
1965 | .soclk(soclk), | |
1966 | .d(fdin[7]), | |
1967 | .si(sout[8]), | |
1968 | .so(sout[7]), | |
1969 | .reset(reset), | |
1970 | .q(dout[7]) | |
1971 | ); | |
1972 | cl_a1_msff_syrst_4x d0_8 ( | |
1973 | .l1clk(l1clk), | |
1974 | .siclk(siclk), | |
1975 | .soclk(soclk), | |
1976 | .d(fdin[8]), | |
1977 | .si(sout[9]), | |
1978 | .so(sout[8]), | |
1979 | .reset(reset), | |
1980 | .q(dout[8]) | |
1981 | ); | |
1982 | cl_a1_msff_syrst_4x d0_9 ( | |
1983 | .l1clk(l1clk), | |
1984 | .siclk(siclk), | |
1985 | .soclk(soclk), | |
1986 | .d(fdin[9]), | |
1987 | .si(sout[10]), | |
1988 | .so(sout[9]), | |
1989 | .reset(reset), | |
1990 | .q(dout[9]) | |
1991 | ); | |
1992 | cl_a1_msff_syrst_4x d0_10 ( | |
1993 | .l1clk(l1clk), | |
1994 | .siclk(siclk), | |
1995 | .soclk(soclk), | |
1996 | .d(fdin[10]), | |
1997 | .si(sout[11]), | |
1998 | .so(sout[10]), | |
1999 | .reset(reset), | |
2000 | .q(dout[10]) | |
2001 | ); | |
2002 | cl_a1_msff_syrst_4x d0_11 ( | |
2003 | .l1clk(l1clk), | |
2004 | .siclk(siclk), | |
2005 | .soclk(soclk), | |
2006 | .d(fdin[11]), | |
2007 | .si(sout[12]), | |
2008 | .so(sout[11]), | |
2009 | .reset(reset), | |
2010 | .q(dout[11]) | |
2011 | ); | |
2012 | cl_a1_msff_syrst_4x d0_12 ( | |
2013 | .l1clk(l1clk), | |
2014 | .siclk(siclk), | |
2015 | .soclk(soclk), | |
2016 | .d(fdin[12]), | |
2017 | .si(sout[13]), | |
2018 | .so(sout[12]), | |
2019 | .reset(reset), | |
2020 | .q(dout[12]) | |
2021 | ); | |
2022 | cl_a1_msff_syrst_4x d0_13 ( | |
2023 | .l1clk(l1clk), | |
2024 | .siclk(siclk), | |
2025 | .soclk(soclk), | |
2026 | .d(fdin[13]), | |
2027 | .si(sout[14]), | |
2028 | .so(sout[13]), | |
2029 | .reset(reset), | |
2030 | .q(dout[13]) | |
2031 | ); | |
2032 | cl_a1_msff_syrst_4x d0_14 ( | |
2033 | .l1clk(l1clk), | |
2034 | .siclk(siclk), | |
2035 | .soclk(soclk), | |
2036 | .d(fdin[14]), | |
2037 | .si(sout[15]), | |
2038 | .so(sout[14]), | |
2039 | .reset(reset), | |
2040 | .q(dout[14]) | |
2041 | ); | |
2042 | cl_a1_msff_syrst_4x d0_15 ( | |
2043 | .l1clk(l1clk), | |
2044 | .siclk(siclk), | |
2045 | .soclk(soclk), | |
2046 | .d(fdin[15]), | |
2047 | .si(sout[16]), | |
2048 | .so(sout[15]), | |
2049 | .reset(reset), | |
2050 | .q(dout[15]) | |
2051 | ); | |
2052 | cl_a1_msff_syrst_4x d0_16 ( | |
2053 | .l1clk(l1clk), | |
2054 | .siclk(siclk), | |
2055 | .soclk(soclk), | |
2056 | .d(fdin[16]), | |
2057 | .si(sout[17]), | |
2058 | .so(sout[16]), | |
2059 | .reset(reset), | |
2060 | .q(dout[16]) | |
2061 | ); | |
2062 | cl_a1_msff_syrst_4x d0_17 ( | |
2063 | .l1clk(l1clk), | |
2064 | .siclk(siclk), | |
2065 | .soclk(soclk), | |
2066 | .d(fdin[17]), | |
2067 | .si(sout[18]), | |
2068 | .so(sout[17]), | |
2069 | .reset(reset), | |
2070 | .q(dout[17]) | |
2071 | ); | |
2072 | cl_a1_msff_syrst_4x d0_18 ( | |
2073 | .l1clk(l1clk), | |
2074 | .siclk(siclk), | |
2075 | .soclk(soclk), | |
2076 | .d(fdin[18]), | |
2077 | .si(sout[19]), | |
2078 | .so(sout[18]), | |
2079 | .reset(reset), | |
2080 | .q(dout[18]) | |
2081 | ); | |
2082 | cl_a1_msff_syrst_4x d0_19 ( | |
2083 | .l1clk(l1clk), | |
2084 | .siclk(siclk), | |
2085 | .soclk(soclk), | |
2086 | .d(fdin[19]), | |
2087 | .si(sout[20]), | |
2088 | .so(sout[19]), | |
2089 | .reset(reset), | |
2090 | .q(dout[19]) | |
2091 | ); | |
2092 | cl_a1_msff_syrst_4x d0_20 ( | |
2093 | .l1clk(l1clk), | |
2094 | .siclk(siclk), | |
2095 | .soclk(soclk), | |
2096 | .d(fdin[20]), | |
2097 | .si(sout[21]), | |
2098 | .so(sout[20]), | |
2099 | .reset(reset), | |
2100 | .q(dout[20]) | |
2101 | ); | |
2102 | cl_a1_msff_syrst_4x d0_21 ( | |
2103 | .l1clk(l1clk), | |
2104 | .siclk(siclk), | |
2105 | .soclk(soclk), | |
2106 | .d(fdin[21]), | |
2107 | .si(sout[22]), | |
2108 | .so(sout[21]), | |
2109 | .reset(reset), | |
2110 | .q(dout[21]) | |
2111 | ); | |
2112 | cl_a1_msff_syrst_4x d0_22 ( | |
2113 | .l1clk(l1clk), | |
2114 | .siclk(siclk), | |
2115 | .soclk(soclk), | |
2116 | .d(fdin[22]), | |
2117 | .si(sout[23]), | |
2118 | .so(sout[22]), | |
2119 | .reset(reset), | |
2120 | .q(dout[22]) | |
2121 | ); | |
2122 | cl_a1_msff_syrst_4x d0_23 ( | |
2123 | .l1clk(l1clk), | |
2124 | .siclk(siclk), | |
2125 | .soclk(soclk), | |
2126 | .d(fdin[23]), | |
2127 | .si(sout[24]), | |
2128 | .so(sout[23]), | |
2129 | .reset(reset), | |
2130 | .q(dout[23]) | |
2131 | ); | |
2132 | cl_a1_msff_syrst_4x d0_24 ( | |
2133 | .l1clk(l1clk), | |
2134 | .siclk(siclk), | |
2135 | .soclk(soclk), | |
2136 | .d(fdin[24]), | |
2137 | .si(sout[25]), | |
2138 | .so(sout[24]), | |
2139 | .reset(reset), | |
2140 | .q(dout[24]) | |
2141 | ); | |
2142 | cl_a1_msff_syrst_4x d0_25 ( | |
2143 | .l1clk(l1clk), | |
2144 | .siclk(siclk), | |
2145 | .soclk(soclk), | |
2146 | .d(fdin[25]), | |
2147 | .si(sout[26]), | |
2148 | .so(sout[25]), | |
2149 | .reset(reset), | |
2150 | .q(dout[25]) | |
2151 | ); | |
2152 | cl_a1_msff_syrst_4x d0_26 ( | |
2153 | .l1clk(l1clk), | |
2154 | .siclk(siclk), | |
2155 | .soclk(soclk), | |
2156 | .d(fdin[26]), | |
2157 | .si(sout[27]), | |
2158 | .so(sout[26]), | |
2159 | .reset(reset), | |
2160 | .q(dout[26]) | |
2161 | ); | |
2162 | cl_a1_msff_syrst_4x d0_27 ( | |
2163 | .l1clk(l1clk), | |
2164 | .siclk(siclk), | |
2165 | .soclk(soclk), | |
2166 | .d(fdin[27]), | |
2167 | .si(sout[28]), | |
2168 | .so(sout[27]), | |
2169 | .reset(reset), | |
2170 | .q(dout[27]) | |
2171 | ); | |
2172 | cl_a1_msff_syrst_4x d0_28 ( | |
2173 | .l1clk(l1clk), | |
2174 | .siclk(siclk), | |
2175 | .soclk(soclk), | |
2176 | .d(fdin[28]), | |
2177 | .si(sout[29]), | |
2178 | .so(sout[28]), | |
2179 | .reset(reset), | |
2180 | .q(dout[28]) | |
2181 | ); | |
2182 | cl_a1_msff_syrst_4x d0_29 ( | |
2183 | .l1clk(l1clk), | |
2184 | .siclk(siclk), | |
2185 | .soclk(soclk), | |
2186 | .d(fdin[29]), | |
2187 | .si(sout[30]), | |
2188 | .so(sout[29]), | |
2189 | .reset(reset), | |
2190 | .q(dout[29]) | |
2191 | ); | |
2192 | cl_a1_msff_syrst_4x d0_30 ( | |
2193 | .l1clk(l1clk), | |
2194 | .siclk(siclk), | |
2195 | .soclk(soclk), | |
2196 | .d(fdin[30]), | |
2197 | .si(sout[31]), | |
2198 | .so(sout[30]), | |
2199 | .reset(reset), | |
2200 | .q(dout[30]) | |
2201 | ); | |
2202 | cl_a1_msff_syrst_4x d0_31 ( | |
2203 | .l1clk(l1clk), | |
2204 | .siclk(siclk), | |
2205 | .soclk(soclk), | |
2206 | .d(fdin[31]), | |
2207 | .si(sout[32]), | |
2208 | .so(sout[31]), | |
2209 | .reset(reset), | |
2210 | .q(dout[31]) | |
2211 | ); | |
2212 | cl_a1_msff_syrst_4x d0_32 ( | |
2213 | .l1clk(l1clk), | |
2214 | .siclk(siclk), | |
2215 | .soclk(soclk), | |
2216 | .d(fdin[32]), | |
2217 | .si(sout[33]), | |
2218 | .so(sout[32]), | |
2219 | .reset(reset), | |
2220 | .q(dout[32]) | |
2221 | ); | |
2222 | cl_a1_msff_syrst_4x d0_33 ( | |
2223 | .l1clk(l1clk), | |
2224 | .siclk(siclk), | |
2225 | .soclk(soclk), | |
2226 | .d(fdin[33]), | |
2227 | .si(sout[34]), | |
2228 | .so(sout[33]), | |
2229 | .reset(reset), | |
2230 | .q(dout[33]) | |
2231 | ); | |
2232 | cl_a1_msff_syrst_4x d0_34 ( | |
2233 | .l1clk(l1clk), | |
2234 | .siclk(siclk), | |
2235 | .soclk(soclk), | |
2236 | .d(fdin[34]), | |
2237 | .si(sout[35]), | |
2238 | .so(sout[34]), | |
2239 | .reset(reset), | |
2240 | .q(dout[34]) | |
2241 | ); | |
2242 | cl_a1_msff_syrst_4x d0_35 ( | |
2243 | .l1clk(l1clk), | |
2244 | .siclk(siclk), | |
2245 | .soclk(soclk), | |
2246 | .d(fdin[35]), | |
2247 | .si(sout[36]), | |
2248 | .so(sout[35]), | |
2249 | .reset(reset), | |
2250 | .q(dout[35]) | |
2251 | ); | |
2252 | cl_a1_msff_syrst_4x d0_36 ( | |
2253 | .l1clk(l1clk), | |
2254 | .siclk(siclk), | |
2255 | .soclk(soclk), | |
2256 | .d(fdin[36]), | |
2257 | .si(sout[37]), | |
2258 | .so(sout[36]), | |
2259 | .reset(reset), | |
2260 | .q(dout[36]) | |
2261 | ); | |
2262 | cl_a1_msff_syrst_4x d0_37 ( | |
2263 | .l1clk(l1clk), | |
2264 | .siclk(siclk), | |
2265 | .soclk(soclk), | |
2266 | .d(fdin[37]), | |
2267 | .si(sout[38]), | |
2268 | .so(sout[37]), | |
2269 | .reset(reset), | |
2270 | .q(dout[37]) | |
2271 | ); | |
2272 | cl_a1_msff_syrst_4x d0_38 ( | |
2273 | .l1clk(l1clk), | |
2274 | .siclk(siclk), | |
2275 | .soclk(soclk), | |
2276 | .d(fdin[38]), | |
2277 | .si(sout[39]), | |
2278 | .so(sout[38]), | |
2279 | .reset(reset), | |
2280 | .q(dout[38]) | |
2281 | ); | |
2282 | cl_a1_msff_syrst_4x d0_39 ( | |
2283 | .l1clk(l1clk), | |
2284 | .siclk(siclk), | |
2285 | .soclk(soclk), | |
2286 | .d(fdin[39]), | |
2287 | .si(scan_in), | |
2288 | .so(sout[39]), | |
2289 | .reset(reset), | |
2290 | .q(dout[39]) | |
2291 | ); | |
2292 | ||
2293 | ||
2294 | ||
2295 | ||
2296 | endmodule | |
2297 | ||
2298 | ||
2299 | ||
2300 | ||
2301 | ||
2302 | ||
2303 | ||
2304 |