[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_pio_imask0_decoder.v

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// 
// OpenSPARC T2 Processor File: niu_pio_imask0_decoder.v
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/*%W%	%G%*/

/*****************************************************************
 *
 * File Name    : niu_pio_imask0_decoder.v
 * Author Name  : John Lo
 * Description  : It contains ldf_mask 0~63 read/write decoder,
 * 
 * Parent Module: niu_pio_imask0_decoder.v
 * Child  Module: 
 * Interface Mod: many.
 * Date Created : 3/30/04
 *
 * Copyright (c) 2020, Sun Microsystems, Inc. 
 * Sun Proprietary and Confidential   
 *
 * Modification :
 * 
 ****************************************************************/

module niu_pio_imask0_decoder (/*AUTOARG*/
   // Outputs
   imask0_ack, imask0_rdata, imask0_err, ld_ldf_mask0, ld_ldf_mask1, 
   ld_ldf_mask2, ld_ldf_mask3, ld_ldf_mask4, ld_ldf_mask5, 
   ld_ldf_mask6, ld_ldf_mask7, ld_ldf_mask8, ld_ldf_mask9, 
   ld_ldf_mask10, ld_ldf_mask11, ld_ldf_mask12, ld_ldf_mask13, 
   ld_ldf_mask14, ld_ldf_mask15, ld_ldf_mask16, ld_ldf_mask17, 
   ld_ldf_mask18, ld_ldf_mask19, ld_ldf_mask20, ld_ldf_mask21, 
   ld_ldf_mask22, ld_ldf_mask23, ld_ldf_mask24, ld_ldf_mask25, 
   ld_ldf_mask26, ld_ldf_mask27, ld_ldf_mask28, ld_ldf_mask29, 
   ld_ldf_mask30, ld_ldf_mask31, ld_ldf_mask32, ld_ldf_mask33, 
   ld_ldf_mask34, ld_ldf_mask35, ld_ldf_mask36, ld_ldf_mask37, 
   ld_ldf_mask38, ld_ldf_mask39, ld_ldf_mask40, ld_ldf_mask41, 
   ld_ldf_mask42, ld_ldf_mask43, ld_ldf_mask44, ld_ldf_mask45, 
   ld_ldf_mask46, ld_ldf_mask47, ld_ldf_mask48, ld_ldf_mask49, 
   ld_ldf_mask50, ld_ldf_mask51, ld_ldf_mask52, ld_ldf_mask53, 
   ld_ldf_mask54, ld_ldf_mask55, ld_ldf_mask56, ld_ldf_mask57, 
   ld_ldf_mask58, ld_ldf_mask59, ld_ldf_mask60, ld_ldf_mask61, 
   ld_ldf_mask62, ld_ldf_mask63, 
   // Inputs
   clk, reset, imask0_sel_reg, addr, rd, ldf_mask0, ldf_mask1, 
   ldf_mask2, ldf_mask3, ldf_mask4, ldf_mask5, ldf_mask6, ldf_mask7, 
   ldf_mask8, ldf_mask9, ldf_mask10, ldf_mask11, ldf_mask12, 
   ldf_mask13, ldf_mask14, ldf_mask15, ldf_mask16, ldf_mask17, 
   ldf_mask18, ldf_mask19, ldf_mask20, ldf_mask21, ldf_mask22, 
   ldf_mask23, ldf_mask24, ldf_mask25, ldf_mask26, ldf_mask27, 
   ldf_mask28, ldf_mask29, ldf_mask30, ldf_mask31, ldf_mask32, 
   ldf_mask33, ldf_mask34, ldf_mask35, ldf_mask36, ldf_mask37, 
   ldf_mask38, ldf_mask39, ldf_mask40, ldf_mask41, ldf_mask42, 
   ldf_mask43, ldf_mask44, ldf_mask45, ldf_mask46, ldf_mask47, 
   ldf_mask48, ldf_mask49, ldf_mask50, ldf_mask51, ldf_mask52, 
   ldf_mask53, ldf_mask54, ldf_mask55, ldf_mask56, ldf_mask57, 
   ldf_mask58, ldf_mask59, ldf_mask60, ldf_mask61, ldf_mask62, 
   ldf_mask63
   );
   input 		      clk;
   input 		      reset;
   input 		      imask0_sel_reg;
                              // pio broadcast signals
   input [18:0] 	      addr;
   input 		      rd;
   input [1:0]		      ldf_mask0 ;
   input [1:0]		      ldf_mask1 ;
   input [1:0]		      ldf_mask2 ;
   input [1:0]		      ldf_mask3 ;
   input [1:0]		      ldf_mask4 ;
   input [1:0]		      ldf_mask5 ;
   input [1:0]		      ldf_mask6 ;
   input [1:0]		      ldf_mask7 ;
   input [1:0]		      ldf_mask8 ;
   input [1:0]		      ldf_mask9 ;
   input [1:0]		      ldf_mask10;
   input [1:0]		      ldf_mask11;
   input [1:0]		      ldf_mask12;
   input [1:0]		      ldf_mask13;
   input [1:0]		      ldf_mask14;
   input [1:0]		      ldf_mask15;
   input [1:0]		      ldf_mask16;
   input [1:0]		      ldf_mask17;
   input [1:0]		      ldf_mask18;
   input [1:0]		      ldf_mask19;
   input [1:0]		      ldf_mask20;
   input [1:0]		      ldf_mask21;
   input [1:0]		      ldf_mask22;
   input [1:0]		      ldf_mask23;
   input [1:0]		      ldf_mask24;
   input [1:0]		      ldf_mask25;
   input [1:0]		      ldf_mask26;
   input [1:0]		      ldf_mask27;
   input [1:0]		      ldf_mask28;
   input [1:0]		      ldf_mask29;
   input [1:0]		      ldf_mask30;
   input [1:0]		      ldf_mask31;
   input [1:0]		      ldf_mask32;
   input [1:0]		      ldf_mask33;
   input [1:0]		      ldf_mask34;
   input [1:0]		      ldf_mask35;
   input [1:0]		      ldf_mask36;
   input [1:0]		      ldf_mask37;
   input [1:0]		      ldf_mask38;
   input [1:0]		      ldf_mask39;
   input [1:0]		      ldf_mask40;
   input [1:0]		      ldf_mask41;
   input [1:0]		      ldf_mask42;
   input [1:0]		      ldf_mask43;
   input [1:0]		      ldf_mask44;
   input [1:0]		      ldf_mask45;
   input [1:0]		      ldf_mask46;
   input [1:0]		      ldf_mask47;
   input [1:0]		      ldf_mask48;
   input [1:0]		      ldf_mask49;
   input [1:0]		      ldf_mask50;
   input [1:0]		      ldf_mask51;
   input [1:0]		      ldf_mask52;
   input [1:0]		      ldf_mask53;
   input [1:0]		      ldf_mask54;
   input [1:0]		      ldf_mask55;
   input [1:0]		      ldf_mask56;
   input [1:0]		      ldf_mask57;
   input [1:0]		      ldf_mask58;
   input [1:0]		      ldf_mask59;
   input [1:0]		      ldf_mask60;
   input [1:0]		      ldf_mask61;
   input [1:0]		      ldf_mask62;
   input [1:0]		      ldf_mask63;

   output 		      imask0_ack;
   output [63:0] 	      imask0_rdata;
   output 		      imask0_err;
   
   output      		      ld_ldf_mask0 ;
   output      		      ld_ldf_mask1 ;
   output      		      ld_ldf_mask2 ;
   output      		      ld_ldf_mask3 ;
   output      		      ld_ldf_mask4 ;
   output      		      ld_ldf_mask5 ;
   output      		      ld_ldf_mask6 ;
   output      		      ld_ldf_mask7 ;
   output      		      ld_ldf_mask8 ;
   output      		      ld_ldf_mask9 ;
   output      		      ld_ldf_mask10;
   output      		      ld_ldf_mask11;
   output      		      ld_ldf_mask12;
   output      		      ld_ldf_mask13;
   output      		      ld_ldf_mask14;
   output      		      ld_ldf_mask15;
   output      		      ld_ldf_mask16;
   output      		      ld_ldf_mask17;
   output      		      ld_ldf_mask18;
   output      		      ld_ldf_mask19;
   output      		      ld_ldf_mask20;
   output      		      ld_ldf_mask21;
   output      		      ld_ldf_mask22;
   output      		      ld_ldf_mask23;
   output      		      ld_ldf_mask24;
   output      		      ld_ldf_mask25;
   output      		      ld_ldf_mask26;
   output      		      ld_ldf_mask27;
   output      		      ld_ldf_mask28;
   output      		      ld_ldf_mask29;
   output      		      ld_ldf_mask30;
   output      		      ld_ldf_mask31;
   output      		      ld_ldf_mask32;
   output      		      ld_ldf_mask33;
   output      		      ld_ldf_mask34;
   output      		      ld_ldf_mask35;
   output      		      ld_ldf_mask36;
   output      		      ld_ldf_mask37;
   output      		      ld_ldf_mask38;
   output      		      ld_ldf_mask39;
   output      		      ld_ldf_mask40;
   output      		      ld_ldf_mask41;
   output      		      ld_ldf_mask42;
   output      		      ld_ldf_mask43;
   output      		      ld_ldf_mask44;
   output      		      ld_ldf_mask45;
   output      		      ld_ldf_mask46;
   output      		      ld_ldf_mask47;
   output      		      ld_ldf_mask48;
   output      		      ld_ldf_mask49;
   output      		      ld_ldf_mask50;
   output      		      ld_ldf_mask51;
   output      		      ld_ldf_mask52;
   output      		      ld_ldf_mask53;
   output      		      ld_ldf_mask54;
   output      		      ld_ldf_mask55;
   output      		      ld_ldf_mask56;
   output      		      ld_ldf_mask57;
   output      		      ld_ldf_mask58;
   output      		      ld_ldf_mask59;
   output      		      ld_ldf_mask60;
   output      		      ld_ldf_mask61;
   output      		      ld_ldf_mask62;
   output      		      ld_ldf_mask63;

// common reg declaration
   reg [63:0] 		      rd_data;
   reg 			      non_qualified_addr_err;
// common wrie declaration
   wire [63:0] 		      imask0_rdata;
   wire 		      rd_en;
   wire 		      wr_en;
   wire 		      rasr;
// output reg declaration
   reg      		      ld_ldf_mask0 ;
   reg      		      ld_ldf_mask1 ;
   reg      		      ld_ldf_mask2 ;
   reg      		      ld_ldf_mask3 ;
   reg      		      ld_ldf_mask4 ;
   reg      		      ld_ldf_mask5 ;
   reg      		      ld_ldf_mask6 ;
   reg      		      ld_ldf_mask7 ;
   reg      		      ld_ldf_mask8 ;
   reg      		      ld_ldf_mask9 ;
   reg      		      ld_ldf_mask10;
   reg      		      ld_ldf_mask11;
   reg      		      ld_ldf_mask12;
   reg      		      ld_ldf_mask13;
   reg      		      ld_ldf_mask14;
   reg      		      ld_ldf_mask15;
   reg      		      ld_ldf_mask16;
   reg      		      ld_ldf_mask17;
   reg      		      ld_ldf_mask18;
   reg      		      ld_ldf_mask19;
   reg      		      ld_ldf_mask20;
   reg      		      ld_ldf_mask21;
   reg      		      ld_ldf_mask22;
   reg      		      ld_ldf_mask23;
   reg      		      ld_ldf_mask24;
   reg      		      ld_ldf_mask25;
   reg      		      ld_ldf_mask26;
   reg      		      ld_ldf_mask27;
   reg      		      ld_ldf_mask28;
   reg      		      ld_ldf_mask29;
   reg      		      ld_ldf_mask30;
   reg      		      ld_ldf_mask31;
   reg      		      ld_ldf_mask32;
   reg      		      ld_ldf_mask33;
   reg      		      ld_ldf_mask34;
   reg      		      ld_ldf_mask35;
   reg      		      ld_ldf_mask36;
   reg      		      ld_ldf_mask37;
   reg      		      ld_ldf_mask38;
   reg      		      ld_ldf_mask39;
   reg      		      ld_ldf_mask40;
   reg      		      ld_ldf_mask41;
   reg      		      ld_ldf_mask42;
   reg      		      ld_ldf_mask43;
   reg      		      ld_ldf_mask44;
   reg      		      ld_ldf_mask45;
   reg      		      ld_ldf_mask46;
   reg      		      ld_ldf_mask47;
   reg      		      ld_ldf_mask48;
   reg      		      ld_ldf_mask49;
   reg      		      ld_ldf_mask50;
   reg      		      ld_ldf_mask51;
   reg      		      ld_ldf_mask52;
   reg      		      ld_ldf_mask53;
   reg      		      ld_ldf_mask54;
   reg      		      ld_ldf_mask55;
   reg      		      ld_ldf_mask56;
   reg      		      ld_ldf_mask57;
   reg      		      ld_ldf_mask58;
   reg      		      ld_ldf_mask59;
   reg      		      ld_ldf_mask60;
   reg      		      ld_ldf_mask61;
   reg      		      ld_ldf_mask62;
   reg      		      ld_ldf_mask63;

`ifdef NEPTUNE
/* ---------------------------------------------------------- */
   reg				imask0_sel_reg_int;
   reg				rd_int;
   reg [18:0]			addr_int;

always @(posedge clk)
 if (reset)
  begin
   imask0_sel_reg_int   <= 1'b0;
   rd_int		<= 1'b0;
   addr_int		<= 19'b0;
  end
 else
  begin
   imask0_sel_reg_int   <= imask0_sel_reg ;
   rd_int		<= rd ;
   addr_int		<= addr;
  end

`else
/* ---------------------------------------------------------- */

   wire				imask0_sel_reg_int;
   wire				rd_int;
   wire [18:0]			addr_int;

   assign imask0_sel_reg_int    = imask0_sel_reg ;
   assign rd_int		= rd ;
   assign addr_int		= addr ;
/* ----------------------------------------------------------- */
`endif
   
niu_rw_ctl imask0_rw_ctl(
		      // Outputs
		      .wr_en		(wr_en),
		      .rd_en		(rd_en),
		      .ack		(imask0_ack),
		      .rdata		(imask0_rdata[63:0]),
		      .err		(imask0_err),
		      .rasr		(rasr),
		      // Inputs
		      .clk		(clk),
		      .sel		(imask0_sel_reg_int),
		      .rd		(rd_int),
		      .rd_data		(rd_data[63:0]),
		      .non_qualified_addr_err(non_qualified_addr_err));


always @ (/*AUTOSENSE*/addr_int or ldf_mask0 or ldf_mask1 or ldf_mask10
	  or ldf_mask11 or ldf_mask12 or ldf_mask13 or ldf_mask14
	  or ldf_mask15 or ldf_mask16 or ldf_mask17 or ldf_mask18
	  or ldf_mask19 or ldf_mask2 or ldf_mask20 or ldf_mask21
	  or ldf_mask22 or ldf_mask23 or ldf_mask24 or ldf_mask25
	  or ldf_mask26 or ldf_mask27 or ldf_mask28 or ldf_mask29
	  or ldf_mask3 or ldf_mask30 or ldf_mask31 or ldf_mask32
	  or ldf_mask33 or ldf_mask34 or ldf_mask35 or ldf_mask36
	  or ldf_mask37 or ldf_mask38 or ldf_mask39 or ldf_mask4
	  or ldf_mask40 or ldf_mask41 or ldf_mask42 or ldf_mask43
	  or ldf_mask44 or ldf_mask45 or ldf_mask46 or ldf_mask47
	  or ldf_mask48 or ldf_mask49 or ldf_mask5 or ldf_mask50
	  or ldf_mask51 or ldf_mask52 or ldf_mask53 or ldf_mask54
	  or ldf_mask55 or ldf_mask56 or ldf_mask57 or ldf_mask58
	  or ldf_mask59 or ldf_mask6 or ldf_mask60 or ldf_mask61
	  or ldf_mask62 or ldf_mask63 or ldf_mask7 or ldf_mask8
	  or ldf_mask9 or wr_en)
  begin
                  non_qualified_addr_err = 0;
                  rd_data            = 64'hdead_beef_dead_beef;

                  ld_ldf_mask0       = 0;
                  ld_ldf_mask1       = 0;
                  ld_ldf_mask2       = 0;
                  ld_ldf_mask3       = 0;
                  ld_ldf_mask4       = 0;
                  ld_ldf_mask5       = 0;
                  ld_ldf_mask6       = 0;
                  ld_ldf_mask7       = 0;
                  ld_ldf_mask8       = 0;
                  ld_ldf_mask9       = 0;
                  ld_ldf_mask10      = 0;
                  ld_ldf_mask11      = 0;
                  ld_ldf_mask12      = 0;
                  ld_ldf_mask13      = 0;
                  ld_ldf_mask14      = 0;
                  ld_ldf_mask15      = 0;
                  ld_ldf_mask16      = 0;
                  ld_ldf_mask17      = 0;
                  ld_ldf_mask18      = 0;
                  ld_ldf_mask19      = 0;
                  ld_ldf_mask20      = 0;
                  ld_ldf_mask21      = 0;
                  ld_ldf_mask22      = 0;
                  ld_ldf_mask23      = 0;
                  ld_ldf_mask24      = 0;
                  ld_ldf_mask25      = 0;
                  ld_ldf_mask26      = 0;
                  ld_ldf_mask27      = 0;
                  ld_ldf_mask28      = 0;
                  ld_ldf_mask29      = 0;
                  ld_ldf_mask30      = 0;
                  ld_ldf_mask31      = 0;
                  ld_ldf_mask32      = 0;
                  ld_ldf_mask33      = 0;
                  ld_ldf_mask34      = 0;
                  ld_ldf_mask35      = 0;
                  ld_ldf_mask36      = 0;
                  ld_ldf_mask37      = 0;
                  ld_ldf_mask38      = 0;
                  ld_ldf_mask39      = 0;
                  ld_ldf_mask40      = 0;
                  ld_ldf_mask41      = 0;
                  ld_ldf_mask42      = 0;
                  ld_ldf_mask43      = 0;
                  ld_ldf_mask44      = 0;
                  ld_ldf_mask45      = 0;
                  ld_ldf_mask46      = 0;
                  ld_ldf_mask47      = 0;
                  ld_ldf_mask48      = 0;
                  ld_ldf_mask49      = 0;
                  ld_ldf_mask50      = 0;
                  ld_ldf_mask51      = 0;
                  ld_ldf_mask52      = 0;
                  ld_ldf_mask53      = 0;
                  ld_ldf_mask54      = 0;
                  ld_ldf_mask55      = 0;
                  ld_ldf_mask56      = 0;
                  ld_ldf_mask57      = 0;
                  ld_ldf_mask58      = 0;
                  ld_ldf_mask59      = 0;
                  ld_ldf_mask60      = 0;
                  ld_ldf_mask61      = 0;
                  ld_ldf_mask62      = 0;
                  ld_ldf_mask63      = 0;
     
    case({addr_int[18:3],3'b0}) //synopsys parallel_case full_case
    19'h0_0000: begin
                  ld_ldf_mask0       = wr_en;
                  rd_data            = {62'b0,ldf_mask0};
                end
    19'h0_2000: begin
                  ld_ldf_mask1       = wr_en;
                  rd_data            = {62'b0,ldf_mask1};
                end
    19'h0_4000: begin
                  ld_ldf_mask2       = wr_en;
                  rd_data            = {62'b0,ldf_mask2};
                end
    19'h0_6000: begin
                  ld_ldf_mask3       = wr_en;
                  rd_data            = {62'b0,ldf_mask3};
                end
    19'h0_8000: begin
                  ld_ldf_mask4       = wr_en;
                  rd_data            = {62'b0,ldf_mask4};
                end
    19'h0_a000: begin
                  ld_ldf_mask5       = wr_en;
                  rd_data            = {62'b0,ldf_mask5};
                end
    19'h0_c000: begin
                  ld_ldf_mask6       = wr_en;
                  rd_data            = {62'b0,ldf_mask6};
                end
    19'h0_e000: begin
                  ld_ldf_mask7       = wr_en;
                  rd_data            = {62'b0,ldf_mask7};
                end
    19'h1_0000: begin
                  ld_ldf_mask8       = wr_en;
                  rd_data            = {62'b0,ldf_mask8};
                end
    19'h1_2000: begin
                  ld_ldf_mask9       = wr_en;
                  rd_data            = {62'b0,ldf_mask9};
                end
    19'h1_4000: begin
                  ld_ldf_mask10      = wr_en;
                  rd_data            = {62'b0,ldf_mask10};
                end
    19'h1_6000: begin
                  ld_ldf_mask11      = wr_en;
                  rd_data            = {62'b0,ldf_mask11};
                end
    19'h1_8000: begin
                  ld_ldf_mask12      = wr_en;
                  rd_data            = {62'b0,ldf_mask12};
                end
    19'h1_a000: begin
                  ld_ldf_mask13      = wr_en;
                  rd_data            = {62'b0,ldf_mask13};
                end
    19'h1_c000: begin
                  ld_ldf_mask14      = wr_en;
                  rd_data            = {62'b0,ldf_mask14};
                end
    19'h1_e000: begin
                  ld_ldf_mask15      = wr_en;
                  rd_data            = {62'b0,ldf_mask15};
                end
    19'h2_0000: begin
                  ld_ldf_mask16      = wr_en;
                  rd_data            = {62'b0,ldf_mask16};
                end
    19'h2_2000: begin
                  ld_ldf_mask17      = wr_en;
                  rd_data            = {62'b0,ldf_mask17};
                end
    19'h2_4000: begin
                  ld_ldf_mask18      = wr_en;
                  rd_data            = {62'b0,ldf_mask18};
                end
    19'h2_6000: begin
                  ld_ldf_mask19      = wr_en;
                  rd_data            = {62'b0,ldf_mask19};
                end
    19'h2_8000: begin
                  ld_ldf_mask20      = wr_en;
                  rd_data            = {62'b0,ldf_mask20};
                end
    19'h2_a000: begin
                  ld_ldf_mask21      = wr_en;
                  rd_data            = {62'b0,ldf_mask21};
                end
    19'h2_c000: begin
                  ld_ldf_mask22      = wr_en;
                  rd_data            = {62'b0,ldf_mask22};
                end
    19'h2_e000: begin
                  ld_ldf_mask23      = wr_en;
                  rd_data            = {62'b0,ldf_mask23};
                end
    19'h3_0000: begin
                  ld_ldf_mask24      = wr_en;
                  rd_data            = {62'b0,ldf_mask24};
                end
    19'h3_2000: begin
                  ld_ldf_mask25      = wr_en;
                  rd_data            = {62'b0,ldf_mask25};
                end
    19'h3_4000: begin
                  ld_ldf_mask26      = wr_en;
                  rd_data            = {62'b0,ldf_mask26};
                end
    19'h3_6000: begin
                  ld_ldf_mask27      = wr_en;
                  rd_data            = {62'b0,ldf_mask27};
                end
    19'h3_8000: begin
                  ld_ldf_mask28      = wr_en;
                  rd_data            = {62'b0,ldf_mask28};
                end
    19'h3_a000: begin
                  ld_ldf_mask29      = wr_en;
                  rd_data            = {62'b0,ldf_mask29};
                end
    19'h3_c000: begin
                  ld_ldf_mask30      = wr_en;
                  rd_data            = {62'b0,ldf_mask30};
                end
    19'h3_e000: begin
                  ld_ldf_mask31      = wr_en;
                  rd_data            = {62'b0,ldf_mask31};
                end
    19'h4_0000: begin
                  ld_ldf_mask32      = wr_en;
                  rd_data            = {62'b0,ldf_mask32};
                end
    19'h4_2000: begin
                  ld_ldf_mask33      = wr_en;
                  rd_data            = {62'b0,ldf_mask33};
                end
    19'h4_4000: begin
                  ld_ldf_mask34      = wr_en;
                  rd_data            = {62'b0,ldf_mask34};
                end
    19'h4_6000: begin
                  ld_ldf_mask35      = wr_en;
                  rd_data            = {62'b0,ldf_mask35};
                end
    19'h4_8000: begin
                  ld_ldf_mask36      = wr_en;
                  rd_data            = {62'b0,ldf_mask36};
                end
    19'h4_a000: begin
                  ld_ldf_mask37      = wr_en;
                  rd_data            = {62'b0,ldf_mask37};
                end
    19'h4_c000: begin
                  ld_ldf_mask38      = wr_en;
                  rd_data            = {62'b0,ldf_mask38};
                end
    19'h4_e000: begin
                  ld_ldf_mask39      = wr_en;
                  rd_data            = {62'b0,ldf_mask39};
                end
    19'h5_0000: begin
                  ld_ldf_mask40      = wr_en;
                  rd_data            = {62'b0,ldf_mask40};
                end
    19'h5_2000: begin
                  ld_ldf_mask41      = wr_en;
                  rd_data            = {62'b0,ldf_mask41};
                end
    19'h5_4000: begin
                  ld_ldf_mask42      = wr_en;
                  rd_data            = {62'b0,ldf_mask42};
                end
    19'h5_6000: begin
                  ld_ldf_mask43      = wr_en;
                  rd_data            = {62'b0,ldf_mask43};
                end
    19'h5_8000: begin
                  ld_ldf_mask44      = wr_en;
                  rd_data            = {62'b0,ldf_mask44};
                end
    19'h5_a000: begin
                  ld_ldf_mask45      = wr_en;
                  rd_data            = {62'b0,ldf_mask45};
                end
    19'h5_c000: begin
                  ld_ldf_mask46      = wr_en;
                  rd_data            = {62'b0,ldf_mask46};
                end
    19'h5_e000: begin
                  ld_ldf_mask47      = wr_en;
                  rd_data            = {62'b0,ldf_mask47};
                end
    19'h6_0000: begin
                  ld_ldf_mask48      = wr_en;
                  rd_data            = {62'b0,ldf_mask48};
                end
    19'h6_2000: begin
                  ld_ldf_mask49      = wr_en;
                  rd_data            = {62'b0,ldf_mask49};
                end
    19'h6_4000: begin
                  ld_ldf_mask50      = wr_en;
                  rd_data            = {62'b0,ldf_mask50};
                end
    19'h6_6000: begin
                  ld_ldf_mask51      = wr_en;
                  rd_data            = {62'b0,ldf_mask51};
                end
    19'h6_8000: begin
                  ld_ldf_mask52      = wr_en;
                  rd_data            = {62'b0,ldf_mask52};
                end
    19'h6_a000: begin
                  ld_ldf_mask53      = wr_en;
                  rd_data            = {62'b0,ldf_mask53};
                end
    19'h6_c000: begin
                  ld_ldf_mask54      = wr_en;
                  rd_data            = {62'b0,ldf_mask54};
                end
    19'h6_e000: begin
                  ld_ldf_mask55      = wr_en;
                  rd_data            = {62'b0,ldf_mask55};
                end
    19'h7_0000: begin
                  ld_ldf_mask56      = wr_en;
                  rd_data            = {62'b0,ldf_mask56};
                end
    19'h7_2000: begin
                  ld_ldf_mask57      = wr_en;
                  rd_data            = {62'b0,ldf_mask57};
                end
    19'h7_4000: begin
                  ld_ldf_mask58      = wr_en;
                  rd_data            = {62'b0,ldf_mask58};
                end
    19'h7_6000: begin
                  ld_ldf_mask59      = wr_en;
                  rd_data            = {62'b0,ldf_mask59};
                end
    19'h7_8000: begin
                  ld_ldf_mask60      = wr_en;
                  rd_data            = {62'b0,ldf_mask60};
                end
    19'h7_a000: begin
                  ld_ldf_mask61      = wr_en;
                  rd_data            = {62'b0,ldf_mask61};
                end
    19'h7_c000: begin
                  ld_ldf_mask62      = wr_en;
                  rd_data            = {62'b0,ldf_mask62};
                end
    19'h7_e000: begin
                  ld_ldf_mask63      = wr_en;
                  rd_data            = {62'b0,ldf_mask63};
                end

    default:    begin
                  rd_data            = 64'hdead_beef_dead_beef;
                  non_qualified_addr_err = 1;
	        end   // case: default
    endcase // case({addr[18:3],3'b0})
  end // always @ (...
   
 
endmodule // niu_pio_imask0_decoder
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_pio_imask0_decoder.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/%W% %G%/
	36
	37	/*****************************************************************
	38	*
	39	* File Name : niu_pio_imask0_decoder.v
	40	* Author Name : John Lo
	41	* Description : It contains ldf_mask 0~63 read/write decoder,
	42	*
	43	* Parent Module: niu_pio_imask0_decoder.v
	44	* Child Module:
	45	* Interface Mod: many.
	46	* Date Created : 3/30/04
	47	*
	48	* Copyright (c) 2020, Sun Microsystems, Inc.
	49	* Sun Proprietary and Confidential
	50	*
	51	* Modification :
	52	*
	53	****************************************************************/
	54
	55	module niu_pio_imask0_decoder (/AUTOARG/
	56	// Outputs
	57	imask0_ack, imask0_rdata, imask0_err, ld_ldf_mask0, ld_ldf_mask1,
	58	ld_ldf_mask2, ld_ldf_mask3, ld_ldf_mask4, ld_ldf_mask5,
	59	ld_ldf_mask6, ld_ldf_mask7, ld_ldf_mask8, ld_ldf_mask9,
	60	ld_ldf_mask10, ld_ldf_mask11, ld_ldf_mask12, ld_ldf_mask13,
	61	ld_ldf_mask14, ld_ldf_mask15, ld_ldf_mask16, ld_ldf_mask17,
	62	ld_ldf_mask18, ld_ldf_mask19, ld_ldf_mask20, ld_ldf_mask21,
	63	ld_ldf_mask22, ld_ldf_mask23, ld_ldf_mask24, ld_ldf_mask25,
	64	ld_ldf_mask26, ld_ldf_mask27, ld_ldf_mask28, ld_ldf_mask29,
65	ld_ldf_mask30, ld_ldf_mask31, ld_ldf_mask32, ld_ldf_mask33,
66	ld_ldf_mask34, ld_ldf_mask35, ld_ldf_mask36, ld_ldf_mask37,
67	ld_ldf_mask38, ld_ldf_mask39, ld_ldf_mask40, ld_ldf_mask41,
68	ld_ldf_mask42, ld_ldf_mask43, ld_ldf_mask44, ld_ldf_mask45,
69	ld_ldf_mask46, ld_ldf_mask47, ld_ldf_mask48, ld_ldf_mask49,
70	ld_ldf_mask50, ld_ldf_mask51, ld_ldf_mask52, ld_ldf_mask53,
71	ld_ldf_mask54, ld_ldf_mask55, ld_ldf_mask56, ld_ldf_mask57,
72	ld_ldf_mask58, ld_ldf_mask59, ld_ldf_mask60, ld_ldf_mask61,
73	ld_ldf_mask62, ld_ldf_mask63,
74	// Inputs
75	clk, reset, imask0_sel_reg, addr, rd, ldf_mask0, ldf_mask1,
76	ldf_mask2, ldf_mask3, ldf_mask4, ldf_mask5, ldf_mask6, ldf_mask7,
77	ldf_mask8, ldf_mask9, ldf_mask10, ldf_mask11, ldf_mask12,
78	ldf_mask13, ldf_mask14, ldf_mask15, ldf_mask16, ldf_mask17,
79	ldf_mask18, ldf_mask19, ldf_mask20, ldf_mask21, ldf_mask22,
80	ldf_mask23, ldf_mask24, ldf_mask25, ldf_mask26, ldf_mask27,
81	ldf_mask28, ldf_mask29, ldf_mask30, ldf_mask31, ldf_mask32,
82	ldf_mask33, ldf_mask34, ldf_mask35, ldf_mask36, ldf_mask37,
83	ldf_mask38, ldf_mask39, ldf_mask40, ldf_mask41, ldf_mask42,
84	ldf_mask43, ldf_mask44, ldf_mask45, ldf_mask46, ldf_mask47,
85	ldf_mask48, ldf_mask49, ldf_mask50, ldf_mask51, ldf_mask52,
86	ldf_mask53, ldf_mask54, ldf_mask55, ldf_mask56, ldf_mask57,
87	ldf_mask58, ldf_mask59, ldf_mask60, ldf_mask61, ldf_mask62,
88	ldf_mask63
89	);
90	input clk;
91	input reset;
92	input imask0_sel_reg;
93	// pio broadcast signals
94	input [18:0] addr;
95	input rd;
96	input [1:0] ldf_mask0 ;
97	input [1:0] ldf_mask1 ;
98	input [1:0] ldf_mask2 ;
99	input [1:0] ldf_mask3 ;
100	input [1:0] ldf_mask4 ;
101	input [1:0] ldf_mask5 ;
102	input [1:0] ldf_mask6 ;
103	input [1:0] ldf_mask7 ;
104	input [1:0] ldf_mask8 ;
105	input [1:0] ldf_mask9 ;
106	input [1:0] ldf_mask10;
107	input [1:0] ldf_mask11;
108	input [1:0] ldf_mask12;
109	input [1:0] ldf_mask13;
110	input [1:0] ldf_mask14;
111	input [1:0] ldf_mask15;
112	input [1:0] ldf_mask16;
113	input [1:0] ldf_mask17;
114	input [1:0] ldf_mask18;
115	input [1:0] ldf_mask19;
116	input [1:0] ldf_mask20;
117	input [1:0] ldf_mask21;
118	input [1:0] ldf_mask22;
119	input [1:0] ldf_mask23;
120	input [1:0] ldf_mask24;
121	input [1:0] ldf_mask25;
122	input [1:0] ldf_mask26;
123	input [1:0] ldf_mask27;
124	input [1:0] ldf_mask28;
125	input [1:0] ldf_mask29;
126	input [1:0] ldf_mask30;
127	input [1:0] ldf_mask31;
128	input [1:0] ldf_mask32;
129	input [1:0] ldf_mask33;
130	input [1:0] ldf_mask34;
131	input [1:0] ldf_mask35;
132	input [1:0] ldf_mask36;
133	input [1:0] ldf_mask37;
134	input [1:0] ldf_mask38;
135	input [1:0] ldf_mask39;
136	input [1:0] ldf_mask40;
137	input [1:0] ldf_mask41;
138	input [1:0] ldf_mask42;
139	input [1:0] ldf_mask43;
140	input [1:0] ldf_mask44;
141	input [1:0] ldf_mask45;
142	input [1:0] ldf_mask46;
143	input [1:0] ldf_mask47;
144	input [1:0] ldf_mask48;
145	input [1:0] ldf_mask49;
146	input [1:0] ldf_mask50;
147	input [1:0] ldf_mask51;
148	input [1:0] ldf_mask52;
149	input [1:0] ldf_mask53;
150	input [1:0] ldf_mask54;
151	input [1:0] ldf_mask55;
152	input [1:0] ldf_mask56;
153	input [1:0] ldf_mask57;
154	input [1:0] ldf_mask58;
155	input [1:0] ldf_mask59;
156	input [1:0] ldf_mask60;
157	input [1:0] ldf_mask61;
158	input [1:0] ldf_mask62;
159	input [1:0] ldf_mask63;
160
161	output imask0_ack;
162	output [63:0] imask0_rdata;
163	output imask0_err;
164
165	output ld_ldf_mask0 ;
166	output ld_ldf_mask1 ;
167	output ld_ldf_mask2 ;
168	output ld_ldf_mask3 ;
169	output ld_ldf_mask4 ;
170	output ld_ldf_mask5 ;
171	output ld_ldf_mask6 ;
172	output ld_ldf_mask7 ;
173	output ld_ldf_mask8 ;
174	output ld_ldf_mask9 ;
175	output ld_ldf_mask10;
176	output ld_ldf_mask11;
177	output ld_ldf_mask12;
178	output ld_ldf_mask13;
179	output ld_ldf_mask14;
180	output ld_ldf_mask15;
181	output ld_ldf_mask16;
182	output ld_ldf_mask17;
183	output ld_ldf_mask18;
184	output ld_ldf_mask19;
185	output ld_ldf_mask20;
186	output ld_ldf_mask21;
187	output ld_ldf_mask22;
188	output ld_ldf_mask23;
189	output ld_ldf_mask24;
190	output ld_ldf_mask25;
191	output ld_ldf_mask26;
192	output ld_ldf_mask27;
193	output ld_ldf_mask28;
194	output ld_ldf_mask29;
195	output ld_ldf_mask30;
196	output ld_ldf_mask31;
197	output ld_ldf_mask32;
198	output ld_ldf_mask33;
199	output ld_ldf_mask34;
200	output ld_ldf_mask35;
201	output ld_ldf_mask36;
202	output ld_ldf_mask37;
203	output ld_ldf_mask38;
204	output ld_ldf_mask39;
205	output ld_ldf_mask40;
206	output ld_ldf_mask41;
207	output ld_ldf_mask42;
208	output ld_ldf_mask43;
209	output ld_ldf_mask44;
210	output ld_ldf_mask45;
211	output ld_ldf_mask46;
212	output ld_ldf_mask47;
213	output ld_ldf_mask48;
214	output ld_ldf_mask49;
215	output ld_ldf_mask50;
216	output ld_ldf_mask51;
217	output ld_ldf_mask52;
218	output ld_ldf_mask53;
219	output ld_ldf_mask54;
220	output ld_ldf_mask55;
221	output ld_ldf_mask56;
222	output ld_ldf_mask57;
223	output ld_ldf_mask58;
224	output ld_ldf_mask59;
225	output ld_ldf_mask60;
226	output ld_ldf_mask61;
227	output ld_ldf_mask62;
228	output ld_ldf_mask63;
229
230	// common reg declaration
231	reg [63:0] rd_data;
232	reg non_qualified_addr_err;
233	// common wrie declaration
234	wire [63:0] imask0_rdata;
235	wire rd_en;
236	wire wr_en;
237	wire rasr;
238	// output reg declaration
239	reg ld_ldf_mask0 ;
240	reg ld_ldf_mask1 ;
241	reg ld_ldf_mask2 ;
242	reg ld_ldf_mask3 ;
243	reg ld_ldf_mask4 ;
244	reg ld_ldf_mask5 ;
245	reg ld_ldf_mask6 ;
246	reg ld_ldf_mask7 ;
247	reg ld_ldf_mask8 ;
248	reg ld_ldf_mask9 ;
249	reg ld_ldf_mask10;
250	reg ld_ldf_mask11;
251	reg ld_ldf_mask12;
252	reg ld_ldf_mask13;
253	reg ld_ldf_mask14;
254	reg ld_ldf_mask15;
255	reg ld_ldf_mask16;
256	reg ld_ldf_mask17;
257	reg ld_ldf_mask18;
258	reg ld_ldf_mask19;
259	reg ld_ldf_mask20;
260	reg ld_ldf_mask21;
261	reg ld_ldf_mask22;
262	reg ld_ldf_mask23;
263	reg ld_ldf_mask24;
264	reg ld_ldf_mask25;
265	reg ld_ldf_mask26;
266	reg ld_ldf_mask27;
267	reg ld_ldf_mask28;
268	reg ld_ldf_mask29;
269	reg ld_ldf_mask30;
270	reg ld_ldf_mask31;
271	reg ld_ldf_mask32;
272	reg ld_ldf_mask33;
273	reg ld_ldf_mask34;
274	reg ld_ldf_mask35;
275	reg ld_ldf_mask36;
276	reg ld_ldf_mask37;
277	reg ld_ldf_mask38;
278	reg ld_ldf_mask39;
279	reg ld_ldf_mask40;
280	reg ld_ldf_mask41;
281	reg ld_ldf_mask42;
282	reg ld_ldf_mask43;
283	reg ld_ldf_mask44;
284	reg ld_ldf_mask45;
285	reg ld_ldf_mask46;
286	reg ld_ldf_mask47;
287	reg ld_ldf_mask48;
288	reg ld_ldf_mask49;
289	reg ld_ldf_mask50;
290	reg ld_ldf_mask51;
291	reg ld_ldf_mask52;
292	reg ld_ldf_mask53;
293	reg ld_ldf_mask54;
294	reg ld_ldf_mask55;
295	reg ld_ldf_mask56;
296	reg ld_ldf_mask57;
297	reg ld_ldf_mask58;
298	reg ld_ldf_mask59;
299	reg ld_ldf_mask60;
300	reg ld_ldf_mask61;
301	reg ld_ldf_mask62;
302	reg ld_ldf_mask63;
303
304	`ifdef NEPTUNE
305	/* ---------------------------------------------------------- */
306	reg imask0_sel_reg_int;
307	reg rd_int;
308	reg [18:0] addr_int;
309
310	always @(posedge clk)
311	if (reset)
312	begin
313	imask0_sel_reg_int <= 1'b0;
314	rd_int <= 1'b0;
315	addr_int <= 19'b0;
316	end
317	else
318	begin
319	imask0_sel_reg_int <= imask0_sel_reg ;
320	rd_int <= rd ;
321	addr_int <= addr;
322	end
323
324	`else
325	/* ---------------------------------------------------------- */
326
327	wire imask0_sel_reg_int;
328	wire rd_int;
329	wire [18:0] addr_int;
330
331	assign imask0_sel_reg_int = imask0_sel_reg ;
332	assign rd_int = rd ;
333	assign addr_int = addr ;
334	/* ----------------------------------------------------------- */
335	`endif
336
337	niu_rw_ctl imask0_rw_ctl(
338	// Outputs
339	.wr_en (wr_en),
340	.rd_en (rd_en),
341	.ack (imask0_ack),
342	.rdata (imask0_rdata[63:0]),
343	.err (imask0_err),
344	.rasr (rasr),
345	// Inputs
346	.clk (clk),
347	.sel (imask0_sel_reg_int),
348	.rd (rd_int),
349	.rd_data (rd_data[63:0]),
350	.non_qualified_addr_err(non_qualified_addr_err));
351
352
353	always @ (/AUTOSENSE/addr_int or ldf_mask0 or ldf_mask1 or ldf_mask10
354	or ldf_mask11 or ldf_mask12 or ldf_mask13 or ldf_mask14
355	or ldf_mask15 or ldf_mask16 or ldf_mask17 or ldf_mask18
356	or ldf_mask19 or ldf_mask2 or ldf_mask20 or ldf_mask21
357	or ldf_mask22 or ldf_mask23 or ldf_mask24 or ldf_mask25
358	or ldf_mask26 or ldf_mask27 or ldf_mask28 or ldf_mask29
359	or ldf_mask3 or ldf_mask30 or ldf_mask31 or ldf_mask32
360	or ldf_mask33 or ldf_mask34 or ldf_mask35 or ldf_mask36
361	or ldf_mask37 or ldf_mask38 or ldf_mask39 or ldf_mask4
362	or ldf_mask40 or ldf_mask41 or ldf_mask42 or ldf_mask43
363	or ldf_mask44 or ldf_mask45 or ldf_mask46 or ldf_mask47
364	or ldf_mask48 or ldf_mask49 or ldf_mask5 or ldf_mask50
365	or ldf_mask51 or ldf_mask52 or ldf_mask53 or ldf_mask54
366	or ldf_mask55 or ldf_mask56 or ldf_mask57 or ldf_mask58
367	or ldf_mask59 or ldf_mask6 or ldf_mask60 or ldf_mask61
368	or ldf_mask62 or ldf_mask63 or ldf_mask7 or ldf_mask8
369	or ldf_mask9 or wr_en)
370	begin
371	non_qualified_addr_err = 0;
372	rd_data = 64'hdead_beef_dead_beef;
373
374	ld_ldf_mask0 = 0;
375	ld_ldf_mask1 = 0;
376	ld_ldf_mask2 = 0;
377	ld_ldf_mask3 = 0;
378	ld_ldf_mask4 = 0;
379	ld_ldf_mask5 = 0;
380	ld_ldf_mask6 = 0;
381	ld_ldf_mask7 = 0;
382	ld_ldf_mask8 = 0;
383	ld_ldf_mask9 = 0;
384	ld_ldf_mask10 = 0;
385	ld_ldf_mask11 = 0;
386	ld_ldf_mask12 = 0;
387	ld_ldf_mask13 = 0;
388	ld_ldf_mask14 = 0;
389	ld_ldf_mask15 = 0;
390	ld_ldf_mask16 = 0;
391	ld_ldf_mask17 = 0;
392	ld_ldf_mask18 = 0;
393	ld_ldf_mask19 = 0;
394	ld_ldf_mask20 = 0;
395	ld_ldf_mask21 = 0;
396	ld_ldf_mask22 = 0;
397	ld_ldf_mask23 = 0;
398	ld_ldf_mask24 = 0;
399	ld_ldf_mask25 = 0;
400	ld_ldf_mask26 = 0;
401	ld_ldf_mask27 = 0;
402	ld_ldf_mask28 = 0;
403	ld_ldf_mask29 = 0;
404	ld_ldf_mask30 = 0;
405	ld_ldf_mask31 = 0;
406	ld_ldf_mask32 = 0;
407	ld_ldf_mask33 = 0;
408	ld_ldf_mask34 = 0;
409	ld_ldf_mask35 = 0;
410	ld_ldf_mask36 = 0;
411	ld_ldf_mask37 = 0;
412	ld_ldf_mask38 = 0;
413	ld_ldf_mask39 = 0;
414	ld_ldf_mask40 = 0;
415	ld_ldf_mask41 = 0;
416	ld_ldf_mask42 = 0;
417	ld_ldf_mask43 = 0;
418	ld_ldf_mask44 = 0;
419	ld_ldf_mask45 = 0;
420	ld_ldf_mask46 = 0;
421	ld_ldf_mask47 = 0;
422	ld_ldf_mask48 = 0;
423	ld_ldf_mask49 = 0;
424	ld_ldf_mask50 = 0;
425	ld_ldf_mask51 = 0;
426	ld_ldf_mask52 = 0;
427	ld_ldf_mask53 = 0;
428	ld_ldf_mask54 = 0;
429	ld_ldf_mask55 = 0;
430	ld_ldf_mask56 = 0;
431	ld_ldf_mask57 = 0;
432	ld_ldf_mask58 = 0;
433	ld_ldf_mask59 = 0;
434	ld_ldf_mask60 = 0;
435	ld_ldf_mask61 = 0;
436	ld_ldf_mask62 = 0;
437	ld_ldf_mask63 = 0;
438
439	case({addr_int[18:3],3'b0}) //synopsys parallel_case full_case
440	19'h0_0000: begin
441	ld_ldf_mask0 = wr_en;
442	rd_data = {62'b0,ldf_mask0};
443	end
444	19'h0_2000: begin
445	ld_ldf_mask1 = wr_en;
446	rd_data = {62'b0,ldf_mask1};
447	end
448	19'h0_4000: begin
449	ld_ldf_mask2 = wr_en;
450	rd_data = {62'b0,ldf_mask2};
451	end
452	19'h0_6000: begin
453	ld_ldf_mask3 = wr_en;
454	rd_data = {62'b0,ldf_mask3};
455	end
456	19'h0_8000: begin
457	ld_ldf_mask4 = wr_en;
458	rd_data = {62'b0,ldf_mask4};
459	end
460	19'h0_a000: begin
461	ld_ldf_mask5 = wr_en;
462	rd_data = {62'b0,ldf_mask5};
463	end
464	19'h0_c000: begin
465	ld_ldf_mask6 = wr_en;
466	rd_data = {62'b0,ldf_mask6};
467	end
468	19'h0_e000: begin
469	ld_ldf_mask7 = wr_en;
470	rd_data = {62'b0,ldf_mask7};
471	end
472	19'h1_0000: begin
473	ld_ldf_mask8 = wr_en;
474	rd_data = {62'b0,ldf_mask8};
475	end
476	19'h1_2000: begin
477	ld_ldf_mask9 = wr_en;
478	rd_data = {62'b0,ldf_mask9};
479	end
480	19'h1_4000: begin
481	ld_ldf_mask10 = wr_en;
482	rd_data = {62'b0,ldf_mask10};
483	end
484	19'h1_6000: begin
485	ld_ldf_mask11 = wr_en;
486	rd_data = {62'b0,ldf_mask11};
487	end
488	19'h1_8000: begin
489	ld_ldf_mask12 = wr_en;
490	rd_data = {62'b0,ldf_mask12};
491	end
492	19'h1_a000: begin
493	ld_ldf_mask13 = wr_en;
494	rd_data = {62'b0,ldf_mask13};
495	end
496	19'h1_c000: begin
497	ld_ldf_mask14 = wr_en;
498	rd_data = {62'b0,ldf_mask14};
499	end
500	19'h1_e000: begin
501	ld_ldf_mask15 = wr_en;
502	rd_data = {62'b0,ldf_mask15};
503	end
504	19'h2_0000: begin
505	ld_ldf_mask16 = wr_en;
506	rd_data = {62'b0,ldf_mask16};
507	end
508	19'h2_2000: begin
509	ld_ldf_mask17 = wr_en;
510	rd_data = {62'b0,ldf_mask17};
511	end
512	19'h2_4000: begin
513	ld_ldf_mask18 = wr_en;
514	rd_data = {62'b0,ldf_mask18};
515	end
516	19'h2_6000: begin
517	ld_ldf_mask19 = wr_en;
518	rd_data = {62'b0,ldf_mask19};
519	end
520	19'h2_8000: begin
521	ld_ldf_mask20 = wr_en;
522	rd_data = {62'b0,ldf_mask20};
523	end
524	19'h2_a000: begin
525	ld_ldf_mask21 = wr_en;
526	rd_data = {62'b0,ldf_mask21};
527	end
528	19'h2_c000: begin
529	ld_ldf_mask22 = wr_en;
530	rd_data = {62'b0,ldf_mask22};
531	end
532	19'h2_e000: begin
533	ld_ldf_mask23 = wr_en;
534	rd_data = {62'b0,ldf_mask23};
535	end
536	19'h3_0000: begin
537	ld_ldf_mask24 = wr_en;
538	rd_data = {62'b0,ldf_mask24};
539	end
540	19'h3_2000: begin
541	ld_ldf_mask25 = wr_en;
542	rd_data = {62'b0,ldf_mask25};
543	end
544	19'h3_4000: begin
545	ld_ldf_mask26 = wr_en;
546	rd_data = {62'b0,ldf_mask26};
547	end
548	19'h3_6000: begin
549	ld_ldf_mask27 = wr_en;
550	rd_data = {62'b0,ldf_mask27};
551	end
552	19'h3_8000: begin
553	ld_ldf_mask28 = wr_en;
554	rd_data = {62'b0,ldf_mask28};
555	end
556	19'h3_a000: begin
557	ld_ldf_mask29 = wr_en;
558	rd_data = {62'b0,ldf_mask29};
559	end
560	19'h3_c000: begin
561	ld_ldf_mask30 = wr_en;
562	rd_data = {62'b0,ldf_mask30};
563	end
564	19'h3_e000: begin
565	ld_ldf_mask31 = wr_en;
566	rd_data = {62'b0,ldf_mask31};
567	end
568	19'h4_0000: begin
569	ld_ldf_mask32 = wr_en;
570	rd_data = {62'b0,ldf_mask32};
571	end
572	19'h4_2000: begin
573	ld_ldf_mask33 = wr_en;
574	rd_data = {62'b0,ldf_mask33};
575	end
576	19'h4_4000: begin
577	ld_ldf_mask34 = wr_en;
578	rd_data = {62'b0,ldf_mask34};
579	end
580	19'h4_6000: begin
581	ld_ldf_mask35 = wr_en;
582	rd_data = {62'b0,ldf_mask35};
583	end
584	19'h4_8000: begin
585	ld_ldf_mask36 = wr_en;
586	rd_data = {62'b0,ldf_mask36};
587	end
588	19'h4_a000: begin
589	ld_ldf_mask37 = wr_en;
590	rd_data = {62'b0,ldf_mask37};
591	end
592	19'h4_c000: begin
593	ld_ldf_mask38 = wr_en;
594	rd_data = {62'b0,ldf_mask38};
595	end
596	19'h4_e000: begin
597	ld_ldf_mask39 = wr_en;
598	rd_data = {62'b0,ldf_mask39};
599	end
600	19'h5_0000: begin
601	ld_ldf_mask40 = wr_en;
602	rd_data = {62'b0,ldf_mask40};
603	end
604	19'h5_2000: begin
605	ld_ldf_mask41 = wr_en;
606	rd_data = {62'b0,ldf_mask41};
607	end
608	19'h5_4000: begin
609	ld_ldf_mask42 = wr_en;
610	rd_data = {62'b0,ldf_mask42};
611	end
612	19'h5_6000: begin
613	ld_ldf_mask43 = wr_en;
614	rd_data = {62'b0,ldf_mask43};
615	end
616	19'h5_8000: begin
617	ld_ldf_mask44 = wr_en;
618	rd_data = {62'b0,ldf_mask44};
619	end
620	19'h5_a000: begin
621	ld_ldf_mask45 = wr_en;
622	rd_data = {62'b0,ldf_mask45};
623	end
624	19'h5_c000: begin
625	ld_ldf_mask46 = wr_en;
626	rd_data = {62'b0,ldf_mask46};
627	end
628	19'h5_e000: begin
629	ld_ldf_mask47 = wr_en;
630	rd_data = {62'b0,ldf_mask47};
631	end
632	19'h6_0000: begin
633	ld_ldf_mask48 = wr_en;
634	rd_data = {62'b0,ldf_mask48};
635	end
636	19'h6_2000: begin
637	ld_ldf_mask49 = wr_en;
638	rd_data = {62'b0,ldf_mask49};
639	end
640	19'h6_4000: begin
641	ld_ldf_mask50 = wr_en;
642	rd_data = {62'b0,ldf_mask50};
643	end
644	19'h6_6000: begin
645	ld_ldf_mask51 = wr_en;
646	rd_data = {62'b0,ldf_mask51};
647	end
648	19'h6_8000: begin
649	ld_ldf_mask52 = wr_en;
650	rd_data = {62'b0,ldf_mask52};
651	end
652	19'h6_a000: begin
653	ld_ldf_mask53 = wr_en;
654	rd_data = {62'b0,ldf_mask53};
655	end
656	19'h6_c000: begin
657	ld_ldf_mask54 = wr_en;
658	rd_data = {62'b0,ldf_mask54};
659	end
660	19'h6_e000: begin
661	ld_ldf_mask55 = wr_en;
662	rd_data = {62'b0,ldf_mask55};
663	end
664	19'h7_0000: begin
665	ld_ldf_mask56 = wr_en;
666	rd_data = {62'b0,ldf_mask56};
667	end
668	19'h7_2000: begin
669	ld_ldf_mask57 = wr_en;
670	rd_data = {62'b0,ldf_mask57};
671	end
672	19'h7_4000: begin
673	ld_ldf_mask58 = wr_en;
674	rd_data = {62'b0,ldf_mask58};
675	end
676	19'h7_6000: begin
677	ld_ldf_mask59 = wr_en;
678	rd_data = {62'b0,ldf_mask59};
679	end
680	19'h7_8000: begin
681	ld_ldf_mask60 = wr_en;
682	rd_data = {62'b0,ldf_mask60};
683	end
684	19'h7_a000: begin
685	ld_ldf_mask61 = wr_en;
686	rd_data = {62'b0,ldf_mask61};
687	end
688	19'h7_c000: begin
689	ld_ldf_mask62 = wr_en;
690	rd_data = {62'b0,ldf_mask62};
691	end
692	19'h7_e000: begin
693	ld_ldf_mask63 = wr_en;
694	rd_data = {62'b0,ldf_mask63};
695	end
696
697	default: begin
698	rd_data = 64'hdead_beef_dead_beef;
699	non_qualified_addr_err = 1;
700	end // case: default
701	endcase // case({addr[18:3],3'b0})
702	end // always @ (...
703
704
705
706
707	endmodule // niu_pio_imask0_decoder
708
709