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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_rdmc_chnl_master.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_rdmc_chnl_master.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35/*************************************************************************
36 *
37 * File Name : niu_rdmc_chnl_master.v
38 * Author Name : Jeanne Cai
39 * Description :
40 * Date Created : 07/18/2004
41 *
42 * Copyright (c) 2001, Sun Microsystems, Inc.
43 * Sun Proprietary and Confidential
44 *
45 *
46 *************************************************************************/
47module niu_rdmc_chnl_master (
48 clk,
49 reset,
50 wred_enable,
51 random_num,
52 clk_div_value,
53
54 dma_chnl_grp_id,
55 pio_32b_mode,
56 pio_wen,
57 pio_addr,
58 pio_wdata,
59 muxed_pkt_len, //from wr_dp
60 muxed_rdc_num_r, //from wr_dp
61 muxed_drop_pkt_r,
62 muxed_s_event_r,
63 sel_buf_en, //from wr_sched
64 pkt_req_cnt_e_done_mod,
65 pkt_buf_done,
66 is_hdr_wr_data,
67 is_jmb1_wr_data,
68 wr_transfer_comp_int,
69 wr_last_pkt_data,
70 update_rcr_shadw,
71 cache_start_addr,
72 cache_end_addr,
73 cache_buf_rd_gnt, //from cache_acc_ctrl
74 cache_buf_rd_data, //from cache_acc_ctrl
75 fetch_desp_gnt, //from desp_acc_ctrl
76 rdmc_resp_rdy_valid, //from desp_acc_ctrl
77 rdmc_req_err,
78 rdmc_resp_cmd,
79 rdmc_resp_cmd_status,
80 rdmc_resp_data_status,
81 rdmc_resp_dma_num,
82 rdmc_resp_data_valid,
83 rdmc_resp_byteenable,
84 rdmc_resp_comp,
85 rdmc_resp_trans_comp,
86 resp_data_in_process,
87
88 shadw_start_addr,
89 shadw_rd_end_addr,
90 shadw_wr_end_addr,
91 rdmc_wr_data_dma_num,
92 rcr_wrbk_gnt,
93 rcr_wrbk_done,
94 rcr_wrbk_pkt_num,
95 rdmc_rcr_ack_valid,
96 rdmc_rcr_ack_err,
97 rdmc_rcr_ack_dma_num,
98 cache_parity_err,
99 shadw_parity_err,
100 data_err_event,
101
102//output
103 pio_rd_gnt,
104 chnl_pio_rd_data,
105 rx_log_page_hdl_reg, //to zcp
106 dma_func_num,
107 fetch_desp_req, //to desp_acc_ctrl
108 fetch_desp_addr, //to desp_acc_ctrl
109 fetch_desp_num, //to desp_acc_ctrl
110 rdmc_resp_accept_sm, //to desp_acc_ctrl
111 fetch_desp_resp_vld, //to desp_acc_ctrl
112 cache_read_req, //to cache_acc_ctrl
113 cache_rd_ptr, //to cache_acc_ctrl
114 cache_wr_ptr, //to cache_acc_ctrl
115 full_header, //to wr_sched
116 drop_pkt,
117 pkt_buf_gnt, //to wr_sched
118 pkt_buf_size,
119 pkt_buf_addr, //to wr_sched
120 orig_buf_addr,
121 pref_buf_used_num,
122 pkt_trans_len,
123
124 shadw_wr_en,
125 shadw_wr_even,
126 shadw_wr_ptr,
127 shadw_rd_ptr,
128 mailbox_data,
129 ldf_a,
130 ldf_b,
131 rcr_wrbk_sched,
132 rcr_wrbk_req,
133 rcr_wrbk_addr,
134 rcr_wrbk_numb,
135 rcr_wrbk_data_type,
136 rcr_ack_accept
137
138
139 );
140
141input clk;
142input reset;
143input wred_enable;
144input[15:0] random_num;
145input[15:0] clk_div_value;
146input[4:0] dma_chnl_grp_id;
147input pio_32b_mode;
148input pio_wen;
149input[19:0] pio_addr;
150input[63:0] pio_wdata;
151input[13:0] muxed_pkt_len;
152input[4:0] muxed_rdc_num_r;
153input muxed_drop_pkt_r;
154input muxed_s_event_r;
155input sel_buf_en;
156input pkt_req_cnt_e_done_mod;
157input pkt_buf_done;
158input is_hdr_wr_data;
159input is_jmb1_wr_data;
160input wr_transfer_comp_int;
161input wr_last_pkt_data;
162input update_rcr_shadw;
163input[7:0] cache_start_addr;
164input[7:0] cache_end_addr;
165input cache_buf_rd_gnt;
166input[131:0] cache_buf_rd_data;
167input fetch_desp_gnt;
168input rdmc_resp_rdy_valid;
169input rdmc_req_err;
170input[4:0] rdmc_resp_cmd;
171input[3:0] rdmc_resp_cmd_status;
172input[3:0] rdmc_resp_data_status;
173input[4:0] rdmc_resp_dma_num;
174input rdmc_resp_data_valid;
175input[15:0] rdmc_resp_byteenable;
176input rdmc_resp_comp;
177input rdmc_resp_trans_comp;
178input resp_data_in_process;
179input cache_parity_err;
180input shadw_parity_err;
181input data_err_event;
182
183input[7:0] shadw_start_addr;
184input[7:0] shadw_rd_end_addr;
185input[7:0] shadw_wr_end_addr;
186input[4:0] rdmc_wr_data_dma_num;
187input rcr_wrbk_gnt;
188input rcr_wrbk_done;
189input[3:0] rcr_wrbk_pkt_num;
190input rdmc_rcr_ack_valid;
191input rdmc_rcr_ack_err;
192input[4:0] rdmc_rcr_ack_dma_num;
193
194
195output pio_rd_gnt;
196output[63:0] chnl_pio_rd_data;
197output[19:0] rx_log_page_hdl_reg;
198output[1:0] dma_func_num;
199output fetch_desp_req;
200output[63:0] fetch_desp_addr;
201output[4:0] fetch_desp_num;
202output rdmc_resp_accept_sm;
203output fetch_desp_resp_vld;
204output cache_read_req;
205output[7:0] cache_rd_ptr;
206output[7:0] cache_wr_ptr;
207output full_header;
208output drop_pkt;
209output pkt_buf_gnt;
210output[1:0] pkt_buf_size;
211output[63:0] pkt_buf_addr;
212output[35:0] orig_buf_addr;
213output[1:0] pref_buf_used_num;
214output[13:0] pkt_trans_len;
215
216output shadw_wr_en;
217output shadw_wr_even;
218output[7:0] shadw_wr_ptr;
219output[7:0] shadw_rd_ptr;
220output[168:0] mailbox_data;
221output ldf_a;
222output ldf_b;
223output rcr_wrbk_sched;
224output rcr_wrbk_req;
225output[63:0] rcr_wrbk_addr;
226output[3:0] rcr_wrbk_numb;
227output rcr_wrbk_data_type;
228output rcr_ack_accept;
229
230wire chnl_sel_buf_en_r;
231wire[1:0] pref_buf_used_num;
232wire[13:0] pkt_trans_len;
233wire desp_init_valid;
234wire fetch_desp_trig;
235wire[63:0] fetch_desp_addr;
236wire[4:0] fetch_desp_num;
237wire cache_read_req;
238wire[7:0] cache_rd_ptr;
239wire[7:0] cache_wr_ptr;
240wire pkt_buf_gnt;
241wire[1:0] pkt_buf_size;
242wire[63:0] pkt_buf_addr;
243wire[35:0] orig_buf_addr;
244wire[15:0] desp_curr_addr;
245wire[16:0] desp_curr_cnt;
246wire desp_addr_not_valid;
247wire buf_addr_not_valid;
248wire rbr_addr_overflow;
249wire desp_curr_cnt_overflow;
250wire rbr_empty;
251wire wred_drop_pkt;
252wire rcr_drop_pkt;
253wire rbr_drop_pkt;
254wire chnl_sel_buf_en;
255wire chnl_cache_parity_err;
256
257wire fetch_desp_req;
258wire rdmc_resp_accept_sm;
259wire fetch_desp_resp_vld;
260wire fetch_desp_req_sm;
261wire fetch_desp_pre_done;
262wire fetch_desp_done;
263wire resp_bus_err;
264wire[3:0] resp_bus_err_type;
265wire rbr_idle_cycle;
266
267wire dma_en;
268wire dma_reset;
269wire[1:0] dma_data_offset;
270wire full_header;
271wire page_valid0;
272wire[31:0] addr_mask0;
273wire[31:0] comp_value0;
274wire[31:0] relo_value0;
275wire page_valid1;
276wire[31:0] addr_mask1;
277wire[31:0] comp_value1;
278wire[31:0] relo_value1;
279wire dma_fatal_err;
280wire[19:0] rx_log_page_hdl_reg;
281wire[1:0] dma_func_num;
282wire[31:0] rdc_red_param_reg;
283wire[53:0] rbr_cfig_a_reg;
284wire[10:0] rbr_cfig_b_reg;
285wire[15:0] rbr_kick_reg;
286wire[53:0] rcr_cfig_a_reg;
287wire[22:0] rcr_cfig_b_reg;
288wire[31:0] rx_dma_ctl_stat_reg;
289wire rx_dma_ctl_stat_reg_bit47;
290wire rcr_flush_reg;
291wire[43:0] mbox_addr;
292wire[168:0] mailbox_data;
293wire ldf_a;
294wire ldf_b;
295wire rbr_cfig_a_reg_wenu;
296wire rbr_cfig_a_reg_wenl;
297wire rbr_kick_reg_wen;
298wire rcr_cfig_a_reg_wenu;
299wire rcr_cfig_a_reg_wenl;
300wire rx_dma_ctl_stat_reg_wenu;
301wire rx_dma_ctl_stat_reg_wenl;
302wire pio_rd_gnt;
303wire[63:0] chnl_pio_rd_data;
304
305wire shadw_wr_en;
306wire shadw_wr_even;
307wire[7:0] shadw_wr_ptr;
308wire[7:0] shadw_rd_ptr;
309wire rcr_wrbk_req;
310wire[63:0] rcr_wrbk_addr;
311wire[3:0] rcr_wrbk_numb;
312wire rcr_wrbk_data_type;
313wire rcr_wrbk_sched;
314wire rcr_ack_accept;
315wire[15:0] rcr_curr_qlen;
316wire[7:0] shadw_curr_space_cnt;
317wire reset_rcr_flush;
318wire m_bit_en;
319wire[2:0] rcr_ctl_stat_word;
320wire[15:0] rcr_curr_addr;
321wire[15:0] rcr_status_a;
322wire rcr_addr_not_valid;
323wire mbox_addr_not_valid;
324wire rcr_addr_overflow;
325wire rcr_curr_cnt_overflow;
326wire rcr_curr_cnt_underflow;
327wire rcr_pkt_cnt_underflow;
328wire rcr_idle_cycle;
329wire chnl_has_pkt;
330wire rcr_ack_err;
331wire chnl_shadw_parity_err;
332
333`ifdef NEPTUNE
334wire [3:0] do_nad;
335wire [3:0] do_nor;
336wire [3:0] do_inv;
337wire [3:0] do_mux;
338wire [3:0] do_q;
339wire so;
340
341nep_spare_rdmc spare_rdmc_0 (
342 .di_nd3 ({1'h1, 1'h1, do_q[3]}),
343 .di_nd2 ({1'h1, 1'h1, do_q[2]}),
344 .di_nd1 ({1'h1, 1'h1, do_q[1]}),
345 .di_nd0 ({1'h1, 1'h1, do_q[0]}),
346 .di_nr3 ({1'h0, 1'h0}),
347 .di_nr2 ({1'h0, 1'h0}),
348 .di_nr1 ({1'h0, 1'h0}),
349 .di_nr0 ({1'h0, 1'h0}),
350 .di_inv (do_nad[3:0]),
351 .di_mx3 ({1'h0, 1'h0}),
352 .di_mx2 ({1'h0, 1'h0}),
353 .di_mx1 ({1'h0, 1'h0}),
354 .di_mx0 ({1'h0, 1'h0}),
355 .mx_sel (do_nor[3:0]),
356 .di_reg (do_inv[3:0]),
357 .wt_ena (do_mux[3:0]),
358 .rst ({reset,reset,reset,reset}),
359 .si (1'h0),
360 .se (1'h0),
361 .clk (clk),
362 .do_nad (do_nad[3:0]),
363 .do_nor (do_nor[3:0]),
364 .do_inv (do_inv[3:0]),
365 .do_mux (do_mux[3:0]),
366 .do_q (do_q[3:0]),
367 .so (so)
368 );
369`endif
370
371
372niu_rdmc_chnl_pio_if niu_rdmc_chnl_pio_if0 (
373 .clk (clk),
374 .reset (reset),
375 .dma_chnl_grp_id (dma_chnl_grp_id),
376 .pio_32b_mode (pio_32b_mode),
377 .pio_wen (pio_wen),
378 .pio_addr (pio_addr),
379 .pio_wdata (pio_wdata),
380 .reset_rcr_flush (reset_rcr_flush),
381 .m_bit_en (m_bit_en),
382 .rcr_ctl_stat_word (rcr_ctl_stat_word),
383 .desp_curr_addr (desp_curr_addr),
384 .desp_curr_cnt (desp_curr_cnt),
385 .desp_addr_not_valid (desp_addr_not_valid),
386 .buf_addr_not_valid (buf_addr_not_valid),
387 .rbr_addr_overflow (rbr_addr_overflow),
388 .desp_curr_cnt_overflow (desp_curr_cnt_overflow),
389 .rbr_empty (rbr_empty),
390 .muxed_drop_pkt_r (muxed_drop_pkt_r),
391 .wred_drop_pkt (wred_drop_pkt),
392 .rcr_drop_pkt (rcr_drop_pkt),
393 .rbr_drop_pkt (rbr_drop_pkt),
394 .chnl_sel_buf_en (chnl_sel_buf_en),
395 .rcr_curr_addr (rcr_curr_addr),
396 .rcr_status_a (rcr_status_a),
397 .rcr_addr_not_valid (rcr_addr_not_valid),
398 .mbox_addr_not_valid (mbox_addr_not_valid),
399 .rcr_addr_overflow (rcr_addr_overflow),
400 .rcr_curr_cnt_overflow (rcr_curr_cnt_overflow),
401 .rcr_curr_cnt_underflow (rcr_curr_cnt_underflow),
402 .rcr_pkt_cnt_underflow (rcr_pkt_cnt_underflow),
403 .rcr_idle_cycle (rcr_idle_cycle),
404 .chnl_has_pkt (chnl_has_pkt),
405 .chnl_shadw_parity_err (chnl_shadw_parity_err),
406 .rbr_idle_cycle (rbr_idle_cycle),
407 .chnl_cache_parity_err (chnl_cache_parity_err),
408 .resp_bus_err (resp_bus_err),
409 .resp_bus_err_type (resp_bus_err_type),
410 .rcr_ack_err (rcr_ack_err),
411 .data_err_event (data_err_event),
412 .rdmc_wr_data_dma_num (rdmc_wr_data_dma_num),
413
414 .dma_en (dma_en),
415 .dma_reset (dma_reset),
416 .dma_data_offset (dma_data_offset),
417 .full_header (full_header),
418 .page_valid0 (page_valid0),
419 .addr_mask0 (addr_mask0),
420 .comp_value0 (comp_value0),
421 .relo_value0 (relo_value0),
422 .page_valid1 (page_valid1),
423 .addr_mask1 (addr_mask1),
424 .comp_value1 (comp_value1),
425 .relo_value1 (relo_value1),
426 .dma_fatal_err (dma_fatal_err),
427 .rx_log_page_hdl_reg (rx_log_page_hdl_reg),
428 .dma_func_num (dma_func_num),
429 .rdc_red_param_reg (rdc_red_param_reg),
430 .rbr_cfig_a_reg (rbr_cfig_a_reg),
431 .rbr_cfig_b_reg (rbr_cfig_b_reg),
432 .rbr_kick_reg (rbr_kick_reg),
433 .rcr_cfig_a_reg (rcr_cfig_a_reg),
434 .rcr_cfig_b_reg (rcr_cfig_b_reg),
435 .rx_dma_ctl_stat_reg_s (rx_dma_ctl_stat_reg),
436 .rx_dma_ctl_stat_reg_bit47 (rx_dma_ctl_stat_reg_bit47),
437 .rcr_flush_reg (rcr_flush_reg),
438 .mbox_addr (mbox_addr),
439 .mailbox_data (mailbox_data),
440 .ldf_a (ldf_a),
441 .ldf_b (ldf_b),
442 .rbr_cfig_a_reg_wenu (rbr_cfig_a_reg_wenu),
443 .rbr_cfig_a_reg_wenl (rbr_cfig_a_reg_wenl),
444 .rbr_kick_reg_wen (rbr_kick_reg_wen),
445 .rcr_cfig_a_reg_wenu (rcr_cfig_a_reg_wenu),
446 .rcr_cfig_a_reg_wenl (rcr_cfig_a_reg_wenl),
447 .rx_dma_ctl_stat_reg_wenu (rx_dma_ctl_stat_reg_wenu),
448 .rx_dma_ctl_stat_reg_wenl (rx_dma_ctl_stat_reg_wenl),
449 .pio_rd_gnt (pio_rd_gnt),
450 .chnl_pio_rd_data (chnl_pio_rd_data)
451
452 );
453
454
455niu_rdmc_buf_manager niu_rdmc_buf_manager0 (
456 .clk (clk),
457 .reset (reset),
458 .wred_enable (wred_enable),
459 .random_num (random_num),
460 .dma_chnl_grp_id (dma_chnl_grp_id),
461 .dma_data_offset (dma_data_offset),
462 .full_header (full_header),
463 .dma_en (dma_en),
464 .dma_reset (dma_reset),
465 .page_valid0 (page_valid0),
466 .addr_mask0 (addr_mask0),
467 .comp_value0 (comp_value0),
468 .relo_value0 (relo_value0),
469 .page_valid1 (page_valid1),
470 .addr_mask1 (addr_mask1),
471 .comp_value1 (comp_value1),
472 .relo_value1 (relo_value1),
473 .dma_fatal_err (dma_fatal_err),
474 .rx_log_page_hdl_reg (rx_log_page_hdl_reg),
475 .rdc_red_param_reg (rdc_red_param_reg),
476 .rbr_cfig_a_reg (rbr_cfig_a_reg),
477 .rbr_cfig_b_reg (rbr_cfig_b_reg),
478 .rbr_kick_reg (rbr_kick_reg),
479 .rbr_cfig_a_reg_wenu (rbr_cfig_a_reg_wenu),
480 .rbr_cfig_a_reg_wenl (rbr_cfig_a_reg_wenl),
481 .rbr_kick_reg_wen (rbr_kick_reg_wen),
482 .muxed_pkt_len (muxed_pkt_len),
483 .muxed_rdc_num_r (muxed_rdc_num_r),
484 .muxed_drop_pkt_r (muxed_drop_pkt_r),
485 .muxed_s_event_r (muxed_s_event_r),
486 .sel_buf_en (sel_buf_en),
487 .pkt_req_cnt_e_done_mod (pkt_req_cnt_e_done_mod),
488 .pkt_buf_done (pkt_buf_done),
489 .is_hdr_wr_data (is_hdr_wr_data),
490 .is_jmb1_wr_data (is_jmb1_wr_data),
491 .fetch_desp_req_sm (fetch_desp_req_sm),
492 .fetch_desp_pre_done (fetch_desp_pre_done),
493 .fetch_desp_done (fetch_desp_done),
494 .fetch_desp_resp_vld (fetch_desp_resp_vld),
495 .rdmc_resp_data_valid (rdmc_resp_data_valid),
496 .cache_start_addr (cache_start_addr),
497 .cache_end_addr (cache_end_addr),
498 .cache_buf_rd_gnt (cache_buf_rd_gnt),
499 .cache_buf_rd_data (cache_buf_rd_data),
500 .cache_parity_err (cache_parity_err),
501 .rcr_curr_qlen (rcr_curr_qlen),
502 .shadw_curr_space_cnt (shadw_curr_space_cnt),
503
504 .chnl_sel_buf_en_r (chnl_sel_buf_en_r),
505 .desp_init_valid (desp_init_valid),
506 .fetch_desp_trig (fetch_desp_trig),
507 .fetch_desp_addr (fetch_desp_addr),
508 .fetch_desp_num (fetch_desp_num),
509 .cache_read_req (cache_read_req),
510 .cache_rd_ptr (cache_rd_ptr),
511 .cache_wr_ptr (cache_wr_ptr),
512 .drop_pkt (drop_pkt),
513 .pkt_buf_gnt (pkt_buf_gnt),
514 .pkt_buf_size (pkt_buf_size),
515 .pkt_buf_addr (pkt_buf_addr),
516 .orig_buf_addr (orig_buf_addr),
517 .pref_buf_used_num (pref_buf_used_num),
518 .pkt_trans_len (pkt_trans_len),
519 .desp_curr_addr (desp_curr_addr),
520 .desp_curr_cnt (desp_curr_cnt),
521 .desp_addr_not_valid (desp_addr_not_valid),
522 .buf_addr_not_valid (buf_addr_not_valid),
523 .rbr_addr_overflow (rbr_addr_overflow),
524 .desp_curr_cnt_overflow (desp_curr_cnt_overflow),
525 .rbr_empty (rbr_empty),
526 .wred_drop_pkt (wred_drop_pkt),
527 .rcr_drop_pkt (rcr_drop_pkt),
528 .rbr_drop_pkt (rbr_drop_pkt),
529 .chnl_sel_buf_en (chnl_sel_buf_en),
530 .chnl_cache_parity_err (chnl_cache_parity_err)
531
532 );
533
534
535niu_rdmc_fetch_desp_sm niu_rdmc_fetch_desp_sm0 (
536 .clk (clk),
537 .reset (reset),
538 .dma_chnl_grp_id (dma_chnl_grp_id),
539 .dma_reset (dma_reset),
540 .dma_fatal_err (dma_fatal_err),
541 .desp_init_valid (desp_init_valid),
542 .fetch_desp_trig (fetch_desp_trig),
543 .fetch_desp_num (fetch_desp_num),
544 .fetch_desp_gnt (fetch_desp_gnt),
545 .rdmc_resp_rdy_valid (rdmc_resp_rdy_valid),
546 .rdmc_req_err (rdmc_req_err),
547 .rdmc_resp_cmd (rdmc_resp_cmd),
548 .rdmc_resp_cmd_status (rdmc_resp_cmd_status),
549 .rdmc_resp_data_status (rdmc_resp_data_status),
550 .rdmc_resp_dma_num (rdmc_resp_dma_num),
551 .rdmc_resp_data_valid (rdmc_resp_data_valid),
552 .rdmc_resp_byteenable (rdmc_resp_byteenable),
553 .rdmc_resp_comp (rdmc_resp_comp),
554 .rdmc_resp_trans_comp (rdmc_resp_trans_comp),
555 .resp_data_in_process (resp_data_in_process),
556
557 .fetch_desp_req (fetch_desp_req),
558 .rdmc_resp_accept_sm (rdmc_resp_accept_sm), //use rdmc_resp_accept if timing
559 .fetch_desp_resp_vld (fetch_desp_resp_vld),
560 .fetch_desp_req_sm (fetch_desp_req_sm),
561 .fetch_desp_pre_done (fetch_desp_pre_done),
562 .fetch_desp_done (fetch_desp_done),
563 .resp_bus_err (resp_bus_err),
564 .resp_bus_err_type (resp_bus_err_type),
565 .rbr_idle_cycle (rbr_idle_cycle)
566
567 );
568
569
570niu_rdmc_rcr_manager niu_rdmc_rcr_manager0 (
571 .clk (clk),
572 .reset (reset),
573 .clk_div_value (clk_div_value),
574 .dma_chnl_grp_id (dma_chnl_grp_id),
575 .shadw_start_addr (shadw_start_addr),
576 .shadw_rd_end_addr (shadw_rd_end_addr),
577 .shadw_wr_end_addr (shadw_wr_end_addr),
578 .dma_en (dma_en),
579 .dma_reset (dma_reset),
580 .page_valid0 (page_valid0),
581 .addr_mask0 (addr_mask0),
582 .comp_value0 (comp_value0),
583 .relo_value0 (relo_value0),
584 .page_valid1 (page_valid1),
585 .addr_mask1 (addr_mask1),
586 .comp_value1 (comp_value1),
587 .relo_value1 (relo_value1),
588 .dma_fatal_err (dma_fatal_err),
589 .rx_log_page_hdl_reg (rx_log_page_hdl_reg),
590 .rcr_cfig_a_reg (rcr_cfig_a_reg),
591 .rcr_cfig_b_reg (rcr_cfig_b_reg),
592 .rx_dma_ctl_stat_reg (rx_dma_ctl_stat_reg),
593 .rx_dma_ctl_stat_reg_bit47 (rx_dma_ctl_stat_reg_bit47),
594 .rcr_flush_reg (rcr_flush_reg),
595 .mbox_addr (mbox_addr),
596 .rcr_cfig_a_reg_wenu (rcr_cfig_a_reg_wenu),
597 .rcr_cfig_a_reg_wenl (rcr_cfig_a_reg_wenl),
598 .rx_dma_ctl_stat_reg_wenu (rx_dma_ctl_stat_reg_wenu),
599 .rx_dma_ctl_stat_reg_wenl (rx_dma_ctl_stat_reg_wenl),
600 .chnl_sel_buf_en_r (chnl_sel_buf_en_r), //from niu_rdmc_buf_manager.v
601 .pref_buf_used_num (pref_buf_used_num), //up to three for jumbo pkts
602 .wr_transfer_comp_int (wr_transfer_comp_int),
603 .wr_last_pkt_data (wr_last_pkt_data),
604 .update_rcr_shadw (update_rcr_shadw), //from niu_rdmc_wr_sched.v
605 .rdmc_wr_data_dma_num (rdmc_wr_data_dma_num),
606 .rcr_wrbk_gnt (rcr_wrbk_gnt),
607 .rcr_wrbk_done (rcr_wrbk_done),
608 .rcr_wrbk_pkt_num (rcr_wrbk_pkt_num),
609 .rdmc_rcr_ack_valid (rdmc_rcr_ack_valid),
610 .rdmc_rcr_ack_err (rdmc_rcr_ack_err),
611 .rdmc_rcr_ack_dma_num (rdmc_rcr_ack_dma_num),
612 .shadw_parity_err (shadw_parity_err),
613
614 .shadw_wr_en (shadw_wr_en),
615 .shadw_wr_even (shadw_wr_even),
616 .shadw_wr_ptr (shadw_wr_ptr),
617 .shadw_rd_ptr (shadw_rd_ptr),
618 .rcr_wrbk_req (rcr_wrbk_req),
619 .rcr_wrbk_addr (rcr_wrbk_addr),
620 .rcr_wrbk_numb (rcr_wrbk_numb),
621 .rcr_wrbk_data_type (rcr_wrbk_data_type),
622 .rcr_wrbk_sched (rcr_wrbk_sched),
623 .rcr_ack_accept (rcr_ack_accept),
624 .rcr_curr_qlen (rcr_curr_qlen),
625 .shadw_curr_space_cnt (shadw_curr_space_cnt),
626 .reset_rcr_flush (reset_rcr_flush),
627 .m_bit_en (m_bit_en),
628 .rcr_ctl_stat_word (rcr_ctl_stat_word),
629 .rcr_curr_addr (rcr_curr_addr),
630 .rcr_status_a (rcr_status_a),
631 .rcr_addr_not_valid (rcr_addr_not_valid),
632 .mbox_addr_not_valid (mbox_addr_not_valid),
633 .rcr_addr_overflow (rcr_addr_overflow),
634 .rcr_curr_cnt_overflow (rcr_curr_cnt_overflow),
635 .rcr_curr_cnt_underflow (rcr_curr_cnt_underflow),
636 .rcr_pkt_cnt_underflow (rcr_pkt_cnt_underflow),
637 .rcr_idle_cycle (rcr_idle_cycle),
638 .chnl_has_pkt (chnl_has_pkt),
639 .rcr_ack_err (rcr_ack_err),
640 .chnl_shadw_parity_err (chnl_shadw_parity_err)
641
642 );
643
644
645endmodule
646
647
648
649
Full OpenSPARC design & verification tarball including full HDL.