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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_rdmc_rcr_acc_ctrl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module niu_rdmc_rcr_acc_ctrl ( | |
36 | clk, | |
37 | reset, | |
38 | rx_addr_32b_mode, | |
39 | rcr_ack_accept, | |
40 | rcr_wrbk_req, | |
41 | rcr_wrbk_data_type, | |
42 | rcr_wrbk_addr0, | |
43 | rcr_wrbk_addr1, | |
44 | rcr_wrbk_addr2, | |
45 | rcr_wrbk_addr3, | |
46 | rcr_wrbk_addr4, | |
47 | rcr_wrbk_addr5, | |
48 | rcr_wrbk_addr6, | |
49 | rcr_wrbk_addr7, | |
50 | rcr_wrbk_addr8, | |
51 | rcr_wrbk_addr9, | |
52 | rcr_wrbk_addr10, | |
53 | rcr_wrbk_addr11, | |
54 | rcr_wrbk_addr12, | |
55 | rcr_wrbk_addr13, | |
56 | rcr_wrbk_addr14, | |
57 | rcr_wrbk_addr15, | |
58 | rcr_wrbk_numb0, | |
59 | rcr_wrbk_numb1, | |
60 | rcr_wrbk_numb2, | |
61 | rcr_wrbk_numb3, | |
62 | rcr_wrbk_numb4, | |
63 | rcr_wrbk_numb5, | |
64 | rcr_wrbk_numb6, | |
65 | rcr_wrbk_numb7, | |
66 | rcr_wrbk_numb8, | |
67 | rcr_wrbk_numb9, | |
68 | rcr_wrbk_numb10, | |
69 | rcr_wrbk_numb11, | |
70 | rcr_wrbk_numb12, | |
71 | rcr_wrbk_numb13, | |
72 | rcr_wrbk_numb14, | |
73 | rcr_wrbk_numb15, | |
74 | dma_func_num0, | |
75 | dma_func_num1, | |
76 | dma_func_num2, | |
77 | dma_func_num3, | |
78 | dma_func_num4, | |
79 | dma_func_num5, | |
80 | dma_func_num6, | |
81 | dma_func_num7, | |
82 | dma_func_num8, | |
83 | dma_func_num9, | |
84 | dma_func_num10, | |
85 | dma_func_num11, | |
86 | dma_func_num12, | |
87 | dma_func_num13, | |
88 | dma_func_num14, | |
89 | dma_func_num15, | |
90 | shadw_rd_data, | |
91 | mailbox_data0, | |
92 | mailbox_data1, | |
93 | mailbox_data2, | |
94 | mailbox_data3, | |
95 | mailbox_data4, | |
96 | mailbox_data5, | |
97 | mailbox_data6, | |
98 | mailbox_data7, | |
99 | mailbox_data8, | |
100 | mailbox_data9, | |
101 | mailbox_data10, | |
102 | mailbox_data11, | |
103 | mailbox_data12, | |
104 | mailbox_data13, | |
105 | mailbox_data14, | |
106 | mailbox_data15, | |
107 | meta0_rdmc_rcr_req_accept, | |
108 | meta0_rdmc_rcr_data_req, | |
109 | meta0_rdmc_rcr_ack_ready, | |
110 | meta0_rdmc_rcr_ack_cmd, | |
111 | meta0_rdmc_rcr_ack_cmd_status, | |
112 | meta0_rdmc_rcr_ack_client, | |
113 | meta0_rdmc_rcr_ack_dma_num, | |
114 | muxed_shadw_rd_strobe_r, | |
115 | //output | |
116 | ||
117 | rcr_wrbk_gnt, | |
118 | rcr_wrbk_done, | |
119 | rcr_wrbk_pkt_num, | |
120 | rdmc_rcr_req_accept, | |
121 | rdmc_rcr_ack_valid, | |
122 | rdmc_rcr_ack_err, | |
123 | rdmc_rcr_ack_dma_num, | |
124 | shadw_rd_strobe, | |
125 | shadw_rd_data_reg, | |
126 | rdmc_meta0_rcr_req, | |
127 | rdmc_meta0_rcr_req_cmd, | |
128 | rdmc_meta0_rcr_req_address, | |
129 | rdmc_meta0_rcr_req_length, | |
130 | rdmc_meta0_rcr_req_port_num, | |
131 | rdmc_meta0_rcr_req_dma_num, | |
132 | rdmc_meta0_rcr_req_func_num, | |
133 | ||
134 | rdmc_meta0_rcr_data_valid, | |
135 | rdmc_meta0_rcr_data, | |
136 | rdmc_meta0_rcr_req_byteenable, | |
137 | rdmc_meta0_rcr_transfer_comp, | |
138 | rdmc_meta0_rcr_status, | |
139 | rdmc_meta0_rcr_ack_accept | |
140 | ||
141 | ); | |
142 | ||
143 | input clk; | |
144 | input reset; | |
145 | input rx_addr_32b_mode; | |
146 | input[15:0] rcr_ack_accept; | |
147 | input[15:0] rcr_wrbk_req; | |
148 | input[15:0] rcr_wrbk_data_type; | |
149 | input[63:0] rcr_wrbk_addr0; | |
150 | input[63:0] rcr_wrbk_addr1; | |
151 | input[63:0] rcr_wrbk_addr2; | |
152 | input[63:0] rcr_wrbk_addr3; | |
153 | input[63:0] rcr_wrbk_addr4; | |
154 | input[63:0] rcr_wrbk_addr5; | |
155 | input[63:0] rcr_wrbk_addr6; | |
156 | input[63:0] rcr_wrbk_addr7; | |
157 | input[63:0] rcr_wrbk_addr8; | |
158 | input[63:0] rcr_wrbk_addr9; | |
159 | input[63:0] rcr_wrbk_addr10; | |
160 | input[63:0] rcr_wrbk_addr11; | |
161 | input[63:0] rcr_wrbk_addr12; | |
162 | input[63:0] rcr_wrbk_addr13; | |
163 | input[63:0] rcr_wrbk_addr14; | |
164 | input[63:0] rcr_wrbk_addr15; | |
165 | input[3:0] rcr_wrbk_numb0; | |
166 | input[3:0] rcr_wrbk_numb1; | |
167 | input[3:0] rcr_wrbk_numb2; | |
168 | input[3:0] rcr_wrbk_numb3; | |
169 | input[3:0] rcr_wrbk_numb4; | |
170 | input[3:0] rcr_wrbk_numb5; | |
171 | input[3:0] rcr_wrbk_numb6; | |
172 | input[3:0] rcr_wrbk_numb7; | |
173 | input[3:0] rcr_wrbk_numb8; | |
174 | input[3:0] rcr_wrbk_numb9; | |
175 | input[3:0] rcr_wrbk_numb10; | |
176 | input[3:0] rcr_wrbk_numb11; | |
177 | input[3:0] rcr_wrbk_numb12; | |
178 | input[3:0] rcr_wrbk_numb13; | |
179 | input[3:0] rcr_wrbk_numb14; | |
180 | input[3:0] rcr_wrbk_numb15; | |
181 | input[1:0] dma_func_num0; | |
182 | input[1:0] dma_func_num1; | |
183 | input[1:0] dma_func_num2; | |
184 | input[1:0] dma_func_num3; | |
185 | input[1:0] dma_func_num4; | |
186 | input[1:0] dma_func_num5; | |
187 | input[1:0] dma_func_num6; | |
188 | input[1:0] dma_func_num7; | |
189 | input[1:0] dma_func_num8; | |
190 | input[1:0] dma_func_num9; | |
191 | input[1:0] dma_func_num10; | |
192 | input[1:0] dma_func_num11; | |
193 | input[1:0] dma_func_num12; | |
194 | input[1:0] dma_func_num13; | |
195 | input[1:0] dma_func_num14; | |
196 | input[1:0] dma_func_num15; | |
197 | input[147:0] shadw_rd_data; | |
198 | input[168:0] mailbox_data0; | |
199 | input[168:0] mailbox_data1; | |
200 | input[168:0] mailbox_data2; | |
201 | input[168:0] mailbox_data3; | |
202 | input[168:0] mailbox_data4; | |
203 | input[168:0] mailbox_data5; | |
204 | input[168:0] mailbox_data6; | |
205 | input[168:0] mailbox_data7; | |
206 | input[168:0] mailbox_data8; | |
207 | input[168:0] mailbox_data9; | |
208 | input[168:0] mailbox_data10; | |
209 | input[168:0] mailbox_data11; | |
210 | input[168:0] mailbox_data12; | |
211 | input[168:0] mailbox_data13; | |
212 | input[168:0] mailbox_data14; | |
213 | input[168:0] mailbox_data15; | |
214 | input meta0_rdmc_rcr_req_accept; | |
215 | input meta0_rdmc_rcr_data_req; | |
216 | input meta0_rdmc_rcr_ack_ready; | |
217 | input[7:0] meta0_rdmc_rcr_ack_cmd; | |
218 | input[3:0] meta0_rdmc_rcr_ack_cmd_status; | |
219 | input meta0_rdmc_rcr_ack_client; | |
220 | input[4:0] meta0_rdmc_rcr_ack_dma_num; | |
221 | input muxed_shadw_rd_strobe_r; | |
222 | ||
223 | output[15:0] rcr_wrbk_gnt; | |
224 | output rcr_wrbk_done; | |
225 | output[3:0] rcr_wrbk_pkt_num; | |
226 | output rdmc_rcr_req_accept; | |
227 | output rdmc_rcr_ack_valid; | |
228 | output rdmc_rcr_ack_err; | |
229 | output[4:0] rdmc_rcr_ack_dma_num; | |
230 | output shadw_rd_strobe; | |
231 | output[147:0] shadw_rd_data_reg; | |
232 | output rdmc_meta0_rcr_req; | |
233 | output[7:0] rdmc_meta0_rcr_req_cmd; | |
234 | output[63:0] rdmc_meta0_rcr_req_address; | |
235 | output[13:0] rdmc_meta0_rcr_req_length; | |
236 | output[1:0] rdmc_meta0_rcr_req_port_num; | |
237 | output[4:0] rdmc_meta0_rcr_req_dma_num; | |
238 | output[1:0] rdmc_meta0_rcr_req_func_num; | |
239 | ||
240 | output rdmc_meta0_rcr_data_valid; | |
241 | output[127:0] rdmc_meta0_rcr_data; | |
242 | output[15:0] rdmc_meta0_rcr_req_byteenable; | |
243 | output rdmc_meta0_rcr_transfer_comp; | |
244 | output[3:0] rdmc_meta0_rcr_status; | |
245 | output rdmc_meta0_rcr_ack_accept; | |
246 | ||
247 | ||
248 | reg rdmc_meta0_rcr_req; | |
249 | reg[7:0] rdmc_meta0_rcr_req_cmd; | |
250 | reg[63:0] rdmc_meta0_rcr_req_address; | |
251 | reg[3:0] rdmc_meta0_rcr_req_dma_num_i; | |
252 | reg[1:0] rdmc_meta0_rcr_req_func_num; | |
253 | ||
254 | reg rdmc_meta0_rcr_data_valid; | |
255 | reg[127:0] rdmc_meta0_rcr_data; | |
256 | reg rdmc_meta0_rcr_transfer_comp; | |
257 | ||
258 | reg rdmc_rcr_req_accept; | |
259 | reg rdmc_rcr_data_req; | |
260 | reg rdmc_rcr_ack_ready; | |
261 | reg[7:0] rdmc_rcr_ack_cmd; | |
262 | reg[3:0] rdmc_rcr_ack_cmd_status; | |
263 | reg rdmc_rcr_ack_client; | |
264 | reg[4:0] rdmc_rcr_ack_dma_num; | |
265 | reg rdmc_meta0_rcr_ack_accept; | |
266 | ||
267 | reg stage0_en; | |
268 | reg stage1_en; | |
269 | reg data_valid_sm; | |
270 | reg rcr_wrbk_done_sm; | |
271 | reg data_cycle0_sm; | |
272 | reg data_cycle1_sm; | |
273 | reg data_cycle2_sm; | |
274 | reg stage0_en_r; | |
275 | reg stage1_en_r; | |
276 | reg data_valid_sm_r; | |
277 | reg rcr_wrbk_done; | |
278 | reg data_cycle0; | |
279 | reg data_cycle1; | |
280 | reg data_cycle2; | |
281 | reg[2:0] state; | |
282 | reg[2:0] next_state; | |
283 | ||
284 | reg[15:0] token; | |
285 | reg[15:0] start_mask_slide_r; | |
286 | reg[15:0] rcr_wrbk_gnt; | |
287 | reg[15:0] rcr_wrbk_gnt_r; | |
288 | ||
289 | reg[3:0] wrbk_addr_cnt; | |
290 | reg[3:0] rcr_wrbk_pkt_num; | |
291 | ||
292 | reg rcr_wrbk_type; | |
293 | reg[168:0] mailbox_data_tmp_r; | |
294 | ||
295 | reg[147:0] shadw_rd_data_reg; | |
296 | ||
297 | reg[3:0] rcr_wrbk_numb_tmp_r; | |
298 | reg[3:0] rcr_wrbk_numb_sub; | |
299 | reg[3:0] data_valid_cnt; | |
300 | reg data_valid_cnt_done_r; | |
301 | reg shadw_rd_strobe_r; | |
302 | ||
303 | ||
304 | wire[15:0] start_mask = 16'h1111; | |
305 | wire[3:0] start_slide_num; | |
306 | wire[15:0] start_mask_slide; | |
307 | wire is_req = |rcr_wrbk_req; | |
308 | wire[15:0] right_req; | |
309 | wire[15:0] left_req; | |
310 | wire sel_left; | |
311 | wire[15:0] req_tmp; | |
312 | wire[15:0] pre_rcr_wrbk_gnt; | |
313 | wire[3:0] rcr_wrbk_gnt_dec; | |
314 | ||
315 | wire inc_wrbk_pkt_num2; | |
316 | wire inc_wrbk_pkt_num1; | |
317 | wire[3:0] wrbk_pkt_num_tmp2; | |
318 | wire[3:0] wrbk_pkt_num_tmp1; | |
319 | ||
320 | parameter | |
321 | ||
322 | RCR_ARB = 3'd0, | |
323 | RCR_GNT = 3'd1, | |
324 | RCR_REQ = 3'd2, | |
325 | RCR_WR_DATA_RDY = 3'd3, | |
326 | RCR_WR_DATA1 = 3'd4, | |
327 | RCR_WR_DATA2 = 3'd5, | |
328 | RCR_WR_DATA3 = 3'd6, | |
329 | RCR_DATA_COMP = 3'd7; | |
330 | ||
331 | always @ (state or is_req or rdmc_rcr_req_accept or rdmc_rcr_data_req) | |
332 | begin | |
333 | stage0_en = 1'b0; | |
334 | stage1_en = 1'b0; | |
335 | data_valid_sm = 1'b0; | |
336 | rcr_wrbk_done_sm= 1'b0; | |
337 | data_cycle0_sm = 1'b0; | |
338 | data_cycle1_sm = 1'b0; | |
339 | data_cycle2_sm = 1'b0; | |
340 | ||
341 | ||
342 | case (state) //synopsys parallel_case full_case | |
343 | ||
344 | RCR_ARB: | |
345 | begin | |
346 | if (is_req) | |
347 | begin | |
348 | stage0_en = 1'b1; | |
349 | next_state = RCR_GNT; | |
350 | end | |
351 | else | |
352 | next_state = state; | |
353 | end | |
354 | ||
355 | RCR_GNT: | |
356 | begin | |
357 | stage1_en = 1'b1; | |
358 | next_state = RCR_REQ; | |
359 | end | |
360 | ||
361 | RCR_REQ: | |
362 | begin | |
363 | if (rdmc_rcr_req_accept) | |
364 | next_state = RCR_WR_DATA_RDY; | |
365 | else | |
366 | next_state = state; | |
367 | end | |
368 | ||
369 | RCR_WR_DATA_RDY: | |
370 | begin | |
371 | if (rdmc_rcr_data_req) | |
372 | begin | |
373 | data_valid_sm = 1'b1; | |
374 | data_cycle0_sm = 1'b1; | |
375 | next_state = RCR_WR_DATA1; | |
376 | end | |
377 | else | |
378 | next_state = state; | |
379 | end | |
380 | ||
381 | RCR_WR_DATA1: | |
382 | begin | |
383 | if (rdmc_rcr_data_req) | |
384 | begin | |
385 | data_valid_sm = 1'b1; | |
386 | data_cycle1_sm = 1'b1; | |
387 | next_state = RCR_WR_DATA2; | |
388 | end | |
389 | else | |
390 | next_state = state; | |
391 | end | |
392 | ||
393 | RCR_WR_DATA2: | |
394 | begin | |
395 | if (rdmc_rcr_data_req) | |
396 | begin | |
397 | data_valid_sm = 1'b1; | |
398 | data_cycle2_sm = 1'b1; | |
399 | next_state = RCR_WR_DATA3; | |
400 | end | |
401 | else | |
402 | next_state = state; | |
403 | end | |
404 | ||
405 | RCR_WR_DATA3: | |
406 | begin | |
407 | if (rdmc_rcr_data_req) | |
408 | begin | |
409 | data_valid_sm = 1'b1; | |
410 | rcr_wrbk_done_sm= 1'b1; | |
411 | next_state = RCR_DATA_COMP; | |
412 | end | |
413 | else | |
414 | next_state = state; | |
415 | end | |
416 | ||
417 | RCR_DATA_COMP: | |
418 | next_state = RCR_ARB; | |
419 | ||
420 | default: next_state = RCR_ARB; | |
421 | ||
422 | endcase | |
423 | end | |
424 | ||
425 | always @ (posedge clk) | |
426 | if (reset) | |
427 | state <= 3'b0; | |
428 | else | |
429 | state <= next_state; | |
430 | ||
431 | ||
432 | ||
433 | /**********************/ | |
434 | //Arbiter | |
435 | /**********************/ | |
436 | niu_rdmc_encode_32 encode_32_inst_a ( | |
437 | .din (token), | |
438 | .dout (start_slide_num) | |
439 | ); | |
440 | ||
441 | niu_rdmc_barrel_shl_32 barrel_shl_32_inst_a ( | |
442 | .din (start_mask), | |
443 | .shift (start_slide_num), | |
444 | .dout (start_mask_slide) | |
445 | ); | |
446 | ||
447 | assign right_req = rcr_wrbk_req & ~start_mask_slide_r; | |
448 | assign left_req = rcr_wrbk_req & start_mask_slide_r; | |
449 | ||
450 | assign sel_left = !(left_req == 16'b0); | |
451 | assign req_tmp = sel_left ? left_req : right_req; | |
452 | ||
453 | niu_rdmc_pri_encode_32 pri_encode_32_inst_a ( | |
454 | .din (req_tmp), | |
455 | .dout (pre_rcr_wrbk_gnt) | |
456 | ); | |
457 | ||
458 | always @ (posedge clk) | |
459 | if (reset) | |
460 | token <= 16'h0001; | |
461 | else if (stage0_en) | |
462 | token <= {token[14:0], token[15]}; | |
463 | else | |
464 | token <= token; | |
465 | ||
466 | always @ (posedge clk) | |
467 | if (reset) | |
468 | start_mask_slide_r <= 16'b0; | |
469 | else | |
470 | start_mask_slide_r <= start_mask_slide; | |
471 | ||
472 | always @ (posedge clk) | |
473 | if (reset) | |
474 | rcr_wrbk_gnt <= 16'h0; | |
475 | else if (stage0_en) | |
476 | rcr_wrbk_gnt <= pre_rcr_wrbk_gnt; | |
477 | else if (rdmc_rcr_req_accept) | |
478 | rcr_wrbk_gnt <= 16'h0; | |
479 | else | |
480 | rcr_wrbk_gnt <= rcr_wrbk_gnt; | |
481 | ||
482 | always @ (posedge clk) | |
483 | if (reset) | |
484 | rcr_wrbk_gnt_r <= 16'b0; | |
485 | else | |
486 | rcr_wrbk_gnt_r <= rcr_wrbk_gnt; | |
487 | ||
488 | ||
489 | wire[63:0] rcr_wrbk_addr_tmp = {64{rcr_wrbk_gnt[0]}} & rcr_wrbk_addr0 | | |
490 | {64{rcr_wrbk_gnt[1]}} & rcr_wrbk_addr1 | | |
491 | {64{rcr_wrbk_gnt[2]}} & rcr_wrbk_addr2 | | |
492 | {64{rcr_wrbk_gnt[3]}} & rcr_wrbk_addr3 | | |
493 | {64{rcr_wrbk_gnt[4]}} & rcr_wrbk_addr4 | | |
494 | {64{rcr_wrbk_gnt[5]}} & rcr_wrbk_addr5 | | |
495 | {64{rcr_wrbk_gnt[6]}} & rcr_wrbk_addr6 | | |
496 | {64{rcr_wrbk_gnt[7]}} & rcr_wrbk_addr7 | | |
497 | {64{rcr_wrbk_gnt[8]}} & rcr_wrbk_addr8 | | |
498 | {64{rcr_wrbk_gnt[9]}} & rcr_wrbk_addr9 | | |
499 | {64{rcr_wrbk_gnt[10]}} & rcr_wrbk_addr10 | | |
500 | {64{rcr_wrbk_gnt[11]}} & rcr_wrbk_addr11 | | |
501 | {64{rcr_wrbk_gnt[12]}} & rcr_wrbk_addr12 | | |
502 | {64{rcr_wrbk_gnt[13]}} & rcr_wrbk_addr13 | | |
503 | {64{rcr_wrbk_gnt[14]}} & rcr_wrbk_addr14 | | |
504 | {64{rcr_wrbk_gnt[15]}} & rcr_wrbk_addr15; | |
505 | ||
506 | wire[3:0] rcr_wrbk_numb_tmp = {4{rcr_wrbk_gnt[0]}} & rcr_wrbk_numb0 | | |
507 | {4{rcr_wrbk_gnt[1]}} & rcr_wrbk_numb1 | | |
508 | {4{rcr_wrbk_gnt[2]}} & rcr_wrbk_numb2 | | |
509 | {4{rcr_wrbk_gnt[3]}} & rcr_wrbk_numb3 | | |
510 | {4{rcr_wrbk_gnt[4]}} & rcr_wrbk_numb4 | | |
511 | {4{rcr_wrbk_gnt[5]}} & rcr_wrbk_numb5 | | |
512 | {4{rcr_wrbk_gnt[6]}} & rcr_wrbk_numb6 | | |
513 | {4{rcr_wrbk_gnt[7]}} & rcr_wrbk_numb7 | | |
514 | {4{rcr_wrbk_gnt[8]}} & rcr_wrbk_numb8 | | |
515 | {4{rcr_wrbk_gnt[9]}} & rcr_wrbk_numb9 | | |
516 | {4{rcr_wrbk_gnt[10]}} & rcr_wrbk_numb10 | | |
517 | {4{rcr_wrbk_gnt[11]}} & rcr_wrbk_numb11 | | |
518 | {4{rcr_wrbk_gnt[12]}} & rcr_wrbk_numb12 | | |
519 | {4{rcr_wrbk_gnt[13]}} & rcr_wrbk_numb13 | | |
520 | {4{rcr_wrbk_gnt[14]}} & rcr_wrbk_numb14 | | |
521 | {4{rcr_wrbk_gnt[15]}} & rcr_wrbk_numb15; | |
522 | ||
523 | wire[1:0] dma_func_num_tmp = {2{rcr_wrbk_gnt[0]}} & dma_func_num0 | | |
524 | {2{rcr_wrbk_gnt[1]}} & dma_func_num1 | | |
525 | {2{rcr_wrbk_gnt[2]}} & dma_func_num2 | | |
526 | {2{rcr_wrbk_gnt[3]}} & dma_func_num3 | | |
527 | {2{rcr_wrbk_gnt[4]}} & dma_func_num4 | | |
528 | {2{rcr_wrbk_gnt[5]}} & dma_func_num5 | | |
529 | {2{rcr_wrbk_gnt[6]}} & dma_func_num6 | | |
530 | {2{rcr_wrbk_gnt[7]}} & dma_func_num7 | | |
531 | {2{rcr_wrbk_gnt[8]}} & dma_func_num8 | | |
532 | {2{rcr_wrbk_gnt[9]}} & dma_func_num9 | | |
533 | {2{rcr_wrbk_gnt[10]}} & dma_func_num10 | | |
534 | {2{rcr_wrbk_gnt[11]}} & dma_func_num11 | | |
535 | {2{rcr_wrbk_gnt[12]}} & dma_func_num12 | | |
536 | {2{rcr_wrbk_gnt[13]}} & dma_func_num13 | | |
537 | {2{rcr_wrbk_gnt[14]}} & dma_func_num14 | | |
538 | {2{rcr_wrbk_gnt[15]}} & dma_func_num15; | |
539 | ||
540 | wire[168:0] mailbox_data_tmp = {169{rcr_wrbk_gnt_r[0]}} & mailbox_data0 | | |
541 | {169{rcr_wrbk_gnt_r[1]}} & mailbox_data1 | | |
542 | {169{rcr_wrbk_gnt_r[2]}} & mailbox_data2 | | |
543 | {169{rcr_wrbk_gnt_r[3]}} & mailbox_data3 | | |
544 | {169{rcr_wrbk_gnt_r[4]}} & mailbox_data4 | | |
545 | {169{rcr_wrbk_gnt_r[5]}} & mailbox_data5 | | |
546 | {169{rcr_wrbk_gnt_r[6]}} & mailbox_data6 | | |
547 | {169{rcr_wrbk_gnt_r[7]}} & mailbox_data7 | | |
548 | {169{rcr_wrbk_gnt_r[8]}} & mailbox_data8 | | |
549 | {169{rcr_wrbk_gnt_r[9]}} & mailbox_data9 | | |
550 | {169{rcr_wrbk_gnt_r[10]}} & mailbox_data10 | | |
551 | {169{rcr_wrbk_gnt_r[11]}} & mailbox_data11 | | |
552 | {169{rcr_wrbk_gnt_r[12]}} & mailbox_data12 | | |
553 | {169{rcr_wrbk_gnt_r[13]}} & mailbox_data13 | | |
554 | {169{rcr_wrbk_gnt_r[14]}} & mailbox_data14 | | |
555 | {169{rcr_wrbk_gnt_r[15]}} & mailbox_data15; | |
556 | ||
557 | wire rcr_wrbk_type_tmp = |(rcr_wrbk_gnt & rcr_wrbk_data_type); | |
558 | ||
559 | niu_rdmc_encode_32 encode_32_inst_b ( | |
560 | .din (rcr_wrbk_gnt), | |
561 | .dout (rcr_wrbk_gnt_dec) | |
562 | ); | |
563 | ||
564 | always @ (posedge clk) | |
565 | if (reset) | |
566 | rcr_wrbk_type <= 1'b0; | |
567 | else if (stage1_en) | |
568 | rcr_wrbk_type <= rcr_wrbk_type_tmp; | |
569 | else | |
570 | rcr_wrbk_type <= rcr_wrbk_type; | |
571 | ||
572 | always @ (posedge clk) | |
573 | if (reset) | |
574 | mailbox_data_tmp_r <= 169'b0; | |
575 | else if (stage1_en_r) | |
576 | mailbox_data_tmp_r <= mailbox_data_tmp; | |
577 | else | |
578 | mailbox_data_tmp_r <= mailbox_data_tmp_r; | |
579 | ||
580 | always @ (posedge clk) | |
581 | if (reset) | |
582 | shadw_rd_data_reg <= 148'b0; | |
583 | else if (muxed_shadw_rd_strobe_r) | |
584 | shadw_rd_data_reg <= shadw_rd_data; | |
585 | else | |
586 | shadw_rd_data_reg <= shadw_rd_data_reg; | |
587 | ||
588 | wire[511:0] mailbox_data_tmp_r1 = {128'b0, | |
589 | 48'b0, mailbox_data_tmp_r[168:153], | |
590 | 20'b0, mailbox_data_tmp_r[152:112], 3'b0, | |
591 | 64'b0, | |
592 | 20'b0, mailbox_data_tmp_r[111:70], 2'b0, | |
593 | 48'b0, mailbox_data_tmp_r[69:54], | |
594 | 10'b0, mailbox_data_tmp_r[53:0]}; | |
595 | ||
596 | wire[127:0] mailbox_data_out = (data_cycle0) ? mailbox_data_tmp_r1[127:0] : | |
597 | (data_cycle1) ? mailbox_data_tmp_r1[255:128] : | |
598 | (data_cycle2) ? mailbox_data_tmp_r1[383:256] : | |
599 | mailbox_data_tmp_r1[511:384]; | |
600 | ||
601 | wire[127:0] rdmc_meta0_rcr_data_tmp = rcr_wrbk_type & shadw_rd_strobe_r ? shadw_rd_data[127:0] : | |
602 | rcr_wrbk_type ? 128'b0 : | |
603 | mailbox_data_out; | |
604 | ||
605 | wire shadw_rd_strobe = rcr_wrbk_type & rdmc_rcr_data_req & !data_valid_cnt_done_r; | |
606 | ||
607 | ||
608 | /**********************************************/ | |
609 | //Write Request Interface | |
610 | /**********************************************/ | |
611 | wire[4:0] rdmc_meta0_rcr_req_dma_num = {1'b0, rdmc_meta0_rcr_req_dma_num_i}; | |
612 | wire[1:0] rdmc_meta0_rcr_req_port_num = 2'b00; | |
613 | wire[13:0] rdmc_meta0_rcr_req_length = 14'd64; | |
614 | ||
615 | always @ (posedge clk) | |
616 | if (reset) | |
617 | rdmc_meta0_rcr_req <= 1'b0; | |
618 | else if (meta0_rdmc_rcr_req_accept) | |
619 | rdmc_meta0_rcr_req <= 1'b0; | |
620 | else if (stage1_en) | |
621 | rdmc_meta0_rcr_req <= 1'b1; | |
622 | else | |
623 | rdmc_meta0_rcr_req <= rdmc_meta0_rcr_req; | |
624 | ||
625 | always @ (posedge clk) | |
626 | if (reset) | |
627 | rdmc_meta0_rcr_req_cmd <= 8'b0; | |
628 | else if (stage1_en & rx_addr_32b_mode) | |
629 | rdmc_meta0_rcr_req_cmd <= 8'b0001_0001; | |
630 | else if (stage1_en) | |
631 | rdmc_meta0_rcr_req_cmd <= 8'b0001_1001; // hardwired to 64 bit addressing | |
632 | else if (rdmc_rcr_req_accept) | |
633 | rdmc_meta0_rcr_req_cmd <= 8'b0; | |
634 | else | |
635 | rdmc_meta0_rcr_req_cmd <= rdmc_meta0_rcr_req_cmd; | |
636 | ||
637 | always @ (posedge clk) | |
638 | if (reset) | |
639 | rdmc_meta0_rcr_req_address <= 64'b0; | |
640 | else if (stage0_en_r & rx_addr_32b_mode) | |
641 | rdmc_meta0_rcr_req_address <= {32'b0, rcr_wrbk_addr_tmp[31:0]}; | |
642 | else if (stage0_en_r) | |
643 | rdmc_meta0_rcr_req_address <= rcr_wrbk_addr_tmp[63:0]; | |
644 | else | |
645 | rdmc_meta0_rcr_req_address <= rdmc_meta0_rcr_req_address; | |
646 | ||
647 | always @ (posedge clk) | |
648 | if (reset) | |
649 | rdmc_meta0_rcr_req_dma_num_i <= 4'b0; | |
650 | else if (stage1_en) | |
651 | rdmc_meta0_rcr_req_dma_num_i <= rcr_wrbk_gnt_dec; | |
652 | else | |
653 | rdmc_meta0_rcr_req_dma_num_i <= rdmc_meta0_rcr_req_dma_num_i; | |
654 | ||
655 | always @ (posedge clk) | |
656 | if (reset) | |
657 | rdmc_meta0_rcr_req_func_num <= 2'b0; | |
658 | else if (stage1_en) | |
659 | rdmc_meta0_rcr_req_func_num <= dma_func_num_tmp[1:0]; | |
660 | else | |
661 | rdmc_meta0_rcr_req_func_num <= rdmc_meta0_rcr_req_func_num; | |
662 | ||
663 | ||
664 | wire[15:0] rdmc_meta0_rcr_req_byteenable = 16'hffff; | |
665 | wire[3:0] rdmc_meta0_rcr_status = 4'b0; | |
666 | ||
667 | always @ (posedge clk) | |
668 | if (reset) | |
669 | rdmc_meta0_rcr_data_valid <= 1'b0; | |
670 | else | |
671 | rdmc_meta0_rcr_data_valid <= data_valid_sm_r; | |
672 | ||
673 | ||
674 | always @ (posedge clk) | |
675 | if (reset) | |
676 | rdmc_meta0_rcr_data <= 128'b0; | |
677 | else if (data_valid_sm_r) | |
678 | rdmc_meta0_rcr_data <= rdmc_meta0_rcr_data_tmp; | |
679 | else | |
680 | rdmc_meta0_rcr_data <= rdmc_meta0_rcr_data; | |
681 | ||
682 | always @ (posedge clk) | |
683 | if (reset) | |
684 | rdmc_meta0_rcr_transfer_comp <= 1'b0; | |
685 | else | |
686 | rdmc_meta0_rcr_transfer_comp <= rcr_wrbk_done; | |
687 | ||
688 | always @ (posedge clk) | |
689 | if (reset) | |
690 | rdmc_meta0_rcr_ack_accept <= 1'b0; | |
691 | else | |
692 | rdmc_meta0_rcr_ack_accept <= |rcr_ack_accept; | |
693 | ||
694 | //Input registers | |
695 | always @ (posedge clk) | |
696 | if (reset) | |
697 | begin | |
698 | rdmc_rcr_req_accept <= 1'b0; | |
699 | rdmc_rcr_data_req <= 1'b0; | |
700 | rdmc_rcr_ack_ready <= 1'b0; | |
701 | rdmc_rcr_ack_cmd <= 8'b0; | |
702 | rdmc_rcr_ack_cmd_status <= 4'b0; | |
703 | rdmc_rcr_ack_client <= 1'b0; | |
704 | rdmc_rcr_ack_dma_num <= 5'b0; | |
705 | end | |
706 | else | |
707 | begin | |
708 | rdmc_rcr_req_accept <= meta0_rdmc_rcr_req_accept; | |
709 | rdmc_rcr_data_req <= meta0_rdmc_rcr_data_req; | |
710 | rdmc_rcr_ack_ready <= meta0_rdmc_rcr_ack_ready; | |
711 | rdmc_rcr_ack_cmd <= meta0_rdmc_rcr_ack_cmd; | |
712 | rdmc_rcr_ack_cmd_status <= meta0_rdmc_rcr_ack_cmd_status; | |
713 | rdmc_rcr_ack_client <= meta0_rdmc_rcr_ack_client; | |
714 | rdmc_rcr_ack_dma_num <= meta0_rdmc_rcr_ack_dma_num; | |
715 | end | |
716 | ||
717 | wire rdmc_rcr_ack_valid = rdmc_rcr_ack_ready & rdmc_rcr_ack_client; | |
718 | wire rdmc_rcr_ack_err = !(rdmc_rcr_ack_cmd[4:0] == 5'b00110) | (rdmc_rcr_ack_cmd_status == 4'b1111); | |
719 | ||
720 | always @ (posedge clk) | |
721 | if (reset) | |
722 | stage0_en_r <= 1'b0; | |
723 | else | |
724 | stage0_en_r <= stage0_en; | |
725 | ||
726 | always @ (posedge clk) | |
727 | if (reset) | |
728 | stage1_en_r <= 1'b0; | |
729 | else | |
730 | stage1_en_r <= stage1_en; | |
731 | ||
732 | always @ (posedge clk) | |
733 | if (reset) | |
734 | begin | |
735 | data_cycle0 <= 1'b0; | |
736 | data_cycle1 <= 1'b0; | |
737 | data_cycle2 <= 1'b0; | |
738 | end | |
739 | else | |
740 | begin | |
741 | data_cycle0 <= data_cycle0_sm; | |
742 | data_cycle1 <= data_cycle1_sm; | |
743 | data_cycle2 <= data_cycle2_sm; | |
744 | end | |
745 | ||
746 | always @ (posedge clk) | |
747 | if (reset) | |
748 | data_valid_sm_r <= 1'b0; | |
749 | else | |
750 | data_valid_sm_r <= data_valid_sm; | |
751 | ||
752 | always @ (posedge clk) | |
753 | if (reset) | |
754 | rcr_wrbk_done <= 1'b0; | |
755 | else | |
756 | rcr_wrbk_done <= rcr_wrbk_done_sm; | |
757 | ||
758 | ||
759 | assign inc_wrbk_pkt_num2 = (|wrbk_addr_cnt[3:1]) & (!rdmc_meta0_rcr_data[127] & !rdmc_meta0_rcr_data[63]); | |
760 | assign inc_wrbk_pkt_num1 = (|wrbk_addr_cnt[3:1]) & (!rdmc_meta0_rcr_data[127] | !rdmc_meta0_rcr_data[63]) | | |
761 | (wrbk_addr_cnt[0] & !rdmc_meta0_rcr_data[63]); | |
762 | assign wrbk_pkt_num_tmp2 = rcr_wrbk_pkt_num + 4'd2; | |
763 | assign wrbk_pkt_num_tmp1 = rcr_wrbk_pkt_num + 4'd1; | |
764 | ||
765 | always @ (posedge clk) | |
766 | if (reset) | |
767 | wrbk_addr_cnt <= 4'b0; | |
768 | else if (stage1_en) | |
769 | wrbk_addr_cnt <= rcr_wrbk_numb_tmp; | |
770 | else if (rdmc_meta0_rcr_data_valid & (wrbk_addr_cnt[3:1] == 3'd0)) | |
771 | wrbk_addr_cnt <= 4'b0; | |
772 | else if (rdmc_meta0_rcr_data_valid) | |
773 | wrbk_addr_cnt <= wrbk_addr_cnt - 4'd2; | |
774 | else | |
775 | wrbk_addr_cnt <= wrbk_addr_cnt; | |
776 | ||
777 | always @ (posedge clk) | |
778 | if (reset) | |
779 | rcr_wrbk_pkt_num <= 4'b0; | |
780 | else if (rdmc_meta0_rcr_data_valid & inc_wrbk_pkt_num2) | |
781 | rcr_wrbk_pkt_num <= wrbk_pkt_num_tmp2; | |
782 | else if (rdmc_meta0_rcr_data_valid & inc_wrbk_pkt_num1) | |
783 | rcr_wrbk_pkt_num <= wrbk_pkt_num_tmp1; | |
784 | else if (rdmc_rcr_req_accept) | |
785 | rcr_wrbk_pkt_num <= 4'b0; | |
786 | else | |
787 | rcr_wrbk_pkt_num <= rcr_wrbk_pkt_num; | |
788 | ||
789 | ||
790 | always @ (posedge clk) | |
791 | if (reset) | |
792 | rcr_wrbk_numb_tmp_r <= 4'b0; | |
793 | else if (stage1_en) | |
794 | rcr_wrbk_numb_tmp_r <= rcr_wrbk_numb_tmp; | |
795 | else if (rcr_wrbk_done) | |
796 | rcr_wrbk_numb_tmp_r <= 4'b0; | |
797 | else | |
798 | rcr_wrbk_numb_tmp_r <= rcr_wrbk_numb_tmp_r; | |
799 | ||
800 | wire[3:0] rcr_wrbk_numb_sub_tmp = (rcr_wrbk_numb_tmp_r > 4'd2) ? (rcr_wrbk_numb_tmp_r - 4'd2) : 4'b0; | |
801 | wire data_valid_cnt_done = (data_valid_cnt >= rcr_wrbk_numb_sub); | |
802 | ||
803 | always @ (posedge clk) | |
804 | if (reset) | |
805 | rcr_wrbk_numb_sub <= 4'b0; | |
806 | else if (rdmc_rcr_req_accept) | |
807 | rcr_wrbk_numb_sub <= rcr_wrbk_numb_sub_tmp; | |
808 | else if (rcr_wrbk_done) | |
809 | rcr_wrbk_numb_sub <= 4'b0; | |
810 | else | |
811 | rcr_wrbk_numb_sub <= rcr_wrbk_numb_sub; | |
812 | ||
813 | ||
814 | always @ (posedge clk) | |
815 | if (reset) | |
816 | data_valid_cnt <= 4'b0; | |
817 | else if (rdmc_rcr_data_req & !data_valid_cnt_done) | |
818 | data_valid_cnt <= data_valid_cnt + 4'd2; | |
819 | else if (rcr_wrbk_done) | |
820 | data_valid_cnt <= 4'b0; | |
821 | else | |
822 | data_valid_cnt <= data_valid_cnt; | |
823 | ||
824 | always @ (posedge clk) | |
825 | if (reset) | |
826 | data_valid_cnt_done_r <= 1'b0; | |
827 | else if (data_valid_cnt_done & rdmc_rcr_data_req) | |
828 | data_valid_cnt_done_r <= 1'b1; | |
829 | else if (rcr_wrbk_done) | |
830 | data_valid_cnt_done_r <= 1'b0; | |
831 | else | |
832 | data_valid_cnt_done_r <= data_valid_cnt_done_r; | |
833 | ||
834 | always @ (posedge clk) | |
835 | if (reset) | |
836 | shadw_rd_strobe_r <= 1'b0; | |
837 | else | |
838 | shadw_rd_strobe_r <= shadw_rd_strobe; | |
839 | ||
840 | ||
841 | ||
842 | endmodule | |
843 | ||
844 | ||
845 | ||
846 |