Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_tcam.v
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: niu_tcam.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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10// it under the terms of the GNU General Public License as published by
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34// ========== Copyright Header End ============================================
35
36/**********************************************************
37***********************************************************
38
39 Project : Niu
40
41 File name : niu_tcam.v
42
43 Module(s) name : niu_tcam
44
45 Parent modules : niu_rxc.v
46
47 Child modules : niu_acam.v, niu_scam.v, niu_tcam_reset_blk
48
49 Author's name : George Chu
50
51 Date : April, 2004
52
53 Description :
54
55 Synthesis Notes:
56
57 Modification History:
58 Date Description
59 ---- -----------
60
61************************************************************
62***********************************************************/
63
64`timescale 1ns/10ps
65
66module niu_tcam (
67 data_inp, cam_compare,
68 pio_wt, pio_rd, pio_sel, cam_index,
69`ifdef NEPTUNE
70`else tcu_se_scancollar_in,
71 tcu_se_scancollar_out,
72 tcu_array_wr_inhibit,
73 tcu_aclk,
74 tcu_bclk,
75 iol2clk,
76 scan_in,
77 scan_out,
78 reset_core_tcam,
79 mbi_wdata,
80 mbi_rw_adr,
81 mbi_pio_sel,
82 mbi_wr_en,
83 mbi_rd_en,
84 mbi_compare,
85 mbi_run,
86`endif reset_l, clk,
87 cam_valid, cam_hit, cam_haddr,
88 reset_core_fflp_l,
89 pio_rd_vld,
90 msk_dat_out);
91
92input [199:0] data_inp; // compare_data/pio_data_input
93input cam_compare; // initiate compare operation
94input pio_wt; // if 1, pio writes to cam's data or mask or valid planes.
95input pio_rd; // if 1, pio reads from cam's data or mask or valid planes.
96input pio_sel; // pio access cam's mask<=1, data<=0 plane
97`ifdef NEPTUNE
98input [7:0] cam_index; // pio access address,
99`else
100input [6:0] cam_index; // pio access address,
101input tcu_se_scancollar_in; // dft - se for input flops default=0
102input tcu_se_scancollar_out; // dft - se for output flops default=0
103input tcu_array_wr_inhibit; // dft - write inhibit during scan default=0
104input tcu_aclk; // dft - scan clock a default=0
105input tcu_bclk; // dft - scan clock b default=0
106input iol2clk;
107input scan_in; // dft - scan in default= previous flop output
108output scan_out; // dft - scan out
109output reset_core_tcam;
110
111input [199:0] mbi_wdata;
112input [6:0] mbi_rw_adr;
113input mbi_pio_sel;
114input mbi_wr_en;
115input mbi_rd_en;
116input mbi_compare;
117input mbi_run;
118`endif
119input reset_l;
120input clk;
121output cam_valid; // if 1, cam is ready to accept a new comparison
122output cam_hit; // if 1, there is a cam match/hit
123`ifdef NEPTUNE
124output [7:0] cam_haddr; // index of a cam match/hit entry, N2: {1'b0,haddr[6:0]}
125`else
126output [6:0] cam_haddr;
127`endif
128output reset_core_fflp_l;
129output pio_rd_vld; // pio_read_out_data valid for the core_clk domain
130output [201:0] msk_dat_out; // pio data read out of cam's mask or data plane
131
132wire cam_valid;
133wire cam_hit;
134`ifdef NEPTUNE
135wire [7:0] cam_haddr;
136`else
137wire [6:0] cam_haddr;
138wire scan_out;
139`endif
140wire reset_core_fflp_l;
141wire pio_rd_vld;
142wire [201:0] msk_dat_out;
143
144/******************************* local reset *********************************/
145wire reset_core_tcam;
146
147 niu_tcam_reset_blk tcam_reset_blk (
148 .reset_l (reset_l),
149 .clk (clk),
150 .reset_core_fflp_l (reset_core_fflp_l),
151 .reset_core_tcam (reset_core_tcam)
152 );
153
154
155// =================================== CAM's arrays =======================================
156
157/* 0in custom -fire (cam_compare && pio_wt) -message "TCAM compare & write at the same time" */
158
159`ifdef NEPTUNE
160 niu_acam niu_acam0 (
161 .data_inp (data_inp[199:0]),
162 .cam_compare (cam_compare),
163 .pio_wt (pio_wt),
164 .pio_rd (pio_rd),
165 .pio_sel (pio_sel),
166 .cam_index (cam_index[7:0]),
167 .reset (reset_core_tcam),
168 .clk (clk),
169 .cam_valid (cam_valid),
170 .cam_hit (cam_hit),
171 .cam_haddr (cam_haddr[7:0]),
172 .pio_rd_vld (pio_rd_vld),
173 .msk_dat_out (msk_dat_out[201:0])
174 );
175
176`else
177
178 niu_cam_128x200 niu_scam0 (
179 .tcu_aclk (tcu_aclk),
180 .tcu_bclk (tcu_bclk),
181 .tcu_se_scancollar_in (tcu_se_scancollar_in),
182 .tcu_se_scancollar_out (tcu_se_scancollar_out),
183 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
184 .scan_in (scan_in),
185 .scan_out (scan_out),
186 .clk (iol2clk),
187 .mbi_wdata (mbi_wdata),
188 .mbi_rw_adr (mbi_rw_adr),
189 .mbi_pio_sel (mbi_pio_sel),
190 .mbi_wr_en (mbi_wr_en),
191 .mbi_rd_en (mbi_rd_en),
192 .mbi_compare (mbi_compare),
193 .mbi_run (mbi_run),
194 .data_inp (data_inp[199:0]),
195 .cam_compare (cam_compare),
196 .pio_wt (pio_wt),
197 .pio_rd (pio_rd),
198 .pio_sel (pio_sel),
199 .cam_index (cam_index[6:0]),
200 .reset (reset_core_tcam),
201 .cam_valid (cam_valid),
202 .cam_hit (cam_hit),
203 .cam_haddr (cam_haddr[6:0]),
204 .pio_rd_vld (pio_rd_vld),
205 .msk_dat_out (msk_dat_out[199:0])
206 );
207
208 assign msk_dat_out[201:200] = 2'h3;
209`endif
210
211endmodule
212
213
214module niu_tcam_reset_blk (reset_l, clk, reset_core_fflp_l, reset_core_tcam);
215
216input reset_l;
217input clk;
218output reset_core_fflp_l;
219output reset_core_tcam;
220
221wire reset_core_fflp_l;
222wire reset_core_tcam;
223
224reg reset;
225wire reset_p = !reset_l;
226
227`ifdef NEPTUNE
228reg reset_d;
229reg reset_nep_tcam_st, n_reset_nep_tcam_st;
230reg [4:0] reset_cyc_cnt, n_reset_cyc_cnt;
231
232wire reset_fall = !reset && reset_d;
233
234 always @(reset_fall or
235 reset_cyc_cnt or
236 reset_nep_tcam_st
237 ) begin
238
239 n_reset_cyc_cnt = 5'h0;
240 n_reset_nep_tcam_st = 1'h0;
241
242 case (reset_nep_tcam_st) //synopsys parallel_case
243 (1'h0): if (reset_fall) begin
244 n_reset_nep_tcam_st = 1'h1;
245 end
246 else begin
247 n_reset_nep_tcam_st = reset_nep_tcam_st;
248 end
249 (1'h1): if (reset_cyc_cnt>=5'h16) begin
250 n_reset_cyc_cnt = 5'h0;
251 n_reset_nep_tcam_st = 1'h0;
252 end
253 else begin
254 n_reset_cyc_cnt = reset_cyc_cnt + 5'h1;
255 n_reset_nep_tcam_st = reset_nep_tcam_st;
256 end
257 default: n_reset_nep_tcam_st = 1'h0;
258 endcase
259 end
260
261 always @(posedge clk) begin
262 if (reset) begin
263 reset_nep_tcam_st <= #1 1'h0;
264 reset_cyc_cnt <= #1 5'h0;
265 end
266 else begin
267 reset_nep_tcam_st <= #1 n_reset_nep_tcam_st;
268 reset_cyc_cnt <= #1 n_reset_cyc_cnt;
269 end
270 end
271
272 always @(posedge clk) begin
273 reset_d <= #1 reset;
274 end
275
276`endif
277
278`ifdef NEPTUNE
279 assign reset_core_tcam = reset_nep_tcam_st;
280 assign reset_core_fflp_l = !(!reset_l || reset_d || reset_nep_tcam_st);
281`else
282 assign reset_core_tcam = reset;
283 assign reset_core_fflp_l = reset_l;
284`endif
285
286 always @(posedge clk)
287 reset <= #1 reset_p;
288
289endmodule
290