[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_txc_ecc_engine.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_txc_ecc_engine.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// ========== Copyright Header End ============================================
/**********************************************************************
 *
 *  niu_txc_ecc_engine.v
 *
 *  TXC ECC Engine
 *
 *  Orignal Author(s):   Rahoul Puri
 *  Modifier(s):
 *  Project(s):          Neptune
 *
 *  Copyright (c) 2005   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/

`include "timescale.v"

module niu_txc_ecc_engine (
        SysClk,
        Reset_L,
        ReOrder_ClearEccError,
        WrReOrderEccState,
        WrReOrderEccData0,
        WrReOrderEccData1,
        WrReOrderEccData2,
        WrReOrderEccData3,
        WrReOrderEccData4,
        StoreForward_ClearEccError,
        WrStoreForwardEccState,
        WrStoreForwardEccData0,
        WrStoreForwardEccData1,
        WrStoreForwardEccData2,
        WrStoreForwardEccData3,
        WrStoreForwardEccData4,
        PioDataIn,
        ReOrder_ECC_State,
        ReOrder_EccData,
        StoreForward_ECC_State,
        StoreForward_EccData,

        ReOrder_CorruptECCSingle,
        ReOrder_CorruptECCDouble,
        ReOrder_FifoRead,
        ReOrder_ReadPtr,
        ReOrder_PreECCData,
        ReOrder_FifoDataOut,
        ReOrder_FifoDataValid,
        ReOrder_UnCorrectError,
        ReOrder_CorrectedData,
        ReOrder_PostECCData,
        StoreForward_CorruptECCSingle,
        StoreForward_CorruptECCDouble,
        StoreForward_FifoRead,
        StoreForward_ReadPtr,
        StoreForward_PreECCData,
        StoreForward_FifoDataOut,
        StoreForward_UnCorrectError,
        StoreForward_CorrectedData,
        StoreForward_PostECCData
       );

    
`include "txc_defines.h"

// Global signals
input          SysClk;
input          Reset_L;

// PIO Access
input          ReOrder_ClearEccError;
input          WrReOrderEccState;
input          WrReOrderEccData0;
input          WrReOrderEccData1;
input          WrReOrderEccData2;
input          WrReOrderEccData3;
input          WrReOrderEccData4;
input          StoreForward_ClearEccError;
input          WrStoreForwardEccState;
input          WrStoreForwardEccData0;
input          WrStoreForwardEccData1;
input          WrStoreForwardEccData2;
input          WrStoreForwardEccData3;
input          WrStoreForwardEccData4;
input  [31:0]  PioDataIn;

output [31:0]  ReOrder_ECC_State;
output [151:0] ReOrder_EccData;

output [31:0]  StoreForward_ECC_State;
output [151:0] StoreForward_EccData;

// Error forcing
input          ReOrder_CorruptECCSingle;
input          ReOrder_CorruptECCDouble;
input          ReOrder_FifoRead;
input  [9:0]   ReOrder_ReadPtr;
input  [135:0] ReOrder_PreECCData;
input  [151:0] ReOrder_FifoDataOut;

output         ReOrder_FifoDataValid;
output         ReOrder_UnCorrectError;
output [135:0] ReOrder_CorrectedData;
output [151:0] ReOrder_PostECCData;

reg            ReOrder_FifoDataValid;

input          StoreForward_CorruptECCSingle;
input          StoreForward_CorruptECCDouble;
input          StoreForward_FifoRead;
input  [9:0]   StoreForward_ReadPtr;
input  [135:0] StoreForward_PreECCData;
input  [151:0] StoreForward_FifoDataOut;

output         StoreForward_UnCorrectError;
output [135:0] StoreForward_CorrectedData;
output [151:0] StoreForward_PostECCData;

/*--------------------------------------------------------------*/
// Wires & Registers
/*--------------------------------------------------------------*/
wire           reOrder_CorrectError;
wire           reOrder_CorrectError0;
wire           reOrder_CorrectError1;
wire           reOrder_UnCorrectError0;
wire           reOrder_UnCorrectError1;
wire           rO_loadEccError;
wire   [1:0]   ro_ForceECCError;
wire   [7:0]   reOrder_ECCSyn0;
wire   [7:0]   reOrder_ECCSyn1;
wire   [75:0]  ro_PostECCData0;
wire   [75:0]  ro_PostECCData1;
wire   [75:0]  ro_ECCDataOut0;
wire   [75:0]  ro_ECCDataOut1;
wire   [151:0] ro_PostECCData;
wire   [151:0] ro_ECCDataOut;

wire           storeForward_CorrectError;
wire           storeForward_CorrectError0;
wire           storeForward_CorrectError1;
wire           storeForward_UnCorrectError0;
wire           storeForward_UnCorrectError1;
wire           sF_loadEccError;
wire           sf_ForceECCErrorBit144;
wire           sf_ForceECCErrorBit151;
wire   [1:0]   sf_ForceECCError;
wire   [7:0]   storeForward_ECCSyn0;
wire   [7:0]   storeForward_ECCSyn1;
wire   [75:0]  sf_PostECCData0;
wire   [75:0]  sf_PostECCData1;
wire   [75:0]  sf_ECCDataOut0;
wire   [75:0]  sf_ECCDataOut1;
wire   [151:0] sf_PostECCData;
wire   [151:0] sf_ECCDataOut;

reg            storeForward_FifoDataValid;
reg            reOrder_FifoReadD1;
reg            rO_ErrorValid;
reg            rO_CorrectError;
reg            rO_UnCorrectError;
reg    [9:0]   rO_EccAddr;
reg    [9:0]   reOrder_ReadAddrD1;
reg    [31:0]  rO_EccData0;
reg    [31:0]  rO_EccData1;
reg    [31:0]  rO_EccData2;
reg    [31:0]  rO_EccData3;
reg    [23:0]  rO_EccData4;
reg    [75:0]  reOrder_FifoDataOutD0;
reg    [75:0]  reOrder_FifoDataOutD1;

reg            storeForward_FifoReadD1;
reg            sF_ErrorValid;
reg            sF_CorrectError;
reg            sF_UnCorrectError;
reg    [9:0]   sF_EccAddr;
reg    [9:0]   storeForward_ReadAddrD1;
reg    [31:0]  sF_EccData0;
reg    [31:0]  sF_EccData1;
reg    [31:0]  sF_EccData2;
reg    [31:0]  sF_EccData3;
reg    [23:0]  sF_EccData4;
reg    [75:0]  storeForward_FifoDataOutD0;
reg    [75:0]  storeForward_FifoDataOutD1;

/*--------------------------------------------------------------*/
// Assigns
/*--------------------------------------------------------------*/
assign ro_PostECCData         = {ro_PostECCData1, ro_PostECCData0};
assign ro_ECCDataOut          = {ro_ECCDataOut1, ro_ECCDataOut0};
assign ReOrder_UnCorrectError = (reOrder_UnCorrectError1
                                 |
                                 reOrder_UnCorrectError0
                                );

assign reOrder_CorrectError   = (reOrder_CorrectError1
                                 |
                                 reOrder_CorrectError0
                                );

assign ReOrder_CorrectedData      = {ro_ECCDataOut1[75:8], ro_ECCDataOut0[75:8]};


assign sf_PostECCData              = {sf_PostECCData1, sf_PostECCData0};
assign sf_ECCDataOut               = {sf_ECCDataOut1, sf_ECCDataOut0};
assign StoreForward_UnCorrectError = (storeForward_UnCorrectError1
                                      |
                                      storeForward_UnCorrectError0
                                     );

assign storeForward_CorrectError   = (storeForward_CorrectError1
                                      |
                                      storeForward_CorrectError0
                                     );

assign StoreForward_CorrectedData = {sf_ECCDataOut1[75:8], sf_ECCDataOut0[75:8]};


assign ro_ForceECCError =
      ReOrder_CorruptECCDouble ? ~ro_PostECCData[1:0] :
      ReOrder_CorruptECCSingle ? {ro_PostECCData[1], ~ro_PostECCData[0]}
                               :  ro_PostECCData[1:0];

assign sf_ForceECCErrorBit144 =
      (StoreForward_CorruptECCDouble & StoreForward_CorruptECCSingle)
                                    ? ~sf_PostECCData[144]
                                    : sf_PostECCData[144];

assign sf_ForceECCErrorBit151 =
      (StoreForward_CorruptECCDouble & StoreForward_CorruptECCSingle)
                                    ? ~sf_PostECCData[151]
                                    : sf_PostECCData[151];
assign sf_ForceECCError =
      StoreForward_CorruptECCDouble ? ~sf_PostECCData[1:0] :
      StoreForward_CorruptECCSingle ? {sf_PostECCData[1], ~sf_PostECCData[0]}
                                    : sf_PostECCData[1:0];

assign ReOrder_PostECCData      = {ro_PostECCData[151:2], ro_ForceECCError}; 

assign StoreForward_PostECCData = {sf_ForceECCErrorBit151,   // Bit 135
                                   sf_PostECCData[150:145],  // Bit 134-129
                                   sf_ForceECCErrorBit144,   // Bit 128
                                   sf_PostECCData[143:84],   // Bits [127:69]
                                   sf_PostECCData[83:76],    // Syndrome
                                   sf_PostECCData[75:8],     // Bits [68:0]
                                   sf_PostECCData[7:2],      // Syndrome
                                   sf_ForceECCError          // Syndrome
                                  }; 

/*--------------------------------------------------------------*/
// Logic
/*--------------------------------------------------------------*/
always @(posedge SysClk)
  if (!Reset_L) reOrder_FifoDataOutD1 <= #`SD 76'h0;
  else          reOrder_FifoDataOutD1 <= #`SD ReOrder_FifoDataOut[151:76];

always @(posedge SysClk)
  if (!Reset_L) reOrder_FifoDataOutD0 <= #`SD 76'h0;
  else          reOrder_FifoDataOutD0 <= #`SD ReOrder_FifoDataOut[75:0];


always @(posedge SysClk)
  if (!Reset_L) reOrder_FifoReadD1 <= #`SD 1'b0;
  else          reOrder_FifoReadD1 <= #`SD ReOrder_FifoRead;


always @(posedge SysClk)
  if (!Reset_L) ReOrder_FifoDataValid <= #`SD 1'b0;
  else          ReOrder_FifoDataValid <= #`SD reOrder_FifoReadD1;


always @(posedge SysClk)
  if (!Reset_L) reOrder_ReadAddrD1 <= #`SD 10'h0;
  else          reOrder_ReadAddrD1 <= #`SD ReOrder_ReadPtr;

always @(posedge SysClk)
  if (!Reset_L) storeForward_FifoDataOutD1 <= #`SD 76'h0;
  else          storeForward_FifoDataOutD1 <= #`SD StoreForward_FifoDataOut[151:76];

always @(posedge SysClk)
  if (!Reset_L) storeForward_FifoDataOutD0 <= #`SD 76'h0;
  else          storeForward_FifoDataOutD0 <= #`SD StoreForward_FifoDataOut[75:0];

always @(posedge SysClk)
  if (!Reset_L) storeForward_FifoReadD1 <= #`SD 1'b0;
  else          storeForward_FifoReadD1 <= #`SD StoreForward_FifoRead;

always @(posedge SysClk)
  if (!Reset_L) storeForward_FifoDataValid <= #`SD 1'b0;
  else          storeForward_FifoDataValid <= #`SD storeForward_FifoReadD1;

always @(posedge SysClk)
  if (!Reset_L) storeForward_ReadAddrD1 <= #`SD 10'h0;
  else          storeForward_ReadAddrD1 <= #`SD StoreForward_ReadPtr;

/*--------------------------------------------------------------*/
// RO Latching of ECC Errors
/*--------------------------------------------------------------*/
assign ReOrder_EccData = {rO_EccData4, rO_EccData3, rO_EccData2,
                          rO_EccData1, rO_EccData0
                         };

assign ReOrder_ECC_State = {14'h0, rO_CorrectError,
                                   rO_UnCorrectError, 6'b0, rO_EccAddr};

assign rO_loadEccError = (ReOrder_FifoDataValid
                          &
                          (reOrder_CorrectError
                           |
                           ReOrder_UnCorrectError
                          )
                          &
                          ~rO_ErrorValid
                         );

always @ (posedge SysClk)
  if (!Reset_L)                   rO_ErrorValid <= 1'b0;
  else if (ReOrder_ClearEccError) rO_ErrorValid <= 1'b0;
  else if (rO_loadEccError)       rO_ErrorValid <= 1'b1;

always @ (posedge SysClk)
  if (!Reset_L)                   rO_CorrectError <= 1'b0;
  else if (ReOrder_ClearEccError) rO_CorrectError <= 1'b0;
  else if (WrReOrderEccState)     rO_CorrectError <= PioDataIn[17];
  else if (rO_loadEccError)       rO_CorrectError <= reOrder_CorrectError;

always @ (posedge SysClk)
  if (!Reset_L)                   rO_UnCorrectError <= 1'b0;
  else if (ReOrder_ClearEccError) rO_UnCorrectError <= 1'b0;
  else if (WrReOrderEccState)     rO_UnCorrectError <= PioDataIn[16];
  else if (rO_loadEccError)       rO_UnCorrectError <= ReOrder_UnCorrectError;

always @ (posedge SysClk)
  if (!Reset_L)                   rO_EccAddr <= 10'b0;
  else if (ReOrder_ClearEccError) rO_EccAddr <= 10'h0;
  else if (WrReOrderEccState)     rO_EccAddr <= PioDataIn[9:0];
  else if (rO_loadEccError)       rO_EccAddr <= reOrder_ReadAddrD1;

always @ (posedge SysClk)
  if (!Reset_L)                   rO_EccData0 <= 32'h0;
  else if (ReOrder_ClearEccError) rO_EccData0 <= 32'h0;
  else if (WrReOrderEccData0)     rO_EccData0 <= PioDataIn[31:0];
  else if (rO_loadEccError)       rO_EccData0 <= ro_ECCDataOut[31:0];

always @ (posedge SysClk)
  if (!Reset_L)                   rO_EccData1 <= 32'h0;
  else if (ReOrder_ClearEccError) rO_EccData1 <= 32'h0;
  else if (WrReOrderEccData1)     rO_EccData1 <= PioDataIn[31:0];
  else if (rO_loadEccError)       rO_EccData1 <= ro_ECCDataOut[63:32];

always @ (posedge SysClk)
  if (!Reset_L)                   rO_EccData2 <= 32'h0;
  else if (ReOrder_ClearEccError) rO_EccData2 <= 32'h0;
  else if (WrReOrderEccData2)     rO_EccData2 <= PioDataIn[31:0];
  else if (rO_loadEccError)       rO_EccData2 <= ro_ECCDataOut[95:64];

always @ (posedge SysClk)
  if (!Reset_L)                   rO_EccData3 <= 32'h0;
  else if (ReOrder_ClearEccError) rO_EccData3 <= 32'h0;
  else if (WrReOrderEccData3)     rO_EccData3 <= PioDataIn[31:0];
  else if (rO_loadEccError)       rO_EccData3 <= ro_ECCDataOut[127:96];

always @ (posedge SysClk)
  if (!Reset_L)                   rO_EccData4 <= 24'h0;
  else if (ReOrder_ClearEccError) rO_EccData4 <= 24'h0;
  else if (WrReOrderEccData4)     rO_EccData4 <= PioDataIn[23:0];
  else if (rO_loadEccError)       rO_EccData4 <= ro_ECCDataOut[151:128];

/*--------------------------------------------------------------*/
// SF Latching of ECC Errors
/*--------------------------------------------------------------*/
assign StoreForward_EccData = {sF_EccData4, sF_EccData3, sF_EccData2,
                               sF_EccData1, sF_EccData0
                              };


assign StoreForward_ECC_State = {14'h0, sF_CorrectError,
                                 sF_UnCorrectError, 6'b0, sF_EccAddr};

assign sF_loadEccError = (storeForward_FifoDataValid
                          &
                          (storeForward_CorrectError
                           |
                           StoreForward_UnCorrectError
                          )
                          &
                          ~sF_ErrorValid
                         );


always @ (posedge SysClk)
  if (!Reset_L)                        sF_ErrorValid <= 1'b0;
  else if (StoreForward_ClearEccError) sF_ErrorValid <= 1'b0;
  else if (sF_loadEccError)            sF_ErrorValid <= 1'b1;

always @ (posedge SysClk)
  if (!Reset_L)
    sF_CorrectError <= 1'b0;
  else if (StoreForward_ClearEccError)
    sF_CorrectError <= 1'b0;
  else if (WrStoreForwardEccState)
    sF_CorrectError <= PioDataIn[17];
  else if (sF_loadEccError) 
    sF_CorrectError <= storeForward_CorrectError;

always @ (posedge SysClk)
  if (!Reset_L)
    sF_UnCorrectError <= 1'b0;
  else if (StoreForward_ClearEccError)
    sF_UnCorrectError <= 1'b0;
  else if (WrStoreForwardEccState)
    sF_UnCorrectError <= PioDataIn[16];
  else if (sF_loadEccError)
    sF_UnCorrectError <= StoreForward_UnCorrectError;

always @ (posedge SysClk)
  if (!Reset_L)                        sF_EccAddr <= 10'b0;
  else if (StoreForward_ClearEccError) sF_EccAddr <= 10'h0;
  else if (WrStoreForwardEccState)     sF_EccAddr <= PioDataIn[9:0];
  else if (sF_loadEccError)            sF_EccAddr <= storeForward_ReadAddrD1;

always @ (posedge SysClk)
  if (!Reset_L)                        sF_EccData0 <= 32'h0;
  else if (StoreForward_ClearEccError) sF_EccData0 <= 32'h0;
  else if (WrStoreForwardEccData0)     sF_EccData0 <= PioDataIn[31:0];
  else if (sF_loadEccError)            sF_EccData0 <= sf_ECCDataOut[31:0];

always @ (posedge SysClk)
  if (!Reset_L)                        sF_EccData1 <= 32'h0;
  else if (StoreForward_ClearEccError) sF_EccData1 <= 32'h0;
  else if (WrStoreForwardEccData1)     sF_EccData1 <= PioDataIn[31:0];
  else if (sF_loadEccError)            sF_EccData1 <= sf_ECCDataOut[63:32];

always @ (posedge SysClk)
  if (!Reset_L)                        sF_EccData2 <= 32'h0;
  else if (StoreForward_ClearEccError) sF_EccData2 <= 32'h0;
  else if (WrStoreForwardEccData2)     sF_EccData2 <= PioDataIn[31:0];
  else if (sF_loadEccError)            sF_EccData2 <= sf_ECCDataOut[95:64];

always @ (posedge SysClk)
  if (!Reset_L)                        sF_EccData3 <= 32'h0;
  else if (StoreForward_ClearEccError) sF_EccData3 <= 32'h0;
  else if (WrStoreForwardEccData3)     sF_EccData3 <= PioDataIn[31:0];
  else if (sF_loadEccError)            sF_EccData3 <= sf_ECCDataOut[127:96];

always @ (posedge SysClk)
  if (!Reset_L)                        sF_EccData4 <= 24'h0;
  else if (StoreForward_ClearEccError) sF_EccData4 <= 24'h0;
  else if (WrStoreForwardEccData4)     sF_EccData4 <= PioDataIn[23:0];
  else if (sF_loadEccError)            sF_EccData4 <= sf_ECCDataOut[151:128];

/*--------------------------------------------------------------*/
// Modules
/*--------------------------------------------------------------*/

niu_txc_ecc_generate niu_txc_RO_ecc_generate1 (
        .din                          (ReOrder_PreECCData[135:68]),
        .dout                         (ro_PostECCData1)
       );

niu_txc_ecc_generate niu_txc_RO_ecc_generate0 (
        .din                          (ReOrder_PreECCData[67:0]),
        .dout                         (ro_PostECCData0)
       );

niu_txc_ecc_syndrome niu_txc_RO_ecc_syndrome1 (
        .din                          (reOrder_FifoDataOutD1),
        .syn                          (reOrder_ECCSyn1)
       );

niu_txc_ecc_syndrome niu_txc_RO_ecc_syndrome0 (
        .din                          (reOrder_FifoDataOutD0),
        .syn                          (reOrder_ECCSyn0)
       );

niu_txc_ecc_correct niu_txc_RO_ecc_correct1 (
        .din                          (reOrder_FifoDataOutD1),
        .syn                          (reOrder_ECCSyn1),
        .dout                         (ro_ECCDataOut1),
        .no_error                     (),
        .error                        (),
        .corr_error                   (reOrder_CorrectError1),
        .uncorr_error                 (reOrder_UnCorrectError1)
       );

niu_txc_ecc_correct niu_txc_RO_ecc_correct0 (
        .din                          (reOrder_FifoDataOutD0),
        .syn                          (reOrder_ECCSyn0),
        .dout                         (ro_ECCDataOut0),
        .no_error                     (),
        .error                        (),
        .corr_error                   (reOrder_CorrectError0),
        .uncorr_error                 (reOrder_UnCorrectError0)
       );

niu_txc_ecc_generate niu_txc_SF_ecc_generate1 (
        .din                          (StoreForward_PreECCData[135:68]),
        .dout                         (sf_PostECCData1)
       );

niu_txc_ecc_generate niu_txc_SF_ecc_generate0 (
        .din                          (StoreForward_PreECCData[67:0]),
        .dout                         (sf_PostECCData0)
       );

niu_txc_ecc_syndrome niu_txc_SF_ecc_syndrome1 (
        .din                          (storeForward_FifoDataOutD1),
        .syn                          (storeForward_ECCSyn1)
       );

niu_txc_ecc_syndrome niu_txc_SF_ecc_syndrome0 (
        .din                          (storeForward_FifoDataOutD0),
        .syn                          (storeForward_ECCSyn0)
       );

niu_txc_ecc_correct niu_txc_SF_ecc_correct1 (
        .din                          (storeForward_FifoDataOutD1),
        .syn                          (storeForward_ECCSyn1),
        .dout                         (sf_ECCDataOut1),
        .no_error                     (),
        .error                        (),
        .corr_error                   (storeForward_CorrectError1),
        .uncorr_error                 (storeForward_UnCorrectError1)
       );

niu_txc_ecc_correct niu_txc_SF_ecc_correct0 (
        .din                          (storeForward_FifoDataOutD0),
        .syn                          (storeForward_ECCSyn0),
        .dout                         (sf_ECCDataOut0),
        .no_error                     (),
        .error                        (),
        .corr_error                   (storeForward_CorrectError0),
        .uncorr_error                 (storeForward_UnCorrectError0)
       );

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_txc_ecc_engine.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/**********************************************************************
	36	*
	37	* niu_txc_ecc_engine.v
	38	*
	39	* TXC ECC Engine
	40	*
	41	* Orignal Author(s): Rahoul Puri
	42	* Modifier(s):
	43	* Project(s): Neptune
	44	*
	45	* Copyright (c) 2005 Sun Microsystems, Inc.
	46	*
	47	* All Rights Reserved.
	48	*
	49	* This verilog model is the confidential and proprietary property of
	50	* Sun Microsystems, Inc., and the possession or use of this model
	51	* requires a written license from Sun Microsystems, Inc.
	52	*
	53	**********************************************************************/
	54
	55	`include "timescale.v"
	56
	57	module niu_txc_ecc_engine (
	58	SysClk,
	59	Reset_L,
	60	ReOrder_ClearEccError,
	61	WrReOrderEccState,
	62	WrReOrderEccData0,
	63	WrReOrderEccData1,
	64	WrReOrderEccData2,
65	WrReOrderEccData3,
66	WrReOrderEccData4,
67	StoreForward_ClearEccError,
68	WrStoreForwardEccState,
69	WrStoreForwardEccData0,
70	WrStoreForwardEccData1,
71	WrStoreForwardEccData2,
72	WrStoreForwardEccData3,
73	WrStoreForwardEccData4,
74	PioDataIn,
75	ReOrder_ECC_State,
76	ReOrder_EccData,
77	StoreForward_ECC_State,
78	StoreForward_EccData,
79
80	ReOrder_CorruptECCSingle,
81	ReOrder_CorruptECCDouble,
82	ReOrder_FifoRead,
83	ReOrder_ReadPtr,
84	ReOrder_PreECCData,
85	ReOrder_FifoDataOut,
86	ReOrder_FifoDataValid,
87	ReOrder_UnCorrectError,
88	ReOrder_CorrectedData,
89	ReOrder_PostECCData,
90	StoreForward_CorruptECCSingle,
91	StoreForward_CorruptECCDouble,
92	StoreForward_FifoRead,
93	StoreForward_ReadPtr,
94	StoreForward_PreECCData,
95	StoreForward_FifoDataOut,
96	StoreForward_UnCorrectError,
97	StoreForward_CorrectedData,
98	StoreForward_PostECCData
99	);
100
101
102	`include "txc_defines.h"
103
104	// Global signals
105	input SysClk;
106	input Reset_L;
107
108	// PIO Access
109	input ReOrder_ClearEccError;
110	input WrReOrderEccState;
111	input WrReOrderEccData0;
112	input WrReOrderEccData1;
113	input WrReOrderEccData2;
114	input WrReOrderEccData3;
115	input WrReOrderEccData4;
116	input StoreForward_ClearEccError;
117	input WrStoreForwardEccState;
118	input WrStoreForwardEccData0;
119	input WrStoreForwardEccData1;
120	input WrStoreForwardEccData2;
121	input WrStoreForwardEccData3;
122	input WrStoreForwardEccData4;
123	input [31:0] PioDataIn;
124
125	output [31:0] ReOrder_ECC_State;
126	output [151:0] ReOrder_EccData;
127
128	output [31:0] StoreForward_ECC_State;
129	output [151:0] StoreForward_EccData;
130
131	// Error forcing
132	input ReOrder_CorruptECCSingle;
133	input ReOrder_CorruptECCDouble;
134	input ReOrder_FifoRead;
135	input [9:0] ReOrder_ReadPtr;
136	input [135:0] ReOrder_PreECCData;
137	input [151:0] ReOrder_FifoDataOut;
138
139	output ReOrder_FifoDataValid;
140	output ReOrder_UnCorrectError;
141	output [135:0] ReOrder_CorrectedData;
142	output [151:0] ReOrder_PostECCData;
143
144	reg ReOrder_FifoDataValid;
145
146	input StoreForward_CorruptECCSingle;
147	input StoreForward_CorruptECCDouble;
148	input StoreForward_FifoRead;
149	input [9:0] StoreForward_ReadPtr;
150	input [135:0] StoreForward_PreECCData;
151	input [151:0] StoreForward_FifoDataOut;
152
153	output StoreForward_UnCorrectError;
154	output [135:0] StoreForward_CorrectedData;
155	output [151:0] StoreForward_PostECCData;
156
157	/--------------------------------------------------------------/
158	// Wires & Registers
159	/--------------------------------------------------------------/
160	wire reOrder_CorrectError;
161	wire reOrder_CorrectError0;
162	wire reOrder_CorrectError1;
163	wire reOrder_UnCorrectError0;
164	wire reOrder_UnCorrectError1;
165	wire rO_loadEccError;
166	wire [1:0] ro_ForceECCError;
167	wire [7:0] reOrder_ECCSyn0;
168	wire [7:0] reOrder_ECCSyn1;
169	wire [75:0] ro_PostECCData0;
170	wire [75:0] ro_PostECCData1;
171	wire [75:0] ro_ECCDataOut0;
172	wire [75:0] ro_ECCDataOut1;
173	wire [151:0] ro_PostECCData;
174	wire [151:0] ro_ECCDataOut;
175
176	wire storeForward_CorrectError;
177	wire storeForward_CorrectError0;
178	wire storeForward_CorrectError1;
179	wire storeForward_UnCorrectError0;
180	wire storeForward_UnCorrectError1;
181	wire sF_loadEccError;
182	wire sf_ForceECCErrorBit144;
183	wire sf_ForceECCErrorBit151;
184	wire [1:0] sf_ForceECCError;
185	wire [7:0] storeForward_ECCSyn0;
186	wire [7:0] storeForward_ECCSyn1;
187	wire [75:0] sf_PostECCData0;
188	wire [75:0] sf_PostECCData1;
189	wire [75:0] sf_ECCDataOut0;
190	wire [75:0] sf_ECCDataOut1;
191	wire [151:0] sf_PostECCData;
192	wire [151:0] sf_ECCDataOut;
193
194	reg storeForward_FifoDataValid;
195	reg reOrder_FifoReadD1;
196	reg rO_ErrorValid;
197	reg rO_CorrectError;
198	reg rO_UnCorrectError;
199	reg [9:0] rO_EccAddr;
200	reg [9:0] reOrder_ReadAddrD1;
201	reg [31:0] rO_EccData0;
202	reg [31:0] rO_EccData1;
203	reg [31:0] rO_EccData2;
204	reg [31:0] rO_EccData3;
205	reg [23:0] rO_EccData4;
206	reg [75:0] reOrder_FifoDataOutD0;
207	reg [75:0] reOrder_FifoDataOutD1;
208
209	reg storeForward_FifoReadD1;
210	reg sF_ErrorValid;
211	reg sF_CorrectError;
212	reg sF_UnCorrectError;
213	reg [9:0] sF_EccAddr;
214	reg [9:0] storeForward_ReadAddrD1;
215	reg [31:0] sF_EccData0;
216	reg [31:0] sF_EccData1;
217	reg [31:0] sF_EccData2;
218	reg [31:0] sF_EccData3;
219	reg [23:0] sF_EccData4;
220	reg [75:0] storeForward_FifoDataOutD0;
221	reg [75:0] storeForward_FifoDataOutD1;
222
223	/--------------------------------------------------------------/
224	// Assigns
225	/--------------------------------------------------------------/
226	assign ro_PostECCData = {ro_PostECCData1, ro_PostECCData0};
227	assign ro_ECCDataOut = {ro_ECCDataOut1, ro_ECCDataOut0};
228	assign ReOrder_UnCorrectError = (reOrder_UnCorrectError1
229	\|
230	reOrder_UnCorrectError0
231	);
232
233	assign reOrder_CorrectError = (reOrder_CorrectError1
234	\|
235	reOrder_CorrectError0
236	);
237
238	assign ReOrder_CorrectedData = {ro_ECCDataOut1[75:8], ro_ECCDataOut0[75:8]};
239
240
241	assign sf_PostECCData = {sf_PostECCData1, sf_PostECCData0};
242	assign sf_ECCDataOut = {sf_ECCDataOut1, sf_ECCDataOut0};
243	assign StoreForward_UnCorrectError = (storeForward_UnCorrectError1
244	\|
245	storeForward_UnCorrectError0
246	);
247
248	assign storeForward_CorrectError = (storeForward_CorrectError1
249	\|
250	storeForward_CorrectError0
251	);
252
253	assign StoreForward_CorrectedData = {sf_ECCDataOut1[75:8], sf_ECCDataOut0[75:8]};
254
255
256	assign ro_ForceECCError =
257	ReOrder_CorruptECCDouble ? ~ro_PostECCData[1:0] :
258	ReOrder_CorruptECCSingle ? {ro_PostECCData[1], ~ro_PostECCData[0]}
259	: ro_PostECCData[1:0];
260
261	assign sf_ForceECCErrorBit144 =
262	(StoreForward_CorruptECCDouble & StoreForward_CorruptECCSingle)
263	? ~sf_PostECCData[144]
264	: sf_PostECCData[144];
265
266	assign sf_ForceECCErrorBit151 =
267	(StoreForward_CorruptECCDouble & StoreForward_CorruptECCSingle)
268	? ~sf_PostECCData[151]
269	: sf_PostECCData[151];
270	assign sf_ForceECCError =
271	StoreForward_CorruptECCDouble ? ~sf_PostECCData[1:0] :
272	StoreForward_CorruptECCSingle ? {sf_PostECCData[1], ~sf_PostECCData[0]}
273	: sf_PostECCData[1:0];
274
275	assign ReOrder_PostECCData = {ro_PostECCData[151:2], ro_ForceECCError};
276
277	assign StoreForward_PostECCData = {sf_ForceECCErrorBit151, // Bit 135
278	sf_PostECCData[150:145], // Bit 134-129
279	sf_ForceECCErrorBit144, // Bit 128
280	sf_PostECCData[143:84], // Bits [127:69]
281	sf_PostECCData[83:76], // Syndrome
282	sf_PostECCData[75:8], // Bits [68:0]
283	sf_PostECCData[7:2], // Syndrome
284	sf_ForceECCError // Syndrome
285	};
286
287	/--------------------------------------------------------------/
288	// Logic
289	/--------------------------------------------------------------/
290	always @(posedge SysClk)
291	if (!Reset_L) reOrder_FifoDataOutD1 <= #`SD 76'h0;
292	else reOrder_FifoDataOutD1 <= #`SD ReOrder_FifoDataOut[151:76];
293
294	always @(posedge SysClk)
295	if (!Reset_L) reOrder_FifoDataOutD0 <= #`SD 76'h0;
296	else reOrder_FifoDataOutD0 <= #`SD ReOrder_FifoDataOut[75:0];
297
298
299	always @(posedge SysClk)
300	if (!Reset_L) reOrder_FifoReadD1 <= #`SD 1'b0;
301	else reOrder_FifoReadD1 <= #`SD ReOrder_FifoRead;
302
303
304	always @(posedge SysClk)
305	if (!Reset_L) ReOrder_FifoDataValid <= #`SD 1'b0;
306	else ReOrder_FifoDataValid <= #`SD reOrder_FifoReadD1;
307
308
309	always @(posedge SysClk)
310	if (!Reset_L) reOrder_ReadAddrD1 <= #`SD 10'h0;
311	else reOrder_ReadAddrD1 <= #`SD ReOrder_ReadPtr;
312
313	always @(posedge SysClk)
314	if (!Reset_L) storeForward_FifoDataOutD1 <= #`SD 76'h0;
315	else storeForward_FifoDataOutD1 <= #`SD StoreForward_FifoDataOut[151:76];
316
317	always @(posedge SysClk)
318	if (!Reset_L) storeForward_FifoDataOutD0 <= #`SD 76'h0;
319	else storeForward_FifoDataOutD0 <= #`SD StoreForward_FifoDataOut[75:0];
320
321	always @(posedge SysClk)
322	if (!Reset_L) storeForward_FifoReadD1 <= #`SD 1'b0;
323	else storeForward_FifoReadD1 <= #`SD StoreForward_FifoRead;
324
325	always @(posedge SysClk)
326	if (!Reset_L) storeForward_FifoDataValid <= #`SD 1'b0;
327	else storeForward_FifoDataValid <= #`SD storeForward_FifoReadD1;
328
329	always @(posedge SysClk)
330	if (!Reset_L) storeForward_ReadAddrD1 <= #`SD 10'h0;
331	else storeForward_ReadAddrD1 <= #`SD StoreForward_ReadPtr;
332
333	/--------------------------------------------------------------/
334	// RO Latching of ECC Errors
335	/--------------------------------------------------------------/
336	assign ReOrder_EccData = {rO_EccData4, rO_EccData3, rO_EccData2,
337	rO_EccData1, rO_EccData0
338	};
339
340	assign ReOrder_ECC_State = {14'h0, rO_CorrectError,
341	rO_UnCorrectError, 6'b0, rO_EccAddr};
342
343	assign rO_loadEccError = (ReOrder_FifoDataValid
344	&
345	(reOrder_CorrectError
346	\|
347	ReOrder_UnCorrectError
348	)
349	&
350	~rO_ErrorValid
351	);
352
353	always @ (posedge SysClk)
354	if (!Reset_L) rO_ErrorValid <= 1'b0;
355	else if (ReOrder_ClearEccError) rO_ErrorValid <= 1'b0;
356	else if (rO_loadEccError) rO_ErrorValid <= 1'b1;
357
358	always @ (posedge SysClk)
359	if (!Reset_L) rO_CorrectError <= 1'b0;
360	else if (ReOrder_ClearEccError) rO_CorrectError <= 1'b0;
361	else if (WrReOrderEccState) rO_CorrectError <= PioDataIn[17];
362	else if (rO_loadEccError) rO_CorrectError <= reOrder_CorrectError;
363
364	always @ (posedge SysClk)
365	if (!Reset_L) rO_UnCorrectError <= 1'b0;
366	else if (ReOrder_ClearEccError) rO_UnCorrectError <= 1'b0;
367	else if (WrReOrderEccState) rO_UnCorrectError <= PioDataIn[16];
368	else if (rO_loadEccError) rO_UnCorrectError <= ReOrder_UnCorrectError;
369
370	always @ (posedge SysClk)
371	if (!Reset_L) rO_EccAddr <= 10'b0;
372	else if (ReOrder_ClearEccError) rO_EccAddr <= 10'h0;
373	else if (WrReOrderEccState) rO_EccAddr <= PioDataIn[9:0];
374	else if (rO_loadEccError) rO_EccAddr <= reOrder_ReadAddrD1;
375
376	always @ (posedge SysClk)
377	if (!Reset_L) rO_EccData0 <= 32'h0;
378	else if (ReOrder_ClearEccError) rO_EccData0 <= 32'h0;
379	else if (WrReOrderEccData0) rO_EccData0 <= PioDataIn[31:0];
380	else if (rO_loadEccError) rO_EccData0 <= ro_ECCDataOut[31:0];
381
382	always @ (posedge SysClk)
383	if (!Reset_L) rO_EccData1 <= 32'h0;
384	else if (ReOrder_ClearEccError) rO_EccData1 <= 32'h0;
385	else if (WrReOrderEccData1) rO_EccData1 <= PioDataIn[31:0];
386	else if (rO_loadEccError) rO_EccData1 <= ro_ECCDataOut[63:32];
387
388	always @ (posedge SysClk)
389	if (!Reset_L) rO_EccData2 <= 32'h0;
390	else if (ReOrder_ClearEccError) rO_EccData2 <= 32'h0;
391	else if (WrReOrderEccData2) rO_EccData2 <= PioDataIn[31:0];
392	else if (rO_loadEccError) rO_EccData2 <= ro_ECCDataOut[95:64];
393
394	always @ (posedge SysClk)
395	if (!Reset_L) rO_EccData3 <= 32'h0;
396	else if (ReOrder_ClearEccError) rO_EccData3 <= 32'h0;
397	else if (WrReOrderEccData3) rO_EccData3 <= PioDataIn[31:0];
398	else if (rO_loadEccError) rO_EccData3 <= ro_ECCDataOut[127:96];
399
400	always @ (posedge SysClk)
401	if (!Reset_L) rO_EccData4 <= 24'h0;
402	else if (ReOrder_ClearEccError) rO_EccData4 <= 24'h0;
403	else if (WrReOrderEccData4) rO_EccData4 <= PioDataIn[23:0];
404	else if (rO_loadEccError) rO_EccData4 <= ro_ECCDataOut[151:128];
405
406	/--------------------------------------------------------------/
407	// SF Latching of ECC Errors
408	/--------------------------------------------------------------/
409	assign StoreForward_EccData = {sF_EccData4, sF_EccData3, sF_EccData2,
410	sF_EccData1, sF_EccData0
411	};
412
413
414	assign StoreForward_ECC_State = {14'h0, sF_CorrectError,
415	sF_UnCorrectError, 6'b0, sF_EccAddr};
416
417	assign sF_loadEccError = (storeForward_FifoDataValid
418	&
419	(storeForward_CorrectError
420	\|
421	StoreForward_UnCorrectError
422	)
423	&
424	~sF_ErrorValid
425	);
426
427
428	always @ (posedge SysClk)
429	if (!Reset_L) sF_ErrorValid <= 1'b0;
430	else if (StoreForward_ClearEccError) sF_ErrorValid <= 1'b0;
431	else if (sF_loadEccError) sF_ErrorValid <= 1'b1;
432
433	always @ (posedge SysClk)
434	if (!Reset_L)
435	sF_CorrectError <= 1'b0;
436	else if (StoreForward_ClearEccError)
437	sF_CorrectError <= 1'b0;
438	else if (WrStoreForwardEccState)
439	sF_CorrectError <= PioDataIn[17];
440	else if (sF_loadEccError)
441	sF_CorrectError <= storeForward_CorrectError;
442
443	always @ (posedge SysClk)
444	if (!Reset_L)
445	sF_UnCorrectError <= 1'b0;
446	else if (StoreForward_ClearEccError)
447	sF_UnCorrectError <= 1'b0;
448	else if (WrStoreForwardEccState)
449	sF_UnCorrectError <= PioDataIn[16];
450	else if (sF_loadEccError)
451	sF_UnCorrectError <= StoreForward_UnCorrectError;
452
453	always @ (posedge SysClk)
454	if (!Reset_L) sF_EccAddr <= 10'b0;
455	else if (StoreForward_ClearEccError) sF_EccAddr <= 10'h0;
456	else if (WrStoreForwardEccState) sF_EccAddr <= PioDataIn[9:0];
457	else if (sF_loadEccError) sF_EccAddr <= storeForward_ReadAddrD1;
458
459	always @ (posedge SysClk)
460	if (!Reset_L) sF_EccData0 <= 32'h0;
461	else if (StoreForward_ClearEccError) sF_EccData0 <= 32'h0;
462	else if (WrStoreForwardEccData0) sF_EccData0 <= PioDataIn[31:0];
463	else if (sF_loadEccError) sF_EccData0 <= sf_ECCDataOut[31:0];
464
465	always @ (posedge SysClk)
466	if (!Reset_L) sF_EccData1 <= 32'h0;
467	else if (StoreForward_ClearEccError) sF_EccData1 <= 32'h0;
468	else if (WrStoreForwardEccData1) sF_EccData1 <= PioDataIn[31:0];
469	else if (sF_loadEccError) sF_EccData1 <= sf_ECCDataOut[63:32];
470
471	always @ (posedge SysClk)
472	if (!Reset_L) sF_EccData2 <= 32'h0;
473	else if (StoreForward_ClearEccError) sF_EccData2 <= 32'h0;
474	else if (WrStoreForwardEccData2) sF_EccData2 <= PioDataIn[31:0];
475	else if (sF_loadEccError) sF_EccData2 <= sf_ECCDataOut[95:64];
476
477	always @ (posedge SysClk)
478	if (!Reset_L) sF_EccData3 <= 32'h0;
479	else if (StoreForward_ClearEccError) sF_EccData3 <= 32'h0;
480	else if (WrStoreForwardEccData3) sF_EccData3 <= PioDataIn[31:0];
481	else if (sF_loadEccError) sF_EccData3 <= sf_ECCDataOut[127:96];
482
483	always @ (posedge SysClk)
484	if (!Reset_L) sF_EccData4 <= 24'h0;
485	else if (StoreForward_ClearEccError) sF_EccData4 <= 24'h0;
486	else if (WrStoreForwardEccData4) sF_EccData4 <= PioDataIn[23:0];
487	else if (sF_loadEccError) sF_EccData4 <= sf_ECCDataOut[151:128];
488
489	/--------------------------------------------------------------/
490	// Modules
491	/--------------------------------------------------------------/
492
493	niu_txc_ecc_generate niu_txc_RO_ecc_generate1 (
494	.din (ReOrder_PreECCData[135:68]),
495	.dout (ro_PostECCData1)
496	);
497
498	niu_txc_ecc_generate niu_txc_RO_ecc_generate0 (
499	.din (ReOrder_PreECCData[67:0]),
500	.dout (ro_PostECCData0)
501	);
502
503	niu_txc_ecc_syndrome niu_txc_RO_ecc_syndrome1 (
504	.din (reOrder_FifoDataOutD1),
505	.syn (reOrder_ECCSyn1)
506	);
507
508	niu_txc_ecc_syndrome niu_txc_RO_ecc_syndrome0 (
509	.din (reOrder_FifoDataOutD0),
510	.syn (reOrder_ECCSyn0)
511	);
512
513	niu_txc_ecc_correct niu_txc_RO_ecc_correct1 (
514	.din (reOrder_FifoDataOutD1),
515	.syn (reOrder_ECCSyn1),
516	.dout (ro_ECCDataOut1),
517	.no_error (),
518	.error (),
519	.corr_error (reOrder_CorrectError1),
520	.uncorr_error (reOrder_UnCorrectError1)
521	);
522
523	niu_txc_ecc_correct niu_txc_RO_ecc_correct0 (
524	.din (reOrder_FifoDataOutD0),
525	.syn (reOrder_ECCSyn0),
526	.dout (ro_ECCDataOut0),
527	.no_error (),
528	.error (),
529	.corr_error (reOrder_CorrectError0),
530	.uncorr_error (reOrder_UnCorrectError0)
531	);
532
533	niu_txc_ecc_generate niu_txc_SF_ecc_generate1 (
534	.din (StoreForward_PreECCData[135:68]),
535	.dout (sf_PostECCData1)
536	);
537
538	niu_txc_ecc_generate niu_txc_SF_ecc_generate0 (
539	.din (StoreForward_PreECCData[67:0]),
540	.dout (sf_PostECCData0)
541	);
542
543	niu_txc_ecc_syndrome niu_txc_SF_ecc_syndrome1 (
544	.din (storeForward_FifoDataOutD1),
545	.syn (storeForward_ECCSyn1)
546	);
547
548	niu_txc_ecc_syndrome niu_txc_SF_ecc_syndrome0 (
549	.din (storeForward_FifoDataOutD0),
550	.syn (storeForward_ECCSyn0)
551	);
552
553	niu_txc_ecc_correct niu_txc_SF_ecc_correct1 (
554	.din (storeForward_FifoDataOutD1),
555	.syn (storeForward_ECCSyn1),
556	.dout (sf_ECCDataOut1),
557	.no_error (),
558	.error (),
559	.corr_error (storeForward_CorrectError1),
560	.uncorr_error (storeForward_UnCorrectError1)
561	);
562
563	niu_txc_ecc_correct niu_txc_SF_ecc_correct0 (
564	.din (storeForward_FifoDataOutD0),
565	.syn (storeForward_ECCSyn0),
566	.dout (sf_ECCDataOut0),
567	.no_error (),
568	.error (),
569	.corr_error (storeForward_CorrectError0),
570	.uncorr_error (storeForward_UnCorrectError0)
571	);
572
573	endmodule