[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_txc_mac_transfer.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu_txc_mac_transfer.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
/*********************************************************************
 *
 *  niu_txc_mac_transfer.v
 *
 *  MAC_ Transfer State Machine
 *
 *  Orignal Author(s):   Rahoul Puri
 *  Modifier(s):
 *  Project(s):          Neptune
 *
 *  Copyright (c) 2004   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/

`include "timescale.v"

module niu_txc_mac_transfer (
        SysClk,              // Clock
        Reset_L,             // Reset_L
        Txc_Enabled,         // NTx Enable
        EnableGMACMode,      // Enable GMAC Mode only

        DisableEccCheking,
        UnCorrectError,
        FifoEmpty,           // Fifo empty signal from the fifo
        FifoDataOut,         // Data word from the Fifo
        FifoRead,            // Fifo read signal

        ClearStatistics,     // Clear All Statistics
        WrPacketXmitted,
        PioDataIn,
        PacketsTransmitted,  // Number of packets transmitted
        BytesTransmitted,    // Number of bytes in the packet transmitted

        MAC_Req,             // Data request from the MAC
        MAC_Ack,             // Ack signal to MAC
        MAC_Tag,             // Tag signal to MAC
        MAC_Abort,           // Abort signal to MAC
        MAC_Status,          // Status to MAC
        MAC_Data,            // Data request from the MAC
        Mac_Xfer_State
       );

`include "txc_defines.h"

// Global signals
input         SysClk;
input         Reset_L;
input         Txc_Enabled;
input         EnableGMACMode;

// Control Reg Interface
input         DisableEccCheking;

// Fifo Interface
input         UnCorrectError;
input         FifoEmpty;
input [135:0] FifoDataOut;

output        FifoRead;

reg           FifoRead;

// Control Register Interface
input         ClearStatistics;
input         WrPacketXmitted;
input [31:0]  PioDataIn;

output [15:0] PacketsTransmitted;
output [15:0] BytesTransmitted;

reg    [15:0] PacketsTransmitted;
reg    [15:0] BytesTransmitted;

// MAC Interface
input         MAC_Req;

output        MAC_Ack;
output        MAC_Tag;
output        MAC_Abort;
output [3:0]  MAC_Status;
output [63:0] MAC_Data;

reg           MAC_Ack;
reg           MAC_Tag;
reg           MAC_Abort;
reg    [3:0]  MAC_Status;
reg    [63:0] MAC_Data;

// MAC Interface
output [3:0]  Mac_Xfer_State;

reg    [3:0]  Mac_Xfer_State;

/*--------------------------------------------------------------*/
// Reg & Wires
/*--------------------------------------------------------------*/
wire        lastLineOfPacket;
wire        packetEndsOnLowBits;
wire        par_error;
wire        abortPacket;
wire        collisionXmit;
wire        collisionBytes;
wire [3:0]  straddleBytesOne;
wire [3:0]  straddleBytesTwo;
wire [63:0] gigMACStatus; 

reg         packetEndsOnHighBits;
reg         latchedAbort;
reg         parityError;
reg         fifoWasEmpty;
reg         detectedFifoEmpty;
reg         macAck;
reg         macTag;
reg         macAbort;
reg         ldFifoDataOut;
reg         clearAllState;
reg         setFifoWasEmpty;
reg         clrFifoWasEmpty;
reg         setDetectedFifoEmpty;
reg         clrDetectedFifoEmpty;
reg         incPacketsTransmitted;
reg         addEightBytes;
reg         addStraddleOne;
reg         addStraddleTwo;
reg         ldStatus;
reg         ldLatchedStatus;
reg         ldFifoHBits;
reg         ldGigMACStatus;
reg  [3:0]  nextXferState;
reg  [3:0]  latchedStatus;
reg  [63:0] fifoHBits; 

/*--------------------------------------------------------------*/
// Parameters and Defines
/*--------------------------------------------------------------*/
parameter  MAC_XFER_IDLE            = 4'h0,
           CHECK_FIFO               = 4'h1,
           XFER_LOW_BITS_0          = 4'h2,
           XFER_HIGH_BITS_0         = 4'h3,
           XFER_LOW_BITS_1          = 4'h4,
           XFER_HIGH_BITS_1         = 4'h5,
           WAIT_FOR_NO_REQ          = 4'h6,
           CHECK_FOR_BURST_REQ      = 4'h7,
           CHECK_FOR_REQ            = 4'h8,
           XFER_STATUS              = 4'h9,
           WAIT_FOR_REQ_LOW         = 4'hA, 
           WAIT_FOR_COUNT_DEC       = 4'hB, 
           WAIT_FOR_FIFO            = 4'hF;

//VCS coverage off
// synopsys translate_off
reg [192:1] TRANSFER_STATE;


always @(Mac_Xfer_State)
begin
  case(Mac_Xfer_State)
    MAC_XFER_IDLE :               TRANSFER_STATE = "MAC_XFER_IDLE";
    CHECK_FIFO:                   TRANSFER_STATE = "CHECK_FIFO";
    XFER_LOW_BITS_0:              TRANSFER_STATE = "XFER_LOW_BITS_0";
    XFER_HIGH_BITS_0:             TRANSFER_STATE = "XFER_HIGH_BITS_0";
    XFER_LOW_BITS_1:              TRANSFER_STATE = "XFER_LOW_BITS_1";
    XFER_HIGH_BITS_1:             TRANSFER_STATE = "XFER_HIGH_BITS_1";
    WAIT_FOR_NO_REQ:              TRANSFER_STATE = "WAIT_FOR_NO_REQ";
    CHECK_FOR_BURST_REQ:          TRANSFER_STATE = "CHECK_FOR_BURST_REQ";
    CHECK_FOR_REQ:                TRANSFER_STATE = "CHECK_FOR_REQ";
    XFER_STATUS:                  TRANSFER_STATE = "XFER_STATUS";
    WAIT_FOR_REQ_LOW:             TRANSFER_STATE = "WAIT_FOR_REQ_LOW";
    WAIT_FOR_COUNT_DEC:           TRANSFER_STATE = "WAIT_FOR_COUNT_DEC";
    WAIT_FOR_FIFO:                TRANSFER_STATE = "WAIT_FOR_FIFO";
       default :    TRANSFER_STATE = "UNKNOWN";
  endcase
end

// synopsys translate_on
//VCS coverage on


/*--------------------------------------------------------------*/
// Zero In Checks
/*--------------------------------------------------------------*/

/*--------------------------------------------------------------*/
// Assigns
/*--------------------------------------------------------------*/
assign lastLineOfPacket    = (FifoDataOut[128] | FifoDataOut[135]);
assign packetEndsOnLowBits = FifoDataOut[134];

assign gigMACStatus = {(latchedAbort | parityError), latchedStatus, 59'h0};

assign abortPacket = (parityError | par_error);

/*--------------------------------------------------------------*/
// Parity Check on Incoming Data
/*--------------------------------------------------------------*/
assign par_error = (UnCorrectError & ~DisableEccCheking);

/*--------------------------------------------------------------*/
// Straddle Bytes
/*--------------------------------------------------------------*/
assign straddleBytesOne = ({1'b0,FifoDataOut[132:130]} + 4'h1);
assign straddleBytesTwo = ({1'b0,latchedStatus[2:0]} + 4'h1);

/*--------------------------------------------------------------*/
// Control Logic
/*--------------------------------------------------------------*/
assign collisionXmit  = ClearStatistics & incPacketsTransmitted;
assign collisionBytes = (ClearStatistics & (addEightBytes
                                            |
                                            addStraddleOne
                                            |
                                            addStraddleTwo
                                           )
                        );

always @ (posedge SysClk)
  if (!Reset_L)                   PacketsTransmitted <= 16'b0;
  else if (collisionXmit)         PacketsTransmitted <= #`SD 16'h1;
  else if (ClearStatistics)       PacketsTransmitted <= #`SD 16'h0;
  else if (WrPacketXmitted)       PacketsTransmitted <= #`SD PioDataIn[15:0];
  else if (incPacketsTransmitted) PacketsTransmitted <= #`SD PacketsTransmitted
                                                             +
                                                             16'b1;

always @ (posedge SysClk)
  if (!Reset_L)           parityError <= 1'b0;
  else if (ldFifoDataOut) parityError <= #`SD parityError | par_error;
  else if (clearAllState) parityError <= #`SD 1'b0;

always @ (posedge SysClk)
  if (!Reset_L)             fifoWasEmpty <= 1'b0;
  else if (setFifoWasEmpty) fifoWasEmpty <= #`SD 1'b1;
  else if (clrFifoWasEmpty) fifoWasEmpty <= #`SD 1'b0;

always @ (posedge SysClk)
  if (!Reset_L)                  detectedFifoEmpty <= 1'b0;
  else if (setDetectedFifoEmpty) detectedFifoEmpty <= #`SD 1'b1;
  else if (clrDetectedFifoEmpty) detectedFifoEmpty <= #`SD 1'b0;

always @ (posedge SysClk)
  if (!Reset_L)             BytesTransmitted <= 16'b0;
  else if (collisionBytes)
    begin
      if (addEightBytes)       BytesTransmitted <= #`SD 16'd8;
      else if (addStraddleOne) BytesTransmitted <= #`SD {12'h0,
                                                         straddleBytesOne};

      else if (addStraddleTwo) BytesTransmitted <= #`SD {12'h0,
                                                         straddleBytesTwo};
    end
  else if (ClearStatistics) BytesTransmitted <= #`SD 16'h0;
  else if (WrPacketXmitted) BytesTransmitted <= #`SD PioDataIn[31:16];
  else if (addEightBytes)   BytesTransmitted <= #`SD BytesTransmitted + 16'd8;
  else if (addStraddleOne)  BytesTransmitted <= #`SD BytesTransmitted
                                                     +
                                                     {12'h0, straddleBytesOne};

  else if (addStraddleTwo)  BytesTransmitted <= #`SD BytesTransmitted
                                                     +
                                                     {12'h0, straddleBytesTwo};

always @ (posedge SysClk)
  if (!Reset_L)           packetEndsOnHighBits <= 1'b0;
  else if (ldFifoDataOut) packetEndsOnHighBits <= #`SD lastLineOfPacket;
  else if (clearAllState) packetEndsOnHighBits <= #`SD 1'b0;

always @ (posedge SysClk)
  if (!Reset_L)           latchedAbort <= #`SD 1'b0;
  else if (ldFifoDataOut) latchedAbort <= #`SD FifoDataOut[129];
  else if (clearAllState) latchedAbort <= #`SD 1'b0;

always @ (posedge SysClk)
  if (!Reset_L)           latchedStatus <= #`SD 4'h0;
  else if (ldFifoDataOut) latchedStatus <= #`SD FifoDataOut[133:130];
  else if (clearAllState) latchedStatus <= #`SD 4'h0;

always @ (posedge SysClk)
  if (!Reset_L)           fifoHBits <= #`SD 64'h0;
  else if (ldFifoDataOut) fifoHBits <= #`SD FifoDataOut[127:64]; 
  else if (clearAllState) fifoHBits <= #`SD 64'b0;

/*--------------------------------------------------------------*/
// MAC Transfer Interface Logic
/*--------------------------------------------------------------*/
always @ (posedge SysClk)
  if (!Reset_L) MAC_Ack <= 1'b0;
  else          MAC_Ack <= #`SD macAck;

always @ (posedge SysClk)
  if (!Reset_L) MAC_Tag <= 1'b0;
  else          MAC_Tag <= #`SD macTag;

always @ (posedge SysClk)
  if (!Reset_L) MAC_Abort <= 1'b0;
  else          MAC_Abort <= #`SD macAbort;

always @ (posedge SysClk)
  if (!Reset_L)             MAC_Status <= #`SD 4'h0;
  else if (ldStatus)        MAC_Status <= #`SD FifoDataOut[133:130];
  else if (ldLatchedStatus) MAC_Status <= #`SD latchedStatus;
  else if (clearAllState)   MAC_Status <= #`SD 4'h0;

always @ (posedge SysClk)
  if (!Reset_L)            MAC_Data <= #`SD 64'h0;
  else if (ldFifoDataOut)  MAC_Data <= #`SD FifoDataOut[63:0]; 
  else if (ldFifoHBits)    MAC_Data <= #`SD fifoHBits; 
  else if (ldGigMACStatus) MAC_Data <= #`SD gigMACStatus;
  else if (clearAllState)  MAC_Data <= 64'h0;

/*--------------------------------------------------------------*/
// Mac Xfer State Vectors
/*--------------------------------------------------------------*/
always @(posedge SysClk)
  if (!Reset_L) Mac_Xfer_State <= #`SD MAC_XFER_IDLE;
  else          Mac_Xfer_State <= #`SD nextXferState;

/*--------------------------------------------------------------*/
// MAC_ Transfer State Machine
/*--------------------------------------------------------------*/
function [3:0] XferDefaults;
input [3:0] currentState;
  begin
    XferDefaults = currentState;
    FifoRead = 1'b0;
    macAck = 1'b0;
    macTag = 1'b0;
    macAbort = 1'b0;
    ldFifoDataOut = 1'b0;
    clearAllState = 1'b0;
    setFifoWasEmpty = 1'b0;
    clrFifoWasEmpty = 1'b0;
    setDetectedFifoEmpty = 1'b0;
    clrDetectedFifoEmpty = 1'b0;
    incPacketsTransmitted = 1'b0;
    addEightBytes = 1'b0;
    addStraddleOne = 1'b0;
    addStraddleTwo = 1'b0;
    ldStatus = 1'b0;
    ldLatchedStatus  = 1'b0;
    ldFifoHBits = 1'b0;
    ldGigMACStatus = 1'b0;
  end
endfunction


always @(/*AUTOSENSE*/Mac_Xfer_State or Txc_Enabled
         or MAC_Req or FifoEmpty or EnableGMACMode
         or lastLineOfPacket or packetEndsOnLowBits
         or FifoDataOut or abortPacket
         or packetEndsOnHighBits or detectedFifoEmpty
         or fifoWasEmpty or parityError
         or latchedAbort or MAC_Abort
        )
    begin
      case(Mac_Xfer_State) // synopsys full_case parallel_case
                           /* 0in < case -full -parallel */
        MAC_XFER_IDLE:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);

            if (Txc_Enabled)
              begin
                if (MAC_Req)
                  begin
                    if (~FifoEmpty)
                      begin
                        FifoRead = 1'b1;
                        nextXferState = CHECK_FIFO;
                      end
                  end
              end
          end


        CHECK_FIFO:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);

            if (MAC_Req | EnableGMACMode)
              begin
                if (~FifoEmpty | lastLineOfPacket)
                  nextXferState = XFER_LOW_BITS_0;
              end
           end

        XFER_LOW_BITS_0:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);
            ldFifoDataOut = 1'b1;

            if (MAC_Req | EnableGMACMode)
              begin
                macAck = 1'b1; 

                if (lastLineOfPacket & packetEndsOnLowBits)
                  begin         
                    macAbort = (FifoDataOut[129] | abortPacket);
                    ldStatus = 1'b1;
                    macTag   = 1'b1;
                    incPacketsTransmitted = 1'b1;
                    addStraddleOne = 1'b1;

                    if (EnableGMACMode)
                      nextXferState = XFER_STATUS;
                    else
                      nextXferState = WAIT_FOR_COUNT_DEC;
                  end         
                else
                  begin
                    nextXferState = XFER_HIGH_BITS_0;
                    addEightBytes = 1'b1;
                  end

                if (~lastLineOfPacket)
                  begin
                    if (FifoEmpty)
                      setDetectedFifoEmpty = 1'b1;
                    else
                      FifoRead = 1'b1;
                  end
              end
          end


        XFER_HIGH_BITS_0:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);

            if (MAC_Req | EnableGMACMode)
              begin
                macAck = 1'b1; 
                ldFifoHBits = 1'b1;

                if (packetEndsOnHighBits) 
                  begin 
                    macTag   = 1'b1;
                    macAbort = (latchedAbort | parityError);
                    ldLatchedStatus  = 1'b1;
                    incPacketsTransmitted = 1'b1;
                    addStraddleTwo = 1'b1;

                    if (EnableGMACMode)
                      nextXferState = XFER_STATUS;
                    else
                      nextXferState = WAIT_FOR_COUNT_DEC;
                  end 
                else // if (!packetEndsOnHighBits)
                  begin
                    if (EnableGMACMode)
                      nextXferState = XFER_LOW_BITS_1;
                    else if (detectedFifoEmpty)
                      nextXferState = WAIT_FOR_FIFO;
                    else 
                    //else if (~FifoEmpty)
                      nextXferState = XFER_LOW_BITS_0;
                    //else 
                    //  nextXferState = CHECK_FIFO;

                    addEightBytes = 1'b1;
                  end
              end 
          end


        XFER_LOW_BITS_1:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);
            macAck = 1'b1; 
            ldFifoDataOut = 1'b1;

            if (~lastLineOfPacket)
              begin
                if (~FifoEmpty)
                  FifoRead = 1'b1;
                else
                  setFifoWasEmpty = 1'b1;
              end

            if (lastLineOfPacket & packetEndsOnLowBits)
              begin         
                macTag   = 1'b1;
                incPacketsTransmitted = 1'b1;
                addStraddleOne = 1'b1;
                nextXferState = XFER_STATUS;
              end         
            else
              begin
                nextXferState = XFER_HIGH_BITS_1;
                addEightBytes = 1'b1;
              end
          end


        XFER_HIGH_BITS_1:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);
            macAck = 1'b1; 
            ldFifoHBits = 1'b1;
            nextXferState = WAIT_FOR_NO_REQ;
 
            if (fifoWasEmpty & ~FifoEmpty)
              begin
                FifoRead = 1'b1;
                clrFifoWasEmpty = 1'b1;
              end

            if (packetEndsOnHighBits)
              begin 
                macTag   = 1'b1;
                incPacketsTransmitted = 1'b1;
                addStraddleTwo = 1'b1;
              end 
            else
              addEightBytes = 1'b1;
          end


        WAIT_FOR_NO_REQ:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);

            if (fifoWasEmpty & ~FifoEmpty)
              begin
                FifoRead = 1'b1;
                clrFifoWasEmpty = 1'b0;
              end

            if (!MAC_Req)
              begin
                if (packetEndsOnHighBits)
                  nextXferState = CHECK_FOR_REQ;
                else
                  nextXferState = CHECK_FOR_BURST_REQ;
              end
          end


        CHECK_FOR_BURST_REQ:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);

            if (MAC_Req)
              begin
                if (fifoWasEmpty)
                  begin
                    if (~FifoEmpty)
                      begin
                        FifoRead = 1'b1;
                        clrFifoWasEmpty = 1'b1;
                        nextXferState = CHECK_FIFO;
                      end
                  end
                else if (~FifoEmpty | lastLineOfPacket)
                  nextXferState = XFER_LOW_BITS_0;
              end
          end


        CHECK_FOR_REQ:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);

            if (MAC_Req)
              nextXferState = XFER_STATUS;
          end


        XFER_STATUS:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);
            macAck = 1'b1; 
            macTag   = 1'b1;
            macAbort = MAC_Abort; // Don't know if need this
            ldGigMACStatus = 1'b1;
            nextXferState = WAIT_FOR_REQ_LOW;
          end


        WAIT_FOR_REQ_LOW:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);
            clearAllState = 1'b1;

            if (!MAC_Req)
              nextXferState = MAC_XFER_IDLE;
          end


        WAIT_FOR_COUNT_DEC:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);
            clearAllState = 1'b1;
            nextXferState = MAC_XFER_IDLE;
          end


        WAIT_FOR_FIFO:
          begin
            nextXferState = XferDefaults(Mac_Xfer_State);
            clrDetectedFifoEmpty = 1'b1;

            if (MAC_Req)
              begin
                if (~FifoEmpty)
                  begin
                    FifoRead = 1'b1;   
                    nextXferState = CHECK_FIFO;
                  end
              end
          end

      endcase
    end

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: niu_txc_mac_transfer.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	/*********************************************************************
	36	*
	37	* niu_txc_mac_transfer.v
	38	*
	39	* MAC_ Transfer State Machine
	40	*
	41	* Orignal Author(s): Rahoul Puri
	42	* Modifier(s):
	43	* Project(s): Neptune
	44	*
	45	* Copyright (c) 2004 Sun Microsystems, Inc.
	46	*
	47	* All Rights Reserved.
	48	*
	49	* This verilog model is the confidential and proprietary property of
	50	* Sun Microsystems, Inc., and the possession or use of this model
	51	* requires a written license from Sun Microsystems, Inc.
	52	*
	53	**********************************************************************/
	54
	55	`include "timescale.v"
	56
	57	module niu_txc_mac_transfer (
	58	SysClk, // Clock
	59	Reset_L, // Reset_L
	60	Txc_Enabled, // NTx Enable
	61	EnableGMACMode, // Enable GMAC Mode only
	62
	63	DisableEccCheking,
	64	UnCorrectError,
65	FifoEmpty, // Fifo empty signal from the fifo
66	FifoDataOut, // Data word from the Fifo
67	FifoRead, // Fifo read signal
68
69	ClearStatistics, // Clear All Statistics
70	WrPacketXmitted,
71	PioDataIn,
72	PacketsTransmitted, // Number of packets transmitted
73	BytesTransmitted, // Number of bytes in the packet transmitted
74
75	MAC_Req, // Data request from the MAC
76	MAC_Ack, // Ack signal to MAC
77	MAC_Tag, // Tag signal to MAC
78	MAC_Abort, // Abort signal to MAC
79	MAC_Status, // Status to MAC
80	MAC_Data, // Data request from the MAC
81	Mac_Xfer_State
82	);
83
84	`include "txc_defines.h"
85
86	// Global signals
87	input SysClk;
88	input Reset_L;
89	input Txc_Enabled;
90	input EnableGMACMode;
91
92	// Control Reg Interface
93	input DisableEccCheking;
94
95	// Fifo Interface
96	input UnCorrectError;
97	input FifoEmpty;
98	input [135:0] FifoDataOut;
99
100	output FifoRead;
101
102	reg FifoRead;
103
104	// Control Register Interface
105	input ClearStatistics;
106	input WrPacketXmitted;
107	input [31:0] PioDataIn;
108
109	output [15:0] PacketsTransmitted;
110	output [15:0] BytesTransmitted;
111
112	reg [15:0] PacketsTransmitted;
113	reg [15:0] BytesTransmitted;
114
115	// MAC Interface
116	input MAC_Req;
117
118	output MAC_Ack;
119	output MAC_Tag;
120	output MAC_Abort;
121	output [3:0] MAC_Status;
122	output [63:0] MAC_Data;
123
124	reg MAC_Ack;
125	reg MAC_Tag;
126	reg MAC_Abort;
127	reg [3:0] MAC_Status;
128	reg [63:0] MAC_Data;
129
130	// MAC Interface
131	output [3:0] Mac_Xfer_State;
132
133	reg [3:0] Mac_Xfer_State;
134
135	/--------------------------------------------------------------/
136	// Reg & Wires
137	/--------------------------------------------------------------/
138	wire lastLineOfPacket;
139	wire packetEndsOnLowBits;
140	wire par_error;
141	wire abortPacket;
142	wire collisionXmit;
143	wire collisionBytes;
144	wire [3:0] straddleBytesOne;
145	wire [3:0] straddleBytesTwo;
146	wire [63:0] gigMACStatus;
147
148	reg packetEndsOnHighBits;
149	reg latchedAbort;
150	reg parityError;
151	reg fifoWasEmpty;
152	reg detectedFifoEmpty;
153	reg macAck;
154	reg macTag;
155	reg macAbort;
156	reg ldFifoDataOut;
157	reg clearAllState;
158	reg setFifoWasEmpty;
159	reg clrFifoWasEmpty;
160	reg setDetectedFifoEmpty;
161	reg clrDetectedFifoEmpty;
162	reg incPacketsTransmitted;
163	reg addEightBytes;
164	reg addStraddleOne;
165	reg addStraddleTwo;
166	reg ldStatus;
167	reg ldLatchedStatus;
168	reg ldFifoHBits;
169	reg ldGigMACStatus;
170	reg [3:0] nextXferState;
171	reg [3:0] latchedStatus;
172	reg [63:0] fifoHBits;
173
174	/--------------------------------------------------------------/
175	// Parameters and Defines
176	/--------------------------------------------------------------/
177	parameter MAC_XFER_IDLE = 4'h0,
178	CHECK_FIFO = 4'h1,
179	XFER_LOW_BITS_0 = 4'h2,
180	XFER_HIGH_BITS_0 = 4'h3,
181	XFER_LOW_BITS_1 = 4'h4,
182	XFER_HIGH_BITS_1 = 4'h5,
183	WAIT_FOR_NO_REQ = 4'h6,
184	CHECK_FOR_BURST_REQ = 4'h7,
185	CHECK_FOR_REQ = 4'h8,
186	XFER_STATUS = 4'h9,
187	WAIT_FOR_REQ_LOW = 4'hA,
188	WAIT_FOR_COUNT_DEC = 4'hB,
189	WAIT_FOR_FIFO = 4'hF;
190
191	//VCS coverage off
192	// synopsys translate_off
193	reg [192:1] TRANSFER_STATE;
194
195
196	always @(Mac_Xfer_State)
197	begin
198	case(Mac_Xfer_State)
199	MAC_XFER_IDLE : TRANSFER_STATE = "MAC_XFER_IDLE";
200	CHECK_FIFO: TRANSFER_STATE = "CHECK_FIFO";
201	XFER_LOW_BITS_0: TRANSFER_STATE = "XFER_LOW_BITS_0";
202	XFER_HIGH_BITS_0: TRANSFER_STATE = "XFER_HIGH_BITS_0";
203	XFER_LOW_BITS_1: TRANSFER_STATE = "XFER_LOW_BITS_1";
204	XFER_HIGH_BITS_1: TRANSFER_STATE = "XFER_HIGH_BITS_1";
205	WAIT_FOR_NO_REQ: TRANSFER_STATE = "WAIT_FOR_NO_REQ";
206	CHECK_FOR_BURST_REQ: TRANSFER_STATE = "CHECK_FOR_BURST_REQ";
207	CHECK_FOR_REQ: TRANSFER_STATE = "CHECK_FOR_REQ";
208	XFER_STATUS: TRANSFER_STATE = "XFER_STATUS";
209	WAIT_FOR_REQ_LOW: TRANSFER_STATE = "WAIT_FOR_REQ_LOW";
210	WAIT_FOR_COUNT_DEC: TRANSFER_STATE = "WAIT_FOR_COUNT_DEC";
211	WAIT_FOR_FIFO: TRANSFER_STATE = "WAIT_FOR_FIFO";
212	default : TRANSFER_STATE = "UNKNOWN";
213	endcase
214	end
215
216	// synopsys translate_on
217	//VCS coverage on
218
219
220	/--------------------------------------------------------------/
221	// Zero In Checks
222	/--------------------------------------------------------------/
223
224	/--------------------------------------------------------------/
225	// Assigns
226	/--------------------------------------------------------------/
227	assign lastLineOfPacket = (FifoDataOut[128] \| FifoDataOut[135]);
228	assign packetEndsOnLowBits = FifoDataOut[134];
229
230	assign gigMACStatus = {(latchedAbort \| parityError), latchedStatus, 59'h0};
231
232	assign abortPacket = (parityError \| par_error);
233
234	/--------------------------------------------------------------/
235	// Parity Check on Incoming Data
236	/--------------------------------------------------------------/
237	assign par_error = (UnCorrectError & ~DisableEccCheking);
238
239	/--------------------------------------------------------------/
240	// Straddle Bytes
241	/--------------------------------------------------------------/
242	assign straddleBytesOne = ({1'b0,FifoDataOut[132:130]} + 4'h1);
243	assign straddleBytesTwo = ({1'b0,latchedStatus[2:0]} + 4'h1);
244
245	/--------------------------------------------------------------/
246	// Control Logic
247	/--------------------------------------------------------------/
248	assign collisionXmit = ClearStatistics & incPacketsTransmitted;
249	assign collisionBytes = (ClearStatistics & (addEightBytes
250	\|
251	addStraddleOne
252	\|
253	addStraddleTwo
254	)
255	);
256
257	always @ (posedge SysClk)
258	if (!Reset_L) PacketsTransmitted <= 16'b0;
259	else if (collisionXmit) PacketsTransmitted <= #`SD 16'h1;
260	else if (ClearStatistics) PacketsTransmitted <= #`SD 16'h0;
261	else if (WrPacketXmitted) PacketsTransmitted <= #`SD PioDataIn[15:0];
262	else if (incPacketsTransmitted) PacketsTransmitted <= #`SD PacketsTransmitted
263	+
264	16'b1;
265
266	always @ (posedge SysClk)
267	if (!Reset_L) parityError <= 1'b0;
268	else if (ldFifoDataOut) parityError <= #`SD parityError \| par_error;
269	else if (clearAllState) parityError <= #`SD 1'b0;
270
271	always @ (posedge SysClk)
272	if (!Reset_L) fifoWasEmpty <= 1'b0;
273	else if (setFifoWasEmpty) fifoWasEmpty <= #`SD 1'b1;
274	else if (clrFifoWasEmpty) fifoWasEmpty <= #`SD 1'b0;
275
276	always @ (posedge SysClk)
277	if (!Reset_L) detectedFifoEmpty <= 1'b0;
278	else if (setDetectedFifoEmpty) detectedFifoEmpty <= #`SD 1'b1;
279	else if (clrDetectedFifoEmpty) detectedFifoEmpty <= #`SD 1'b0;
280
281	always @ (posedge SysClk)
282	if (!Reset_L) BytesTransmitted <= 16'b0;
283	else if (collisionBytes)
284	begin
285	if (addEightBytes) BytesTransmitted <= #`SD 16'd8;
286	else if (addStraddleOne) BytesTransmitted <= #`SD {12'h0,
287	straddleBytesOne};
288
289	else if (addStraddleTwo) BytesTransmitted <= #`SD {12'h0,
290	straddleBytesTwo};
291	end
292	else if (ClearStatistics) BytesTransmitted <= #`SD 16'h0;
293	else if (WrPacketXmitted) BytesTransmitted <= #`SD PioDataIn[31:16];
294	else if (addEightBytes) BytesTransmitted <= #`SD BytesTransmitted + 16'd8;
295	else if (addStraddleOne) BytesTransmitted <= #`SD BytesTransmitted
296	+
297	{12'h0, straddleBytesOne};
298
299	else if (addStraddleTwo) BytesTransmitted <= #`SD BytesTransmitted
300	+
301	{12'h0, straddleBytesTwo};
302
303	always @ (posedge SysClk)
304	if (!Reset_L) packetEndsOnHighBits <= 1'b0;
305	else if (ldFifoDataOut) packetEndsOnHighBits <= #`SD lastLineOfPacket;
306	else if (clearAllState) packetEndsOnHighBits <= #`SD 1'b0;
307
308	always @ (posedge SysClk)
309	if (!Reset_L) latchedAbort <= #`SD 1'b0;
310	else if (ldFifoDataOut) latchedAbort <= #`SD FifoDataOut[129];
311	else if (clearAllState) latchedAbort <= #`SD 1'b0;
312
313	always @ (posedge SysClk)
314	if (!Reset_L) latchedStatus <= #`SD 4'h0;
315	else if (ldFifoDataOut) latchedStatus <= #`SD FifoDataOut[133:130];
316	else if (clearAllState) latchedStatus <= #`SD 4'h0;
317
318	always @ (posedge SysClk)
319	if (!Reset_L) fifoHBits <= #`SD 64'h0;
320	else if (ldFifoDataOut) fifoHBits <= #`SD FifoDataOut[127:64];
321	else if (clearAllState) fifoHBits <= #`SD 64'b0;
322
323	/--------------------------------------------------------------/
324	// MAC Transfer Interface Logic
325	/--------------------------------------------------------------/
326	always @ (posedge SysClk)
327	if (!Reset_L) MAC_Ack <= 1'b0;
328	else MAC_Ack <= #`SD macAck;
329
330	always @ (posedge SysClk)
331	if (!Reset_L) MAC_Tag <= 1'b0;
332	else MAC_Tag <= #`SD macTag;
333
334	always @ (posedge SysClk)
335	if (!Reset_L) MAC_Abort <= 1'b0;
336	else MAC_Abort <= #`SD macAbort;
337
338	always @ (posedge SysClk)
339	if (!Reset_L) MAC_Status <= #`SD 4'h0;
340	else if (ldStatus) MAC_Status <= #`SD FifoDataOut[133:130];
341	else if (ldLatchedStatus) MAC_Status <= #`SD latchedStatus;
342	else if (clearAllState) MAC_Status <= #`SD 4'h0;
343
344	always @ (posedge SysClk)
345	if (!Reset_L) MAC_Data <= #`SD 64'h0;
346	else if (ldFifoDataOut) MAC_Data <= #`SD FifoDataOut[63:0];
347	else if (ldFifoHBits) MAC_Data <= #`SD fifoHBits;
348	else if (ldGigMACStatus) MAC_Data <= #`SD gigMACStatus;
349	else if (clearAllState) MAC_Data <= 64'h0;
350
351	/--------------------------------------------------------------/
352	// Mac Xfer State Vectors
353	/--------------------------------------------------------------/
354	always @(posedge SysClk)
355	if (!Reset_L) Mac_Xfer_State <= #`SD MAC_XFER_IDLE;
356	else Mac_Xfer_State <= #`SD nextXferState;
357
358	/--------------------------------------------------------------/
359	// MAC_ Transfer State Machine
360	/--------------------------------------------------------------/
361	function [3:0] XferDefaults;
362	input [3:0] currentState;
363	begin
364	XferDefaults = currentState;
365	FifoRead = 1'b0;
366	macAck = 1'b0;
367	macTag = 1'b0;
368	macAbort = 1'b0;
369	ldFifoDataOut = 1'b0;
370	clearAllState = 1'b0;
371	setFifoWasEmpty = 1'b0;
372	clrFifoWasEmpty = 1'b0;
373	setDetectedFifoEmpty = 1'b0;
374	clrDetectedFifoEmpty = 1'b0;
375	incPacketsTransmitted = 1'b0;
376	addEightBytes = 1'b0;
377	addStraddleOne = 1'b0;
378	addStraddleTwo = 1'b0;
379	ldStatus = 1'b0;
380	ldLatchedStatus = 1'b0;
381	ldFifoHBits = 1'b0;
382	ldGigMACStatus = 1'b0;
383	end
384	endfunction
385
386
387	always @(/AUTOSENSE/Mac_Xfer_State or Txc_Enabled
388	or MAC_Req or FifoEmpty or EnableGMACMode
389	or lastLineOfPacket or packetEndsOnLowBits
390	or FifoDataOut or abortPacket
391	or packetEndsOnHighBits or detectedFifoEmpty
392	or fifoWasEmpty or parityError
393	or latchedAbort or MAC_Abort
394	)
395	begin
396	case(Mac_Xfer_State) // synopsys full_case parallel_case
397	/* 0in < case -full -parallel */
398	MAC_XFER_IDLE:
399	begin
400	nextXferState = XferDefaults(Mac_Xfer_State);
401
402	if (Txc_Enabled)
403	begin
404	if (MAC_Req)
405	begin
406	if (~FifoEmpty)
407	begin
408	FifoRead = 1'b1;
409	nextXferState = CHECK_FIFO;
410	end
411	end
412	end
413	end
414
415
416	CHECK_FIFO:
417	begin
418	nextXferState = XferDefaults(Mac_Xfer_State);
419
420	if (MAC_Req \| EnableGMACMode)
421	begin
422	if (~FifoEmpty \| lastLineOfPacket)
423	nextXferState = XFER_LOW_BITS_0;
424	end
425	end
426
427	XFER_LOW_BITS_0:
428	begin
429	nextXferState = XferDefaults(Mac_Xfer_State);
430	ldFifoDataOut = 1'b1;
431
432	if (MAC_Req \| EnableGMACMode)
433	begin
434	macAck = 1'b1;
435
436	if (lastLineOfPacket & packetEndsOnLowBits)
437	begin
438	macAbort = (FifoDataOut[129] \| abortPacket);
439	ldStatus = 1'b1;
440	macTag = 1'b1;
441	incPacketsTransmitted = 1'b1;
442	addStraddleOne = 1'b1;
443
444	if (EnableGMACMode)
445	nextXferState = XFER_STATUS;
446	else
447	nextXferState = WAIT_FOR_COUNT_DEC;
448	end
449	else
450	begin
451	nextXferState = XFER_HIGH_BITS_0;
452	addEightBytes = 1'b1;
453	end
454
455	if (~lastLineOfPacket)
456	begin
457	if (FifoEmpty)
458	setDetectedFifoEmpty = 1'b1;
459	else
460	FifoRead = 1'b1;
461	end
462	end
463	end
464
465
466	XFER_HIGH_BITS_0:
467	begin
468	nextXferState = XferDefaults(Mac_Xfer_State);
469
470	if (MAC_Req \| EnableGMACMode)
471	begin
472	macAck = 1'b1;
473	ldFifoHBits = 1'b1;
474
475	if (packetEndsOnHighBits)
476	begin
477	macTag = 1'b1;
478	macAbort = (latchedAbort \| parityError);
479	ldLatchedStatus = 1'b1;
480	incPacketsTransmitted = 1'b1;
481	addStraddleTwo = 1'b1;
482
483	if (EnableGMACMode)
484	nextXferState = XFER_STATUS;
485	else
486	nextXferState = WAIT_FOR_COUNT_DEC;
487	end
488	else // if (!packetEndsOnHighBits)
489	begin
490	if (EnableGMACMode)
491	nextXferState = XFER_LOW_BITS_1;
492	else if (detectedFifoEmpty)
493	nextXferState = WAIT_FOR_FIFO;
494	else
495	//else if (~FifoEmpty)
496	nextXferState = XFER_LOW_BITS_0;
497	//else
498	// nextXferState = CHECK_FIFO;
499
500	addEightBytes = 1'b1;
501	end
502	end
503	end
504
505
506	XFER_LOW_BITS_1:
507	begin
508	nextXferState = XferDefaults(Mac_Xfer_State);
509	macAck = 1'b1;
510	ldFifoDataOut = 1'b1;
511
512	if (~lastLineOfPacket)
513	begin
514	if (~FifoEmpty)
515	FifoRead = 1'b1;
516	else
517	setFifoWasEmpty = 1'b1;
518	end
519
520	if (lastLineOfPacket & packetEndsOnLowBits)
521	begin
522	macTag = 1'b1;
523	incPacketsTransmitted = 1'b1;
524	addStraddleOne = 1'b1;
525	nextXferState = XFER_STATUS;
526	end
527	else
528	begin
529	nextXferState = XFER_HIGH_BITS_1;
530	addEightBytes = 1'b1;
531	end
532	end
533
534
535	XFER_HIGH_BITS_1:
536	begin
537	nextXferState = XferDefaults(Mac_Xfer_State);
538	macAck = 1'b1;
539	ldFifoHBits = 1'b1;
540	nextXferState = WAIT_FOR_NO_REQ;
541
542	if (fifoWasEmpty & ~FifoEmpty)
543	begin
544	FifoRead = 1'b1;
545	clrFifoWasEmpty = 1'b1;
546	end
547
548	if (packetEndsOnHighBits)
549	begin
550	macTag = 1'b1;
551	incPacketsTransmitted = 1'b1;
552	addStraddleTwo = 1'b1;
553	end
554	else
555	addEightBytes = 1'b1;
556	end
557
558
559	WAIT_FOR_NO_REQ:
560	begin
561	nextXferState = XferDefaults(Mac_Xfer_State);
562
563	if (fifoWasEmpty & ~FifoEmpty)
564	begin
565	FifoRead = 1'b1;
566	clrFifoWasEmpty = 1'b0;
567	end
568
569	if (!MAC_Req)
570	begin
571	if (packetEndsOnHighBits)
572	nextXferState = CHECK_FOR_REQ;
573	else
574	nextXferState = CHECK_FOR_BURST_REQ;
575	end
576	end
577
578
579	CHECK_FOR_BURST_REQ:
580	begin
581	nextXferState = XferDefaults(Mac_Xfer_State);
582
583	if (MAC_Req)
584	begin
585	if (fifoWasEmpty)
586	begin
587	if (~FifoEmpty)
588	begin
589	FifoRead = 1'b1;
590	clrFifoWasEmpty = 1'b1;
591	nextXferState = CHECK_FIFO;
592	end
593	end
594	else if (~FifoEmpty \| lastLineOfPacket)
595	nextXferState = XFER_LOW_BITS_0;
596	end
597	end
598
599
600	CHECK_FOR_REQ:
601	begin
602	nextXferState = XferDefaults(Mac_Xfer_State);
603
604	if (MAC_Req)
605	nextXferState = XFER_STATUS;
606	end
607
608
609	XFER_STATUS:
610	begin
611	nextXferState = XferDefaults(Mac_Xfer_State);
612	macAck = 1'b1;
613	macTag = 1'b1;
614	macAbort = MAC_Abort; // Don't know if need this
615	ldGigMACStatus = 1'b1;
616	nextXferState = WAIT_FOR_REQ_LOW;
617	end
618
619
620	WAIT_FOR_REQ_LOW:
621	begin
622	nextXferState = XferDefaults(Mac_Xfer_State);
623	clearAllState = 1'b1;
624
625	if (!MAC_Req)
626	nextXferState = MAC_XFER_IDLE;
627	end
628
629
630	WAIT_FOR_COUNT_DEC:
631	begin
632	nextXferState = XferDefaults(Mac_Xfer_State);
633	clearAllState = 1'b1;
634	nextXferState = MAC_XFER_IDLE;
635	end
636
637
638	WAIT_FOR_FIFO:
639	begin
640	nextXferState = XferDefaults(Mac_Xfer_State);
641	clrDetectedFifoEmpty = 1'b1;
642
643	if (MAC_Req)
644	begin
645	if (~FifoEmpty)
646	begin
647	FifoRead = 1'b1;
648	nextXferState = CHECK_FIFO;
649	end
650	end
651	end
652
653	endcase
654	end
655
656	endmodule