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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: niu_txc_portRequest.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /********************************************************************* | |
36 | * | |
37 | * niu_txc_portRequest.v | |
38 | * | |
39 | * TXC Data PortReq | |
40 | * | |
41 | * Orignal Author(s): Rahoul Puri | |
42 | * Modifier(s): | |
43 | * Project(s): Neptune | |
44 | * | |
45 | * Copyright (c) 2004 Sun Microsystems, Inc. | |
46 | * | |
47 | * All Rights Reserved. | |
48 | * | |
49 | * This verilog model is the confidential and proprietary property of | |
50 | * Sun Microsystems, Inc., and the possession or use of this model | |
51 | * requires a written license from Sun Microsystems, Inc. | |
52 | * | |
53 | **********************************************************************/ | |
54 | ||
55 | `include "timescale.v" | |
56 | ||
57 | module niu_txc_portRequest ( | |
58 | SysClk, | |
59 | Reset_L, | |
60 | Txc_Enabled, | |
61 | ||
62 | Port_Enabled, | |
63 | ||
64 | Pkt_Size_Err, | |
65 | DMA_Pkt_Size_Err, | |
66 | Pkt_Size_Err_Addr, | |
67 | ||
68 | DMA0_EofList, | |
69 | DMA0_Error, | |
70 | DMA0_GotNxtDesc, | |
71 | DMA0_Mark, | |
72 | DMA0_SOP, | |
73 | DMA0_Func_Num, | |
74 | DMA0_DescList, | |
75 | DMA0_Length, | |
76 | DMA0_PageHandle, | |
77 | DMA0_Address, | |
78 | SetGetNextDescDMA0, | |
79 | ||
80 | DMA1_EofList, | |
81 | DMA1_Error, | |
82 | DMA1_GotNxtDesc, | |
83 | DMA1_Mark, | |
84 | DMA1_SOP, | |
85 | DMA1_Func_Num, | |
86 | DMA1_DescList, | |
87 | DMA1_Length, | |
88 | DMA1_PageHandle, | |
89 | DMA1_Address, | |
90 | SetGetNextDescDMA1, | |
91 | ||
92 | DMA2_EofList, | |
93 | DMA2_Error, | |
94 | DMA2_GotNxtDesc, | |
95 | DMA2_Mark, | |
96 | DMA2_SOP, | |
97 | DMA2_Func_Num, | |
98 | DMA2_DescList, | |
99 | DMA2_Length, | |
100 | DMA2_PageHandle, | |
101 | DMA2_Address, | |
102 | SetGetNextDescDMA2, | |
103 | ||
104 | DMA3_EofList, | |
105 | DMA3_Error, | |
106 | DMA3_GotNxtDesc, | |
107 | DMA3_Mark, | |
108 | DMA3_SOP, | |
109 | DMA3_Func_Num, | |
110 | DMA3_DescList, | |
111 | DMA3_Length, | |
112 | DMA3_PageHandle, | |
113 | DMA3_Address, | |
114 | SetGetNextDescDMA3, | |
115 | ||
116 | DMA4_EofList, | |
117 | DMA4_Error, | |
118 | DMA4_GotNxtDesc, | |
119 | DMA4_Mark, | |
120 | DMA4_SOP, | |
121 | DMA4_Func_Num, | |
122 | DMA4_DescList, | |
123 | DMA4_Length, | |
124 | DMA4_PageHandle, | |
125 | DMA4_Address, | |
126 | SetGetNextDescDMA4, | |
127 | ||
128 | DMA5_EofList, | |
129 | DMA5_Error, | |
130 | DMA5_GotNxtDesc, | |
131 | DMA5_Mark, | |
132 | DMA5_SOP, | |
133 | DMA5_Func_Num, | |
134 | DMA5_DescList, | |
135 | DMA5_Length, | |
136 | DMA5_PageHandle, | |
137 | DMA5_Address, | |
138 | SetGetNextDescDMA5, | |
139 | ||
140 | DMA6_EofList, | |
141 | DMA6_Error, | |
142 | DMA6_GotNxtDesc, | |
143 | DMA6_Mark, | |
144 | DMA6_SOP, | |
145 | DMA6_Func_Num, | |
146 | DMA6_DescList, | |
147 | DMA6_Length, | |
148 | DMA6_PageHandle, | |
149 | DMA6_Address, | |
150 | SetGetNextDescDMA6, | |
151 | ||
152 | DMA7_EofList, | |
153 | DMA7_Error, | |
154 | DMA7_GotNxtDesc, | |
155 | DMA7_Mark, | |
156 | DMA7_SOP, | |
157 | DMA7_Func_Num, | |
158 | DMA7_DescList, | |
159 | DMA7_Length, | |
160 | DMA7_PageHandle, | |
161 | DMA7_Address, | |
162 | SetGetNextDescDMA7, | |
163 | ||
164 | DMA8_EofList, | |
165 | DMA8_Error, | |
166 | DMA8_GotNxtDesc, | |
167 | DMA8_Mark, | |
168 | DMA8_SOP, | |
169 | DMA8_Func_Num, | |
170 | DMA8_DescList, | |
171 | DMA8_Length, | |
172 | DMA8_PageHandle, | |
173 | DMA8_Address, | |
174 | SetGetNextDescDMA8, | |
175 | ||
176 | DMA9_EofList, | |
177 | DMA9_Error, | |
178 | DMA9_GotNxtDesc, | |
179 | DMA9_Mark, | |
180 | DMA9_SOP, | |
181 | DMA9_Func_Num, | |
182 | DMA9_DescList, | |
183 | DMA9_Length, | |
184 | DMA9_PageHandle, | |
185 | DMA9_Address, | |
186 | SetGetNextDescDMA9, | |
187 | ||
188 | DMA10_EofList, | |
189 | DMA10_Error, | |
190 | DMA10_GotNxtDesc, | |
191 | DMA10_Mark, | |
192 | DMA10_SOP, | |
193 | DMA10_Func_Num, | |
194 | DMA10_DescList, | |
195 | DMA10_Length, | |
196 | DMA10_PageHandle, | |
197 | DMA10_Address, | |
198 | SetGetNextDescDMA10, | |
199 | ||
200 | DMA11_EofList, | |
201 | DMA11_Error, | |
202 | DMA11_GotNxtDesc, | |
203 | DMA11_Mark, | |
204 | DMA11_SOP, | |
205 | DMA11_Func_Num, | |
206 | DMA11_DescList, | |
207 | DMA11_Length, | |
208 | DMA11_PageHandle, | |
209 | DMA11_Address, | |
210 | SetGetNextDescDMA11, | |
211 | ||
212 | DMA12_EofList, | |
213 | DMA12_Error, | |
214 | DMA12_GotNxtDesc, | |
215 | DMA12_Mark, | |
216 | DMA12_SOP, | |
217 | DMA12_Func_Num, | |
218 | DMA12_DescList, | |
219 | DMA12_Length, | |
220 | DMA12_PageHandle, | |
221 | DMA12_Address, | |
222 | SetGetNextDescDMA12, | |
223 | ||
224 | DMA13_EofList, | |
225 | DMA13_Error, | |
226 | DMA13_GotNxtDesc, | |
227 | DMA13_Mark, | |
228 | DMA13_SOP, | |
229 | DMA13_Func_Num, | |
230 | DMA13_DescList, | |
231 | DMA13_Length, | |
232 | DMA13_PageHandle, | |
233 | DMA13_Address, | |
234 | SetGetNextDescDMA13, | |
235 | ||
236 | DMA14_EofList, | |
237 | DMA14_Error, | |
238 | DMA14_GotNxtDesc, | |
239 | DMA14_Mark, | |
240 | DMA14_SOP, | |
241 | DMA14_Func_Num, | |
242 | DMA14_DescList, | |
243 | DMA14_Length, | |
244 | DMA14_PageHandle, | |
245 | DMA14_Address, | |
246 | SetGetNextDescDMA14, | |
247 | ||
248 | DMA15_EofList, | |
249 | DMA15_Error, | |
250 | DMA15_GotNxtDesc, | |
251 | DMA15_Mark, | |
252 | DMA15_SOP, | |
253 | DMA15_Func_Num, | |
254 | DMA15_DescList, | |
255 | DMA15_Length, | |
256 | DMA15_PageHandle, | |
257 | DMA15_Address, | |
258 | SetGetNextDescDMA15, | |
259 | ||
260 | DMA16_EofList, | |
261 | DMA16_Error, | |
262 | DMA16_GotNxtDesc, | |
263 | DMA16_Mark, | |
264 | DMA16_SOP, | |
265 | DMA16_Func_Num, | |
266 | DMA16_DescList, | |
267 | DMA16_Length, | |
268 | DMA16_PageHandle, | |
269 | DMA16_Address, | |
270 | SetGetNextDescDMA16, | |
271 | ||
272 | DMA17_EofList, | |
273 | DMA17_Error, | |
274 | DMA17_GotNxtDesc, | |
275 | DMA17_Mark, | |
276 | DMA17_SOP, | |
277 | DMA17_Func_Num, | |
278 | DMA17_DescList, | |
279 | DMA17_Length, | |
280 | DMA17_PageHandle, | |
281 | DMA17_Address, | |
282 | SetGetNextDescDMA17, | |
283 | ||
284 | DMA18_EofList, | |
285 | DMA18_Error, | |
286 | DMA18_GotNxtDesc, | |
287 | DMA18_Mark, | |
288 | DMA18_SOP, | |
289 | DMA18_Func_Num, | |
290 | DMA18_DescList, | |
291 | DMA18_Length, | |
292 | DMA18_PageHandle, | |
293 | DMA18_Address, | |
294 | SetGetNextDescDMA18, | |
295 | ||
296 | DMA19_EofList, | |
297 | DMA19_Error, | |
298 | DMA19_GotNxtDesc, | |
299 | DMA19_Mark, | |
300 | DMA19_SOP, | |
301 | DMA19_Func_Num, | |
302 | DMA19_DescList, | |
303 | DMA19_Length, | |
304 | DMA19_PageHandle, | |
305 | DMA19_Address, | |
306 | SetGetNextDescDMA19, | |
307 | ||
308 | DMA20_EofList, | |
309 | DMA20_Error, | |
310 | DMA20_GotNxtDesc, | |
311 | DMA20_Mark, | |
312 | DMA20_SOP, | |
313 | DMA20_Func_Num, | |
314 | DMA20_DescList, | |
315 | DMA20_Length, | |
316 | DMA20_PageHandle, | |
317 | DMA20_Address, | |
318 | SetGetNextDescDMA20, | |
319 | ||
320 | DMA21_EofList, | |
321 | DMA21_Error, | |
322 | DMA21_GotNxtDesc, | |
323 | DMA21_Mark, | |
324 | DMA21_SOP, | |
325 | DMA21_Func_Num, | |
326 | DMA21_DescList, | |
327 | DMA21_Length, | |
328 | DMA21_PageHandle, | |
329 | DMA21_Address, | |
330 | SetGetNextDescDMA21, | |
331 | ||
332 | DMA22_EofList, | |
333 | DMA22_Error, | |
334 | DMA22_GotNxtDesc, | |
335 | DMA22_Mark, | |
336 | DMA22_SOP, | |
337 | DMA22_Func_Num, | |
338 | DMA22_DescList, | |
339 | DMA22_Length, | |
340 | DMA22_PageHandle, | |
341 | DMA22_Address, | |
342 | SetGetNextDescDMA22, | |
343 | ||
344 | DMA23_EofList, | |
345 | DMA23_Error, | |
346 | DMA23_GotNxtDesc, | |
347 | DMA23_Mark, | |
348 | DMA23_SOP, | |
349 | DMA23_Func_Num, | |
350 | DMA23_DescList, | |
351 | DMA23_Length, | |
352 | DMA23_PageHandle, | |
353 | DMA23_Address, | |
354 | SetGetNextDescDMA23, | |
355 | ||
356 | DRR_Arb_Valid, | |
357 | DRR_NextDMAChannel, | |
358 | DRR_PacketDone, | |
359 | PacketByteCount, | |
360 | ||
361 | Anchor_Done, | |
362 | Anchor_MarkBit, | |
363 | Anchor_SopBit, | |
364 | Anchor_GatherLast, | |
365 | Anchor_LoadTID, | |
366 | Anchor_DMA, | |
367 | Anchor_TransID, | |
368 | Anchor_Length, | |
369 | Anchor_Address, | |
370 | Req_Anchor, | |
371 | ||
372 | DMC_TXC_Req_Ack, | |
373 | DMC_TXC_Req_TransID, | |
374 | ||
375 | Port_Selected, | |
376 | Port_Request, | |
377 | Port_Request_Func_Num, | |
378 | Port_Request_DMA_Num, | |
379 | Port_Request_Length, | |
380 | Port_Request_Address, | |
381 | ||
382 | DataPortReq_State | |
383 | ); | |
384 | ||
385 | `include "txc_defines.h" | |
386 | ||
387 | // Global Signals | |
388 | input SysClk; | |
389 | input Reset_L; | |
390 | input Txc_Enabled; | |
391 | ||
392 | // Control Registers | |
393 | input Port_Enabled; | |
394 | ||
395 | // Tx Error Interface | |
396 | output Pkt_Size_Err; | |
397 | output [23:0] DMA_Pkt_Size_Err; | |
398 | output [43:0] Pkt_Size_Err_Addr; | |
399 | ||
400 | reg Pkt_Size_Err; | |
401 | reg [23:0] DMA_Pkt_Size_Err; | |
402 | reg [43:0] Pkt_Size_Err_Addr; | |
403 | ||
404 | //DMA0 | |
405 | input DMA0_EofList; | |
406 | input DMA0_Error; | |
407 | input DMA0_GotNxtDesc; | |
408 | input DMA0_Mark; | |
409 | input DMA0_SOP; | |
410 | input [1:0] DMA0_Func_Num; | |
411 | input [3:0] DMA0_DescList; | |
412 | input [12:0] DMA0_Length; | |
413 | input [19:0] DMA0_PageHandle; | |
414 | input [43:0] DMA0_Address; | |
415 | ||
416 | output SetGetNextDescDMA0; | |
417 | ||
418 | //DMA1 | |
419 | input DMA1_EofList; | |
420 | input DMA1_Error; | |
421 | input DMA1_GotNxtDesc; | |
422 | input DMA1_Mark; | |
423 | input DMA1_SOP; | |
424 | input [1:0] DMA1_Func_Num; | |
425 | input [3:0] DMA1_DescList; | |
426 | input [12:0] DMA1_Length; | |
427 | input [19:0] DMA1_PageHandle; | |
428 | input [43:0] DMA1_Address; | |
429 | ||
430 | output SetGetNextDescDMA1; | |
431 | ||
432 | //DMA2 | |
433 | input DMA2_EofList; | |
434 | input DMA2_Error; | |
435 | input DMA2_GotNxtDesc; | |
436 | input DMA2_Mark; | |
437 | input DMA2_SOP; | |
438 | input [1:0] DMA2_Func_Num; | |
439 | input [3:0] DMA2_DescList; | |
440 | input [12:0] DMA2_Length; | |
441 | input [19:0] DMA2_PageHandle; | |
442 | input [43:0] DMA2_Address; | |
443 | ||
444 | output SetGetNextDescDMA2; | |
445 | ||
446 | //DMA3 | |
447 | input DMA3_EofList; | |
448 | input DMA3_Error; | |
449 | input DMA3_GotNxtDesc; | |
450 | input DMA3_Mark; | |
451 | input DMA3_SOP; | |
452 | input [1:0] DMA3_Func_Num; | |
453 | input [3:0] DMA3_DescList; | |
454 | input [12:0] DMA3_Length; | |
455 | input [19:0] DMA3_PageHandle; | |
456 | input [43:0] DMA3_Address; | |
457 | ||
458 | output SetGetNextDescDMA3; | |
459 | ||
460 | //DMA4 | |
461 | input DMA4_EofList; | |
462 | input DMA4_Error; | |
463 | input DMA4_GotNxtDesc; | |
464 | input DMA4_Mark; | |
465 | input DMA4_SOP; | |
466 | input [1:0] DMA4_Func_Num; | |
467 | input [3:0] DMA4_DescList; | |
468 | input [12:0] DMA4_Length; | |
469 | input [19:0] DMA4_PageHandle; | |
470 | input [43:0] DMA4_Address; | |
471 | ||
472 | output SetGetNextDescDMA4; | |
473 | ||
474 | //DMA5 | |
475 | input DMA5_EofList; | |
476 | input DMA5_Error; | |
477 | input DMA5_GotNxtDesc; | |
478 | input DMA5_Mark; | |
479 | input DMA5_SOP; | |
480 | input [1:0] DMA5_Func_Num; | |
481 | input [3:0] DMA5_DescList; | |
482 | input [12:0] DMA5_Length; | |
483 | input [19:0] DMA5_PageHandle; | |
484 | input [43:0] DMA5_Address; | |
485 | ||
486 | output SetGetNextDescDMA5; | |
487 | ||
488 | //DMA6 | |
489 | input DMA6_EofList; | |
490 | input DMA6_Error; | |
491 | input DMA6_GotNxtDesc; | |
492 | input DMA6_Mark; | |
493 | input DMA6_SOP; | |
494 | input [1:0] DMA6_Func_Num; | |
495 | input [3:0] DMA6_DescList; | |
496 | input [12:0] DMA6_Length; | |
497 | input [19:0] DMA6_PageHandle; | |
498 | input [43:0] DMA6_Address; | |
499 | ||
500 | output SetGetNextDescDMA6; | |
501 | ||
502 | //DMA7 | |
503 | input DMA7_EofList; | |
504 | input DMA7_Error; | |
505 | input DMA7_GotNxtDesc; | |
506 | input DMA7_Mark; | |
507 | input DMA7_SOP; | |
508 | input [1:0] DMA7_Func_Num; | |
509 | input [3:0] DMA7_DescList; | |
510 | input [12:0] DMA7_Length; | |
511 | input [19:0] DMA7_PageHandle; | |
512 | input [43:0] DMA7_Address; | |
513 | ||
514 | output SetGetNextDescDMA7; | |
515 | ||
516 | //DMA8 | |
517 | input DMA8_EofList; | |
518 | input DMA8_Error; | |
519 | input DMA8_GotNxtDesc; | |
520 | input DMA8_Mark; | |
521 | input DMA8_SOP; | |
522 | input [1:0] DMA8_Func_Num; | |
523 | input [3:0] DMA8_DescList; | |
524 | input [12:0] DMA8_Length; | |
525 | input [19:0] DMA8_PageHandle; | |
526 | input [43:0] DMA8_Address; | |
527 | ||
528 | output SetGetNextDescDMA8; | |
529 | ||
530 | //DMA9 | |
531 | input DMA9_EofList; | |
532 | input DMA9_Error; | |
533 | input DMA9_GotNxtDesc; | |
534 | input DMA9_Mark; | |
535 | input DMA9_SOP; | |
536 | input [1:0] DMA9_Func_Num; | |
537 | input [3:0] DMA9_DescList; | |
538 | input [12:0] DMA9_Length; | |
539 | input [19:0] DMA9_PageHandle; | |
540 | input [43:0] DMA9_Address; | |
541 | ||
542 | output SetGetNextDescDMA9; | |
543 | ||
544 | //DMA10 | |
545 | input DMA10_EofList; | |
546 | input DMA10_Error; | |
547 | input DMA10_GotNxtDesc; | |
548 | input DMA10_Mark; | |
549 | input DMA10_SOP; | |
550 | input [1:0] DMA10_Func_Num; | |
551 | input [3:0] DMA10_DescList; | |
552 | input [12:0] DMA10_Length; | |
553 | input [19:0] DMA10_PageHandle; | |
554 | input [43:0] DMA10_Address; | |
555 | ||
556 | output SetGetNextDescDMA10; | |
557 | ||
558 | //DMA11 | |
559 | input DMA11_EofList; | |
560 | input DMA11_Error; | |
561 | input DMA11_GotNxtDesc; | |
562 | input DMA11_Mark; | |
563 | input DMA11_SOP; | |
564 | input [1:0] DMA11_Func_Num; | |
565 | input [3:0] DMA11_DescList; | |
566 | input [12:0] DMA11_Length; | |
567 | input [19:0] DMA11_PageHandle; | |
568 | input [43:0] DMA11_Address; | |
569 | ||
570 | output SetGetNextDescDMA11; | |
571 | ||
572 | //DMA12 | |
573 | input DMA12_EofList; | |
574 | input DMA12_Error; | |
575 | input DMA12_GotNxtDesc; | |
576 | input DMA12_Mark; | |
577 | input DMA12_SOP; | |
578 | input [1:0] DMA12_Func_Num; | |
579 | input [3:0] DMA12_DescList; | |
580 | input [12:0] DMA12_Length; | |
581 | input [19:0] DMA12_PageHandle; | |
582 | input [43:0] DMA12_Address; | |
583 | ||
584 | output SetGetNextDescDMA12; | |
585 | ||
586 | //DMA13 | |
587 | input DMA13_EofList; | |
588 | input DMA13_Error; | |
589 | input DMA13_GotNxtDesc; | |
590 | input DMA13_Mark; | |
591 | input DMA13_SOP; | |
592 | input [1:0] DMA13_Func_Num; | |
593 | input [3:0] DMA13_DescList; | |
594 | input [12:0] DMA13_Length; | |
595 | input [19:0] DMA13_PageHandle; | |
596 | input [43:0] DMA13_Address; | |
597 | ||
598 | output SetGetNextDescDMA13; | |
599 | ||
600 | //DMA14 | |
601 | input DMA14_EofList; | |
602 | input DMA14_Error; | |
603 | input DMA14_GotNxtDesc; | |
604 | input DMA14_Mark; | |
605 | input DMA14_SOP; | |
606 | input [1:0] DMA14_Func_Num; | |
607 | input [3:0] DMA14_DescList; | |
608 | input [12:0] DMA14_Length; | |
609 | input [19:0] DMA14_PageHandle; | |
610 | input [43:0] DMA14_Address; | |
611 | ||
612 | output SetGetNextDescDMA14; | |
613 | ||
614 | //DMA15 | |
615 | input DMA15_EofList; | |
616 | input DMA15_Error; | |
617 | input DMA15_GotNxtDesc; | |
618 | input DMA15_Mark; | |
619 | input DMA15_SOP; | |
620 | input [1:0] DMA15_Func_Num; | |
621 | input [3:0] DMA15_DescList; | |
622 | input [12:0] DMA15_Length; | |
623 | input [19:0] DMA15_PageHandle; | |
624 | input [43:0] DMA15_Address; | |
625 | ||
626 | output SetGetNextDescDMA15; | |
627 | ||
628 | //DMA16 | |
629 | input DMA16_EofList; | |
630 | input DMA16_Error; | |
631 | input DMA16_GotNxtDesc; | |
632 | input DMA16_Mark; | |
633 | input DMA16_SOP; | |
634 | input [1:0] DMA16_Func_Num; | |
635 | input [3:0] DMA16_DescList; | |
636 | input [12:0] DMA16_Length; | |
637 | input [19:0] DMA16_PageHandle; | |
638 | input [43:0] DMA16_Address; | |
639 | ||
640 | output SetGetNextDescDMA16; | |
641 | ||
642 | //DMA17 | |
643 | input DMA17_EofList; | |
644 | input DMA17_Error; | |
645 | input DMA17_GotNxtDesc; | |
646 | input DMA17_Mark; | |
647 | input DMA17_SOP; | |
648 | input [1:0] DMA17_Func_Num; | |
649 | input [3:0] DMA17_DescList; | |
650 | input [12:0] DMA17_Length; | |
651 | input [19:0] DMA17_PageHandle; | |
652 | input [43:0] DMA17_Address; | |
653 | ||
654 | output SetGetNextDescDMA17; | |
655 | ||
656 | //DMA18 | |
657 | input DMA18_EofList; | |
658 | input DMA18_Error; | |
659 | input DMA18_GotNxtDesc; | |
660 | input DMA18_Mark; | |
661 | input DMA18_SOP; | |
662 | input [1:0] DMA18_Func_Num; | |
663 | input [3:0] DMA18_DescList; | |
664 | input [12:0] DMA18_Length; | |
665 | input [19:0] DMA18_PageHandle; | |
666 | input [43:0] DMA18_Address; | |
667 | ||
668 | output SetGetNextDescDMA18; | |
669 | ||
670 | //DMA19 | |
671 | input DMA19_EofList; | |
672 | input DMA19_Error; | |
673 | input DMA19_GotNxtDesc; | |
674 | input DMA19_Mark; | |
675 | input DMA19_SOP; | |
676 | input [1:0] DMA19_Func_Num; | |
677 | input [3:0] DMA19_DescList; | |
678 | input [12:0] DMA19_Length; | |
679 | input [19:0] DMA19_PageHandle; | |
680 | input [43:0] DMA19_Address; | |
681 | ||
682 | output SetGetNextDescDMA19; | |
683 | ||
684 | //DMA20 | |
685 | input DMA20_EofList; | |
686 | input DMA20_Error; | |
687 | input DMA20_GotNxtDesc; | |
688 | input DMA20_Mark; | |
689 | input DMA20_SOP; | |
690 | input [1:0] DMA20_Func_Num; | |
691 | input [3:0] DMA20_DescList; | |
692 | input [12:0] DMA20_Length; | |
693 | input [19:0] DMA20_PageHandle; | |
694 | input [43:0] DMA20_Address; | |
695 | ||
696 | output SetGetNextDescDMA20; | |
697 | ||
698 | //DMA21 | |
699 | input DMA21_EofList; | |
700 | input DMA21_Error; | |
701 | input DMA21_GotNxtDesc; | |
702 | input DMA21_Mark; | |
703 | input DMA21_SOP; | |
704 | input [1:0] DMA21_Func_Num; | |
705 | input [3:0] DMA21_DescList; | |
706 | input [12:0] DMA21_Length; | |
707 | input [19:0] DMA21_PageHandle; | |
708 | input [43:0] DMA21_Address; | |
709 | ||
710 | output SetGetNextDescDMA21; | |
711 | ||
712 | //DMA22 | |
713 | input DMA22_EofList; | |
714 | input DMA22_Error; | |
715 | input DMA22_GotNxtDesc; | |
716 | input DMA22_Mark; | |
717 | input DMA22_SOP; | |
718 | input [1:0] DMA22_Func_Num; | |
719 | input [3:0] DMA22_DescList; | |
720 | input [12:0] DMA22_Length; | |
721 | input [19:0] DMA22_PageHandle; | |
722 | input [43:0] DMA22_Address; | |
723 | ||
724 | output SetGetNextDescDMA22; | |
725 | ||
726 | //DMA23 | |
727 | input DMA23_EofList; | |
728 | input DMA23_Error; | |
729 | input DMA23_GotNxtDesc; | |
730 | input DMA23_Mark; | |
731 | input DMA23_SOP; | |
732 | input [1:0] DMA23_Func_Num; | |
733 | input [3:0] DMA23_DescList; | |
734 | input [12:0] DMA23_Length; | |
735 | input [19:0] DMA23_PageHandle; | |
736 | input [43:0] DMA23_Address; | |
737 | ||
738 | output SetGetNextDescDMA23; | |
739 | ||
740 | // DRR Engines Interface | |
741 | input DRR_Arb_Valid; | |
742 | input [4:0] DRR_NextDMAChannel; | |
743 | ||
744 | output DRR_PacketDone; | |
745 | output [15:0] PacketByteCount; | |
746 | ||
747 | reg [15:0] PacketByteCount; | |
748 | ||
749 | // ReAligner Interface | |
750 | input Anchor_Done; | |
751 | ||
752 | output Req_Anchor; | |
753 | output Anchor_MarkBit; | |
754 | output Anchor_SopBit; | |
755 | output Anchor_GatherLast; | |
756 | output Anchor_LoadTID; | |
757 | output [4:0] Anchor_DMA; | |
758 | output [5:0] Anchor_TransID; | |
759 | output [12:0] Anchor_Length; | |
760 | output [63:0] Anchor_Address; | |
761 | ||
762 | reg Anchor_MarkBit; | |
763 | reg Anchor_SopBit; | |
764 | reg Anchor_GatherLast; | |
765 | reg Req_Anchor; | |
766 | reg Anchor_LoadTID; | |
767 | reg [4:0] Anchor_DMA; | |
768 | reg [5:0] Anchor_TransID; | |
769 | reg [12:0] Anchor_Length; | |
770 | reg [63:0] Anchor_Address; | |
771 | ||
772 | // Meta Bus | |
773 | input DMC_TXC_Req_Ack; | |
774 | input [5:0] DMC_TXC_Req_TransID; | |
775 | ||
776 | // Data Fetch Interface | |
777 | input Port_Selected; | |
778 | ||
779 | output Port_Request; | |
780 | output [1:0] Port_Request_Func_Num; | |
781 | output [4:0] Port_Request_DMA_Num; | |
782 | output [12:0] Port_Request_Length; | |
783 | output [63:0] Port_Request_Address; | |
784 | ||
785 | reg Port_Request; | |
786 | reg [1:0] Port_Request_Func_Num; | |
787 | reg [4:0] Port_Request_DMA_Num; | |
788 | reg [12:0] Port_Request_Length; | |
789 | reg [63:0] Port_Request_Address; | |
790 | ||
791 | // State Machine | |
792 | output [3:0] DataPortReq_State; | |
793 | ||
794 | reg [3:0] DataPortReq_State; | |
795 | ||
796 | /*--------------------------------------------------------------*/ | |
797 | // Wires & Registers | |
798 | /*--------------------------------------------------------------*/ | |
799 | wire nullDescriptor; | |
800 | wire singleDescriptor; | |
801 | wire multiDescriptor; | |
802 | wire decrementDescList; | |
803 | wire setPacketSizeErr; | |
804 | wire sopBitNotSet; | |
805 | wire [63:0] requestAddress; | |
806 | ||
807 | reg portRequestDone; | |
808 | reg ldDescList; | |
809 | reg anchorRequest; | |
810 | reg drrPacketDone; | |
811 | reg DRR_PacketDone; | |
812 | reg setPortRequest; | |
813 | reg gotNextDescriptor; | |
814 | reg setGetNextDescriptor; | |
815 | reg sopBitSet; | |
816 | reg eofListBitSet; | |
817 | reg errorBitSet; | |
818 | reg markBitSet; | |
819 | reg enableSizeCheck; | |
820 | reg setEnableSizeCheck; | |
821 | reg clrEnableSizeCheck; | |
822 | reg [1:0] dmaFunctionNumber; | |
823 | reg [3:0] nextPortReqState; | |
824 | reg [3:0] descriptorList; | |
825 | reg [3:0] anchorDescList; | |
826 | reg [12:0] anchorLength; | |
827 | reg [12:0] anchorLengthD1; | |
828 | reg [15:0] pktSizeCheck; | |
829 | reg [19:0] pageHandle; | |
830 | reg [23:0] currentDMAChannel; | |
831 | reg [43:0] anchorAddress; | |
832 | ||
833 | /*--------------------------------------------------------------*/ | |
834 | // Parameters and Defines | |
835 | /*--------------------------------------------------------------*/ | |
836 | parameter PORT_REQUEST_IDLE = 4'h0, | |
837 | CHECK_FOR_DESCRIPTOR = 4'h1, | |
838 | REQ_ANCHOR = 4'h2, | |
839 | WAIT_FOR_ANCHOR = 4'h3, | |
840 | PORT_REQUEST = 4'h4, | |
841 | WAIT_FOR_REQ_ACCEPT = 4'h5, | |
842 | WAIT_FOR_NEXT_DESC = 4'h6, | |
843 | CHECK_PACKET_SIZE = 4'h7, | |
844 | WAIT_FOR_DRR_UPDATE = 4'h8, | |
845 | ERROR_STATE = 4'h9; | |
846 | ||
847 | //VCS coverage off | |
848 | // synopsys translate_off | |
849 | reg [192:1] PORT_REQUEST_STATE; | |
850 | ||
851 | always @(DataPortReq_State) | |
852 | begin | |
853 | case(DataPortReq_State) | |
854 | PORT_REQUEST_IDLE : PORT_REQUEST_STATE = "PORT_REQUEST_IDLE"; | |
855 | CHECK_FOR_DESCRIPTOR : PORT_REQUEST_STATE = "CHECK_FOR_DESCRIPTOR"; | |
856 | REQ_ANCHOR : PORT_REQUEST_STATE = "REQ_ANCHOR"; | |
857 | WAIT_FOR_ANCHOR : PORT_REQUEST_STATE = "WAIT_FOR_ANCHOR"; | |
858 | PORT_REQUEST: PORT_REQUEST_STATE = "PORT_REQUEST"; | |
859 | WAIT_FOR_REQ_ACCEPT : PORT_REQUEST_STATE = "WAIT_FOR_REQ_ACCEPT"; | |
860 | WAIT_FOR_NEXT_DESC : PORT_REQUEST_STATE = "WAIT_FOR_NEXT_DESC"; | |
861 | CHECK_PACKET_SIZE : PORT_REQUEST_STATE = "CHECK_PACKET_SIZE"; | |
862 | WAIT_FOR_DRR_UPDATE : PORT_REQUEST_STATE = "WAIT_FOR_DRR_UPDATE"; | |
863 | ERROR_STATE : PORT_REQUEST_STATE = "ERROR_STATE"; | |
864 | default : PORT_REQUEST_STATE = "UNKNOWN"; | |
865 | endcase | |
866 | end | |
867 | ||
868 | // synopsys translate_on | |
869 | //VCS coverage on | |
870 | ||
871 | /*--------------------------------------------------------------*/ | |
872 | // Zero In Checks | |
873 | /*--------------------------------------------------------------*/ | |
874 | ||
875 | ||
876 | /*--------------------------------------------------------------*/ | |
877 | // Assigns | |
878 | /*--------------------------------------------------------------*/ | |
879 | assign sopBitNotSet = ~sopBitSet; | |
880 | ||
881 | /*--------------------------------------------------------------*/ | |
882 | // DRR_NextDMAChannel to one hot encoding | |
883 | /*--------------------------------------------------------------*/ | |
884 | always @(DRR_NextDMAChannel | |
885 | ) | |
886 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
887 | `DMA_CHANNEL_ZERO: currentDMAChannel = 24'h000001; | |
888 | `DMA_CHANNEL_ONE: currentDMAChannel = 24'h000002; | |
889 | `DMA_CHANNEL_TWO: currentDMAChannel = 24'h000004; | |
890 | `DMA_CHANNEL_THREE: currentDMAChannel = 24'h000008; | |
891 | `DMA_CHANNEL_FOUR: currentDMAChannel = 24'h000010; | |
892 | `DMA_CHANNEL_FIVE: currentDMAChannel = 24'h000020; | |
893 | `DMA_CHANNEL_SIX: currentDMAChannel = 24'h000040; | |
894 | `DMA_CHANNEL_SEVEN: currentDMAChannel = 24'h000080; | |
895 | `DMA_CHANNEL_EIGHT: currentDMAChannel = 24'h000100; | |
896 | `DMA_CHANNEL_NINE: currentDMAChannel = 24'h000200; | |
897 | `DMA_CHANNEL_TEN: currentDMAChannel = 24'h000400; | |
898 | `DMA_CHANNEL_ELEVEN: currentDMAChannel = 24'h000800; | |
899 | `DMA_CHANNEL_TWELVE: currentDMAChannel = 24'h001000; | |
900 | `DMA_CHANNEL_THIRTEEN: currentDMAChannel = 24'h002000; | |
901 | `DMA_CHANNEL_FOURTEEN: currentDMAChannel = 24'h004000; | |
902 | `DMA_CHANNEL_FIFTEEN: currentDMAChannel = 24'h008000; | |
903 | `DMA_CHANNEL_SIXTEEN: currentDMAChannel = 24'h010000; | |
904 | `DMA_CHANNEL_SEVENTEEN: currentDMAChannel = 24'h020000; | |
905 | `DMA_CHANNEL_EIGHTEEN: currentDMAChannel = 24'h040000; | |
906 | `DMA_CHANNEL_NINETEEN: currentDMAChannel = 24'h080000; | |
907 | `DMA_CHANNEL_TWENTY: currentDMAChannel = 24'h100000; | |
908 | `DMA_CHANNEL_TWENTYONE: currentDMAChannel = 24'h200000; | |
909 | `DMA_CHANNEL_TWENTYTWO: currentDMAChannel = 24'h400000; | |
910 | `DMA_CHANNEL_TWENTYTHREE: currentDMAChannel = 24'h800000; | |
911 | default: currentDMAChannel = 24'hx; | |
912 | endcase | |
913 | ||
914 | ||
915 | /*--------------------------------------------------------------*/ | |
916 | // Request State Variables | |
917 | /*--------------------------------------------------------------*/ | |
918 | always @(posedge SysClk) | |
919 | if (!Reset_L) portRequestDone <= #`SD 1'b0; | |
920 | else portRequestDone <= #`SD (DMC_TXC_Req_Ack & Port_Selected); | |
921 | ||
922 | /*--------------------------------------------------------------*/ | |
923 | // Anchor Request State Variables | |
924 | /*--------------------------------------------------------------*/ | |
925 | assign requestAddress = {pageHandle, anchorAddress}; | |
926 | ||
927 | always @(posedge SysClk) | |
928 | if (!Reset_L) Req_Anchor <= #`SD 1'b0; | |
929 | else if (anchorRequest) Req_Anchor <= #`SD 1'b1; | |
930 | else if (Anchor_Done) Req_Anchor <= #`SD 1'b0; | |
931 | ||
932 | always @(posedge SysClk) | |
933 | if (!Reset_L) Anchor_Length <= #`SD 13'h0; | |
934 | else Anchor_Length <= #`SD anchorLength; | |
935 | ||
936 | always @(posedge SysClk) | |
937 | if (!Reset_L) Anchor_Address <= #`SD 64'h0; | |
938 | else Anchor_Address <= #`SD requestAddress; | |
939 | ||
940 | always @(posedge SysClk) | |
941 | if (!Reset_L) Anchor_MarkBit <= #`SD 1'b0; | |
942 | else Anchor_MarkBit <= #`SD markBitSet; | |
943 | ||
944 | always @(posedge SysClk) | |
945 | if (!Reset_L) Anchor_SopBit <= #`SD 1'b0; | |
946 | else Anchor_SopBit <= #`SD sopBitSet; | |
947 | ||
948 | always @(posedge SysClk) | |
949 | if (!Reset_L) Anchor_GatherLast <= #`SD 1'b0; | |
950 | else Anchor_GatherLast <= #`SD singleDescriptor; | |
951 | ||
952 | always @(posedge SysClk) | |
953 | if (!Reset_L) Anchor_DMA <= #`SD 5'h0; | |
954 | else Anchor_DMA <= #`SD DRR_NextDMAChannel; | |
955 | ||
956 | always @(posedge SysClk) | |
957 | if (!Reset_L) Anchor_TransID <= #`SD 6'h0; | |
958 | else if (Port_Selected) Anchor_TransID <= #`SD DMC_TXC_Req_TransID; | |
959 | else Anchor_TransID <= #`SD 6'h0; | |
960 | ||
961 | always @(posedge SysClk) | |
962 | if (!Reset_L) Anchor_LoadTID <= #`SD 1'b0; | |
963 | else if (Port_Selected) Anchor_LoadTID <= #`SD DMC_TXC_Req_Ack; | |
964 | else Anchor_LoadTID <= #`SD 1'b0; | |
965 | ||
966 | /*--------------------------------------------------------------*/ | |
967 | // DMA Channel Variables | |
968 | /*--------------------------------------------------------------*/ | |
969 | always @(posedge SysClk) | |
970 | if (!Reset_L) Port_Request <= #`SD 1'b0; | |
971 | else if (setPortRequest) Port_Request <= #`SD 1'b1; | |
972 | else if (DMC_TXC_Req_Ack & Port_Selected) Port_Request <= #`SD 1'b0; | |
973 | ||
974 | always @(posedge SysClk) | |
975 | if (!Reset_L) Port_Request_Func_Num <= #`SD 2'h0; | |
976 | else if (setPortRequest) Port_Request_Func_Num <= #`SD dmaFunctionNumber; | |
977 | ||
978 | always @(posedge SysClk) | |
979 | if (!Reset_L) Port_Request_DMA_Num <= #`SD 5'h0; | |
980 | else if (setPortRequest) Port_Request_DMA_Num <= #`SD DRR_NextDMAChannel; | |
981 | ||
982 | always @(posedge SysClk) | |
983 | if (!Reset_L) Port_Request_Length <= #`SD 13'h0; | |
984 | else if (setPortRequest) Port_Request_Length <= #`SD anchorLength; | |
985 | ||
986 | always @(posedge SysClk) | |
987 | if (!Reset_L) Port_Request_Address <= #`SD 64'h0; | |
988 | else if (setPortRequest) Port_Request_Address <= #`SD requestAddress; | |
989 | ||
990 | /*--------------------------------------------------------------*/ | |
991 | // DMA Channel Variables | |
992 | /*--------------------------------------------------------------*/ | |
993 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
994 | or DMA23_Func_Num or DMA22_Func_Num or DMA21_Func_Num | |
995 | or DMA20_Func_Num or DMA19_Func_Num or DMA18_Func_Num | |
996 | or DMA17_Func_Num or DMA16_Func_Num or DMA15_Func_Num | |
997 | or DMA14_Func_Num or DMA13_Func_Num or DMA12_Func_Num | |
998 | or DMA11_Func_Num or DMA10_Func_Num or DMA9_Func_Num | |
999 | or DMA8_Func_Num or DMA7_Func_Num or DMA6_Func_Num | |
1000 | or DMA5_Func_Num or DMA4_Func_Num or DMA3_Func_Num | |
1001 | or DMA2_Func_Num or DMA1_Func_Num or DMA0_Func_Num | |
1002 | ) | |
1003 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1004 | `DMA_CHANNEL_ZERO: dmaFunctionNumber = DMA0_Func_Num; | |
1005 | `DMA_CHANNEL_ONE: dmaFunctionNumber = DMA1_Func_Num; | |
1006 | `DMA_CHANNEL_TWO: dmaFunctionNumber = DMA2_Func_Num; | |
1007 | `DMA_CHANNEL_THREE: dmaFunctionNumber = DMA3_Func_Num; | |
1008 | `DMA_CHANNEL_FOUR: dmaFunctionNumber = DMA4_Func_Num; | |
1009 | `DMA_CHANNEL_FIVE: dmaFunctionNumber = DMA5_Func_Num; | |
1010 | `DMA_CHANNEL_SIX: dmaFunctionNumber = DMA6_Func_Num; | |
1011 | `DMA_CHANNEL_SEVEN: dmaFunctionNumber = DMA7_Func_Num; | |
1012 | `DMA_CHANNEL_EIGHT: dmaFunctionNumber = DMA8_Func_Num; | |
1013 | `DMA_CHANNEL_NINE: dmaFunctionNumber = DMA9_Func_Num; | |
1014 | `DMA_CHANNEL_TEN: dmaFunctionNumber = DMA10_Func_Num; | |
1015 | `DMA_CHANNEL_ELEVEN: dmaFunctionNumber = DMA11_Func_Num; | |
1016 | `DMA_CHANNEL_TWELVE: dmaFunctionNumber = DMA12_Func_Num; | |
1017 | `DMA_CHANNEL_THIRTEEN: dmaFunctionNumber = DMA13_Func_Num; | |
1018 | `DMA_CHANNEL_FOURTEEN: dmaFunctionNumber = DMA14_Func_Num; | |
1019 | `DMA_CHANNEL_FIFTEEN: dmaFunctionNumber = DMA15_Func_Num; | |
1020 | `DMA_CHANNEL_SIXTEEN: dmaFunctionNumber = DMA16_Func_Num; | |
1021 | `DMA_CHANNEL_SEVENTEEN: dmaFunctionNumber = DMA17_Func_Num; | |
1022 | `DMA_CHANNEL_EIGHTEEN: dmaFunctionNumber = DMA18_Func_Num; | |
1023 | `DMA_CHANNEL_NINETEEN: dmaFunctionNumber = DMA19_Func_Num; | |
1024 | `DMA_CHANNEL_TWENTY: dmaFunctionNumber = DMA20_Func_Num; | |
1025 | `DMA_CHANNEL_TWENTYONE: dmaFunctionNumber = DMA21_Func_Num; | |
1026 | `DMA_CHANNEL_TWENTYTWO: dmaFunctionNumber = DMA22_Func_Num; | |
1027 | `DMA_CHANNEL_TWENTYTHREE: dmaFunctionNumber = DMA23_Func_Num; | |
1028 | default: dmaFunctionNumber = 2'hx; | |
1029 | endcase | |
1030 | ||
1031 | ||
1032 | ||
1033 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1034 | or DMA23_SOP or DMA22_SOP or DMA21_SOP or DMA20_SOP | |
1035 | or DMA19_SOP or DMA18_SOP or DMA17_SOP or DMA16_SOP | |
1036 | or DMA15_SOP or DMA14_SOP or DMA13_SOP or DMA12_SOP | |
1037 | or DMA11_SOP or DMA10_SOP or DMA9_SOP or DMA8_SOP | |
1038 | or DMA7_SOP or DMA6_SOP or DMA5_SOP or DMA4_SOP | |
1039 | or DMA3_SOP or DMA2_SOP or DMA1_SOP or DMA0_SOP | |
1040 | ) | |
1041 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1042 | `DMA_CHANNEL_ZERO: sopBitSet = DMA0_SOP; | |
1043 | `DMA_CHANNEL_ONE: sopBitSet = DMA1_SOP; | |
1044 | `DMA_CHANNEL_TWO: sopBitSet = DMA2_SOP; | |
1045 | `DMA_CHANNEL_THREE: sopBitSet = DMA3_SOP; | |
1046 | `DMA_CHANNEL_FOUR: sopBitSet = DMA4_SOP; | |
1047 | `DMA_CHANNEL_FIVE: sopBitSet = DMA5_SOP; | |
1048 | `DMA_CHANNEL_SIX: sopBitSet = DMA6_SOP; | |
1049 | `DMA_CHANNEL_SEVEN: sopBitSet = DMA7_SOP; | |
1050 | `DMA_CHANNEL_EIGHT: sopBitSet = DMA8_SOP; | |
1051 | `DMA_CHANNEL_NINE: sopBitSet = DMA9_SOP; | |
1052 | `DMA_CHANNEL_TEN: sopBitSet = DMA10_SOP; | |
1053 | `DMA_CHANNEL_ELEVEN: sopBitSet = DMA11_SOP; | |
1054 | `DMA_CHANNEL_TWELVE: sopBitSet = DMA12_SOP; | |
1055 | `DMA_CHANNEL_THIRTEEN: sopBitSet = DMA13_SOP; | |
1056 | `DMA_CHANNEL_FOURTEEN: sopBitSet = DMA14_SOP; | |
1057 | `DMA_CHANNEL_FIFTEEN: sopBitSet = DMA15_SOP; | |
1058 | `DMA_CHANNEL_SIXTEEN: sopBitSet = DMA16_SOP; | |
1059 | `DMA_CHANNEL_SEVENTEEN: sopBitSet = DMA17_SOP; | |
1060 | `DMA_CHANNEL_EIGHTEEN: sopBitSet = DMA18_SOP; | |
1061 | `DMA_CHANNEL_NINETEEN: sopBitSet = DMA19_SOP; | |
1062 | `DMA_CHANNEL_TWENTY: sopBitSet = DMA20_SOP; | |
1063 | `DMA_CHANNEL_TWENTYONE: sopBitSet = DMA21_SOP; | |
1064 | `DMA_CHANNEL_TWENTYTWO: sopBitSet = DMA22_SOP; | |
1065 | `DMA_CHANNEL_TWENTYTHREE: sopBitSet = DMA23_SOP; | |
1066 | default: sopBitSet = 1'bx; | |
1067 | endcase | |
1068 | ||
1069 | ||
1070 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1071 | or DMA23_EofList or DMA22_EofList or DMA21_EofList or DMA20_EofList | |
1072 | or DMA19_EofList or DMA18_EofList or DMA17_EofList or DMA16_EofList | |
1073 | or DMA15_EofList or DMA14_EofList or DMA13_EofList or DMA12_EofList | |
1074 | or DMA11_EofList or DMA10_EofList or DMA9_EofList or DMA8_EofList | |
1075 | or DMA7_EofList or DMA6_EofList or DMA5_EofList or DMA4_EofList | |
1076 | or DMA3_EofList or DMA2_EofList or DMA1_EofList or DMA0_EofList | |
1077 | ) | |
1078 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1079 | `DMA_CHANNEL_ZERO: eofListBitSet = DMA0_EofList; | |
1080 | `DMA_CHANNEL_ONE: eofListBitSet = DMA1_EofList; | |
1081 | `DMA_CHANNEL_TWO: eofListBitSet = DMA2_EofList; | |
1082 | `DMA_CHANNEL_THREE: eofListBitSet = DMA3_EofList; | |
1083 | `DMA_CHANNEL_FOUR: eofListBitSet = DMA4_EofList; | |
1084 | `DMA_CHANNEL_FIVE: eofListBitSet = DMA5_EofList; | |
1085 | `DMA_CHANNEL_SIX: eofListBitSet = DMA6_EofList; | |
1086 | `DMA_CHANNEL_SEVEN: eofListBitSet = DMA7_EofList; | |
1087 | `DMA_CHANNEL_EIGHT: eofListBitSet = DMA8_EofList; | |
1088 | `DMA_CHANNEL_NINE: eofListBitSet = DMA9_EofList; | |
1089 | `DMA_CHANNEL_TEN: eofListBitSet = DMA10_EofList; | |
1090 | `DMA_CHANNEL_ELEVEN: eofListBitSet = DMA11_EofList; | |
1091 | `DMA_CHANNEL_TWELVE: eofListBitSet = DMA12_EofList; | |
1092 | `DMA_CHANNEL_THIRTEEN: eofListBitSet = DMA13_EofList; | |
1093 | `DMA_CHANNEL_FOURTEEN: eofListBitSet = DMA14_EofList; | |
1094 | `DMA_CHANNEL_FIFTEEN: eofListBitSet = DMA15_EofList; | |
1095 | `DMA_CHANNEL_SIXTEEN: eofListBitSet = DMA16_EofList; | |
1096 | `DMA_CHANNEL_SEVENTEEN: eofListBitSet = DMA17_EofList; | |
1097 | `DMA_CHANNEL_EIGHTEEN: eofListBitSet = DMA18_EofList; | |
1098 | `DMA_CHANNEL_NINETEEN: eofListBitSet = DMA19_EofList; | |
1099 | `DMA_CHANNEL_TWENTY: eofListBitSet = DMA20_EofList; | |
1100 | `DMA_CHANNEL_TWENTYONE: eofListBitSet = DMA21_EofList; | |
1101 | `DMA_CHANNEL_TWENTYTWO: eofListBitSet = DMA22_EofList; | |
1102 | `DMA_CHANNEL_TWENTYTHREE: eofListBitSet = DMA23_EofList; | |
1103 | default: eofListBitSet = 1'bx; | |
1104 | endcase | |
1105 | ||
1106 | ||
1107 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1108 | or DMA23_Error or DMA22_Error or DMA21_Error or DMA20_Error | |
1109 | or DMA19_Error or DMA18_Error or DMA17_Error or DMA16_Error | |
1110 | or DMA15_Error or DMA14_Error or DMA13_Error or DMA12_Error | |
1111 | or DMA11_Error or DMA10_Error or DMA9_Error or DMA8_Error | |
1112 | or DMA7_Error or DMA6_Error or DMA5_Error or DMA4_Error | |
1113 | or DMA3_Error or DMA2_Error or DMA1_Error or DMA0_Error | |
1114 | ) | |
1115 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1116 | `DMA_CHANNEL_ZERO: errorBitSet = DMA0_Error; | |
1117 | `DMA_CHANNEL_ONE: errorBitSet = DMA1_Error; | |
1118 | `DMA_CHANNEL_TWO: errorBitSet = DMA2_Error; | |
1119 | `DMA_CHANNEL_THREE: errorBitSet = DMA3_Error; | |
1120 | `DMA_CHANNEL_FOUR: errorBitSet = DMA4_Error; | |
1121 | `DMA_CHANNEL_FIVE: errorBitSet = DMA5_Error; | |
1122 | `DMA_CHANNEL_SIX: errorBitSet = DMA6_Error; | |
1123 | `DMA_CHANNEL_SEVEN: errorBitSet = DMA7_Error; | |
1124 | `DMA_CHANNEL_EIGHT: errorBitSet = DMA8_Error; | |
1125 | `DMA_CHANNEL_NINE: errorBitSet = DMA9_Error; | |
1126 | `DMA_CHANNEL_TEN: errorBitSet = DMA10_Error; | |
1127 | `DMA_CHANNEL_ELEVEN: errorBitSet = DMA11_Error; | |
1128 | `DMA_CHANNEL_TWELVE: errorBitSet = DMA12_Error; | |
1129 | `DMA_CHANNEL_THIRTEEN: errorBitSet = DMA13_Error; | |
1130 | `DMA_CHANNEL_FOURTEEN: errorBitSet = DMA14_Error; | |
1131 | `DMA_CHANNEL_FIFTEEN: errorBitSet = DMA15_Error; | |
1132 | `DMA_CHANNEL_SIXTEEN: errorBitSet = DMA16_Error; | |
1133 | `DMA_CHANNEL_SEVENTEEN: errorBitSet = DMA17_Error; | |
1134 | `DMA_CHANNEL_EIGHTEEN: errorBitSet = DMA18_Error; | |
1135 | `DMA_CHANNEL_NINETEEN: errorBitSet = DMA19_Error; | |
1136 | `DMA_CHANNEL_TWENTY: errorBitSet = DMA20_Error; | |
1137 | `DMA_CHANNEL_TWENTYONE: errorBitSet = DMA21_Error; | |
1138 | `DMA_CHANNEL_TWENTYTWO: errorBitSet = DMA22_Error; | |
1139 | `DMA_CHANNEL_TWENTYTHREE: errorBitSet = DMA23_Error; | |
1140 | default: errorBitSet = 1'bx; | |
1141 | endcase | |
1142 | ||
1143 | ||
1144 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1145 | or DMA23_Mark or DMA22_Mark or DMA21_Mark or DMA20_Mark | |
1146 | or DMA19_Mark or DMA18_Mark or DMA17_Mark or DMA16_Mark | |
1147 | or DMA15_Mark or DMA14_Mark or DMA13_Mark or DMA12_Mark | |
1148 | or DMA11_Mark or DMA10_Mark or DMA9_Mark or DMA8_Mark | |
1149 | or DMA7_Mark or DMA6_Mark or DMA5_Mark or DMA4_Mark | |
1150 | or DMA3_Mark or DMA2_Mark or DMA1_Mark or DMA0_Mark | |
1151 | ) | |
1152 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1153 | `DMA_CHANNEL_ZERO: markBitSet = DMA0_Mark; | |
1154 | `DMA_CHANNEL_ONE: markBitSet = DMA1_Mark; | |
1155 | `DMA_CHANNEL_TWO: markBitSet = DMA2_Mark; | |
1156 | `DMA_CHANNEL_THREE: markBitSet = DMA3_Mark; | |
1157 | `DMA_CHANNEL_FOUR: markBitSet = DMA4_Mark; | |
1158 | `DMA_CHANNEL_FIVE: markBitSet = DMA5_Mark; | |
1159 | `DMA_CHANNEL_SIX: markBitSet = DMA6_Mark; | |
1160 | `DMA_CHANNEL_SEVEN: markBitSet = DMA7_Mark; | |
1161 | `DMA_CHANNEL_EIGHT: markBitSet = DMA8_Mark; | |
1162 | `DMA_CHANNEL_NINE: markBitSet = DMA9_Mark; | |
1163 | `DMA_CHANNEL_TEN: markBitSet = DMA10_Mark; | |
1164 | `DMA_CHANNEL_ELEVEN: markBitSet = DMA11_Mark; | |
1165 | `DMA_CHANNEL_TWELVE: markBitSet = DMA12_Mark; | |
1166 | `DMA_CHANNEL_THIRTEEN: markBitSet = DMA13_Mark; | |
1167 | `DMA_CHANNEL_FOURTEEN: markBitSet = DMA14_Mark; | |
1168 | `DMA_CHANNEL_FIFTEEN: markBitSet = DMA15_Mark; | |
1169 | `DMA_CHANNEL_SIXTEEN: markBitSet = DMA16_Mark; | |
1170 | `DMA_CHANNEL_SEVENTEEN: markBitSet = DMA17_Mark; | |
1171 | `DMA_CHANNEL_EIGHTEEN: markBitSet = DMA18_Mark; | |
1172 | `DMA_CHANNEL_NINETEEN: markBitSet = DMA19_Mark; | |
1173 | `DMA_CHANNEL_TWENTY: markBitSet = DMA20_Mark; | |
1174 | `DMA_CHANNEL_TWENTYONE: markBitSet = DMA21_Mark; | |
1175 | `DMA_CHANNEL_TWENTYTWO: markBitSet = DMA22_Mark; | |
1176 | `DMA_CHANNEL_TWENTYTHREE: markBitSet = DMA23_Mark; | |
1177 | default: markBitSet = 1'bx; | |
1178 | endcase | |
1179 | ||
1180 | ||
1181 | ||
1182 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1183 | or DMA23_Length or DMA22_Length or DMA21_Length or DMA20_Length | |
1184 | or DMA19_Length or DMA18_Length or DMA17_Length or DMA16_Length | |
1185 | or DMA15_Length or DMA14_Length or DMA13_Length or DMA12_Length | |
1186 | or DMA11_Length or DMA10_Length or DMA9_Length or DMA8_Length | |
1187 | or DMA7_Length or DMA6_Length or DMA5_Length or DMA4_Length | |
1188 | or DMA3_Length or DMA2_Length or DMA1_Length or DMA0_Length | |
1189 | ) | |
1190 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1191 | `DMA_CHANNEL_ZERO: anchorLength = DMA0_Length; | |
1192 | `DMA_CHANNEL_ONE: anchorLength = DMA1_Length; | |
1193 | `DMA_CHANNEL_TWO: anchorLength = DMA2_Length; | |
1194 | `DMA_CHANNEL_THREE: anchorLength = DMA3_Length; | |
1195 | `DMA_CHANNEL_FOUR: anchorLength = DMA4_Length; | |
1196 | `DMA_CHANNEL_FIVE: anchorLength = DMA5_Length; | |
1197 | `DMA_CHANNEL_SIX: anchorLength = DMA6_Length; | |
1198 | `DMA_CHANNEL_SEVEN: anchorLength = DMA7_Length; | |
1199 | `DMA_CHANNEL_EIGHT: anchorLength = DMA8_Length; | |
1200 | `DMA_CHANNEL_NINE: anchorLength = DMA9_Length; | |
1201 | `DMA_CHANNEL_TEN: anchorLength = DMA10_Length; | |
1202 | `DMA_CHANNEL_ELEVEN: anchorLength = DMA11_Length; | |
1203 | `DMA_CHANNEL_TWELVE: anchorLength = DMA12_Length; | |
1204 | `DMA_CHANNEL_THIRTEEN: anchorLength = DMA13_Length; | |
1205 | `DMA_CHANNEL_FOURTEEN: anchorLength = DMA14_Length; | |
1206 | `DMA_CHANNEL_FIFTEEN: anchorLength = DMA15_Length; | |
1207 | `DMA_CHANNEL_SIXTEEN: anchorLength = DMA16_Length; | |
1208 | `DMA_CHANNEL_SEVENTEEN: anchorLength = DMA17_Length; | |
1209 | `DMA_CHANNEL_EIGHTEEN: anchorLength = DMA18_Length; | |
1210 | `DMA_CHANNEL_NINETEEN: anchorLength = DMA19_Length; | |
1211 | `DMA_CHANNEL_TWENTY: anchorLength = DMA20_Length; | |
1212 | `DMA_CHANNEL_TWENTYONE: anchorLength = DMA21_Length; | |
1213 | `DMA_CHANNEL_TWENTYTWO: anchorLength = DMA22_Length; | |
1214 | `DMA_CHANNEL_TWENTYTHREE: anchorLength = DMA23_Length; | |
1215 | default: anchorLength = 13'hx; | |
1216 | endcase | |
1217 | ||
1218 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1219 | or DMA23_PageHandle | |
1220 | or DMA22_PageHandle or DMA21_PageHandle or DMA20_PageHandle | |
1221 | or DMA19_PageHandle or DMA18_PageHandle or DMA17_PageHandle | |
1222 | or DMA16_PageHandle or DMA15_PageHandle or DMA14_PageHandle | |
1223 | or DMA13_PageHandle or DMA12_PageHandle or DMA11_PageHandle | |
1224 | or DMA10_PageHandle or DMA9_PageHandle or DMA8_PageHandle | |
1225 | or DMA7_PageHandle or DMA6_PageHandle or DMA5_PageHandle | |
1226 | or DMA4_PageHandle or DMA3_PageHandle or DMA2_PageHandle | |
1227 | or DMA1_PageHandle or DMA0_PageHandle | |
1228 | ) | |
1229 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1230 | `DMA_CHANNEL_ZERO: pageHandle = DMA0_PageHandle; | |
1231 | `DMA_CHANNEL_ONE: pageHandle = DMA1_PageHandle; | |
1232 | `DMA_CHANNEL_TWO: pageHandle = DMA2_PageHandle; | |
1233 | `DMA_CHANNEL_THREE: pageHandle = DMA3_PageHandle; | |
1234 | `DMA_CHANNEL_FOUR: pageHandle = DMA4_PageHandle; | |
1235 | `DMA_CHANNEL_FIVE: pageHandle = DMA5_PageHandle; | |
1236 | `DMA_CHANNEL_SIX: pageHandle = DMA6_PageHandle; | |
1237 | `DMA_CHANNEL_SEVEN: pageHandle = DMA7_PageHandle; | |
1238 | `DMA_CHANNEL_EIGHT: pageHandle = DMA8_PageHandle; | |
1239 | `DMA_CHANNEL_NINE: pageHandle = DMA9_PageHandle; | |
1240 | `DMA_CHANNEL_TEN: pageHandle = DMA10_PageHandle; | |
1241 | `DMA_CHANNEL_ELEVEN: pageHandle = DMA11_PageHandle; | |
1242 | `DMA_CHANNEL_TWELVE: pageHandle = DMA12_PageHandle; | |
1243 | `DMA_CHANNEL_THIRTEEN: pageHandle = DMA13_PageHandle; | |
1244 | `DMA_CHANNEL_FOURTEEN: pageHandle = DMA14_PageHandle; | |
1245 | `DMA_CHANNEL_FIFTEEN: pageHandle = DMA15_PageHandle; | |
1246 | `DMA_CHANNEL_SIXTEEN: pageHandle = DMA16_PageHandle; | |
1247 | `DMA_CHANNEL_SEVENTEEN: pageHandle = DMA17_PageHandle; | |
1248 | `DMA_CHANNEL_EIGHTEEN: pageHandle = DMA18_PageHandle; | |
1249 | `DMA_CHANNEL_NINETEEN: pageHandle = DMA19_PageHandle; | |
1250 | `DMA_CHANNEL_TWENTY: pageHandle = DMA20_PageHandle; | |
1251 | `DMA_CHANNEL_TWENTYONE: pageHandle = DMA21_PageHandle; | |
1252 | `DMA_CHANNEL_TWENTYTWO: pageHandle = DMA22_PageHandle; | |
1253 | `DMA_CHANNEL_TWENTYTHREE: pageHandle = DMA23_PageHandle; | |
1254 | default: pageHandle = 20'hx; | |
1255 | endcase | |
1256 | ||
1257 | ||
1258 | // synopsys infer_mux "AnchorAddress_Mux" | |
1259 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1260 | or DMA23_Address or DMA22_Address or DMA21_Address or DMA20_Address | |
1261 | or DMA19_Address or DMA18_Address or DMA17_Address or DMA16_Address | |
1262 | or DMA15_Address or DMA14_Address or DMA13_Address or DMA12_Address | |
1263 | or DMA11_Address or DMA10_Address or DMA9_Address or DMA8_Address | |
1264 | or DMA7_Address or DMA6_Address or DMA5_Address or DMA4_Address | |
1265 | or DMA3_Address or DMA2_Address or DMA1_Address or DMA0_Address | |
1266 | ) | |
1267 | begin: AnchorAddress_Mux | |
1268 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1269 | `DMA_CHANNEL_ZERO: anchorAddress = DMA0_Address; | |
1270 | `DMA_CHANNEL_ONE: anchorAddress = DMA1_Address; | |
1271 | `DMA_CHANNEL_TWO: anchorAddress = DMA2_Address; | |
1272 | `DMA_CHANNEL_THREE: anchorAddress = DMA3_Address; | |
1273 | `DMA_CHANNEL_FOUR: anchorAddress = DMA4_Address; | |
1274 | `DMA_CHANNEL_FIVE: anchorAddress = DMA5_Address; | |
1275 | `DMA_CHANNEL_SIX: anchorAddress = DMA6_Address; | |
1276 | `DMA_CHANNEL_SEVEN: anchorAddress = DMA7_Address; | |
1277 | `DMA_CHANNEL_EIGHT: anchorAddress = DMA8_Address; | |
1278 | `DMA_CHANNEL_NINE: anchorAddress = DMA9_Address; | |
1279 | `DMA_CHANNEL_TEN: anchorAddress = DMA10_Address; | |
1280 | `DMA_CHANNEL_ELEVEN: anchorAddress = DMA11_Address; | |
1281 | `DMA_CHANNEL_TWELVE: anchorAddress = DMA12_Address; | |
1282 | `DMA_CHANNEL_THIRTEEN: anchorAddress = DMA13_Address; | |
1283 | `DMA_CHANNEL_FOURTEEN: anchorAddress = DMA14_Address; | |
1284 | `DMA_CHANNEL_FIFTEEN: anchorAddress = DMA15_Address; | |
1285 | `DMA_CHANNEL_SIXTEEN: anchorAddress = DMA16_Address; | |
1286 | `DMA_CHANNEL_SEVENTEEN: anchorAddress = DMA17_Address; | |
1287 | `DMA_CHANNEL_EIGHTEEN: anchorAddress = DMA18_Address; | |
1288 | `DMA_CHANNEL_NINETEEN: anchorAddress = DMA19_Address; | |
1289 | `DMA_CHANNEL_TWENTY: anchorAddress = DMA20_Address; | |
1290 | `DMA_CHANNEL_TWENTYONE: anchorAddress = DMA21_Address; | |
1291 | `DMA_CHANNEL_TWENTYTWO: anchorAddress = DMA22_Address; | |
1292 | `DMA_CHANNEL_TWENTYTHREE: anchorAddress = DMA23_Address; | |
1293 | default: anchorAddress = 44'hx; | |
1294 | endcase | |
1295 | end | |
1296 | ||
1297 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1298 | or DMA23_DescList | |
1299 | or DMA22_DescList or DMA21_DescList or DMA20_DescList | |
1300 | or DMA19_DescList or DMA18_DescList or DMA17_DescList | |
1301 | or DMA16_DescList or DMA15_DescList or DMA14_DescList | |
1302 | or DMA13_DescList or DMA12_DescList or DMA11_DescList | |
1303 | or DMA10_DescList or DMA9_DescList or DMA8_DescList | |
1304 | or DMA7_DescList or DMA6_DescList or DMA5_DescList | |
1305 | or DMA4_DescList or DMA3_DescList or DMA2_DescList | |
1306 | or DMA1_DescList or DMA0_DescList | |
1307 | ) | |
1308 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1309 | `DMA_CHANNEL_ZERO: anchorDescList = DMA0_DescList; | |
1310 | `DMA_CHANNEL_ONE: anchorDescList = DMA1_DescList; | |
1311 | `DMA_CHANNEL_TWO: anchorDescList = DMA2_DescList; | |
1312 | `DMA_CHANNEL_THREE: anchorDescList = DMA3_DescList; | |
1313 | `DMA_CHANNEL_FOUR: anchorDescList = DMA4_DescList; | |
1314 | `DMA_CHANNEL_FIVE: anchorDescList = DMA5_DescList; | |
1315 | `DMA_CHANNEL_SIX: anchorDescList = DMA6_DescList; | |
1316 | `DMA_CHANNEL_SEVEN: anchorDescList = DMA7_DescList; | |
1317 | `DMA_CHANNEL_EIGHT: anchorDescList = DMA8_DescList; | |
1318 | `DMA_CHANNEL_NINE: anchorDescList = DMA9_DescList; | |
1319 | `DMA_CHANNEL_TEN: anchorDescList = DMA10_DescList; | |
1320 | `DMA_CHANNEL_ELEVEN: anchorDescList = DMA11_DescList; | |
1321 | `DMA_CHANNEL_TWELVE: anchorDescList = DMA12_DescList; | |
1322 | `DMA_CHANNEL_THIRTEEN: anchorDescList = DMA13_DescList; | |
1323 | `DMA_CHANNEL_FOURTEEN: anchorDescList = DMA14_DescList; | |
1324 | `DMA_CHANNEL_FIFTEEN: anchorDescList = DMA15_DescList; | |
1325 | `DMA_CHANNEL_SIXTEEN: anchorDescList = DMA16_DescList; | |
1326 | `DMA_CHANNEL_SEVENTEEN: anchorDescList = DMA17_DescList; | |
1327 | `DMA_CHANNEL_EIGHTEEN: anchorDescList = DMA18_DescList; | |
1328 | `DMA_CHANNEL_NINETEEN: anchorDescList = DMA19_DescList; | |
1329 | `DMA_CHANNEL_TWENTY: anchorDescList = DMA20_DescList; | |
1330 | `DMA_CHANNEL_TWENTYONE: anchorDescList = DMA21_DescList; | |
1331 | `DMA_CHANNEL_TWENTYTWO: anchorDescList = DMA22_DescList; | |
1332 | `DMA_CHANNEL_TWENTYTHREE: anchorDescList = DMA23_DescList; | |
1333 | default: anchorDescList = 4'hx; | |
1334 | endcase | |
1335 | ||
1336 | always @(/*AUTOSENSE*/DRR_NextDMAChannel | |
1337 | or DMA23_GotNxtDesc | |
1338 | or DMA22_GotNxtDesc or DMA21_GotNxtDesc or DMA20_GotNxtDesc | |
1339 | or DMA19_GotNxtDesc or DMA18_GotNxtDesc or DMA17_GotNxtDesc | |
1340 | or DMA16_GotNxtDesc or DMA15_GotNxtDesc or DMA14_GotNxtDesc | |
1341 | or DMA13_GotNxtDesc or DMA12_GotNxtDesc or DMA11_GotNxtDesc | |
1342 | or DMA10_GotNxtDesc or DMA9_GotNxtDesc or DMA8_GotNxtDesc | |
1343 | or DMA7_GotNxtDesc or DMA6_GotNxtDesc or DMA5_GotNxtDesc | |
1344 | or DMA4_GotNxtDesc or DMA3_GotNxtDesc or DMA2_GotNxtDesc | |
1345 | or DMA1_GotNxtDesc or DMA0_GotNxtDesc | |
1346 | ) | |
1347 | case(DRR_NextDMAChannel) // synopsys full_case parallel_case | |
1348 | `DMA_CHANNEL_ZERO: gotNextDescriptor = DMA0_GotNxtDesc; | |
1349 | `DMA_CHANNEL_ONE: gotNextDescriptor = DMA1_GotNxtDesc; | |
1350 | `DMA_CHANNEL_TWO: gotNextDescriptor = DMA2_GotNxtDesc; | |
1351 | `DMA_CHANNEL_THREE: gotNextDescriptor = DMA3_GotNxtDesc; | |
1352 | `DMA_CHANNEL_FOUR: gotNextDescriptor = DMA4_GotNxtDesc; | |
1353 | `DMA_CHANNEL_FIVE: gotNextDescriptor = DMA5_GotNxtDesc; | |
1354 | `DMA_CHANNEL_SIX: gotNextDescriptor = DMA6_GotNxtDesc; | |
1355 | `DMA_CHANNEL_SEVEN: gotNextDescriptor = DMA7_GotNxtDesc; | |
1356 | `DMA_CHANNEL_EIGHT: gotNextDescriptor = DMA8_GotNxtDesc; | |
1357 | `DMA_CHANNEL_NINE: gotNextDescriptor = DMA9_GotNxtDesc; | |
1358 | `DMA_CHANNEL_TEN: gotNextDescriptor = DMA10_GotNxtDesc; | |
1359 | `DMA_CHANNEL_ELEVEN: gotNextDescriptor = DMA11_GotNxtDesc; | |
1360 | `DMA_CHANNEL_TWELVE: gotNextDescriptor = DMA12_GotNxtDesc; | |
1361 | `DMA_CHANNEL_THIRTEEN: gotNextDescriptor = DMA13_GotNxtDesc; | |
1362 | `DMA_CHANNEL_FOURTEEN: gotNextDescriptor = DMA14_GotNxtDesc; | |
1363 | `DMA_CHANNEL_FIFTEEN: gotNextDescriptor = DMA15_GotNxtDesc; | |
1364 | `DMA_CHANNEL_SIXTEEN: gotNextDescriptor = DMA16_GotNxtDesc; | |
1365 | `DMA_CHANNEL_SEVENTEEN: gotNextDescriptor = DMA17_GotNxtDesc; | |
1366 | `DMA_CHANNEL_EIGHTEEN: gotNextDescriptor = DMA18_GotNxtDesc; | |
1367 | `DMA_CHANNEL_NINETEEN: gotNextDescriptor = DMA19_GotNxtDesc; | |
1368 | `DMA_CHANNEL_TWENTY: gotNextDescriptor = DMA20_GotNxtDesc; | |
1369 | `DMA_CHANNEL_TWENTYONE: gotNextDescriptor = DMA21_GotNxtDesc; | |
1370 | `DMA_CHANNEL_TWENTYTWO: gotNextDescriptor = DMA22_GotNxtDesc; | |
1371 | `DMA_CHANNEL_TWENTYTHREE: gotNextDescriptor = DMA23_GotNxtDesc; | |
1372 | default: gotNextDescriptor = 1'b0; | |
1373 | endcase | |
1374 | ||
1375 | /*--------------------------------------------------------------*/ | |
1376 | // DRR State Update | |
1377 | // Make sure that packetbytecount works when we abort the data request | |
1378 | // when anchor fails; | |
1379 | /*--------------------------------------------------------------*/ | |
1380 | always @(posedge SysClk) | |
1381 | if (!Reset_L) DRR_PacketDone <= #`SD 1'b0; | |
1382 | else DRR_PacketDone <= #`SD drrPacketDone; | |
1383 | ||
1384 | always @(posedge SysClk) | |
1385 | if (!Reset_L) PacketByteCount <= #`SD 16'h0; | |
1386 | else if (Anchor_Done) PacketByteCount <= #`SD PacketByteCount | |
1387 | + | |
1388 | {3'h0, Anchor_Length}; | |
1389 | else if (DRR_PacketDone) PacketByteCount <= #`SD 16'h0; | |
1390 | ||
1391 | /*--------------------------------------------------------------*/ | |
1392 | // Set Get Next Descriptor Logic | |
1393 | /*--------------------------------------------------------------*/ | |
1394 | assign SetGetNextDescDMA0 = currentDMAChannel[0] & setGetNextDescriptor; | |
1395 | assign SetGetNextDescDMA1 = currentDMAChannel[1] & setGetNextDescriptor; | |
1396 | assign SetGetNextDescDMA2 = currentDMAChannel[2] & setGetNextDescriptor; | |
1397 | assign SetGetNextDescDMA3 = currentDMAChannel[3] & setGetNextDescriptor; | |
1398 | assign SetGetNextDescDMA4 = currentDMAChannel[4] & setGetNextDescriptor; | |
1399 | assign SetGetNextDescDMA5 = currentDMAChannel[5] & setGetNextDescriptor; | |
1400 | assign SetGetNextDescDMA6 = currentDMAChannel[6] & setGetNextDescriptor; | |
1401 | assign SetGetNextDescDMA7 = currentDMAChannel[7] & setGetNextDescriptor; | |
1402 | assign SetGetNextDescDMA8 = currentDMAChannel[8] & setGetNextDescriptor; | |
1403 | assign SetGetNextDescDMA9 = currentDMAChannel[9] & setGetNextDescriptor; | |
1404 | assign SetGetNextDescDMA10 = currentDMAChannel[10] & setGetNextDescriptor; | |
1405 | assign SetGetNextDescDMA11 = currentDMAChannel[11] & setGetNextDescriptor; | |
1406 | assign SetGetNextDescDMA12 = currentDMAChannel[12] & setGetNextDescriptor; | |
1407 | assign SetGetNextDescDMA13 = currentDMAChannel[13] & setGetNextDescriptor; | |
1408 | assign SetGetNextDescDMA14 = currentDMAChannel[14] & setGetNextDescriptor; | |
1409 | assign SetGetNextDescDMA15 = currentDMAChannel[15] & setGetNextDescriptor; | |
1410 | assign SetGetNextDescDMA16 = currentDMAChannel[16] & setGetNextDescriptor; | |
1411 | assign SetGetNextDescDMA17 = currentDMAChannel[17] & setGetNextDescriptor; | |
1412 | assign SetGetNextDescDMA18 = currentDMAChannel[18] & setGetNextDescriptor; | |
1413 | assign SetGetNextDescDMA19 = currentDMAChannel[19] & setGetNextDescriptor; | |
1414 | assign SetGetNextDescDMA20 = currentDMAChannel[20] & setGetNextDescriptor; | |
1415 | assign SetGetNextDescDMA21 = currentDMAChannel[21] & setGetNextDescriptor; | |
1416 | assign SetGetNextDescDMA22 = currentDMAChannel[22] & setGetNextDescriptor; | |
1417 | assign SetGetNextDescDMA23 = currentDMAChannel[23] & setGetNextDescriptor; | |
1418 | ||
1419 | /*--------------------------------------------------------------*/ | |
1420 | // Descriptor Gather logic | |
1421 | /*--------------------------------------------------------------*/ | |
1422 | always @(posedge SysClk) | |
1423 | if (!Reset_L) descriptorList <= #`SD 4'h0; | |
1424 | else if (ldDescList) descriptorList <= #`SD anchorDescList; | |
1425 | else if (decrementDescList) descriptorList <= #`SD descriptorList - 4'h1; | |
1426 | ||
1427 | assign decrementDescList = ((descriptorList != 4'h0) && portRequestDone); | |
1428 | assign nullDescriptor = (descriptorList == 4'h0); | |
1429 | assign singleDescriptor = (descriptorList == 4'h1); | |
1430 | assign multiDescriptor = (descriptorList >= 4'h2); | |
1431 | ||
1432 | /*--------------------------------------------------------------*/ | |
1433 | // Packet Size Error Logic | |
1434 | /*--------------------------------------------------------------*/ | |
1435 | assign setPacketSizeErr = enableSizeCheck | |
1436 | ? (pktSizeCheck + {3'h0, anchorLengthD1}) > 16'd9600 | |
1437 | : 1'b0; | |
1438 | ||
1439 | always @(posedge SysClk) | |
1440 | if (!Reset_L) enableSizeCheck <= #`SD 1'b0; | |
1441 | else if (setEnableSizeCheck) enableSizeCheck <= #`SD 1'b1; | |
1442 | else if (anchorRequest) enableSizeCheck <= #`SD 1'b0; | |
1443 | else if (clrEnableSizeCheck) enableSizeCheck <= #`SD 1'b0; | |
1444 | ||
1445 | always @(posedge SysClk) | |
1446 | if (!Reset_L) anchorLengthD1 <= #`SD 13'h0; | |
1447 | else anchorLengthD1 <= #`SD anchorLength; | |
1448 | ||
1449 | always @(posedge SysClk) | |
1450 | if (!Reset_L) pktSizeCheck <= #`SD 16'h0; | |
1451 | else if (anchorRequest) pktSizeCheck <= #`SD pktSizeCheck | |
1452 | + | |
1453 | {3'h0, anchorLengthD1}; | |
1454 | else if (DRR_PacketDone) pktSizeCheck <= #`SD 16'b0; | |
1455 | ||
1456 | always @(posedge SysClk) | |
1457 | if (!Reset_L) Pkt_Size_Err <= #`SD 1'b0; | |
1458 | else if (setPacketSizeErr) Pkt_Size_Err <= #`SD 1'b1; | |
1459 | else if (DRR_PacketDone) Pkt_Size_Err <= #`SD 1'b0; | |
1460 | ||
1461 | always @(posedge SysClk) | |
1462 | if (!Reset_L) DMA_Pkt_Size_Err <= #`SD 24'h0; | |
1463 | else if (setPacketSizeErr) DMA_Pkt_Size_Err <= #`SD currentDMAChannel; | |
1464 | else if (DRR_PacketDone) DMA_Pkt_Size_Err <= #`SD 24'h0; | |
1465 | ||
1466 | always @(posedge SysClk) | |
1467 | if (!Reset_L) Pkt_Size_Err_Addr <= #`SD 44'h0; | |
1468 | else if (setPacketSizeErr) Pkt_Size_Err_Addr <= #`SD anchorAddress; | |
1469 | else if (DRR_PacketDone) Pkt_Size_Err_Addr <= #`SD 44'h0; | |
1470 | ||
1471 | /*--------------------------------------------------------------*/ | |
1472 | // Port Select, Data PortReq & Data Write State Vector | |
1473 | /*--------------------------------------------------------------*/ | |
1474 | always @(posedge SysClk) | |
1475 | if (!Reset_L) DataPortReq_State <= #`SD PORT_REQUEST_IDLE; | |
1476 | else DataPortReq_State <= #`SD nextPortReqState; | |
1477 | ||
1478 | /*--------------------------------------------------------------*/ | |
1479 | // Data PortReq State Machine | |
1480 | /*--------------------------------------------------------------*/ | |
1481 | function [3:0] PortReqDefaults; | |
1482 | input [3:0] currentState; | |
1483 | begin | |
1484 | PortReqDefaults = currentState; | |
1485 | anchorRequest = 1'b0; | |
1486 | setPortRequest = 1'b0; | |
1487 | drrPacketDone = 1'b0; | |
1488 | ldDescList = 1'b0; | |
1489 | setGetNextDescriptor = 1'b0; | |
1490 | setEnableSizeCheck = 1'b0; | |
1491 | clrEnableSizeCheck = 1'b0; | |
1492 | end | |
1493 | endfunction | |
1494 | ||
1495 | ||
1496 | always @(/*AUTOSENSE*/DataPortReq_State or Txc_Enabled | |
1497 | or Port_Enabled or DRR_Arb_Valid | |
1498 | or Anchor_Done or portRequestDone | |
1499 | or gotNextDescriptor or multiDescriptor or nullDescriptor | |
1500 | or setPacketSizeErr | |
1501 | or sopBitNotSet or eofListBitSet or errorBitSet | |
1502 | ) | |
1503 | ||
1504 | case(DataPortReq_State) // synopsys full_case parallel_case | |
1505 | /* 0in < case -full -parallel */ | |
1506 | PORT_REQUEST_IDLE: | |
1507 | begin | |
1508 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1509 | ||
1510 | if (Txc_Enabled) | |
1511 | begin | |
1512 | if (Port_Enabled) | |
1513 | begin | |
1514 | if (DRR_Arb_Valid) | |
1515 | nextPortReqState = CHECK_FOR_DESCRIPTOR; | |
1516 | end | |
1517 | end | |
1518 | end | |
1519 | ||
1520 | CHECK_FOR_DESCRIPTOR: | |
1521 | begin | |
1522 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1523 | ||
1524 | if (errorBitSet) | |
1525 | nextPortReqState = ERROR_STATE; | |
1526 | else if (gotNextDescriptor) | |
1527 | begin | |
1528 | setEnableSizeCheck = 1'b1; | |
1529 | nextPortReqState = REQ_ANCHOR; | |
1530 | end | |
1531 | end | |
1532 | ||
1533 | REQ_ANCHOR: | |
1534 | begin | |
1535 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1536 | ||
1537 | if (setPacketSizeErr | eofListBitSet | errorBitSet | sopBitNotSet) | |
1538 | begin | |
1539 | clrEnableSizeCheck = 1'b1; | |
1540 | nextPortReqState = ERROR_STATE; | |
1541 | end | |
1542 | else | |
1543 | begin | |
1544 | anchorRequest = 1'b1; | |
1545 | ldDescList = 1'b1; | |
1546 | nextPortReqState = WAIT_FOR_ANCHOR; | |
1547 | end | |
1548 | end | |
1549 | ||
1550 | WAIT_FOR_ANCHOR: | |
1551 | begin | |
1552 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1553 | if (Anchor_Done) | |
1554 | nextPortReqState = PORT_REQUEST; | |
1555 | end | |
1556 | ||
1557 | PORT_REQUEST: | |
1558 | begin | |
1559 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1560 | setPortRequest = 1'b1; | |
1561 | ||
1562 | if (!nullDescriptor) | |
1563 | setGetNextDescriptor = 1'b1; | |
1564 | ||
1565 | nextPortReqState = WAIT_FOR_REQ_ACCEPT; | |
1566 | end | |
1567 | ||
1568 | WAIT_FOR_REQ_ACCEPT: | |
1569 | begin | |
1570 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1571 | ||
1572 | if (portRequestDone) | |
1573 | begin | |
1574 | if (multiDescriptor) | |
1575 | nextPortReqState = WAIT_FOR_NEXT_DESC; | |
1576 | else | |
1577 | begin | |
1578 | drrPacketDone = 1'b1; | |
1579 | nextPortReqState = WAIT_FOR_DRR_UPDATE; | |
1580 | end | |
1581 | end | |
1582 | end | |
1583 | ||
1584 | WAIT_FOR_NEXT_DESC: | |
1585 | begin | |
1586 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1587 | ||
1588 | if (errorBitSet) | |
1589 | nextPortReqState = ERROR_STATE; | |
1590 | else if (gotNextDescriptor) | |
1591 | begin | |
1592 | setEnableSizeCheck = 1'b1; | |
1593 | nextPortReqState = CHECK_PACKET_SIZE; | |
1594 | end | |
1595 | end | |
1596 | ||
1597 | CHECK_PACKET_SIZE: | |
1598 | begin | |
1599 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1600 | ||
1601 | if (setPacketSizeErr | eofListBitSet | errorBitSet) | |
1602 | begin | |
1603 | clrEnableSizeCheck = 1'b1; | |
1604 | nextPortReqState = ERROR_STATE; | |
1605 | end | |
1606 | else | |
1607 | begin | |
1608 | anchorRequest = 1'b1; | |
1609 | nextPortReqState = WAIT_FOR_ANCHOR; | |
1610 | end | |
1611 | end | |
1612 | ||
1613 | WAIT_FOR_DRR_UPDATE: | |
1614 | begin | |
1615 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1616 | ||
1617 | if (!DRR_Arb_Valid) | |
1618 | nextPortReqState = PORT_REQUEST_IDLE; | |
1619 | end | |
1620 | ||
1621 | ERROR_STATE: | |
1622 | begin | |
1623 | nextPortReqState = PortReqDefaults(DataPortReq_State); | |
1624 | ||
1625 | if (errorBitSet) | |
1626 | begin | |
1627 | drrPacketDone = 1'b1; | |
1628 | nextPortReqState = WAIT_FOR_DRR_UPDATE; | |
1629 | end | |
1630 | end | |
1631 | ||
1632 | ||
1633 | endcase | |
1634 | ||
1635 | endmodule |